2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
49 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
50 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
52 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
54 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
57 if (!i915_gem_object_is_coherent(obj))
60 return obj->pin_display;
64 insert_mappable_node(struct i915_ggtt *ggtt,
65 struct drm_mm_node *node, u32 size)
67 memset(node, 0, sizeof(*node));
68 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
69 size, 0, I915_COLOR_UNEVICTABLE,
70 0, ggtt->mappable_end,
75 remove_mappable_node(struct drm_mm_node *node)
77 drm_mm_remove_node(node);
80 /* some bookkeeping */
81 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
84 spin_lock(&dev_priv->mm.object_stat_lock);
85 dev_priv->mm.object_count++;
86 dev_priv->mm.object_memory += size;
87 spin_unlock(&dev_priv->mm.object_stat_lock);
90 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
93 spin_lock(&dev_priv->mm.object_stat_lock);
94 dev_priv->mm.object_count--;
95 dev_priv->mm.object_memory -= size;
96 spin_unlock(&dev_priv->mm.object_stat_lock);
100 i915_gem_wait_for_error(struct i915_gpu_error *error)
106 if (!i915_reset_in_progress(error))
110 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
111 * userspace. If it takes that long something really bad is going on and
112 * we should simply try to bail out and fail as gracefully as possible.
114 ret = wait_event_interruptible_timeout(error->reset_queue,
115 !i915_reset_in_progress(error),
118 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
120 } else if (ret < 0) {
127 int i915_mutex_lock_interruptible(struct drm_device *dev)
129 struct drm_i915_private *dev_priv = to_i915(dev);
132 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
136 ret = mutex_lock_interruptible(&dev->struct_mutex);
144 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
145 struct drm_file *file)
147 struct drm_i915_private *dev_priv = to_i915(dev);
148 struct i915_ggtt *ggtt = &dev_priv->ggtt;
149 struct drm_i915_gem_get_aperture *args = data;
150 struct i915_vma *vma;
154 mutex_lock(&dev->struct_mutex);
155 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
156 if (i915_vma_is_pinned(vma))
157 pinned += vma->node.size;
158 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
159 if (i915_vma_is_pinned(vma))
160 pinned += vma->node.size;
161 mutex_unlock(&dev->struct_mutex);
163 args->aper_size = ggtt->base.total;
164 args->aper_available_size = args->aper_size - pinned;
169 static struct sg_table *
170 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
172 struct address_space *mapping = obj->base.filp->f_mapping;
173 drm_dma_handle_t *phys;
175 struct scatterlist *sg;
179 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 return ERR_PTR(-EINVAL);
182 /* Always aligning to the object size, allows a single allocation
183 * to handle all possible callers, and given typical object sizes,
184 * the alignment of the buddy allocation will naturally match.
186 phys = drm_pci_alloc(obj->base.dev,
188 roundup_pow_of_two(obj->base.size));
190 return ERR_PTR(-ENOMEM);
193 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
197 page = shmem_read_mapping_page(mapping, i);
203 src = kmap_atomic(page);
204 memcpy(vaddr, src, PAGE_SIZE);
205 drm_clflush_virt_range(vaddr, PAGE_SIZE);
212 i915_gem_chipset_flush(to_i915(obj->base.dev));
214 st = kmalloc(sizeof(*st), GFP_KERNEL);
216 st = ERR_PTR(-ENOMEM);
220 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
222 st = ERR_PTR(-ENOMEM);
228 sg->length = obj->base.size;
230 sg_dma_address(sg) = phys->busaddr;
231 sg_dma_len(sg) = obj->base.size;
233 obj->phys_handle = phys;
237 drm_pci_free(obj->base.dev, phys);
242 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
243 struct sg_table *pages,
246 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
248 if (obj->mm.madv == I915_MADV_DONTNEED)
249 obj->mm.dirty = false;
252 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
253 !i915_gem_object_is_coherent(obj))
254 drm_clflush_sg(pages);
256 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
257 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
261 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
262 struct sg_table *pages)
264 __i915_gem_object_release_shmem(obj, pages, false);
267 struct address_space *mapping = obj->base.filp->f_mapping;
268 char *vaddr = obj->phys_handle->vaddr;
271 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
275 page = shmem_read_mapping_page(mapping, i);
279 dst = kmap_atomic(page);
280 drm_clflush_virt_range(vaddr, PAGE_SIZE);
281 memcpy(dst, vaddr, PAGE_SIZE);
284 set_page_dirty(page);
285 if (obj->mm.madv == I915_MADV_WILLNEED)
286 mark_page_accessed(page);
290 obj->mm.dirty = false;
293 sg_free_table(pages);
296 drm_pci_free(obj->base.dev, obj->phys_handle);
300 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
302 i915_gem_object_unpin_pages(obj);
305 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
306 .get_pages = i915_gem_object_get_pages_phys,
307 .put_pages = i915_gem_object_put_pages_phys,
308 .release = i915_gem_object_release_phys,
311 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
313 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
315 struct i915_vma *vma;
316 LIST_HEAD(still_in_list);
319 lockdep_assert_held(&obj->base.dev->struct_mutex);
321 /* Closed vma are removed from the obj->vma_list - but they may
322 * still have an active binding on the object. To remove those we
323 * must wait for all rendering to complete to the object (as unbinding
324 * must anyway), and retire the requests.
326 ret = i915_gem_object_wait(obj,
327 I915_WAIT_INTERRUPTIBLE |
330 MAX_SCHEDULE_TIMEOUT,
335 i915_gem_retire_requests(to_i915(obj->base.dev));
337 while ((vma = list_first_entry_or_null(&obj->vma_list,
340 list_move_tail(&vma->obj_link, &still_in_list);
341 ret = i915_vma_unbind(vma);
345 list_splice(&still_in_list, &obj->vma_list);
351 i915_gem_object_wait_fence(struct dma_fence *fence,
354 struct intel_rps_client *rps)
356 struct drm_i915_gem_request *rq;
358 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
360 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
363 if (!dma_fence_is_i915(fence))
364 return dma_fence_wait_timeout(fence,
365 flags & I915_WAIT_INTERRUPTIBLE,
368 rq = to_request(fence);
369 if (i915_gem_request_completed(rq))
372 /* This client is about to stall waiting for the GPU. In many cases
373 * this is undesirable and limits the throughput of the system, as
374 * many clients cannot continue processing user input/output whilst
375 * blocked. RPS autotuning may take tens of milliseconds to respond
376 * to the GPU load and thus incurs additional latency for the client.
377 * We can circumvent that by promoting the GPU frequency to maximum
378 * before we wait. This makes the GPU throttle up much more quickly
379 * (good for benchmarks and user experience, e.g. window animations),
380 * but at a cost of spending more power processing the workload
381 * (bad for battery). Not all clients even want their results
382 * immediately and for them we should just let the GPU select its own
383 * frequency to maximise efficiency. To prevent a single client from
384 * forcing the clocks too high for the whole system, we only allow
385 * each client to waitboost once in a busy period.
388 if (INTEL_GEN(rq->i915) >= 6)
389 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
394 timeout = i915_wait_request(rq, flags, timeout);
397 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
398 i915_gem_request_retire_upto(rq);
400 if (rps && i915_gem_request_global_seqno(rq) == intel_engine_last_submit(rq->engine)) {
401 /* The GPU is now idle and this client has stalled.
402 * Since no other client has submitted a request in the
403 * meantime, assume that this client is the only one
404 * supplying work to the GPU but is unable to keep that
405 * work supplied because it is waiting. Since the GPU is
406 * then never kept fully busy, RPS autoclocking will
407 * keep the clocks relatively low, causing further delays.
408 * Compensate by giving the synchronous client credit for
409 * a waitboost next time.
411 spin_lock(&rq->i915->rps.client_lock);
412 list_del_init(&rps->link);
413 spin_unlock(&rq->i915->rps.client_lock);
420 i915_gem_object_wait_reservation(struct reservation_object *resv,
423 struct intel_rps_client *rps)
425 unsigned int seq = __read_seqcount_begin(&resv->seq);
426 struct dma_fence *excl;
427 bool prune_fences = false;
429 if (flags & I915_WAIT_ALL) {
430 struct dma_fence **shared;
431 unsigned int count, i;
434 ret = reservation_object_get_fences_rcu(resv,
435 &excl, &count, &shared);
439 for (i = 0; i < count; i++) {
440 timeout = i915_gem_object_wait_fence(shared[i],
446 dma_fence_put(shared[i]);
449 for (; i < count; i++)
450 dma_fence_put(shared[i]);
453 prune_fences = count && timeout >= 0;
455 excl = reservation_object_get_excl_rcu(resv);
458 if (excl && timeout >= 0) {
459 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
460 prune_fences = timeout >= 0;
465 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
466 reservation_object_lock(resv, NULL);
467 if (!__read_seqcount_retry(&resv->seq, seq))
468 reservation_object_add_excl_fence(resv, NULL);
469 reservation_object_unlock(resv);
475 static void __fence_set_priority(struct dma_fence *fence, int prio)
477 struct drm_i915_gem_request *rq;
478 struct intel_engine_cs *engine;
480 if (!dma_fence_is_i915(fence))
483 rq = to_request(fence);
485 if (!engine->schedule)
488 engine->schedule(rq, prio);
491 static void fence_set_priority(struct dma_fence *fence, int prio)
493 /* Recurse once into a fence-array */
494 if (dma_fence_is_array(fence)) {
495 struct dma_fence_array *array = to_dma_fence_array(fence);
498 for (i = 0; i < array->num_fences; i++)
499 __fence_set_priority(array->fences[i], prio);
501 __fence_set_priority(fence, prio);
506 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
510 struct dma_fence *excl;
512 if (flags & I915_WAIT_ALL) {
513 struct dma_fence **shared;
514 unsigned int count, i;
517 ret = reservation_object_get_fences_rcu(obj->resv,
518 &excl, &count, &shared);
522 for (i = 0; i < count; i++) {
523 fence_set_priority(shared[i], prio);
524 dma_fence_put(shared[i]);
529 excl = reservation_object_get_excl_rcu(obj->resv);
533 fence_set_priority(excl, prio);
540 * Waits for rendering to the object to be completed
541 * @obj: i915 gem object
542 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
543 * @timeout: how long to wait
544 * @rps: client (user process) to charge for any waitboosting
547 i915_gem_object_wait(struct drm_i915_gem_object *obj,
550 struct intel_rps_client *rps)
553 #if IS_ENABLED(CONFIG_LOCKDEP)
554 GEM_BUG_ON(debug_locks &&
555 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
556 !!(flags & I915_WAIT_LOCKED));
558 GEM_BUG_ON(timeout < 0);
560 timeout = i915_gem_object_wait_reservation(obj->resv,
563 return timeout < 0 ? timeout : 0;
566 static struct intel_rps_client *to_rps_client(struct drm_file *file)
568 struct drm_i915_file_private *fpriv = file->driver_priv;
574 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
579 if (align > obj->base.size)
582 if (obj->ops == &i915_gem_phys_ops)
585 if (obj->mm.madv != I915_MADV_WILLNEED)
588 if (obj->base.filp == NULL)
591 ret = i915_gem_object_unbind(obj);
595 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
599 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
600 obj->ops = &i915_gem_phys_ops;
602 ret = i915_gem_object_pin_pages(obj);
609 obj->ops = &i915_gem_object_ops;
614 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
615 struct drm_i915_gem_pwrite *args,
616 struct drm_file *file)
618 void *vaddr = obj->phys_handle->vaddr + args->offset;
619 char __user *user_data = u64_to_user_ptr(args->data_ptr);
621 /* We manually control the domain here and pretend that it
622 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
624 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
625 if (copy_from_user(vaddr, user_data, args->size))
628 drm_clflush_virt_range(vaddr, args->size);
629 i915_gem_chipset_flush(to_i915(obj->base.dev));
631 intel_fb_obj_flush(obj, ORIGIN_CPU);
635 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
637 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
640 void i915_gem_object_free(struct drm_i915_gem_object *obj)
642 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
643 kmem_cache_free(dev_priv->objects, obj);
647 i915_gem_create(struct drm_file *file,
648 struct drm_i915_private *dev_priv,
652 struct drm_i915_gem_object *obj;
656 size = roundup(size, PAGE_SIZE);
660 /* Allocate the new object */
661 obj = i915_gem_object_create(dev_priv, size);
665 ret = drm_gem_handle_create(file, &obj->base, &handle);
666 /* drop reference from allocate - handle holds it now */
667 i915_gem_object_put(obj);
676 i915_gem_dumb_create(struct drm_file *file,
677 struct drm_device *dev,
678 struct drm_mode_create_dumb *args)
680 /* have to work out size/pitch and return them */
681 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
682 args->size = args->pitch * args->height;
683 return i915_gem_create(file, to_i915(dev),
684 args->size, &args->handle);
688 * Creates a new mm object and returns a handle to it.
689 * @dev: drm device pointer
690 * @data: ioctl data blob
691 * @file: drm file pointer
694 i915_gem_create_ioctl(struct drm_device *dev, void *data,
695 struct drm_file *file)
697 struct drm_i915_private *dev_priv = to_i915(dev);
698 struct drm_i915_gem_create *args = data;
700 i915_gem_flush_free_objects(dev_priv);
702 return i915_gem_create(file, dev_priv,
703 args->size, &args->handle);
707 __copy_to_user_swizzled(char __user *cpu_vaddr,
708 const char *gpu_vaddr, int gpu_offset,
711 int ret, cpu_offset = 0;
714 int cacheline_end = ALIGN(gpu_offset + 1, 64);
715 int this_length = min(cacheline_end - gpu_offset, length);
716 int swizzled_gpu_offset = gpu_offset ^ 64;
718 ret = __copy_to_user(cpu_vaddr + cpu_offset,
719 gpu_vaddr + swizzled_gpu_offset,
724 cpu_offset += this_length;
725 gpu_offset += this_length;
726 length -= this_length;
733 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
734 const char __user *cpu_vaddr,
737 int ret, cpu_offset = 0;
740 int cacheline_end = ALIGN(gpu_offset + 1, 64);
741 int this_length = min(cacheline_end - gpu_offset, length);
742 int swizzled_gpu_offset = gpu_offset ^ 64;
744 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
745 cpu_vaddr + cpu_offset,
750 cpu_offset += this_length;
751 gpu_offset += this_length;
752 length -= this_length;
759 * Pins the specified object's pages and synchronizes the object with
760 * GPU accesses. Sets needs_clflush to non-zero if the caller should
761 * flush the object from the CPU cache.
763 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
764 unsigned int *needs_clflush)
768 lockdep_assert_held(&obj->base.dev->struct_mutex);
771 if (!i915_gem_object_has_struct_page(obj))
774 ret = i915_gem_object_wait(obj,
775 I915_WAIT_INTERRUPTIBLE |
777 MAX_SCHEDULE_TIMEOUT,
782 ret = i915_gem_object_pin_pages(obj);
786 i915_gem_object_flush_gtt_write_domain(obj);
788 /* If we're not in the cpu read domain, set ourself into the gtt
789 * read domain and manually flush cachelines (if required). This
790 * optimizes for the case when the gpu will dirty the data
791 * anyway again before the next pread happens.
793 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
794 *needs_clflush = !i915_gem_object_is_coherent(obj);
796 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
797 ret = i915_gem_object_set_to_cpu_domain(obj, false);
804 /* return with the pages pinned */
808 i915_gem_object_unpin_pages(obj);
812 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
813 unsigned int *needs_clflush)
817 lockdep_assert_held(&obj->base.dev->struct_mutex);
820 if (!i915_gem_object_has_struct_page(obj))
823 ret = i915_gem_object_wait(obj,
824 I915_WAIT_INTERRUPTIBLE |
827 MAX_SCHEDULE_TIMEOUT,
832 ret = i915_gem_object_pin_pages(obj);
836 i915_gem_object_flush_gtt_write_domain(obj);
838 /* If we're not in the cpu write domain, set ourself into the
839 * gtt write domain and manually flush cachelines (as required).
840 * This optimizes for the case when the gpu will use the data
841 * right away and we therefore have to clflush anyway.
843 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
844 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
846 /* Same trick applies to invalidate partially written cachelines read
849 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
850 *needs_clflush |= !i915_gem_object_is_coherent(obj);
852 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
853 ret = i915_gem_object_set_to_cpu_domain(obj, true);
860 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
861 obj->cache_dirty = true;
863 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
864 obj->mm.dirty = true;
865 /* return with the pages pinned */
869 i915_gem_object_unpin_pages(obj);
874 shmem_clflush_swizzled_range(char *addr, unsigned long length,
877 if (unlikely(swizzled)) {
878 unsigned long start = (unsigned long) addr;
879 unsigned long end = (unsigned long) addr + length;
881 /* For swizzling simply ensure that we always flush both
882 * channels. Lame, but simple and it works. Swizzled
883 * pwrite/pread is far from a hotpath - current userspace
884 * doesn't use it at all. */
885 start = round_down(start, 128);
886 end = round_up(end, 128);
888 drm_clflush_virt_range((void *)start, end - start);
890 drm_clflush_virt_range(addr, length);
895 /* Only difference to the fast-path function is that this can handle bit17
896 * and uses non-atomic copy and kmap functions. */
898 shmem_pread_slow(struct page *page, int offset, int length,
899 char __user *user_data,
900 bool page_do_bit17_swizzling, bool needs_clflush)
907 shmem_clflush_swizzled_range(vaddr + offset, length,
908 page_do_bit17_swizzling);
910 if (page_do_bit17_swizzling)
911 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
913 ret = __copy_to_user(user_data, vaddr + offset, length);
916 return ret ? - EFAULT : 0;
920 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
921 bool page_do_bit17_swizzling, bool needs_clflush)
926 if (!page_do_bit17_swizzling) {
927 char *vaddr = kmap_atomic(page);
930 drm_clflush_virt_range(vaddr + offset, length);
931 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
932 kunmap_atomic(vaddr);
937 return shmem_pread_slow(page, offset, length, user_data,
938 page_do_bit17_swizzling, needs_clflush);
942 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
943 struct drm_i915_gem_pread *args)
945 char __user *user_data;
947 unsigned int obj_do_bit17_swizzling;
948 unsigned int needs_clflush;
949 unsigned int idx, offset;
952 obj_do_bit17_swizzling = 0;
953 if (i915_gem_object_needs_bit17_swizzle(obj))
954 obj_do_bit17_swizzling = BIT(17);
956 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
960 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
961 mutex_unlock(&obj->base.dev->struct_mutex);
966 user_data = u64_to_user_ptr(args->data_ptr);
967 offset = offset_in_page(args->offset);
968 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
969 struct page *page = i915_gem_object_get_page(obj, idx);
973 if (offset + length > PAGE_SIZE)
974 length = PAGE_SIZE - offset;
976 ret = shmem_pread(page, offset, length, user_data,
977 page_to_phys(page) & obj_do_bit17_swizzling,
987 i915_gem_obj_finish_shmem_access(obj);
992 gtt_user_read(struct io_mapping *mapping,
993 loff_t base, int offset,
994 char __user *user_data, int length)
997 unsigned long unwritten;
999 /* We can use the cpu mem copy function because this is X86. */
1000 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1001 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1002 io_mapping_unmap_atomic(vaddr);
1004 vaddr = (void __force *)
1005 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1006 unwritten = copy_to_user(user_data, vaddr + offset, length);
1007 io_mapping_unmap(vaddr);
1013 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1014 const struct drm_i915_gem_pread *args)
1016 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1017 struct i915_ggtt *ggtt = &i915->ggtt;
1018 struct drm_mm_node node;
1019 struct i915_vma *vma;
1020 void __user *user_data;
1024 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1028 intel_runtime_pm_get(i915);
1029 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1030 PIN_MAPPABLE | PIN_NONBLOCK);
1032 node.start = i915_ggtt_offset(vma);
1033 node.allocated = false;
1034 ret = i915_vma_put_fence(vma);
1036 i915_vma_unpin(vma);
1041 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1044 GEM_BUG_ON(!node.allocated);
1047 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1051 mutex_unlock(&i915->drm.struct_mutex);
1053 user_data = u64_to_user_ptr(args->data_ptr);
1054 remain = args->size;
1055 offset = args->offset;
1057 while (remain > 0) {
1058 /* Operation in this page
1060 * page_base = page offset within aperture
1061 * page_offset = offset within page
1062 * page_length = bytes to copy for this page
1064 u32 page_base = node.start;
1065 unsigned page_offset = offset_in_page(offset);
1066 unsigned page_length = PAGE_SIZE - page_offset;
1067 page_length = remain < page_length ? remain : page_length;
1068 if (node.allocated) {
1070 ggtt->base.insert_page(&ggtt->base,
1071 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1072 node.start, I915_CACHE_NONE, 0);
1075 page_base += offset & PAGE_MASK;
1078 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1079 user_data, page_length)) {
1084 remain -= page_length;
1085 user_data += page_length;
1086 offset += page_length;
1089 mutex_lock(&i915->drm.struct_mutex);
1091 if (node.allocated) {
1093 ggtt->base.clear_range(&ggtt->base,
1094 node.start, node.size);
1095 remove_mappable_node(&node);
1097 i915_vma_unpin(vma);
1100 intel_runtime_pm_put(i915);
1101 mutex_unlock(&i915->drm.struct_mutex);
1107 * Reads data from the object referenced by handle.
1108 * @dev: drm device pointer
1109 * @data: ioctl data blob
1110 * @file: drm file pointer
1112 * On error, the contents of *data are undefined.
1115 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1116 struct drm_file *file)
1118 struct drm_i915_gem_pread *args = data;
1119 struct drm_i915_gem_object *obj;
1122 if (args->size == 0)
1125 if (!access_ok(VERIFY_WRITE,
1126 u64_to_user_ptr(args->data_ptr),
1130 obj = i915_gem_object_lookup(file, args->handle);
1134 /* Bounds check source. */
1135 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1140 trace_i915_gem_object_pread(obj, args->offset, args->size);
1142 ret = i915_gem_object_wait(obj,
1143 I915_WAIT_INTERRUPTIBLE,
1144 MAX_SCHEDULE_TIMEOUT,
1145 to_rps_client(file));
1149 ret = i915_gem_object_pin_pages(obj);
1153 ret = i915_gem_shmem_pread(obj, args);
1154 if (ret == -EFAULT || ret == -ENODEV)
1155 ret = i915_gem_gtt_pread(obj, args);
1157 i915_gem_object_unpin_pages(obj);
1159 i915_gem_object_put(obj);
1163 /* This is the fast write path which cannot handle
1164 * page faults in the source data
1168 ggtt_write(struct io_mapping *mapping,
1169 loff_t base, int offset,
1170 char __user *user_data, int length)
1173 unsigned long unwritten;
1175 /* We can use the cpu mem copy function because this is X86. */
1176 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1177 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1179 io_mapping_unmap_atomic(vaddr);
1181 vaddr = (void __force *)
1182 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1183 unwritten = copy_from_user(vaddr + offset, user_data, length);
1184 io_mapping_unmap(vaddr);
1191 * This is the fast pwrite path, where we copy the data directly from the
1192 * user into the GTT, uncached.
1193 * @obj: i915 GEM object
1194 * @args: pwrite arguments structure
1197 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1198 const struct drm_i915_gem_pwrite *args)
1200 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1201 struct i915_ggtt *ggtt = &i915->ggtt;
1202 struct drm_mm_node node;
1203 struct i915_vma *vma;
1205 void __user *user_data;
1208 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1212 intel_runtime_pm_get(i915);
1213 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1214 PIN_MAPPABLE | PIN_NONBLOCK);
1216 node.start = i915_ggtt_offset(vma);
1217 node.allocated = false;
1218 ret = i915_vma_put_fence(vma);
1220 i915_vma_unpin(vma);
1225 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1228 GEM_BUG_ON(!node.allocated);
1231 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1235 mutex_unlock(&i915->drm.struct_mutex);
1237 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1239 user_data = u64_to_user_ptr(args->data_ptr);
1240 offset = args->offset;
1241 remain = args->size;
1243 /* Operation in this page
1245 * page_base = page offset within aperture
1246 * page_offset = offset within page
1247 * page_length = bytes to copy for this page
1249 u32 page_base = node.start;
1250 unsigned int page_offset = offset_in_page(offset);
1251 unsigned int page_length = PAGE_SIZE - page_offset;
1252 page_length = remain < page_length ? remain : page_length;
1253 if (node.allocated) {
1254 wmb(); /* flush the write before we modify the GGTT */
1255 ggtt->base.insert_page(&ggtt->base,
1256 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1257 node.start, I915_CACHE_NONE, 0);
1258 wmb(); /* flush modifications to the GGTT (insert_page) */
1260 page_base += offset & PAGE_MASK;
1262 /* If we get a fault while copying data, then (presumably) our
1263 * source page isn't available. Return the error and we'll
1264 * retry in the slow path.
1265 * If the object is non-shmem backed, we retry again with the
1266 * path that handles page fault.
1268 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1269 user_data, page_length)) {
1274 remain -= page_length;
1275 user_data += page_length;
1276 offset += page_length;
1278 intel_fb_obj_flush(obj, ORIGIN_CPU);
1280 mutex_lock(&i915->drm.struct_mutex);
1282 if (node.allocated) {
1284 ggtt->base.clear_range(&ggtt->base,
1285 node.start, node.size);
1286 remove_mappable_node(&node);
1288 i915_vma_unpin(vma);
1291 intel_runtime_pm_put(i915);
1292 mutex_unlock(&i915->drm.struct_mutex);
1297 shmem_pwrite_slow(struct page *page, int offset, int length,
1298 char __user *user_data,
1299 bool page_do_bit17_swizzling,
1300 bool needs_clflush_before,
1301 bool needs_clflush_after)
1307 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1308 shmem_clflush_swizzled_range(vaddr + offset, length,
1309 page_do_bit17_swizzling);
1310 if (page_do_bit17_swizzling)
1311 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1314 ret = __copy_from_user(vaddr + offset, user_data, length);
1315 if (needs_clflush_after)
1316 shmem_clflush_swizzled_range(vaddr + offset, length,
1317 page_do_bit17_swizzling);
1320 return ret ? -EFAULT : 0;
1323 /* Per-page copy function for the shmem pwrite fastpath.
1324 * Flushes invalid cachelines before writing to the target if
1325 * needs_clflush_before is set and flushes out any written cachelines after
1326 * writing if needs_clflush is set.
1329 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1330 bool page_do_bit17_swizzling,
1331 bool needs_clflush_before,
1332 bool needs_clflush_after)
1337 if (!page_do_bit17_swizzling) {
1338 char *vaddr = kmap_atomic(page);
1340 if (needs_clflush_before)
1341 drm_clflush_virt_range(vaddr + offset, len);
1342 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1343 if (needs_clflush_after)
1344 drm_clflush_virt_range(vaddr + offset, len);
1346 kunmap_atomic(vaddr);
1351 return shmem_pwrite_slow(page, offset, len, user_data,
1352 page_do_bit17_swizzling,
1353 needs_clflush_before,
1354 needs_clflush_after);
1358 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1359 const struct drm_i915_gem_pwrite *args)
1361 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1362 void __user *user_data;
1364 unsigned int obj_do_bit17_swizzling;
1365 unsigned int partial_cacheline_write;
1366 unsigned int needs_clflush;
1367 unsigned int offset, idx;
1370 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1374 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1375 mutex_unlock(&i915->drm.struct_mutex);
1379 obj_do_bit17_swizzling = 0;
1380 if (i915_gem_object_needs_bit17_swizzle(obj))
1381 obj_do_bit17_swizzling = BIT(17);
1383 /* If we don't overwrite a cacheline completely we need to be
1384 * careful to have up-to-date data by first clflushing. Don't
1385 * overcomplicate things and flush the entire patch.
1387 partial_cacheline_write = 0;
1388 if (needs_clflush & CLFLUSH_BEFORE)
1389 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1391 user_data = u64_to_user_ptr(args->data_ptr);
1392 remain = args->size;
1393 offset = offset_in_page(args->offset);
1394 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1395 struct page *page = i915_gem_object_get_page(obj, idx);
1399 if (offset + length > PAGE_SIZE)
1400 length = PAGE_SIZE - offset;
1402 ret = shmem_pwrite(page, offset, length, user_data,
1403 page_to_phys(page) & obj_do_bit17_swizzling,
1404 (offset | length) & partial_cacheline_write,
1405 needs_clflush & CLFLUSH_AFTER);
1410 user_data += length;
1414 intel_fb_obj_flush(obj, ORIGIN_CPU);
1415 i915_gem_obj_finish_shmem_access(obj);
1420 * Writes data to the object referenced by handle.
1422 * @data: ioctl data blob
1425 * On error, the contents of the buffer that were to be modified are undefined.
1428 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *file)
1431 struct drm_i915_gem_pwrite *args = data;
1432 struct drm_i915_gem_object *obj;
1435 if (args->size == 0)
1438 if (!access_ok(VERIFY_READ,
1439 u64_to_user_ptr(args->data_ptr),
1443 obj = i915_gem_object_lookup(file, args->handle);
1447 /* Bounds check destination. */
1448 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1453 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1455 ret = i915_gem_object_wait(obj,
1456 I915_WAIT_INTERRUPTIBLE |
1458 MAX_SCHEDULE_TIMEOUT,
1459 to_rps_client(file));
1463 ret = i915_gem_object_pin_pages(obj);
1468 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1469 * it would end up going through the fenced access, and we'll get
1470 * different detiling behavior between reading and writing.
1471 * pread/pwrite currently are reading and writing from the CPU
1472 * perspective, requiring manual detiling by the client.
1474 if (!i915_gem_object_has_struct_page(obj) ||
1475 cpu_write_needs_clflush(obj))
1476 /* Note that the gtt paths might fail with non-page-backed user
1477 * pointers (e.g. gtt mappings when moving data between
1478 * textures). Fallback to the shmem path in that case.
1480 ret = i915_gem_gtt_pwrite_fast(obj, args);
1482 if (ret == -EFAULT || ret == -ENOSPC) {
1483 if (obj->phys_handle)
1484 ret = i915_gem_phys_pwrite(obj, args, file);
1486 ret = i915_gem_shmem_pwrite(obj, args);
1489 i915_gem_object_unpin_pages(obj);
1491 i915_gem_object_put(obj);
1495 static inline enum fb_op_origin
1496 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1498 return (domain == I915_GEM_DOMAIN_GTT ?
1499 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1502 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1504 struct drm_i915_private *i915;
1505 struct list_head *list;
1506 struct i915_vma *vma;
1508 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1509 if (!i915_vma_is_ggtt(vma))
1512 if (i915_vma_is_active(vma))
1515 if (!drm_mm_node_allocated(&vma->node))
1518 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1521 i915 = to_i915(obj->base.dev);
1522 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1523 list_move_tail(&obj->global_link, list);
1527 * Called when user space prepares to use an object with the CPU, either
1528 * through the mmap ioctl's mapping or a GTT mapping.
1530 * @data: ioctl data blob
1534 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1535 struct drm_file *file)
1537 struct drm_i915_gem_set_domain *args = data;
1538 struct drm_i915_gem_object *obj;
1539 uint32_t read_domains = args->read_domains;
1540 uint32_t write_domain = args->write_domain;
1543 /* Only handle setting domains to types used by the CPU. */
1544 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1547 /* Having something in the write domain implies it's in the read
1548 * domain, and only that read domain. Enforce that in the request.
1550 if (write_domain != 0 && read_domains != write_domain)
1553 obj = i915_gem_object_lookup(file, args->handle);
1557 /* Try to flush the object off the GPU without holding the lock.
1558 * We will repeat the flush holding the lock in the normal manner
1559 * to catch cases where we are gazumped.
1561 err = i915_gem_object_wait(obj,
1562 I915_WAIT_INTERRUPTIBLE |
1563 (write_domain ? I915_WAIT_ALL : 0),
1564 MAX_SCHEDULE_TIMEOUT,
1565 to_rps_client(file));
1569 /* Flush and acquire obj->pages so that we are coherent through
1570 * direct access in memory with previous cached writes through
1571 * shmemfs and that our cache domain tracking remains valid.
1572 * For example, if the obj->filp was moved to swap without us
1573 * being notified and releasing the pages, we would mistakenly
1574 * continue to assume that the obj remained out of the CPU cached
1577 err = i915_gem_object_pin_pages(obj);
1581 err = i915_mutex_lock_interruptible(dev);
1585 if (read_domains & I915_GEM_DOMAIN_GTT)
1586 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1588 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1590 /* And bump the LRU for this access */
1591 i915_gem_object_bump_inactive_ggtt(obj);
1593 mutex_unlock(&dev->struct_mutex);
1595 if (write_domain != 0)
1596 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1599 i915_gem_object_unpin_pages(obj);
1601 i915_gem_object_put(obj);
1606 * Called when user space has done writes to this buffer
1608 * @data: ioctl data blob
1612 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1613 struct drm_file *file)
1615 struct drm_i915_gem_sw_finish *args = data;
1616 struct drm_i915_gem_object *obj;
1618 obj = i915_gem_object_lookup(file, args->handle);
1622 /* Pinned buffers may be scanout, so flush the cache */
1623 i915_gem_object_flush_if_display(obj);
1624 i915_gem_object_put(obj);
1630 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1633 * @data: ioctl data blob
1636 * While the mapping holds a reference on the contents of the object, it doesn't
1637 * imply a ref on the object itself.
1641 * DRM driver writers who look a this function as an example for how to do GEM
1642 * mmap support, please don't implement mmap support like here. The modern way
1643 * to implement DRM mmap support is with an mmap offset ioctl (like
1644 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1645 * That way debug tooling like valgrind will understand what's going on, hiding
1646 * the mmap call in a driver private ioctl will break that. The i915 driver only
1647 * does cpu mmaps this way because we didn't know better.
1650 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1651 struct drm_file *file)
1653 struct drm_i915_gem_mmap *args = data;
1654 struct drm_i915_gem_object *obj;
1657 if (args->flags & ~(I915_MMAP_WC))
1660 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1663 obj = i915_gem_object_lookup(file, args->handle);
1667 /* prime objects have no backing filp to GEM mmap
1670 if (!obj->base.filp) {
1671 i915_gem_object_put(obj);
1675 addr = vm_mmap(obj->base.filp, 0, args->size,
1676 PROT_READ | PROT_WRITE, MAP_SHARED,
1678 if (args->flags & I915_MMAP_WC) {
1679 struct mm_struct *mm = current->mm;
1680 struct vm_area_struct *vma;
1682 if (down_write_killable(&mm->mmap_sem)) {
1683 i915_gem_object_put(obj);
1686 vma = find_vma(mm, addr);
1689 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1692 up_write(&mm->mmap_sem);
1694 /* This may race, but that's ok, it only gets set */
1695 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1697 i915_gem_object_put(obj);
1698 if (IS_ERR((void *)addr))
1701 args->addr_ptr = (uint64_t) addr;
1706 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1708 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1712 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1714 * A history of the GTT mmap interface:
1716 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1717 * aligned and suitable for fencing, and still fit into the available
1718 * mappable space left by the pinned display objects. A classic problem
1719 * we called the page-fault-of-doom where we would ping-pong between
1720 * two objects that could not fit inside the GTT and so the memcpy
1721 * would page one object in at the expense of the other between every
1724 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1725 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1726 * object is too large for the available space (or simply too large
1727 * for the mappable aperture!), a view is created instead and faulted
1728 * into userspace. (This view is aligned and sized appropriately for
1733 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1734 * hangs on some architectures, corruption on others. An attempt to service
1735 * a GTT page fault from a snoopable object will generate a SIGBUS.
1737 * * the object must be able to fit into RAM (physical memory, though no
1738 * limited to the mappable aperture).
1743 * * a new GTT page fault will synchronize rendering from the GPU and flush
1744 * all data to system memory. Subsequent access will not be synchronized.
1746 * * all mappings are revoked on runtime device suspend.
1748 * * there are only 8, 16 or 32 fence registers to share between all users
1749 * (older machines require fence register for display and blitter access
1750 * as well). Contention of the fence registers will cause the previous users
1751 * to be unmapped and any new access will generate new page faults.
1753 * * running out of memory while servicing a fault may generate a SIGBUS,
1754 * rather than the expected SIGSEGV.
1756 int i915_gem_mmap_gtt_version(void)
1761 static inline struct i915_ggtt_view
1762 compute_partial_view(struct drm_i915_gem_object *obj,
1763 pgoff_t page_offset,
1766 struct i915_ggtt_view view;
1768 if (i915_gem_object_is_tiled(obj))
1769 chunk = roundup(chunk, tile_row_pages(obj));
1771 view.type = I915_GGTT_VIEW_PARTIAL;
1772 view.partial.offset = rounddown(page_offset, chunk);
1774 min_t(unsigned int, chunk,
1775 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1777 /* If the partial covers the entire object, just create a normal VMA. */
1778 if (chunk >= obj->base.size >> PAGE_SHIFT)
1779 view.type = I915_GGTT_VIEW_NORMAL;
1785 * i915_gem_fault - fault a page into the GTT
1788 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1789 * from userspace. The fault handler takes care of binding the object to
1790 * the GTT (if needed), allocating and programming a fence register (again,
1791 * only if needed based on whether the old reg is still valid or the object
1792 * is tiled) and inserting a new PTE into the faulting process.
1794 * Note that the faulting process may involve evicting existing objects
1795 * from the GTT and/or fence registers to make room. So performance may
1796 * suffer if the GTT working set is large or there are few fence registers
1799 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1800 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1802 int i915_gem_fault(struct vm_fault *vmf)
1804 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1805 struct vm_area_struct *area = vmf->vma;
1806 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1807 struct drm_device *dev = obj->base.dev;
1808 struct drm_i915_private *dev_priv = to_i915(dev);
1809 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1810 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1811 struct i915_vma *vma;
1812 pgoff_t page_offset;
1816 /* We don't use vmf->pgoff since that has the fake offset */
1817 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1819 trace_i915_gem_object_fault(obj, page_offset, true, write);
1821 /* Try to flush the object off the GPU first without holding the lock.
1822 * Upon acquiring the lock, we will perform our sanity checks and then
1823 * repeat the flush holding the lock in the normal manner to catch cases
1824 * where we are gazumped.
1826 ret = i915_gem_object_wait(obj,
1827 I915_WAIT_INTERRUPTIBLE,
1828 MAX_SCHEDULE_TIMEOUT,
1833 ret = i915_gem_object_pin_pages(obj);
1837 intel_runtime_pm_get(dev_priv);
1839 ret = i915_mutex_lock_interruptible(dev);
1843 /* Access to snoopable pages through the GTT is incoherent. */
1844 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1849 /* If the object is smaller than a couple of partial vma, it is
1850 * not worth only creating a single partial vma - we may as well
1851 * clear enough space for the full object.
1853 flags = PIN_MAPPABLE;
1854 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1855 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1857 /* Now pin it into the GTT as needed */
1858 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1860 /* Use a partial view if it is bigger than available space */
1861 struct i915_ggtt_view view =
1862 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1864 /* Userspace is now writing through an untracked VMA, abandon
1865 * all hope that the hardware is able to track future writes.
1867 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1869 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1876 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1880 ret = i915_vma_get_fence(vma);
1884 /* Mark as being mmapped into userspace for later revocation */
1885 assert_rpm_wakelock_held(dev_priv);
1886 if (list_empty(&obj->userfault_link))
1887 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1889 /* Finally, remap it using the new GTT offset */
1890 ret = remap_io_mapping(area,
1891 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1892 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1893 min_t(u64, vma->size, area->vm_end - area->vm_start),
1897 __i915_vma_unpin(vma);
1899 mutex_unlock(&dev->struct_mutex);
1901 intel_runtime_pm_put(dev_priv);
1902 i915_gem_object_unpin_pages(obj);
1907 * We eat errors when the gpu is terminally wedged to avoid
1908 * userspace unduly crashing (gl has no provisions for mmaps to
1909 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1910 * and so needs to be reported.
1912 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1913 ret = VM_FAULT_SIGBUS;
1918 * EAGAIN means the gpu is hung and we'll wait for the error
1919 * handler to reset everything when re-faulting in
1920 * i915_mutex_lock_interruptible.
1927 * EBUSY is ok: this just means that another thread
1928 * already did the job.
1930 ret = VM_FAULT_NOPAGE;
1937 ret = VM_FAULT_SIGBUS;
1940 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1941 ret = VM_FAULT_SIGBUS;
1948 * i915_gem_release_mmap - remove physical page mappings
1949 * @obj: obj in question
1951 * Preserve the reservation of the mmapping with the DRM core code, but
1952 * relinquish ownership of the pages back to the system.
1954 * It is vital that we remove the page mapping if we have mapped a tiled
1955 * object through the GTT and then lose the fence register due to
1956 * resource pressure. Similarly if the object has been moved out of the
1957 * aperture, than pages mapped into userspace must be revoked. Removing the
1958 * mapping will then trigger a page fault on the next user access, allowing
1959 * fixup by i915_gem_fault().
1962 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1964 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1966 /* Serialisation between user GTT access and our code depends upon
1967 * revoking the CPU's PTE whilst the mutex is held. The next user
1968 * pagefault then has to wait until we release the mutex.
1970 * Note that RPM complicates somewhat by adding an additional
1971 * requirement that operations to the GGTT be made holding the RPM
1974 lockdep_assert_held(&i915->drm.struct_mutex);
1975 intel_runtime_pm_get(i915);
1977 if (list_empty(&obj->userfault_link))
1980 list_del_init(&obj->userfault_link);
1981 drm_vma_node_unmap(&obj->base.vma_node,
1982 obj->base.dev->anon_inode->i_mapping);
1984 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1985 * memory transactions from userspace before we return. The TLB
1986 * flushing implied above by changing the PTE above *should* be
1987 * sufficient, an extra barrier here just provides us with a bit
1988 * of paranoid documentation about our requirement to serialise
1989 * memory writes before touching registers / GSM.
1994 intel_runtime_pm_put(i915);
1997 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1999 struct drm_i915_gem_object *obj, *on;
2003 * Only called during RPM suspend. All users of the userfault_list
2004 * must be holding an RPM wakeref to ensure that this can not
2005 * run concurrently with themselves (and use the struct_mutex for
2006 * protection between themselves).
2009 list_for_each_entry_safe(obj, on,
2010 &dev_priv->mm.userfault_list, userfault_link) {
2011 list_del_init(&obj->userfault_link);
2012 drm_vma_node_unmap(&obj->base.vma_node,
2013 obj->base.dev->anon_inode->i_mapping);
2016 /* The fence will be lost when the device powers down. If any were
2017 * in use by hardware (i.e. they are pinned), we should not be powering
2018 * down! All other fences will be reacquired by the user upon waking.
2020 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2021 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2023 /* Ideally we want to assert that the fence register is not
2024 * live at this point (i.e. that no piece of code will be
2025 * trying to write through fence + GTT, as that both violates
2026 * our tracking of activity and associated locking/barriers,
2027 * but also is illegal given that the hw is powered down).
2029 * Previously we used reg->pin_count as a "liveness" indicator.
2030 * That is not sufficient, and we need a more fine-grained
2031 * tool if we want to have a sanity check here.
2037 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2042 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2044 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2047 err = drm_gem_create_mmap_offset(&obj->base);
2051 /* Attempt to reap some mmap space from dead objects */
2053 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2057 i915_gem_drain_freed_objects(dev_priv);
2058 err = drm_gem_create_mmap_offset(&obj->base);
2062 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2067 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2069 drm_gem_free_mmap_offset(&obj->base);
2073 i915_gem_mmap_gtt(struct drm_file *file,
2074 struct drm_device *dev,
2078 struct drm_i915_gem_object *obj;
2081 obj = i915_gem_object_lookup(file, handle);
2085 ret = i915_gem_object_create_mmap_offset(obj);
2087 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2089 i915_gem_object_put(obj);
2094 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2096 * @data: GTT mapping ioctl data
2097 * @file: GEM object info
2099 * Simply returns the fake offset to userspace so it can mmap it.
2100 * The mmap call will end up in drm_gem_mmap(), which will set things
2101 * up so we can get faults in the handler above.
2103 * The fault handler will take care of binding the object into the GTT
2104 * (since it may have been evicted to make room for something), allocating
2105 * a fence register, and mapping the appropriate aperture address into
2109 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2110 struct drm_file *file)
2112 struct drm_i915_gem_mmap_gtt *args = data;
2114 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2117 /* Immediately discard the backing storage */
2119 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2121 i915_gem_object_free_mmap_offset(obj);
2123 if (obj->base.filp == NULL)
2126 /* Our goal here is to return as much of the memory as
2127 * is possible back to the system as we are called from OOM.
2128 * To do this we must instruct the shmfs to drop all of its
2129 * backing pages, *now*.
2131 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2132 obj->mm.madv = __I915_MADV_PURGED;
2135 /* Try to discard unwanted pages */
2136 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2138 struct address_space *mapping;
2140 lockdep_assert_held(&obj->mm.lock);
2141 GEM_BUG_ON(obj->mm.pages);
2143 switch (obj->mm.madv) {
2144 case I915_MADV_DONTNEED:
2145 i915_gem_object_truncate(obj);
2146 case __I915_MADV_PURGED:
2150 if (obj->base.filp == NULL)
2153 mapping = obj->base.filp->f_mapping,
2154 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2158 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2159 struct sg_table *pages)
2161 struct sgt_iter sgt_iter;
2164 __i915_gem_object_release_shmem(obj, pages, true);
2166 i915_gem_gtt_finish_pages(obj, pages);
2168 if (i915_gem_object_needs_bit17_swizzle(obj))
2169 i915_gem_object_save_bit_17_swizzle(obj, pages);
2171 for_each_sgt_page(page, sgt_iter, pages) {
2173 set_page_dirty(page);
2175 if (obj->mm.madv == I915_MADV_WILLNEED)
2176 mark_page_accessed(page);
2180 obj->mm.dirty = false;
2182 sg_free_table(pages);
2186 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2188 struct radix_tree_iter iter;
2191 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2192 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2195 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2196 enum i915_mm_subclass subclass)
2198 struct sg_table *pages;
2200 if (i915_gem_object_has_pinned_pages(obj))
2203 GEM_BUG_ON(obj->bind_count);
2204 if (!READ_ONCE(obj->mm.pages))
2207 /* May be called by shrinker from within get_pages() (on another bo) */
2208 mutex_lock_nested(&obj->mm.lock, subclass);
2209 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2212 /* ->put_pages might need to allocate memory for the bit17 swizzle
2213 * array, hence protect them from being reaped by removing them from gtt
2215 pages = fetch_and_zero(&obj->mm.pages);
2218 if (obj->mm.mapping) {
2221 ptr = ptr_mask_bits(obj->mm.mapping);
2222 if (is_vmalloc_addr(ptr))
2225 kunmap(kmap_to_page(ptr));
2227 obj->mm.mapping = NULL;
2230 __i915_gem_object_reset_page_iter(obj);
2232 obj->ops->put_pages(obj, pages);
2234 mutex_unlock(&obj->mm.lock);
2237 static bool i915_sg_trim(struct sg_table *orig_st)
2239 struct sg_table new_st;
2240 struct scatterlist *sg, *new_sg;
2243 if (orig_st->nents == orig_st->orig_nents)
2246 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2249 new_sg = new_st.sgl;
2250 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2251 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2252 /* called before being DMA mapped, no need to copy sg->dma_* */
2253 new_sg = sg_next(new_sg);
2255 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2257 sg_free_table(orig_st);
2263 static struct sg_table *
2264 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2266 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2267 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2269 struct address_space *mapping;
2270 struct sg_table *st;
2271 struct scatterlist *sg;
2272 struct sgt_iter sgt_iter;
2274 unsigned long last_pfn = 0; /* suppress gcc warning */
2275 unsigned int max_segment;
2279 /* Assert that the object is not currently in any GPU domain. As it
2280 * wasn't in the GTT, there shouldn't be any way it could have been in
2283 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2284 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2286 max_segment = swiotlb_max_segment();
2288 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2290 st = kmalloc(sizeof(*st), GFP_KERNEL);
2292 return ERR_PTR(-ENOMEM);
2295 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2297 return ERR_PTR(-ENOMEM);
2300 /* Get the list of pages out of our struct file. They'll be pinned
2301 * at this point until we release them.
2303 * Fail silently without starting the shrinker
2305 mapping = obj->base.filp->f_mapping;
2306 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2307 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2310 for (i = 0; i < page_count; i++) {
2311 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2313 i915_gem_shrink(dev_priv,
2316 I915_SHRINK_UNBOUND |
2317 I915_SHRINK_PURGEABLE);
2318 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2321 /* We've tried hard to allocate the memory by reaping
2322 * our own buffer, now let the real VM do its job and
2323 * go down in flames if truly OOM.
2325 page = shmem_read_mapping_page(mapping, i);
2327 ret = PTR_ERR(page);
2332 sg->length >= max_segment ||
2333 page_to_pfn(page) != last_pfn + 1) {
2337 sg_set_page(sg, page, PAGE_SIZE, 0);
2339 sg->length += PAGE_SIZE;
2341 last_pfn = page_to_pfn(page);
2343 /* Check that the i965g/gm workaround works. */
2344 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2346 if (sg) /* loop terminated early; short sg table */
2349 /* Trim unused sg entries to avoid wasting memory. */
2352 ret = i915_gem_gtt_prepare_pages(obj, st);
2354 /* DMA remapping failed? One possible cause is that
2355 * it could not reserve enough large entries, asking
2356 * for PAGE_SIZE chunks instead may be helpful.
2358 if (max_segment > PAGE_SIZE) {
2359 for_each_sgt_page(page, sgt_iter, st)
2363 max_segment = PAGE_SIZE;
2366 dev_warn(&dev_priv->drm.pdev->dev,
2367 "Failed to DMA remap %lu pages\n",
2373 if (i915_gem_object_needs_bit17_swizzle(obj))
2374 i915_gem_object_do_bit_17_swizzle(obj, st);
2381 for_each_sgt_page(page, sgt_iter, st)
2386 /* shmemfs first checks if there is enough memory to allocate the page
2387 * and reports ENOSPC should there be insufficient, along with the usual
2388 * ENOMEM for a genuine allocation failure.
2390 * We use ENOSPC in our driver to mean that we have run out of aperture
2391 * space and so want to translate the error from shmemfs back to our
2392 * usual understanding of ENOMEM.
2397 return ERR_PTR(ret);
2400 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2401 struct sg_table *pages)
2403 lockdep_assert_held(&obj->mm.lock);
2405 obj->mm.get_page.sg_pos = pages->sgl;
2406 obj->mm.get_page.sg_idx = 0;
2408 obj->mm.pages = pages;
2410 if (i915_gem_object_is_tiled(obj) &&
2411 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2412 GEM_BUG_ON(obj->mm.quirked);
2413 __i915_gem_object_pin_pages(obj);
2414 obj->mm.quirked = true;
2418 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2420 struct sg_table *pages;
2422 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2424 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2425 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2429 pages = obj->ops->get_pages(obj);
2430 if (unlikely(IS_ERR(pages)))
2431 return PTR_ERR(pages);
2433 __i915_gem_object_set_pages(obj, pages);
2437 /* Ensure that the associated pages are gathered from the backing storage
2438 * and pinned into our object. i915_gem_object_pin_pages() may be called
2439 * multiple times before they are released by a single call to
2440 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2441 * either as a result of memory pressure (reaping pages under the shrinker)
2442 * or as the object is itself released.
2444 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2448 err = mutex_lock_interruptible(&obj->mm.lock);
2452 if (unlikely(!obj->mm.pages)) {
2453 err = ____i915_gem_object_get_pages(obj);
2457 smp_mb__before_atomic();
2459 atomic_inc(&obj->mm.pages_pin_count);
2462 mutex_unlock(&obj->mm.lock);
2466 /* The 'mapping' part of i915_gem_object_pin_map() below */
2467 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2468 enum i915_map_type type)
2470 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2471 struct sg_table *sgt = obj->mm.pages;
2472 struct sgt_iter sgt_iter;
2474 struct page *stack_pages[32];
2475 struct page **pages = stack_pages;
2476 unsigned long i = 0;
2480 /* A single page can always be kmapped */
2481 if (n_pages == 1 && type == I915_MAP_WB)
2482 return kmap(sg_page(sgt->sgl));
2484 if (n_pages > ARRAY_SIZE(stack_pages)) {
2485 /* Too big for stack -- allocate temporary array instead */
2486 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2491 for_each_sgt_page(page, sgt_iter, sgt)
2494 /* Check that we have the expected number of pages */
2495 GEM_BUG_ON(i != n_pages);
2499 pgprot = PAGE_KERNEL;
2502 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2505 addr = vmap(pages, n_pages, 0, pgprot);
2507 if (pages != stack_pages)
2508 drm_free_large(pages);
2513 /* get, pin, and map the pages of the object into kernel space */
2514 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2515 enum i915_map_type type)
2517 enum i915_map_type has_type;
2522 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2524 ret = mutex_lock_interruptible(&obj->mm.lock);
2526 return ERR_PTR(ret);
2529 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2530 if (unlikely(!obj->mm.pages)) {
2531 ret = ____i915_gem_object_get_pages(obj);
2535 smp_mb__before_atomic();
2537 atomic_inc(&obj->mm.pages_pin_count);
2540 GEM_BUG_ON(!obj->mm.pages);
2542 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2543 if (ptr && has_type != type) {
2549 if (is_vmalloc_addr(ptr))
2552 kunmap(kmap_to_page(ptr));
2554 ptr = obj->mm.mapping = NULL;
2558 ptr = i915_gem_object_map(obj, type);
2564 obj->mm.mapping = ptr_pack_bits(ptr, type);
2568 mutex_unlock(&obj->mm.lock);
2572 atomic_dec(&obj->mm.pages_pin_count);
2578 static bool ban_context(const struct i915_gem_context *ctx)
2580 return (i915_gem_context_is_bannable(ctx) &&
2581 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2584 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2586 ctx->guilty_count++;
2587 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2588 if (ban_context(ctx))
2589 i915_gem_context_set_banned(ctx);
2591 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2592 ctx->name, ctx->ban_score,
2593 yesno(i915_gem_context_is_banned(ctx)));
2595 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2598 ctx->file_priv->context_bans++;
2599 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2600 ctx->name, ctx->file_priv->context_bans);
2603 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2605 ctx->active_count++;
2608 struct drm_i915_gem_request *
2609 i915_gem_find_active_request(struct intel_engine_cs *engine)
2611 struct drm_i915_gem_request *request, *active = NULL;
2612 unsigned long flags;
2614 /* We are called by the error capture and reset at a random
2615 * point in time. In particular, note that neither is crucially
2616 * ordered with an interrupt. After a hang, the GPU is dead and we
2617 * assume that no more writes can happen (we waited long enough for
2618 * all writes that were in transaction to be flushed) - adding an
2619 * extra delay for a recent interrupt is pointless. Hence, we do
2620 * not need an engine->irq_seqno_barrier() before the seqno reads.
2622 spin_lock_irqsave(&engine->timeline->lock, flags);
2623 list_for_each_entry(request, &engine->timeline->requests, link) {
2624 if (__i915_gem_request_completed(request,
2625 request->global_seqno))
2628 GEM_BUG_ON(request->engine != engine);
2629 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2630 &request->fence.flags));
2635 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2640 static bool engine_stalled(struct intel_engine_cs *engine)
2642 if (!engine->hangcheck.stalled)
2645 /* Check for possible seqno movement after hang declaration */
2646 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2647 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2654 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2656 struct intel_engine_cs *engine;
2657 enum intel_engine_id id;
2660 /* Ensure irq handler finishes, and not run again. */
2661 for_each_engine(engine, dev_priv, id) {
2662 struct drm_i915_gem_request *request;
2664 /* Prevent the signaler thread from updating the request
2665 * state (by calling dma_fence_signal) as we are processing
2666 * the reset. The write from the GPU of the seqno is
2667 * asynchronous and the signaler thread may see a different
2668 * value to us and declare the request complete, even though
2669 * the reset routine have picked that request as the active
2670 * (incomplete) request. This conflict is not handled
2673 kthread_park(engine->breadcrumbs.signaler);
2675 /* Prevent request submission to the hardware until we have
2676 * completed the reset in i915_gem_reset_finish(). If a request
2677 * is completed by one engine, it may then queue a request
2678 * to a second via its engine->irq_tasklet *just* as we are
2679 * calling engine->init_hw() and also writing the ELSP.
2680 * Turning off the engine->irq_tasklet until the reset is over
2681 * prevents the race.
2683 tasklet_kill(&engine->irq_tasklet);
2684 tasklet_disable(&engine->irq_tasklet);
2686 if (engine->irq_seqno_barrier)
2687 engine->irq_seqno_barrier(engine);
2689 if (engine_stalled(engine)) {
2690 request = i915_gem_find_active_request(engine);
2691 if (request && request->fence.error == -EIO)
2692 err = -EIO; /* Previous reset failed! */
2696 i915_gem_revoke_fences(dev_priv);
2701 static void skip_request(struct drm_i915_gem_request *request)
2703 void *vaddr = request->ring->vaddr;
2706 /* As this request likely depends on state from the lost
2707 * context, clear out all the user operations leaving the
2708 * breadcrumb at the end (so we get the fence notifications).
2710 head = request->head;
2711 if (request->postfix < head) {
2712 memset(vaddr + head, 0, request->ring->size - head);
2715 memset(vaddr + head, 0, request->postfix - head);
2717 dma_fence_set_error(&request->fence, -EIO);
2720 static void engine_skip_context(struct drm_i915_gem_request *request)
2722 struct intel_engine_cs *engine = request->engine;
2723 struct i915_gem_context *hung_ctx = request->ctx;
2724 struct intel_timeline *timeline;
2725 unsigned long flags;
2727 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2729 spin_lock_irqsave(&engine->timeline->lock, flags);
2730 spin_lock(&timeline->lock);
2732 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2733 if (request->ctx == hung_ctx)
2734 skip_request(request);
2736 list_for_each_entry(request, &timeline->requests, link)
2737 skip_request(request);
2739 spin_unlock(&timeline->lock);
2740 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2743 /* Returns true if the request was guilty of hang */
2744 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2746 /* Read once and return the resolution */
2747 const bool guilty = engine_stalled(request->engine);
2749 /* The guilty request will get skipped on a hung engine.
2751 * Users of client default contexts do not rely on logical
2752 * state preserved between batches so it is safe to execute
2753 * queued requests following the hang. Non default contexts
2754 * rely on preserved state, so skipping a batch loses the
2755 * evolution of the state and it needs to be considered corrupted.
2756 * Executing more queued batches on top of corrupted state is
2757 * risky. But we take the risk by trying to advance through
2758 * the queued requests in order to make the client behaviour
2759 * more predictable around resets, by not throwing away random
2760 * amount of batches it has prepared for execution. Sophisticated
2761 * clients can use gem_reset_stats_ioctl and dma fence status
2762 * (exported via sync_file info ioctl on explicit fences) to observe
2763 * when it loses the context state and should rebuild accordingly.
2765 * The context ban, and ultimately the client ban, mechanism are safety
2766 * valves if client submission ends up resulting in nothing more than
2771 i915_gem_context_mark_guilty(request->ctx);
2772 skip_request(request);
2774 i915_gem_context_mark_innocent(request->ctx);
2775 dma_fence_set_error(&request->fence, -EAGAIN);
2781 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2783 struct drm_i915_gem_request *request;
2785 request = i915_gem_find_active_request(engine);
2786 if (request && i915_gem_reset_request(request)) {
2787 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2788 engine->name, request->global_seqno);
2790 /* If this context is now banned, skip all pending requests. */
2791 if (i915_gem_context_is_banned(request->ctx))
2792 engine_skip_context(request);
2795 /* Setup the CS to resume from the breadcrumb of the hung request */
2796 engine->reset_hw(engine, request);
2799 void i915_gem_reset(struct drm_i915_private *dev_priv)
2801 struct intel_engine_cs *engine;
2802 enum intel_engine_id id;
2804 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2806 i915_gem_retire_requests(dev_priv);
2808 for_each_engine(engine, dev_priv, id) {
2809 struct i915_gem_context *ctx;
2811 i915_gem_reset_engine(engine);
2812 ctx = fetch_and_zero(&engine->last_retired_context);
2814 engine->context_unpin(engine, ctx);
2817 i915_gem_restore_fences(dev_priv);
2819 if (dev_priv->gt.awake) {
2820 intel_sanitize_gt_powersave(dev_priv);
2821 intel_enable_gt_powersave(dev_priv);
2822 if (INTEL_GEN(dev_priv) >= 6)
2823 gen6_rps_busy(dev_priv);
2827 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
2829 struct intel_engine_cs *engine;
2830 enum intel_engine_id id;
2832 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2834 for_each_engine(engine, dev_priv, id) {
2835 tasklet_enable(&engine->irq_tasklet);
2836 kthread_unpark(engine->breadcrumbs.signaler);
2840 static void nop_submit_request(struct drm_i915_gem_request *request)
2842 dma_fence_set_error(&request->fence, -EIO);
2843 i915_gem_request_submit(request);
2844 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2847 static void engine_set_wedged(struct intel_engine_cs *engine)
2849 struct drm_i915_gem_request *request;
2850 unsigned long flags;
2852 /* We need to be sure that no thread is running the old callback as
2853 * we install the nop handler (otherwise we would submit a request
2854 * to hardware that will never complete). In order to prevent this
2855 * race, we wait until the machine is idle before making the swap
2856 * (using stop_machine()).
2858 engine->submit_request = nop_submit_request;
2860 /* Mark all executing requests as skipped */
2861 spin_lock_irqsave(&engine->timeline->lock, flags);
2862 list_for_each_entry(request, &engine->timeline->requests, link)
2863 dma_fence_set_error(&request->fence, -EIO);
2864 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2866 /* Mark all pending requests as complete so that any concurrent
2867 * (lockless) lookup doesn't try and wait upon the request as we
2870 intel_engine_init_global_seqno(engine,
2871 intel_engine_last_submit(engine));
2874 * Clear the execlists queue up before freeing the requests, as those
2875 * are the ones that keep the context and ringbuffer backing objects
2879 if (i915.enable_execlists) {
2880 unsigned long flags;
2882 spin_lock_irqsave(&engine->timeline->lock, flags);
2884 i915_gem_request_put(engine->execlist_port[0].request);
2885 i915_gem_request_put(engine->execlist_port[1].request);
2886 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2887 engine->execlist_queue = RB_ROOT;
2888 engine->execlist_first = NULL;
2890 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2894 static int __i915_gem_set_wedged_BKL(void *data)
2896 struct drm_i915_private *i915 = data;
2897 struct intel_engine_cs *engine;
2898 enum intel_engine_id id;
2900 for_each_engine(engine, i915, id)
2901 engine_set_wedged(engine);
2906 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2908 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2909 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2911 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
2913 i915_gem_context_lost(dev_priv);
2914 i915_gem_retire_requests(dev_priv);
2916 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2920 i915_gem_retire_work_handler(struct work_struct *work)
2922 struct drm_i915_private *dev_priv =
2923 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2924 struct drm_device *dev = &dev_priv->drm;
2926 /* Come back later if the device is busy... */
2927 if (mutex_trylock(&dev->struct_mutex)) {
2928 i915_gem_retire_requests(dev_priv);
2929 mutex_unlock(&dev->struct_mutex);
2932 /* Keep the retire handler running until we are finally idle.
2933 * We do not need to do this test under locking as in the worst-case
2934 * we queue the retire worker once too often.
2936 if (READ_ONCE(dev_priv->gt.awake)) {
2937 i915_queue_hangcheck(dev_priv);
2938 queue_delayed_work(dev_priv->wq,
2939 &dev_priv->gt.retire_work,
2940 round_jiffies_up_relative(HZ));
2945 i915_gem_idle_work_handler(struct work_struct *work)
2947 struct drm_i915_private *dev_priv =
2948 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2949 struct drm_device *dev = &dev_priv->drm;
2950 struct intel_engine_cs *engine;
2951 enum intel_engine_id id;
2952 bool rearm_hangcheck;
2954 if (!READ_ONCE(dev_priv->gt.awake))
2958 * Wait for last execlists context complete, but bail out in case a
2959 * new request is submitted.
2961 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2962 intel_engines_are_idle(dev_priv),
2964 if (READ_ONCE(dev_priv->gt.active_requests))
2968 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2970 if (!mutex_trylock(&dev->struct_mutex)) {
2971 /* Currently busy, come back later */
2972 mod_delayed_work(dev_priv->wq,
2973 &dev_priv->gt.idle_work,
2974 msecs_to_jiffies(50));
2979 * New request retired after this work handler started, extend active
2980 * period until next instance of the work.
2982 if (work_pending(work))
2985 if (dev_priv->gt.active_requests)
2988 if (wait_for(intel_engines_are_idle(dev_priv), 10))
2989 DRM_ERROR("Timeout waiting for engines to idle\n");
2991 for_each_engine(engine, dev_priv, id) {
2992 intel_engine_disarm_breadcrumbs(engine);
2993 i915_gem_batch_pool_fini(&engine->batch_pool);
2996 GEM_BUG_ON(!dev_priv->gt.awake);
2997 dev_priv->gt.awake = false;
2998 rearm_hangcheck = false;
3000 if (INTEL_GEN(dev_priv) >= 6)
3001 gen6_rps_idle(dev_priv);
3002 intel_runtime_pm_put(dev_priv);
3004 mutex_unlock(&dev->struct_mutex);
3007 if (rearm_hangcheck) {
3008 GEM_BUG_ON(!dev_priv->gt.awake);
3009 i915_queue_hangcheck(dev_priv);
3013 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3015 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3016 struct drm_i915_file_private *fpriv = file->driver_priv;
3017 struct i915_vma *vma, *vn;
3019 mutex_lock(&obj->base.dev->struct_mutex);
3020 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3021 if (vma->vm->file == fpriv)
3022 i915_vma_close(vma);
3024 if (i915_gem_object_is_active(obj) &&
3025 !i915_gem_object_has_active_reference(obj)) {
3026 i915_gem_object_set_active_reference(obj);
3027 i915_gem_object_get(obj);
3029 mutex_unlock(&obj->base.dev->struct_mutex);
3032 static unsigned long to_wait_timeout(s64 timeout_ns)
3035 return MAX_SCHEDULE_TIMEOUT;
3037 if (timeout_ns == 0)
3040 return nsecs_to_jiffies_timeout(timeout_ns);
3044 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3045 * @dev: drm device pointer
3046 * @data: ioctl data blob
3047 * @file: drm file pointer
3049 * Returns 0 if successful, else an error is returned with the remaining time in
3050 * the timeout parameter.
3051 * -ETIME: object is still busy after timeout
3052 * -ERESTARTSYS: signal interrupted the wait
3053 * -ENONENT: object doesn't exist
3054 * Also possible, but rare:
3055 * -EAGAIN: GPU wedged
3057 * -ENODEV: Internal IRQ fail
3058 * -E?: The add request failed
3060 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3061 * non-zero timeout parameter the wait ioctl will wait for the given number of
3062 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3063 * without holding struct_mutex the object may become re-busied before this
3064 * function completes. A similar but shorter * race condition exists in the busy
3068 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3070 struct drm_i915_gem_wait *args = data;
3071 struct drm_i915_gem_object *obj;
3075 if (args->flags != 0)
3078 obj = i915_gem_object_lookup(file, args->bo_handle);
3082 start = ktime_get();
3084 ret = i915_gem_object_wait(obj,
3085 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3086 to_wait_timeout(args->timeout_ns),
3087 to_rps_client(file));
3089 if (args->timeout_ns > 0) {
3090 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3091 if (args->timeout_ns < 0)
3092 args->timeout_ns = 0;
3095 * Apparently ktime isn't accurate enough and occasionally has a
3096 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3097 * things up to make the test happy. We allow up to 1 jiffy.
3099 * This is a regression from the timespec->ktime conversion.
3101 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3102 args->timeout_ns = 0;
3105 i915_gem_object_put(obj);
3109 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3113 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3114 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3122 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3126 if (flags & I915_WAIT_LOCKED) {
3127 struct i915_gem_timeline *tl;
3129 lockdep_assert_held(&i915->drm.struct_mutex);
3131 list_for_each_entry(tl, &i915->gt.timelines, link) {
3132 ret = wait_for_timeline(tl, flags);
3137 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3145 /** Flushes the GTT write domain for the object if it's dirty. */
3147 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3149 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3151 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3154 /* No actual flushing is required for the GTT write domain. Writes
3155 * to it "immediately" go to main memory as far as we know, so there's
3156 * no chipset flush. It also doesn't land in render cache.
3158 * However, we do have to enforce the order so that all writes through
3159 * the GTT land before any writes to the device, such as updates to
3162 * We also have to wait a bit for the writes to land from the GTT.
3163 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3164 * timing. This issue has only been observed when switching quickly
3165 * between GTT writes and CPU reads from inside the kernel on recent hw,
3166 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3167 * system agents we cannot reproduce this behaviour).
3170 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3171 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3173 intel_fb_obj_flush(obj, write_origin(obj, I915_GEM_DOMAIN_GTT));
3175 obj->base.write_domain = 0;
3178 /** Flushes the CPU write domain for the object if it's dirty. */
3180 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3182 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3185 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3186 obj->base.write_domain = 0;
3189 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3191 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU && !obj->cache_dirty)
3194 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3195 obj->base.write_domain = 0;
3198 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3200 if (!READ_ONCE(obj->pin_display))
3203 mutex_lock(&obj->base.dev->struct_mutex);
3204 __i915_gem_object_flush_for_display(obj);
3205 mutex_unlock(&obj->base.dev->struct_mutex);
3209 * Moves a single object to the GTT read, and possibly write domain.
3210 * @obj: object to act on
3211 * @write: ask for write access or read only
3213 * This function returns when the move is complete, including waiting on
3217 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3221 lockdep_assert_held(&obj->base.dev->struct_mutex);
3223 ret = i915_gem_object_wait(obj,
3224 I915_WAIT_INTERRUPTIBLE |
3226 (write ? I915_WAIT_ALL : 0),
3227 MAX_SCHEDULE_TIMEOUT,
3232 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3235 /* Flush and acquire obj->pages so that we are coherent through
3236 * direct access in memory with previous cached writes through
3237 * shmemfs and that our cache domain tracking remains valid.
3238 * For example, if the obj->filp was moved to swap without us
3239 * being notified and releasing the pages, we would mistakenly
3240 * continue to assume that the obj remained out of the CPU cached
3243 ret = i915_gem_object_pin_pages(obj);
3247 i915_gem_object_flush_cpu_write_domain(obj);
3249 /* Serialise direct access to this object with the barriers for
3250 * coherent writes from the GPU, by effectively invalidating the
3251 * GTT domain upon first access.
3253 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3256 /* It should now be out of any other write domains, and we can update
3257 * the domain values for our changes.
3259 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3260 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3262 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3263 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3264 obj->mm.dirty = true;
3267 i915_gem_object_unpin_pages(obj);
3272 * Changes the cache-level of an object across all VMA.
3273 * @obj: object to act on
3274 * @cache_level: new cache level to set for the object
3276 * After this function returns, the object will be in the new cache-level
3277 * across all GTT and the contents of the backing storage will be coherent,
3278 * with respect to the new cache-level. In order to keep the backing storage
3279 * coherent for all users, we only allow a single cache level to be set
3280 * globally on the object and prevent it from being changed whilst the
3281 * hardware is reading from the object. That is if the object is currently
3282 * on the scanout it will be set to uncached (or equivalent display
3283 * cache coherency) and all non-MOCS GPU access will also be uncached so
3284 * that all direct access to the scanout remains coherent.
3286 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3287 enum i915_cache_level cache_level)
3289 struct i915_vma *vma;
3292 lockdep_assert_held(&obj->base.dev->struct_mutex);
3294 if (obj->cache_level == cache_level)
3297 /* Inspect the list of currently bound VMA and unbind any that would
3298 * be invalid given the new cache-level. This is principally to
3299 * catch the issue of the CS prefetch crossing page boundaries and
3300 * reading an invalid PTE on older architectures.
3303 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3304 if (!drm_mm_node_allocated(&vma->node))
3307 if (i915_vma_is_pinned(vma)) {
3308 DRM_DEBUG("can not change the cache level of pinned objects\n");
3312 if (i915_gem_valid_gtt_space(vma, cache_level))
3315 ret = i915_vma_unbind(vma);
3319 /* As unbinding may affect other elements in the
3320 * obj->vma_list (due to side-effects from retiring
3321 * an active vma), play safe and restart the iterator.
3326 /* We can reuse the existing drm_mm nodes but need to change the
3327 * cache-level on the PTE. We could simply unbind them all and
3328 * rebind with the correct cache-level on next use. However since
3329 * we already have a valid slot, dma mapping, pages etc, we may as
3330 * rewrite the PTE in the belief that doing so tramples upon less
3331 * state and so involves less work.
3333 if (obj->bind_count) {
3334 /* Before we change the PTE, the GPU must not be accessing it.
3335 * If we wait upon the object, we know that all the bound
3336 * VMA are no longer active.
3338 ret = i915_gem_object_wait(obj,
3339 I915_WAIT_INTERRUPTIBLE |
3342 MAX_SCHEDULE_TIMEOUT,
3347 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3348 cache_level != I915_CACHE_NONE) {
3349 /* Access to snoopable pages through the GTT is
3350 * incoherent and on some machines causes a hard
3351 * lockup. Relinquish the CPU mmaping to force
3352 * userspace to refault in the pages and we can
3353 * then double check if the GTT mapping is still
3354 * valid for that pointer access.
3356 i915_gem_release_mmap(obj);
3358 /* As we no longer need a fence for GTT access,
3359 * we can relinquish it now (and so prevent having
3360 * to steal a fence from someone else on the next
3361 * fence request). Note GPU activity would have
3362 * dropped the fence as all snoopable access is
3363 * supposed to be linear.
3365 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3366 ret = i915_vma_put_fence(vma);
3371 /* We either have incoherent backing store and
3372 * so no GTT access or the architecture is fully
3373 * coherent. In such cases, existing GTT mmaps
3374 * ignore the cache bit in the PTE and we can
3375 * rewrite it without confusing the GPU or having
3376 * to force userspace to fault back in its mmaps.
3380 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3381 if (!drm_mm_node_allocated(&vma->node))
3384 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3390 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3391 i915_gem_object_is_coherent(obj))
3392 obj->cache_dirty = true;
3394 list_for_each_entry(vma, &obj->vma_list, obj_link)
3395 vma->node.color = cache_level;
3396 obj->cache_level = cache_level;
3401 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3402 struct drm_file *file)
3404 struct drm_i915_gem_caching *args = data;
3405 struct drm_i915_gem_object *obj;
3409 obj = i915_gem_object_lookup_rcu(file, args->handle);
3415 switch (obj->cache_level) {
3416 case I915_CACHE_LLC:
3417 case I915_CACHE_L3_LLC:
3418 args->caching = I915_CACHING_CACHED;
3422 args->caching = I915_CACHING_DISPLAY;
3426 args->caching = I915_CACHING_NONE;
3434 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3435 struct drm_file *file)
3437 struct drm_i915_private *i915 = to_i915(dev);
3438 struct drm_i915_gem_caching *args = data;
3439 struct drm_i915_gem_object *obj;
3440 enum i915_cache_level level;
3443 switch (args->caching) {
3444 case I915_CACHING_NONE:
3445 level = I915_CACHE_NONE;
3447 case I915_CACHING_CACHED:
3449 * Due to a HW issue on BXT A stepping, GPU stores via a
3450 * snooped mapping may leave stale data in a corresponding CPU
3451 * cacheline, whereas normally such cachelines would get
3454 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3457 level = I915_CACHE_LLC;
3459 case I915_CACHING_DISPLAY:
3460 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3466 obj = i915_gem_object_lookup(file, args->handle);
3470 if (obj->cache_level == level)
3473 ret = i915_gem_object_wait(obj,
3474 I915_WAIT_INTERRUPTIBLE,
3475 MAX_SCHEDULE_TIMEOUT,
3476 to_rps_client(file));
3480 ret = i915_mutex_lock_interruptible(dev);
3484 ret = i915_gem_object_set_cache_level(obj, level);
3485 mutex_unlock(&dev->struct_mutex);
3488 i915_gem_object_put(obj);
3493 * Prepare buffer for display plane (scanout, cursors, etc).
3494 * Can be called from an uninterruptible phase (modesetting) and allows
3495 * any flushes to be pipelined (for pageflips).
3498 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3500 const struct i915_ggtt_view *view)
3502 struct i915_vma *vma;
3505 lockdep_assert_held(&obj->base.dev->struct_mutex);
3507 /* Mark the pin_display early so that we account for the
3508 * display coherency whilst setting up the cache domains.
3512 /* The display engine is not coherent with the LLC cache on gen6. As
3513 * a result, we make sure that the pinning that is about to occur is
3514 * done with uncached PTEs. This is lowest common denominator for all
3517 * However for gen6+, we could do better by using the GFDT bit instead
3518 * of uncaching, which would allow us to flush all the LLC-cached data
3519 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3521 ret = i915_gem_object_set_cache_level(obj,
3522 HAS_WT(to_i915(obj->base.dev)) ?
3523 I915_CACHE_WT : I915_CACHE_NONE);
3526 goto err_unpin_display;
3529 /* As the user may map the buffer once pinned in the display plane
3530 * (e.g. libkms for the bootup splash), we have to ensure that we
3531 * always use map_and_fenceable for all scanout buffers. However,
3532 * it may simply be too big to fit into mappable, in which case
3533 * put it anyway and hope that userspace can cope (but always first
3534 * try to preserve the existing ABI).
3536 vma = ERR_PTR(-ENOSPC);
3537 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3538 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3539 PIN_MAPPABLE | PIN_NONBLOCK);
3541 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3544 /* Valleyview is definitely limited to scanning out the first
3545 * 512MiB. Lets presume this behaviour was inherited from the
3546 * g4x display engine and that all earlier gen are similarly
3547 * limited. Testing suggests that it is a little more
3548 * complicated than this. For example, Cherryview appears quite
3549 * happy to scanout from anywhere within its global aperture.
3552 if (HAS_GMCH_DISPLAY(i915))
3553 flags = PIN_MAPPABLE;
3554 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3557 goto err_unpin_display;
3559 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3561 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3562 __i915_gem_object_flush_for_display(obj);
3563 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3565 /* It should now be out of any other write domains, and we can update
3566 * the domain values for our changes.
3568 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3578 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3580 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3582 if (WARN_ON(vma->obj->pin_display == 0))
3585 if (--vma->obj->pin_display == 0)
3586 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3588 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3589 i915_gem_object_bump_inactive_ggtt(vma->obj);
3591 i915_vma_unpin(vma);
3595 * Moves a single object to the CPU read, and possibly write domain.
3596 * @obj: object to act on
3597 * @write: requesting write or read-only access
3599 * This function returns when the move is complete, including waiting on
3603 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3607 lockdep_assert_held(&obj->base.dev->struct_mutex);
3609 ret = i915_gem_object_wait(obj,
3610 I915_WAIT_INTERRUPTIBLE |
3612 (write ? I915_WAIT_ALL : 0),
3613 MAX_SCHEDULE_TIMEOUT,
3618 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3621 i915_gem_object_flush_gtt_write_domain(obj);
3623 /* Flush the CPU cache if it's still invalid. */
3624 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3625 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3626 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3629 /* It should now be out of any other write domains, and we can update
3630 * the domain values for our changes.
3632 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3634 /* If we're writing through the CPU, then the GPU read domains will
3635 * need to be invalidated at next use.
3638 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3639 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3645 /* Throttle our rendering by waiting until the ring has completed our requests
3646 * emitted over 20 msec ago.
3648 * Note that if we were to use the current jiffies each time around the loop,
3649 * we wouldn't escape the function with any frames outstanding if the time to
3650 * render a frame was over 20ms.
3652 * This should get us reasonable parallelism between CPU and GPU but also
3653 * relatively low latency when blocking on a particular request to finish.
3656 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3658 struct drm_i915_private *dev_priv = to_i915(dev);
3659 struct drm_i915_file_private *file_priv = file->driver_priv;
3660 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3661 struct drm_i915_gem_request *request, *target = NULL;
3664 /* ABI: return -EIO if already wedged */
3665 if (i915_terminally_wedged(&dev_priv->gpu_error))
3668 spin_lock(&file_priv->mm.lock);
3669 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3670 if (time_after_eq(request->emitted_jiffies, recent_enough))
3674 list_del(&target->client_link);
3675 target->file_priv = NULL;
3681 i915_gem_request_get(target);
3682 spin_unlock(&file_priv->mm.lock);
3687 ret = i915_wait_request(target,
3688 I915_WAIT_INTERRUPTIBLE,
3689 MAX_SCHEDULE_TIMEOUT);
3690 i915_gem_request_put(target);
3692 return ret < 0 ? ret : 0;
3696 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3697 const struct i915_ggtt_view *view,
3702 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3703 struct i915_address_space *vm = &dev_priv->ggtt.base;
3704 struct i915_vma *vma;
3707 lockdep_assert_held(&obj->base.dev->struct_mutex);
3709 vma = i915_vma_instance(obj, vm, view);
3710 if (unlikely(IS_ERR(vma)))
3713 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3714 if (flags & PIN_NONBLOCK &&
3715 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3716 return ERR_PTR(-ENOSPC);
3718 if (flags & PIN_MAPPABLE) {
3719 /* If the required space is larger than the available
3720 * aperture, we will not able to find a slot for the
3721 * object and unbinding the object now will be in
3722 * vain. Worse, doing so may cause us to ping-pong
3723 * the object in and out of the Global GTT and
3724 * waste a lot of cycles under the mutex.
3726 if (vma->fence_size > dev_priv->ggtt.mappable_end)
3727 return ERR_PTR(-E2BIG);
3729 /* If NONBLOCK is set the caller is optimistically
3730 * trying to cache the full object within the mappable
3731 * aperture, and *must* have a fallback in place for
3732 * situations where we cannot bind the object. We
3733 * can be a little more lax here and use the fallback
3734 * more often to avoid costly migrations of ourselves
3735 * and other objects within the aperture.
3737 * Half-the-aperture is used as a simple heuristic.
3738 * More interesting would to do search for a free
3739 * block prior to making the commitment to unbind.
3740 * That caters for the self-harm case, and with a
3741 * little more heuristics (e.g. NOFAULT, NOEVICT)
3742 * we could try to minimise harm to others.
3744 if (flags & PIN_NONBLOCK &&
3745 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
3746 return ERR_PTR(-ENOSPC);
3749 WARN(i915_vma_is_pinned(vma),
3750 "bo is already pinned in ggtt with incorrect alignment:"
3751 " offset=%08x, req.alignment=%llx,"
3752 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3753 i915_ggtt_offset(vma), alignment,
3754 !!(flags & PIN_MAPPABLE),
3755 i915_vma_is_map_and_fenceable(vma));
3756 ret = i915_vma_unbind(vma);
3758 return ERR_PTR(ret);
3761 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3763 return ERR_PTR(ret);
3768 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3770 /* Note that we could alias engines in the execbuf API, but
3771 * that would be very unwise as it prevents userspace from
3772 * fine control over engine selection. Ahem.
3774 * This should be something like EXEC_MAX_ENGINE instead of
3777 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3778 return 0x10000 << id;
3781 static __always_inline unsigned int __busy_write_id(unsigned int id)
3783 /* The uABI guarantees an active writer is also amongst the read
3784 * engines. This would be true if we accessed the activity tracking
3785 * under the lock, but as we perform the lookup of the object and
3786 * its activity locklessly we can not guarantee that the last_write
3787 * being active implies that we have set the same engine flag from
3788 * last_read - hence we always set both read and write busy for
3791 return id | __busy_read_flag(id);
3794 static __always_inline unsigned int
3795 __busy_set_if_active(const struct dma_fence *fence,
3796 unsigned int (*flag)(unsigned int id))
3798 struct drm_i915_gem_request *rq;
3800 /* We have to check the current hw status of the fence as the uABI
3801 * guarantees forward progress. We could rely on the idle worker
3802 * to eventually flush us, but to minimise latency just ask the
3805 * Note we only report on the status of native fences.
3807 if (!dma_fence_is_i915(fence))
3810 /* opencode to_request() in order to avoid const warnings */
3811 rq = container_of(fence, struct drm_i915_gem_request, fence);
3812 if (i915_gem_request_completed(rq))
3815 return flag(rq->engine->exec_id);
3818 static __always_inline unsigned int
3819 busy_check_reader(const struct dma_fence *fence)
3821 return __busy_set_if_active(fence, __busy_read_flag);
3824 static __always_inline unsigned int
3825 busy_check_writer(const struct dma_fence *fence)
3830 return __busy_set_if_active(fence, __busy_write_id);
3834 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3835 struct drm_file *file)
3837 struct drm_i915_gem_busy *args = data;
3838 struct drm_i915_gem_object *obj;
3839 struct reservation_object_list *list;
3845 obj = i915_gem_object_lookup_rcu(file, args->handle);
3849 /* A discrepancy here is that we do not report the status of
3850 * non-i915 fences, i.e. even though we may report the object as idle,
3851 * a call to set-domain may still stall waiting for foreign rendering.
3852 * This also means that wait-ioctl may report an object as busy,
3853 * where busy-ioctl considers it idle.
3855 * We trade the ability to warn of foreign fences to report on which
3856 * i915 engines are active for the object.
3858 * Alternatively, we can trade that extra information on read/write
3861 * !reservation_object_test_signaled_rcu(obj->resv, true);
3862 * to report the overall busyness. This is what the wait-ioctl does.
3866 seq = raw_read_seqcount(&obj->resv->seq);
3868 /* Translate the exclusive fence to the READ *and* WRITE engine */
3869 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3871 /* Translate shared fences to READ set of engines */
3872 list = rcu_dereference(obj->resv->fence);
3874 unsigned int shared_count = list->shared_count, i;
3876 for (i = 0; i < shared_count; ++i) {
3877 struct dma_fence *fence =
3878 rcu_dereference(list->shared[i]);
3880 args->busy |= busy_check_reader(fence);
3884 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3894 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3895 struct drm_file *file_priv)
3897 return i915_gem_ring_throttle(dev, file_priv);
3901 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3902 struct drm_file *file_priv)
3904 struct drm_i915_private *dev_priv = to_i915(dev);
3905 struct drm_i915_gem_madvise *args = data;
3906 struct drm_i915_gem_object *obj;
3909 switch (args->madv) {
3910 case I915_MADV_DONTNEED:
3911 case I915_MADV_WILLNEED:
3917 obj = i915_gem_object_lookup(file_priv, args->handle);
3921 err = mutex_lock_interruptible(&obj->mm.lock);
3925 if (obj->mm.pages &&
3926 i915_gem_object_is_tiled(obj) &&
3927 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3928 if (obj->mm.madv == I915_MADV_WILLNEED) {
3929 GEM_BUG_ON(!obj->mm.quirked);
3930 __i915_gem_object_unpin_pages(obj);
3931 obj->mm.quirked = false;
3933 if (args->madv == I915_MADV_WILLNEED) {
3934 GEM_BUG_ON(obj->mm.quirked);
3935 __i915_gem_object_pin_pages(obj);
3936 obj->mm.quirked = true;
3940 if (obj->mm.madv != __I915_MADV_PURGED)
3941 obj->mm.madv = args->madv;
3943 /* if the object is no longer attached, discard its backing storage */
3944 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3945 i915_gem_object_truncate(obj);
3947 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3948 mutex_unlock(&obj->mm.lock);
3951 i915_gem_object_put(obj);
3956 frontbuffer_retire(struct i915_gem_active *active,
3957 struct drm_i915_gem_request *request)
3959 struct drm_i915_gem_object *obj =
3960 container_of(active, typeof(*obj), frontbuffer_write);
3962 intel_fb_obj_flush(obj, ORIGIN_CS);
3965 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3966 const struct drm_i915_gem_object_ops *ops)
3968 mutex_init(&obj->mm.lock);
3970 INIT_LIST_HEAD(&obj->global_link);
3971 INIT_LIST_HEAD(&obj->userfault_link);
3972 INIT_LIST_HEAD(&obj->obj_exec_link);
3973 INIT_LIST_HEAD(&obj->vma_list);
3974 INIT_LIST_HEAD(&obj->batch_pool_link);
3978 reservation_object_init(&obj->__builtin_resv);
3979 obj->resv = &obj->__builtin_resv;
3981 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
3982 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
3984 obj->mm.madv = I915_MADV_WILLNEED;
3985 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
3986 mutex_init(&obj->mm.get_page.lock);
3988 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3991 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3992 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
3993 I915_GEM_OBJECT_IS_SHRINKABLE,
3994 .get_pages = i915_gem_object_get_pages_gtt,
3995 .put_pages = i915_gem_object_put_pages_gtt,
3998 struct drm_i915_gem_object *
3999 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4001 struct drm_i915_gem_object *obj;
4002 struct address_space *mapping;
4006 /* There is a prevalence of the assumption that we fit the object's
4007 * page count inside a 32bit _signed_ variable. Let's document this and
4008 * catch if we ever need to fix it. In the meantime, if you do spot
4009 * such a local variable, please consider fixing!
4011 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
4012 return ERR_PTR(-E2BIG);
4014 if (overflows_type(size, obj->base.size))
4015 return ERR_PTR(-E2BIG);
4017 obj = i915_gem_object_alloc(dev_priv);
4019 return ERR_PTR(-ENOMEM);
4021 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4025 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4026 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4027 /* 965gm cannot relocate objects above 4GiB. */
4028 mask &= ~__GFP_HIGHMEM;
4029 mask |= __GFP_DMA32;
4032 mapping = obj->base.filp->f_mapping;
4033 mapping_set_gfp_mask(mapping, mask);
4035 i915_gem_object_init(obj, &i915_gem_object_ops);
4037 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4038 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4040 if (HAS_LLC(dev_priv)) {
4041 /* On some devices, we can have the GPU use the LLC (the CPU
4042 * cache) for about a 10% performance improvement
4043 * compared to uncached. Graphics requests other than
4044 * display scanout are coherent with the CPU in
4045 * accessing this cache. This means in this mode we
4046 * don't need to clflush on the CPU side, and on the
4047 * GPU side we only need to flush internal caches to
4048 * get data visible to the CPU.
4050 * However, we maintain the display planes as UC, and so
4051 * need to rebind when first used as such.
4053 obj->cache_level = I915_CACHE_LLC;
4055 obj->cache_level = I915_CACHE_NONE;
4057 trace_i915_gem_object_create(obj);
4062 i915_gem_object_free(obj);
4063 return ERR_PTR(ret);
4066 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4068 /* If we are the last user of the backing storage (be it shmemfs
4069 * pages or stolen etc), we know that the pages are going to be
4070 * immediately released. In this case, we can then skip copying
4071 * back the contents from the GPU.
4074 if (obj->mm.madv != I915_MADV_WILLNEED)
4077 if (obj->base.filp == NULL)
4080 /* At first glance, this looks racy, but then again so would be
4081 * userspace racing mmap against close. However, the first external
4082 * reference to the filp can only be obtained through the
4083 * i915_gem_mmap_ioctl() which safeguards us against the user
4084 * acquiring such a reference whilst we are in the middle of
4085 * freeing the object.
4087 return atomic_long_read(&obj->base.filp->f_count) == 1;
4090 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4091 struct llist_node *freed)
4093 struct drm_i915_gem_object *obj, *on;
4095 mutex_lock(&i915->drm.struct_mutex);
4096 intel_runtime_pm_get(i915);
4097 llist_for_each_entry(obj, freed, freed) {
4098 struct i915_vma *vma, *vn;
4100 trace_i915_gem_object_destroy(obj);
4102 GEM_BUG_ON(i915_gem_object_is_active(obj));
4103 list_for_each_entry_safe(vma, vn,
4104 &obj->vma_list, obj_link) {
4105 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4106 GEM_BUG_ON(i915_vma_is_active(vma));
4107 vma->flags &= ~I915_VMA_PIN_MASK;
4108 i915_vma_close(vma);
4110 GEM_BUG_ON(!list_empty(&obj->vma_list));
4111 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4113 list_del(&obj->global_link);
4115 intel_runtime_pm_put(i915);
4116 mutex_unlock(&i915->drm.struct_mutex);
4118 llist_for_each_entry_safe(obj, on, freed, freed) {
4119 GEM_BUG_ON(obj->bind_count);
4120 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4122 if (obj->ops->release)
4123 obj->ops->release(obj);
4125 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4126 atomic_set(&obj->mm.pages_pin_count, 0);
4127 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4128 GEM_BUG_ON(obj->mm.pages);
4130 if (obj->base.import_attach)
4131 drm_prime_gem_destroy(&obj->base, NULL);
4133 reservation_object_fini(&obj->__builtin_resv);
4134 drm_gem_object_release(&obj->base);
4135 i915_gem_info_remove_obj(i915, obj->base.size);
4138 i915_gem_object_free(obj);
4142 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4144 struct llist_node *freed;
4146 freed = llist_del_all(&i915->mm.free_list);
4147 if (unlikely(freed))
4148 __i915_gem_free_objects(i915, freed);
4151 static void __i915_gem_free_work(struct work_struct *work)
4153 struct drm_i915_private *i915 =
4154 container_of(work, struct drm_i915_private, mm.free_work);
4155 struct llist_node *freed;
4157 /* All file-owned VMA should have been released by this point through
4158 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4159 * However, the object may also be bound into the global GTT (e.g.
4160 * older GPUs without per-process support, or for direct access through
4161 * the GTT either for the user or for scanout). Those VMA still need to
4165 while ((freed = llist_del_all(&i915->mm.free_list)))
4166 __i915_gem_free_objects(i915, freed);
4169 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4171 struct drm_i915_gem_object *obj =
4172 container_of(head, typeof(*obj), rcu);
4173 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4175 /* We can't simply use call_rcu() from i915_gem_free_object()
4176 * as we need to block whilst unbinding, and the call_rcu
4177 * task may be called from softirq context. So we take a
4178 * detour through a worker.
4180 if (llist_add(&obj->freed, &i915->mm.free_list))
4181 schedule_work(&i915->mm.free_work);
4184 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4186 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4188 if (obj->mm.quirked)
4189 __i915_gem_object_unpin_pages(obj);
4191 if (discard_backing_storage(obj))
4192 obj->mm.madv = I915_MADV_DONTNEED;
4194 /* Before we free the object, make sure any pure RCU-only
4195 * read-side critical sections are complete, e.g.
4196 * i915_gem_busy_ioctl(). For the corresponding synchronized
4197 * lookup see i915_gem_object_lookup_rcu().
4199 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4202 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4204 lockdep_assert_held(&obj->base.dev->struct_mutex);
4206 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4207 if (i915_gem_object_is_active(obj))
4208 i915_gem_object_set_active_reference(obj);
4210 i915_gem_object_put(obj);
4213 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4215 struct intel_engine_cs *engine;
4216 enum intel_engine_id id;
4218 for_each_engine(engine, dev_priv, id)
4219 GEM_BUG_ON(engine->last_retired_context &&
4220 !i915_gem_context_is_kernel(engine->last_retired_context));
4223 void i915_gem_sanitize(struct drm_i915_private *i915)
4226 * If we inherit context state from the BIOS or earlier occupants
4227 * of the GPU, the GPU may be in an inconsistent state when we
4228 * try to take over. The only way to remove the earlier state
4229 * is by resetting. However, resetting on earlier gen is tricky as
4230 * it may impact the display and we are uncertain about the stability
4231 * of the reset, so we only reset recent machines with logical
4232 * context support (that must be reset to remove any stray contexts).
4234 if (HAS_HW_CONTEXTS(i915)) {
4235 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4236 WARN_ON(reset && reset != -ENODEV);
4240 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4242 struct drm_device *dev = &dev_priv->drm;
4245 intel_runtime_pm_get(dev_priv);
4246 intel_suspend_gt_powersave(dev_priv);
4248 mutex_lock(&dev->struct_mutex);
4250 /* We have to flush all the executing contexts to main memory so
4251 * that they can saved in the hibernation image. To ensure the last
4252 * context image is coherent, we have to switch away from it. That
4253 * leaves the dev_priv->kernel_context still active when
4254 * we actually suspend, and its image in memory may not match the GPU
4255 * state. Fortunately, the kernel_context is disposable and we do
4256 * not rely on its state.
4258 ret = i915_gem_switch_to_kernel_context(dev_priv);
4262 ret = i915_gem_wait_for_idle(dev_priv,
4263 I915_WAIT_INTERRUPTIBLE |
4268 i915_gem_retire_requests(dev_priv);
4269 GEM_BUG_ON(dev_priv->gt.active_requests);
4271 assert_kernel_context_is_current(dev_priv);
4272 i915_gem_context_lost(dev_priv);
4273 mutex_unlock(&dev->struct_mutex);
4275 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4276 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4278 /* As the idle_work is rearming if it detects a race, play safe and
4279 * repeat the flush until it is definitely idle.
4281 while (flush_delayed_work(&dev_priv->gt.idle_work))
4284 i915_gem_drain_freed_objects(dev_priv);
4286 /* Assert that we sucessfully flushed all the work and
4287 * reset the GPU back to its idle, low power state.
4289 WARN_ON(dev_priv->gt.awake);
4290 WARN_ON(!intel_engines_are_idle(dev_priv));
4293 * Neither the BIOS, ourselves or any other kernel
4294 * expects the system to be in execlists mode on startup,
4295 * so we need to reset the GPU back to legacy mode. And the only
4296 * known way to disable logical contexts is through a GPU reset.
4298 * So in order to leave the system in a known default configuration,
4299 * always reset the GPU upon unload and suspend. Afterwards we then
4300 * clean up the GEM state tracking, flushing off the requests and
4301 * leaving the system in a known idle state.
4303 * Note that is of the upmost importance that the GPU is idle and
4304 * all stray writes are flushed *before* we dismantle the backing
4305 * storage for the pinned objects.
4307 * However, since we are uncertain that resetting the GPU on older
4308 * machines is a good idea, we don't - just in case it leaves the
4309 * machine in an unusable condition.
4311 i915_gem_sanitize(dev_priv);
4315 mutex_unlock(&dev->struct_mutex);
4317 intel_runtime_pm_put(dev_priv);
4321 void i915_gem_resume(struct drm_i915_private *dev_priv)
4323 struct drm_device *dev = &dev_priv->drm;
4325 WARN_ON(dev_priv->gt.awake);
4327 mutex_lock(&dev->struct_mutex);
4328 i915_gem_restore_gtt_mappings(dev_priv);
4330 /* As we didn't flush the kernel context before suspend, we cannot
4331 * guarantee that the context image is complete. So let's just reset
4332 * it and start again.
4334 dev_priv->gt.resume(dev_priv);
4336 mutex_unlock(&dev->struct_mutex);
4339 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4341 if (INTEL_GEN(dev_priv) < 5 ||
4342 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4345 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4346 DISP_TILE_SURFACE_SWIZZLING);
4348 if (IS_GEN5(dev_priv))
4351 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4352 if (IS_GEN6(dev_priv))
4353 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4354 else if (IS_GEN7(dev_priv))
4355 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4356 else if (IS_GEN8(dev_priv))
4357 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4362 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4364 I915_WRITE(RING_CTL(base), 0);
4365 I915_WRITE(RING_HEAD(base), 0);
4366 I915_WRITE(RING_TAIL(base), 0);
4367 I915_WRITE(RING_START(base), 0);
4370 static void init_unused_rings(struct drm_i915_private *dev_priv)
4372 if (IS_I830(dev_priv)) {
4373 init_unused_ring(dev_priv, PRB1_BASE);
4374 init_unused_ring(dev_priv, SRB0_BASE);
4375 init_unused_ring(dev_priv, SRB1_BASE);
4376 init_unused_ring(dev_priv, SRB2_BASE);
4377 init_unused_ring(dev_priv, SRB3_BASE);
4378 } else if (IS_GEN2(dev_priv)) {
4379 init_unused_ring(dev_priv, SRB0_BASE);
4380 init_unused_ring(dev_priv, SRB1_BASE);
4381 } else if (IS_GEN3(dev_priv)) {
4382 init_unused_ring(dev_priv, PRB1_BASE);
4383 init_unused_ring(dev_priv, PRB2_BASE);
4387 static int __i915_gem_restart_engines(void *data)
4389 struct drm_i915_private *i915 = data;
4390 struct intel_engine_cs *engine;
4391 enum intel_engine_id id;
4394 for_each_engine(engine, i915, id) {
4395 err = engine->init_hw(engine);
4403 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4407 dev_priv->gt.last_init_time = ktime_get();
4409 /* Double layer security blanket, see i915_gem_init() */
4410 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4412 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4413 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4415 if (IS_HASWELL(dev_priv))
4416 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4417 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4419 if (HAS_PCH_NOP(dev_priv)) {
4420 if (IS_IVYBRIDGE(dev_priv)) {
4421 u32 temp = I915_READ(GEN7_MSG_CTL);
4422 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4423 I915_WRITE(GEN7_MSG_CTL, temp);
4424 } else if (INTEL_GEN(dev_priv) >= 7) {
4425 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4426 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4427 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4431 i915_gem_init_swizzling(dev_priv);
4434 * At least 830 can leave some of the unused rings
4435 * "active" (ie. head != tail) after resume which
4436 * will prevent c3 entry. Makes sure all unused rings
4439 init_unused_rings(dev_priv);
4441 BUG_ON(!dev_priv->kernel_context);
4443 ret = i915_ppgtt_init_hw(dev_priv);
4445 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4449 /* Need to do basic initialisation of all rings first: */
4450 ret = __i915_gem_restart_engines(dev_priv);
4454 intel_mocs_init_l3cc_table(dev_priv);
4456 /* We can't enable contexts until all firmware is loaded */
4457 ret = intel_guc_setup(dev_priv);
4462 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4466 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4468 if (INTEL_INFO(dev_priv)->gen < 6)
4471 /* TODO: make semaphores and Execlists play nicely together */
4472 if (i915.enable_execlists)
4478 #ifdef CONFIG_INTEL_IOMMU
4479 /* Enable semaphores on SNB when IO remapping is off */
4480 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4487 int i915_gem_init(struct drm_i915_private *dev_priv)
4491 mutex_lock(&dev_priv->drm.struct_mutex);
4493 i915_gem_clflush_init(dev_priv);
4495 if (!i915.enable_execlists) {
4496 dev_priv->gt.resume = intel_legacy_submission_resume;
4497 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4499 dev_priv->gt.resume = intel_lr_context_resume;
4500 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4503 /* This is just a security blanket to placate dragons.
4504 * On some systems, we very sporadically observe that the first TLBs
4505 * used by the CS may be stale, despite us poking the TLB reset. If
4506 * we hold the forcewake during initialisation these problems
4507 * just magically go away.
4509 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4511 i915_gem_init_userptr(dev_priv);
4513 ret = i915_gem_init_ggtt(dev_priv);
4517 ret = i915_gem_context_init(dev_priv);
4521 ret = intel_engines_init(dev_priv);
4525 ret = i915_gem_init_hw(dev_priv);
4527 /* Allow engine initialisation to fail by marking the GPU as
4528 * wedged. But we only want to do this where the GPU is angry,
4529 * for all other failure, such as an allocation failure, bail.
4531 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4532 i915_gem_set_wedged(dev_priv);
4537 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4538 mutex_unlock(&dev_priv->drm.struct_mutex);
4543 void i915_gem_init_mmio(struct drm_i915_private *i915)
4545 i915_gem_sanitize(i915);
4549 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4551 struct intel_engine_cs *engine;
4552 enum intel_engine_id id;
4554 for_each_engine(engine, dev_priv, id)
4555 dev_priv->gt.cleanup_engine(engine);
4559 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4563 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4564 !IS_CHERRYVIEW(dev_priv))
4565 dev_priv->num_fence_regs = 32;
4566 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4567 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4568 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4569 dev_priv->num_fence_regs = 16;
4571 dev_priv->num_fence_regs = 8;
4573 if (intel_vgpu_active(dev_priv))
4574 dev_priv->num_fence_regs =
4575 I915_READ(vgtif_reg(avail_rs.fence_num));
4577 /* Initialize fence registers to zero */
4578 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4579 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4581 fence->i915 = dev_priv;
4583 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4585 i915_gem_restore_fences(dev_priv);
4587 i915_gem_detect_bit_6_swizzle(dev_priv);
4591 i915_gem_load_init(struct drm_i915_private *dev_priv)
4595 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4596 if (!dev_priv->objects)
4599 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4600 if (!dev_priv->vmas)
4603 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4604 SLAB_HWCACHE_ALIGN |
4605 SLAB_RECLAIM_ACCOUNT |
4606 SLAB_DESTROY_BY_RCU);
4607 if (!dev_priv->requests)
4610 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4611 SLAB_HWCACHE_ALIGN |
4612 SLAB_RECLAIM_ACCOUNT);
4613 if (!dev_priv->dependencies)
4616 mutex_lock(&dev_priv->drm.struct_mutex);
4617 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4618 err = i915_gem_timeline_init__global(dev_priv);
4619 mutex_unlock(&dev_priv->drm.struct_mutex);
4621 goto err_dependencies;
4623 INIT_LIST_HEAD(&dev_priv->context_list);
4624 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4625 init_llist_head(&dev_priv->mm.free_list);
4626 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4627 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4628 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4629 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4630 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4631 i915_gem_retire_work_handler);
4632 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4633 i915_gem_idle_work_handler);
4634 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4635 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4637 init_waitqueue_head(&dev_priv->pending_flip_queue);
4639 dev_priv->mm.interruptible = true;
4641 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4643 spin_lock_init(&dev_priv->fb_tracking.lock);
4648 kmem_cache_destroy(dev_priv->dependencies);
4650 kmem_cache_destroy(dev_priv->requests);
4652 kmem_cache_destroy(dev_priv->vmas);
4654 kmem_cache_destroy(dev_priv->objects);
4659 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4661 i915_gem_drain_freed_objects(dev_priv);
4662 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4663 WARN_ON(dev_priv->mm.object_count);
4665 mutex_lock(&dev_priv->drm.struct_mutex);
4666 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4667 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4668 mutex_unlock(&dev_priv->drm.struct_mutex);
4670 kmem_cache_destroy(dev_priv->dependencies);
4671 kmem_cache_destroy(dev_priv->requests);
4672 kmem_cache_destroy(dev_priv->vmas);
4673 kmem_cache_destroy(dev_priv->objects);
4675 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4679 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4681 mutex_lock(&dev_priv->drm.struct_mutex);
4682 i915_gem_shrink_all(dev_priv);
4683 mutex_unlock(&dev_priv->drm.struct_mutex);
4688 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4690 struct drm_i915_gem_object *obj;
4691 struct list_head *phases[] = {
4692 &dev_priv->mm.unbound_list,
4693 &dev_priv->mm.bound_list,
4697 /* Called just before we write the hibernation image.
4699 * We need to update the domain tracking to reflect that the CPU
4700 * will be accessing all the pages to create and restore from the
4701 * hibernation, and so upon restoration those pages will be in the
4704 * To make sure the hibernation image contains the latest state,
4705 * we update that state just before writing out the image.
4707 * To try and reduce the hibernation image, we manually shrink
4708 * the objects as well.
4711 mutex_lock(&dev_priv->drm.struct_mutex);
4712 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4714 for (p = phases; *p; p++) {
4715 list_for_each_entry(obj, *p, global_link) {
4716 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4717 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4720 mutex_unlock(&dev_priv->drm.struct_mutex);
4725 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4727 struct drm_i915_file_private *file_priv = file->driver_priv;
4728 struct drm_i915_gem_request *request;
4730 /* Clean up our request list when the client is going away, so that
4731 * later retire_requests won't dereference our soon-to-be-gone
4734 spin_lock(&file_priv->mm.lock);
4735 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
4736 request->file_priv = NULL;
4737 spin_unlock(&file_priv->mm.lock);
4739 if (!list_empty(&file_priv->rps.link)) {
4740 spin_lock(&to_i915(dev)->rps.client_lock);
4741 list_del(&file_priv->rps.link);
4742 spin_unlock(&to_i915(dev)->rps.client_lock);
4746 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4748 struct drm_i915_file_private *file_priv;
4753 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4757 file->driver_priv = file_priv;
4758 file_priv->dev_priv = to_i915(dev);
4759 file_priv->file = file;
4760 INIT_LIST_HEAD(&file_priv->rps.link);
4762 spin_lock_init(&file_priv->mm.lock);
4763 INIT_LIST_HEAD(&file_priv->mm.request_list);
4765 file_priv->bsd_engine = -1;
4767 ret = i915_gem_context_open(dev, file);
4775 * i915_gem_track_fb - update frontbuffer tracking
4776 * @old: current GEM buffer for the frontbuffer slots
4777 * @new: new GEM buffer for the frontbuffer slots
4778 * @frontbuffer_bits: bitmask of frontbuffer slots
4780 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4781 * from @old and setting them in @new. Both @old and @new can be NULL.
4783 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4784 struct drm_i915_gem_object *new,
4785 unsigned frontbuffer_bits)
4787 /* Control of individual bits within the mask are guarded by
4788 * the owning plane->mutex, i.e. we can never see concurrent
4789 * manipulation of individual bits. But since the bitfield as a whole
4790 * is updated using RMW, we need to use atomics in order to update
4793 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4794 sizeof(atomic_t) * BITS_PER_BYTE);
4797 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4798 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4802 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4803 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4807 /* Allocate a new GEM object and fill it with the supplied data */
4808 struct drm_i915_gem_object *
4809 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
4810 const void *data, size_t size)
4812 struct drm_i915_gem_object *obj;
4813 struct sg_table *sg;
4817 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
4821 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4825 ret = i915_gem_object_pin_pages(obj);
4830 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4831 obj->mm.dirty = true; /* Backing store is now out of date */
4832 i915_gem_object_unpin_pages(obj);
4834 if (WARN_ON(bytes != size)) {
4835 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4843 i915_gem_object_put(obj);
4844 return ERR_PTR(ret);
4847 struct scatterlist *
4848 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4850 unsigned int *offset)
4852 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4853 struct scatterlist *sg;
4854 unsigned int idx, count;
4857 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4858 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4860 /* As we iterate forward through the sg, we record each entry in a
4861 * radixtree for quick repeated (backwards) lookups. If we have seen
4862 * this index previously, we will have an entry for it.
4864 * Initial lookup is O(N), but this is amortized to O(1) for
4865 * sequential page access (where each new request is consecutive
4866 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4867 * i.e. O(1) with a large constant!
4869 if (n < READ_ONCE(iter->sg_idx))
4872 mutex_lock(&iter->lock);
4874 /* We prefer to reuse the last sg so that repeated lookup of this
4875 * (or the subsequent) sg are fast - comparing against the last
4876 * sg is faster than going through the radixtree.
4881 count = __sg_page_count(sg);
4883 while (idx + count <= n) {
4884 unsigned long exception, i;
4887 /* If we cannot allocate and insert this entry, or the
4888 * individual pages from this range, cancel updating the
4889 * sg_idx so that on this lookup we are forced to linearly
4890 * scan onwards, but on future lookups we will try the
4891 * insertion again (in which case we need to be careful of
4892 * the error return reporting that we have already inserted
4895 ret = radix_tree_insert(&iter->radix, idx, sg);
4896 if (ret && ret != -EEXIST)
4900 RADIX_TREE_EXCEPTIONAL_ENTRY |
4901 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4902 for (i = 1; i < count; i++) {
4903 ret = radix_tree_insert(&iter->radix, idx + i,
4905 if (ret && ret != -EEXIST)
4910 sg = ____sg_next(sg);
4911 count = __sg_page_count(sg);
4918 mutex_unlock(&iter->lock);
4920 if (unlikely(n < idx)) /* insertion completed by another thread */
4923 /* In case we failed to insert the entry into the radixtree, we need
4924 * to look beyond the current sg.
4926 while (idx + count <= n) {
4928 sg = ____sg_next(sg);
4929 count = __sg_page_count(sg);
4938 sg = radix_tree_lookup(&iter->radix, n);
4941 /* If this index is in the middle of multi-page sg entry,
4942 * the radixtree will contain an exceptional entry that points
4943 * to the start of that range. We will return the pointer to
4944 * the base page and the offset of this page within the
4948 if (unlikely(radix_tree_exception(sg))) {
4949 unsigned long base =
4950 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4952 sg = radix_tree_lookup(&iter->radix, base);
4964 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4966 struct scatterlist *sg;
4967 unsigned int offset;
4969 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4971 sg = i915_gem_object_get_sg(obj, n, &offset);
4972 return nth_page(sg_page(sg), offset);
4975 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4977 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
4982 page = i915_gem_object_get_page(obj, n);
4984 set_page_dirty(page);
4990 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
4993 struct scatterlist *sg;
4994 unsigned int offset;
4996 sg = i915_gem_object_get_sg(obj, n, &offset);
4997 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5000 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5001 #include "selftests/scatterlist.c"
5002 #include "selftests/mock_gem_device.c"
5003 #include "selftests/huge_gem_object.c"
5004 #include "selftests/i915_gem_object.c"
5005 #include "selftests/i915_gem_coherency.c"