2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915_prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915_prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
975 * __wait_seqno - wait until execution of seqno has finished
976 * @ring: the ring expected to report seqno
978 * @reset_counter: reset sequence associated with the given seqno
979 * @interruptible: do an interruptible wait (normally yes)
980 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
982 * Note: It is of utmost importance that the passed in seqno and reset_counter
983 * values have been read by the caller in an smp safe manner. Where read-side
984 * locks are involved, it is sufficient to read the reset_counter before
985 * unlocking the lock that protects the seqno. For lockless tricks, the
986 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
989 * Returns 0 if the seqno was found within the alloted time. Else returns the
990 * errno with remaining time filled in timeout argument.
992 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
993 unsigned reset_counter,
994 bool interruptible, struct timespec *timeout)
996 drm_i915_private_t *dev_priv = ring->dev->dev_private;
997 struct timespec before, now, wait_time={1,0};
998 unsigned long timeout_jiffies;
1000 bool wait_forever = true;
1003 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1005 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1008 trace_i915_gem_request_wait_begin(ring, seqno);
1010 if (timeout != NULL) {
1011 wait_time = *timeout;
1012 wait_forever = false;
1015 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1017 if (WARN_ON(!ring->irq_get(ring)))
1020 /* Record current time in case interrupted by signal, or wedged * */
1021 getrawmonotonic(&before);
1024 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1025 i915_reset_in_progress(&dev_priv->gpu_error) || \
1026 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1029 end = wait_event_interruptible_timeout(ring->irq_queue,
1033 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1036 /* We need to check whether any gpu reset happened in between
1037 * the caller grabbing the seqno and now ... */
1038 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1041 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1043 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1046 } while (end == 0 && wait_forever);
1048 getrawmonotonic(&now);
1050 ring->irq_put(ring);
1051 trace_i915_gem_request_wait_end(ring, seqno);
1055 struct timespec sleep_time = timespec_sub(now, before);
1056 *timeout = timespec_sub(*timeout, sleep_time);
1057 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1058 set_normalized_timespec(timeout, 0, 0);
1063 case -EAGAIN: /* Wedged */
1064 case -ERESTARTSYS: /* Signal */
1066 case 0: /* Timeout */
1068 default: /* Completed */
1069 WARN_ON(end < 0); /* We're not aware of other errors */
1075 * Waits for a sequence number to be signaled, and cleans up the
1076 * request and object lists appropriately for that event.
1079 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1081 struct drm_device *dev = ring->dev;
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 bool interruptible = dev_priv->mm.interruptible;
1086 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1089 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1093 ret = i915_gem_check_olr(ring, seqno);
1097 return __wait_seqno(ring, seqno,
1098 atomic_read(&dev_priv->gpu_error.reset_counter),
1099 interruptible, NULL);
1103 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1104 struct intel_ring_buffer *ring)
1106 i915_gem_retire_requests_ring(ring);
1108 /* Manually manage the write flush as we may have not yet
1109 * retired the buffer.
1111 * Note that the last_write_seqno is always the earlier of
1112 * the two (read/write) seqno, so if we haved successfully waited,
1113 * we know we have passed the last write.
1115 obj->last_write_seqno = 0;
1116 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1122 * Ensures that all rendering to the object has completed and the object is
1123 * safe to unbind from the GTT or access from the CPU.
1125 static __must_check int
1126 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1129 struct intel_ring_buffer *ring = obj->ring;
1133 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1137 ret = i915_wait_seqno(ring, seqno);
1141 return i915_gem_object_wait_rendering__tail(obj, ring);
1144 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1145 * as the object state may change during this call.
1147 static __must_check int
1148 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1151 struct drm_device *dev = obj->base.dev;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 struct intel_ring_buffer *ring = obj->ring;
1154 unsigned reset_counter;
1158 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1159 BUG_ON(!dev_priv->mm.interruptible);
1161 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1165 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1169 ret = i915_gem_check_olr(ring, seqno);
1173 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1174 mutex_unlock(&dev->struct_mutex);
1175 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1176 mutex_lock(&dev->struct_mutex);
1180 return i915_gem_object_wait_rendering__tail(obj, ring);
1184 * Called when user space prepares to use an object with the CPU, either
1185 * through the mmap ioctl's mapping or a GTT mapping.
1188 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1189 struct drm_file *file)
1191 struct drm_i915_gem_set_domain *args = data;
1192 struct drm_i915_gem_object *obj;
1193 uint32_t read_domains = args->read_domains;
1194 uint32_t write_domain = args->write_domain;
1197 /* Only handle setting domains to types used by the CPU. */
1198 if (write_domain & I915_GEM_GPU_DOMAINS)
1201 if (read_domains & I915_GEM_GPU_DOMAINS)
1204 /* Having something in the write domain implies it's in the read
1205 * domain, and only that read domain. Enforce that in the request.
1207 if (write_domain != 0 && read_domains != write_domain)
1210 ret = i915_mutex_lock_interruptible(dev);
1214 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1215 if (&obj->base == NULL) {
1220 /* Try to flush the object off the GPU without holding the lock.
1221 * We will repeat the flush holding the lock in the normal manner
1222 * to catch cases where we are gazumped.
1224 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1228 if (read_domains & I915_GEM_DOMAIN_GTT) {
1229 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1231 /* Silently promote "you're not bound, there was nothing to do"
1232 * to success, since the client was just asking us to
1233 * make sure everything was done.
1238 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1242 drm_gem_object_unreference(&obj->base);
1244 mutex_unlock(&dev->struct_mutex);
1249 * Called when user space has done writes to this buffer
1252 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1253 struct drm_file *file)
1255 struct drm_i915_gem_sw_finish *args = data;
1256 struct drm_i915_gem_object *obj;
1259 ret = i915_mutex_lock_interruptible(dev);
1263 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1264 if (&obj->base == NULL) {
1269 /* Pinned buffers may be scanout, so flush the cache */
1270 if (obj->pin_display)
1271 i915_gem_object_flush_cpu_write_domain(obj, true);
1273 drm_gem_object_unreference(&obj->base);
1275 mutex_unlock(&dev->struct_mutex);
1280 * Maps the contents of an object, returning the address it is mapped
1283 * While the mapping holds a reference on the contents of the object, it doesn't
1284 * imply a ref on the object itself.
1287 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1288 struct drm_file *file)
1290 struct drm_i915_gem_mmap *args = data;
1291 struct drm_gem_object *obj;
1294 obj = drm_gem_object_lookup(dev, file, args->handle);
1298 /* prime objects have no backing filp to GEM mmap
1302 drm_gem_object_unreference_unlocked(obj);
1306 addr = vm_mmap(obj->filp, 0, args->size,
1307 PROT_READ | PROT_WRITE, MAP_SHARED,
1309 drm_gem_object_unreference_unlocked(obj);
1310 if (IS_ERR((void *)addr))
1313 args->addr_ptr = (uint64_t) addr;
1319 * i915_gem_fault - fault a page into the GTT
1320 * vma: VMA in question
1323 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1324 * from userspace. The fault handler takes care of binding the object to
1325 * the GTT (if needed), allocating and programming a fence register (again,
1326 * only if needed based on whether the old reg is still valid or the object
1327 * is tiled) and inserting a new PTE into the faulting process.
1329 * Note that the faulting process may involve evicting existing objects
1330 * from the GTT and/or fence registers to make room. So performance may
1331 * suffer if the GTT working set is large or there are few fence registers
1334 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1336 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1337 struct drm_device *dev = obj->base.dev;
1338 drm_i915_private_t *dev_priv = dev->dev_private;
1339 pgoff_t page_offset;
1342 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1344 /* We don't use vmf->pgoff since that has the fake offset */
1345 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1348 ret = i915_mutex_lock_interruptible(dev);
1352 trace_i915_gem_object_fault(obj, page_offset, true, write);
1354 /* Access to snoopable pages through the GTT is incoherent. */
1355 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1360 /* Now bind it into the GTT if needed */
1361 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1365 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1369 ret = i915_gem_object_get_fence(obj);
1373 obj->fault_mappable = true;
1375 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1379 /* Finally, remap it using the new GTT offset */
1380 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1382 i915_gem_object_unpin(obj);
1384 mutex_unlock(&dev->struct_mutex);
1388 /* If this -EIO is due to a gpu hang, give the reset code a
1389 * chance to clean up the mess. Otherwise return the proper
1391 if (i915_terminally_wedged(&dev_priv->gpu_error))
1392 return VM_FAULT_SIGBUS;
1395 * EAGAIN means the gpu is hung and we'll wait for the error
1396 * handler to reset everything when re-faulting in
1397 * i915_mutex_lock_interruptible.
1404 * EBUSY is ok: this just means that another thread
1405 * already did the job.
1407 return VM_FAULT_NOPAGE;
1409 return VM_FAULT_OOM;
1411 return VM_FAULT_SIGBUS;
1413 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1414 return VM_FAULT_SIGBUS;
1419 * i915_gem_release_mmap - remove physical page mappings
1420 * @obj: obj in question
1422 * Preserve the reservation of the mmapping with the DRM core code, but
1423 * relinquish ownership of the pages back to the system.
1425 * It is vital that we remove the page mapping if we have mapped a tiled
1426 * object through the GTT and then lose the fence register due to
1427 * resource pressure. Similarly if the object has been moved out of the
1428 * aperture, than pages mapped into userspace must be revoked. Removing the
1429 * mapping will then trigger a page fault on the next user access, allowing
1430 * fixup by i915_gem_fault().
1433 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1435 if (!obj->fault_mappable)
1438 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1439 obj->fault_mappable = false;
1443 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1447 if (INTEL_INFO(dev)->gen >= 4 ||
1448 tiling_mode == I915_TILING_NONE)
1451 /* Previous chips need a power-of-two fence region when tiling */
1452 if (INTEL_INFO(dev)->gen == 3)
1453 gtt_size = 1024*1024;
1455 gtt_size = 512*1024;
1457 while (gtt_size < size)
1464 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1465 * @obj: object to check
1467 * Return the required GTT alignment for an object, taking into account
1468 * potential fence register mapping.
1471 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1472 int tiling_mode, bool fenced)
1475 * Minimum alignment is 4k (GTT page size), but might be greater
1476 * if a fence register is needed for the object.
1478 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1479 tiling_mode == I915_TILING_NONE)
1483 * Previous chips need to be aligned to the size of the smallest
1484 * fence register that can contain the object.
1486 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1489 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1491 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1494 if (drm_vma_node_has_offset(&obj->base.vma_node))
1497 dev_priv->mm.shrinker_no_lock_stealing = true;
1499 ret = drm_gem_create_mmap_offset(&obj->base);
1503 /* Badly fragmented mmap space? The only way we can recover
1504 * space is by destroying unwanted objects. We can't randomly release
1505 * mmap_offsets as userspace expects them to be persistent for the
1506 * lifetime of the objects. The closest we can is to release the
1507 * offsets on purgeable objects by truncating it and marking it purged,
1508 * which prevents userspace from ever using that object again.
1510 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1511 ret = drm_gem_create_mmap_offset(&obj->base);
1515 i915_gem_shrink_all(dev_priv);
1516 ret = drm_gem_create_mmap_offset(&obj->base);
1518 dev_priv->mm.shrinker_no_lock_stealing = false;
1523 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1525 drm_gem_free_mmap_offset(&obj->base);
1529 i915_gem_mmap_gtt(struct drm_file *file,
1530 struct drm_device *dev,
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_i915_gem_object *obj;
1538 ret = i915_mutex_lock_interruptible(dev);
1542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1543 if (&obj->base == NULL) {
1548 if (obj->base.size > dev_priv->gtt.mappable_end) {
1553 if (obj->madv != I915_MADV_WILLNEED) {
1554 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1559 ret = i915_gem_object_create_mmap_offset(obj);
1563 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1566 drm_gem_object_unreference(&obj->base);
1568 mutex_unlock(&dev->struct_mutex);
1573 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1575 * @data: GTT mapping ioctl data
1576 * @file: GEM object info
1578 * Simply returns the fake offset to userspace so it can mmap it.
1579 * The mmap call will end up in drm_gem_mmap(), which will set things
1580 * up so we can get faults in the handler above.
1582 * The fault handler will take care of binding the object into the GTT
1583 * (since it may have been evicted to make room for something), allocating
1584 * a fence register, and mapping the appropriate aperture address into
1588 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1589 struct drm_file *file)
1591 struct drm_i915_gem_mmap_gtt *args = data;
1593 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1596 /* Immediately discard the backing storage */
1598 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1600 struct inode *inode;
1602 i915_gem_object_free_mmap_offset(obj);
1604 if (obj->base.filp == NULL)
1607 /* Our goal here is to return as much of the memory as
1608 * is possible back to the system as we are called from OOM.
1609 * To do this we must instruct the shmfs to drop all of its
1610 * backing pages, *now*.
1612 inode = file_inode(obj->base.filp);
1613 shmem_truncate_range(inode, 0, (loff_t)-1);
1615 obj->madv = __I915_MADV_PURGED;
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1621 return obj->madv == I915_MADV_DONTNEED;
1625 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1627 struct sg_page_iter sg_iter;
1630 BUG_ON(obj->madv == __I915_MADV_PURGED);
1632 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1634 /* In the event of a disaster, abandon all caches and
1635 * hope for the best.
1637 WARN_ON(ret != -EIO);
1638 i915_gem_clflush_object(obj, true);
1639 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1642 if (i915_gem_object_needs_bit17_swizzle(obj))
1643 i915_gem_object_save_bit_17_swizzle(obj);
1645 if (obj->madv == I915_MADV_DONTNEED)
1648 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1649 struct page *page = sg_page_iter_page(&sg_iter);
1652 set_page_dirty(page);
1654 if (obj->madv == I915_MADV_WILLNEED)
1655 mark_page_accessed(page);
1657 page_cache_release(page);
1661 sg_free_table(obj->pages);
1666 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1668 const struct drm_i915_gem_object_ops *ops = obj->ops;
1670 if (obj->pages == NULL)
1673 if (obj->pages_pin_count)
1676 BUG_ON(i915_gem_obj_bound_any(obj));
1678 /* ->put_pages might need to allocate memory for the bit17 swizzle
1679 * array, hence protect them from being reaped by removing them from gtt
1681 list_del(&obj->global_list);
1683 ops->put_pages(obj);
1686 if (i915_gem_object_is_purgeable(obj))
1687 i915_gem_object_truncate(obj);
1693 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1694 bool purgeable_only)
1696 struct list_head still_bound_list;
1697 struct drm_i915_gem_object *obj, *next;
1700 list_for_each_entry_safe(obj, next,
1701 &dev_priv->mm.unbound_list,
1703 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1704 i915_gem_object_put_pages(obj) == 0) {
1705 count += obj->base.size >> PAGE_SHIFT;
1706 if (count >= target)
1712 * As we may completely rewrite the bound list whilst unbinding
1713 * (due to retiring requests) we have to strictly process only
1714 * one element of the list at the time, and recheck the list
1715 * on every iteration.
1717 INIT_LIST_HEAD(&still_bound_list);
1718 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1719 struct i915_vma *vma, *v;
1721 obj = list_first_entry(&dev_priv->mm.bound_list,
1722 typeof(*obj), global_list);
1723 list_move_tail(&obj->global_list, &still_bound_list);
1725 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1729 * Hold a reference whilst we unbind this object, as we may
1730 * end up waiting for and retiring requests. This might
1731 * release the final reference (held by the active list)
1732 * and result in the object being freed from under us.
1733 * in this object being freed.
1735 * Note 1: Shrinking the bound list is special since only active
1736 * (and hence bound objects) can contain such limbo objects, so
1737 * we don't need special tricks for shrinking the unbound list.
1738 * The only other place where we have to be careful with active
1739 * objects suddenly disappearing due to retiring requests is the
1742 * Note 2: Even though the bound list doesn't hold a reference
1743 * to the object we can safely grab one here: The final object
1744 * unreferencing and the bound_list are both protected by the
1745 * dev->struct_mutex and so we won't ever be able to observe an
1746 * object on the bound_list with a reference count equals 0.
1748 drm_gem_object_reference(&obj->base);
1750 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1751 if (i915_vma_unbind(vma))
1754 if (i915_gem_object_put_pages(obj) == 0)
1755 count += obj->base.size >> PAGE_SHIFT;
1757 drm_gem_object_unreference(&obj->base);
1759 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1765 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1767 return __i915_gem_shrink(dev_priv, target, true);
1771 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1773 struct drm_i915_gem_object *obj, *next;
1776 i915_gem_evict_everything(dev_priv->dev);
1778 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1780 if (obj->pages_pin_count == 0)
1781 freed += obj->base.size >> PAGE_SHIFT;
1782 i915_gem_object_put_pages(obj);
1788 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1790 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1792 struct address_space *mapping;
1793 struct sg_table *st;
1794 struct scatterlist *sg;
1795 struct sg_page_iter sg_iter;
1797 unsigned long last_pfn = 0; /* suppress gcc warning */
1800 /* Assert that the object is not currently in any GPU domain. As it
1801 * wasn't in the GTT, there shouldn't be any way it could have been in
1804 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1805 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1807 st = kmalloc(sizeof(*st), GFP_KERNEL);
1811 page_count = obj->base.size / PAGE_SIZE;
1812 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1817 /* Get the list of pages out of our struct file. They'll be pinned
1818 * at this point until we release them.
1820 * Fail silently without starting the shrinker
1822 mapping = file_inode(obj->base.filp)->i_mapping;
1823 gfp = mapping_gfp_mask(mapping);
1824 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1825 gfp &= ~(__GFP_IO | __GFP_WAIT);
1828 for (i = 0; i < page_count; i++) {
1829 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1831 i915_gem_purge(dev_priv, page_count);
1832 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1835 /* We've tried hard to allocate the memory by reaping
1836 * our own buffer, now let the real VM do its job and
1837 * go down in flames if truly OOM.
1839 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1840 gfp |= __GFP_IO | __GFP_WAIT;
1842 i915_gem_shrink_all(dev_priv);
1843 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1847 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1848 gfp &= ~(__GFP_IO | __GFP_WAIT);
1850 #ifdef CONFIG_SWIOTLB
1851 if (swiotlb_nr_tbl()) {
1853 sg_set_page(sg, page, PAGE_SIZE, 0);
1858 if (!i || page_to_pfn(page) != last_pfn + 1) {
1862 sg_set_page(sg, page, PAGE_SIZE, 0);
1864 sg->length += PAGE_SIZE;
1866 last_pfn = page_to_pfn(page);
1868 #ifdef CONFIG_SWIOTLB
1869 if (!swiotlb_nr_tbl())
1874 if (i915_gem_object_needs_bit17_swizzle(obj))
1875 i915_gem_object_do_bit_17_swizzle(obj);
1881 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1882 page_cache_release(sg_page_iter_page(&sg_iter));
1885 return PTR_ERR(page);
1888 /* Ensure that the associated pages are gathered from the backing storage
1889 * and pinned into our object. i915_gem_object_get_pages() may be called
1890 * multiple times before they are released by a single call to
1891 * i915_gem_object_put_pages() - once the pages are no longer referenced
1892 * either as a result of memory pressure (reaping pages under the shrinker)
1893 * or as the object is itself released.
1896 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1898 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1899 const struct drm_i915_gem_object_ops *ops = obj->ops;
1905 if (obj->madv != I915_MADV_WILLNEED) {
1906 DRM_ERROR("Attempting to obtain a purgeable object\n");
1910 BUG_ON(obj->pages_pin_count);
1912 ret = ops->get_pages(obj);
1916 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1921 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1922 struct intel_ring_buffer *ring)
1924 struct drm_device *dev = obj->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 u32 seqno = intel_ring_get_seqno(ring);
1928 BUG_ON(ring == NULL);
1929 if (obj->ring != ring && obj->last_write_seqno) {
1930 /* Keep the seqno relative to the current ring */
1931 obj->last_write_seqno = seqno;
1935 /* Add a reference if we're newly entering the active list. */
1937 drm_gem_object_reference(&obj->base);
1941 list_move_tail(&obj->ring_list, &ring->active_list);
1943 obj->last_read_seqno = seqno;
1945 if (obj->fenced_gpu_access) {
1946 obj->last_fenced_seqno = seqno;
1948 /* Bump MRU to take account of the delayed flush */
1949 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1950 struct drm_i915_fence_reg *reg;
1952 reg = &dev_priv->fence_regs[obj->fence_reg];
1953 list_move_tail(®->lru_list,
1954 &dev_priv->mm.fence_list);
1960 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1962 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1963 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1964 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1966 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1967 BUG_ON(!obj->active);
1969 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1971 list_del_init(&obj->ring_list);
1974 obj->last_read_seqno = 0;
1975 obj->last_write_seqno = 0;
1976 obj->base.write_domain = 0;
1978 obj->last_fenced_seqno = 0;
1979 obj->fenced_gpu_access = false;
1982 drm_gem_object_unreference(&obj->base);
1984 WARN_ON(i915_verify_lists(dev));
1988 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_ring_buffer *ring;
1994 /* Carefully retire all requests without writing to the rings */
1995 for_each_ring(ring, dev_priv, i) {
1996 ret = intel_ring_idle(ring);
2000 i915_gem_retire_requests(dev);
2002 /* Finally reset hw state */
2003 for_each_ring(ring, dev_priv, i) {
2004 intel_ring_init_seqno(ring, seqno);
2006 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2007 ring->sync_seqno[j] = 0;
2013 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2015 struct drm_i915_private *dev_priv = dev->dev_private;
2021 /* HWS page needs to be set less than what we
2022 * will inject to ring
2024 ret = i915_gem_init_seqno(dev, seqno - 1);
2028 /* Carefully set the last_seqno value so that wrap
2029 * detection still works
2031 dev_priv->next_seqno = seqno;
2032 dev_priv->last_seqno = seqno - 1;
2033 if (dev_priv->last_seqno == 0)
2034 dev_priv->last_seqno--;
2040 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2044 /* reserve 0 for non-seqno */
2045 if (dev_priv->next_seqno == 0) {
2046 int ret = i915_gem_init_seqno(dev, 0);
2050 dev_priv->next_seqno = 1;
2053 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2057 int __i915_add_request(struct intel_ring_buffer *ring,
2058 struct drm_file *file,
2059 struct drm_i915_gem_object *obj,
2062 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2063 struct drm_i915_gem_request *request;
2064 u32 request_ring_position, request_start;
2068 request_start = intel_ring_get_tail(ring);
2070 * Emit any outstanding flushes - execbuf can fail to emit the flush
2071 * after having emitted the batchbuffer command. Hence we need to fix
2072 * things up similar to emitting the lazy request. The difference here
2073 * is that the flush _must_ happen before the next request, no matter
2076 ret = intel_ring_flush_all_caches(ring);
2080 request = ring->preallocated_lazy_request;
2081 if (WARN_ON(request == NULL))
2084 /* Record the position of the start of the request so that
2085 * should we detect the updated seqno part-way through the
2086 * GPU processing the request, we never over-estimate the
2087 * position of the head.
2089 request_ring_position = intel_ring_get_tail(ring);
2091 ret = ring->add_request(ring);
2095 request->seqno = intel_ring_get_seqno(ring);
2096 request->ring = ring;
2097 request->head = request_start;
2098 request->tail = request_ring_position;
2100 /* Whilst this request exists, batch_obj will be on the
2101 * active_list, and so will hold the active reference. Only when this
2102 * request is retired will the the batch_obj be moved onto the
2103 * inactive_list and lose its active reference. Hence we do not need
2104 * to explicitly hold another reference here.
2106 request->batch_obj = obj;
2108 /* Hold a reference to the current context so that we can inspect
2109 * it later in case a hangcheck error event fires.
2111 request->ctx = ring->last_context;
2113 i915_gem_context_reference(request->ctx);
2115 request->emitted_jiffies = jiffies;
2116 was_empty = list_empty(&ring->request_list);
2117 list_add_tail(&request->list, &ring->request_list);
2118 request->file_priv = NULL;
2121 struct drm_i915_file_private *file_priv = file->driver_priv;
2123 spin_lock(&file_priv->mm.lock);
2124 request->file_priv = file_priv;
2125 list_add_tail(&request->client_list,
2126 &file_priv->mm.request_list);
2127 spin_unlock(&file_priv->mm.lock);
2130 trace_i915_gem_request_add(ring, request->seqno);
2131 ring->outstanding_lazy_seqno = 0;
2132 ring->preallocated_lazy_request = NULL;
2134 if (!dev_priv->ums.mm_suspended) {
2135 i915_queue_hangcheck(ring->dev);
2138 queue_delayed_work(dev_priv->wq,
2139 &dev_priv->mm.retire_work,
2140 round_jiffies_up_relative(HZ));
2141 intel_mark_busy(dev_priv->dev);
2146 *out_seqno = request->seqno;
2151 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2153 struct drm_i915_file_private *file_priv = request->file_priv;
2158 spin_lock(&file_priv->mm.lock);
2159 if (request->file_priv) {
2160 list_del(&request->client_list);
2161 request->file_priv = NULL;
2163 spin_unlock(&file_priv->mm.lock);
2166 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2167 struct i915_address_space *vm)
2169 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2170 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2176 static bool i915_head_inside_request(const u32 acthd_unmasked,
2177 const u32 request_start,
2178 const u32 request_end)
2180 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2182 if (request_start < request_end) {
2183 if (acthd >= request_start && acthd < request_end)
2185 } else if (request_start > request_end) {
2186 if (acthd >= request_start || acthd < request_end)
2193 static struct i915_address_space *
2194 request_to_vm(struct drm_i915_gem_request *request)
2196 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2197 struct i915_address_space *vm;
2199 vm = &dev_priv->gtt.base;
2204 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2205 const u32 acthd, bool *inside)
2207 /* There is a possibility that unmasked head address
2208 * pointing inside the ring, matches the batch_obj address range.
2209 * However this is extremely unlikely.
2211 if (request->batch_obj) {
2212 if (i915_head_inside_object(acthd, request->batch_obj,
2213 request_to_vm(request))) {
2219 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2227 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2229 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2234 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2235 DRM_ERROR("context hanging too fast, declaring banned!\n");
2242 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2243 struct drm_i915_gem_request *request,
2246 struct i915_ctx_hang_stats *hs = NULL;
2247 bool inside, guilty;
2248 unsigned long offset = 0;
2250 /* Innocent until proven guilty */
2253 if (request->batch_obj)
2254 offset = i915_gem_obj_offset(request->batch_obj,
2255 request_to_vm(request));
2257 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2258 i915_request_guilty(request, acthd, &inside)) {
2259 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2261 inside ? "inside" : "flushing",
2263 request->ctx ? request->ctx->id : 0,
2269 /* If contexts are disabled or this is the default context, use
2270 * file_priv->reset_state
2272 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2273 hs = &request->ctx->hang_stats;
2274 else if (request->file_priv)
2275 hs = &request->file_priv->hang_stats;
2279 hs->banned = i915_context_is_banned(hs);
2281 hs->guilty_ts = get_seconds();
2283 hs->batch_pending++;
2288 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2290 list_del(&request->list);
2291 i915_gem_request_remove_from_client(request);
2294 i915_gem_context_unreference(request->ctx);
2299 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2300 struct intel_ring_buffer *ring)
2302 u32 completed_seqno;
2305 acthd = intel_ring_get_active_head(ring);
2306 completed_seqno = ring->get_seqno(ring, false);
2308 while (!list_empty(&ring->request_list)) {
2309 struct drm_i915_gem_request *request;
2311 request = list_first_entry(&ring->request_list,
2312 struct drm_i915_gem_request,
2315 if (request->seqno > completed_seqno)
2316 i915_set_reset_status(ring, request, acthd);
2318 i915_gem_free_request(request);
2321 while (!list_empty(&ring->active_list)) {
2322 struct drm_i915_gem_object *obj;
2324 obj = list_first_entry(&ring->active_list,
2325 struct drm_i915_gem_object,
2328 i915_gem_object_move_to_inactive(obj);
2332 void i915_gem_restore_fences(struct drm_device *dev)
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2337 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2338 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2341 * Commit delayed tiling changes if we have an object still
2342 * attached to the fence, otherwise just clear the fence.
2345 i915_gem_object_update_fence(reg->obj, reg,
2346 reg->obj->tiling_mode);
2348 i915_gem_write_fence(dev, i, NULL);
2353 void i915_gem_reset(struct drm_device *dev)
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_ring_buffer *ring;
2359 for_each_ring(ring, dev_priv, i)
2360 i915_gem_reset_ring_lists(dev_priv, ring);
2362 i915_gem_restore_fences(dev);
2366 * This function clears the request list as sequence numbers are passed.
2369 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2373 if (list_empty(&ring->request_list))
2376 WARN_ON(i915_verify_lists(ring->dev));
2378 seqno = ring->get_seqno(ring, true);
2380 while (!list_empty(&ring->request_list)) {
2381 struct drm_i915_gem_request *request;
2383 request = list_first_entry(&ring->request_list,
2384 struct drm_i915_gem_request,
2387 if (!i915_seqno_passed(seqno, request->seqno))
2390 trace_i915_gem_request_retire(ring, request->seqno);
2391 /* We know the GPU must have read the request to have
2392 * sent us the seqno + interrupt, so use the position
2393 * of tail of the request to update the last known position
2396 ring->last_retired_head = request->tail;
2398 i915_gem_free_request(request);
2401 /* Move any buffers on the active list that are no longer referenced
2402 * by the ringbuffer to the flushing/inactive lists as appropriate.
2404 while (!list_empty(&ring->active_list)) {
2405 struct drm_i915_gem_object *obj;
2407 obj = list_first_entry(&ring->active_list,
2408 struct drm_i915_gem_object,
2411 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2414 i915_gem_object_move_to_inactive(obj);
2417 if (unlikely(ring->trace_irq_seqno &&
2418 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2419 ring->irq_put(ring);
2420 ring->trace_irq_seqno = 0;
2423 WARN_ON(i915_verify_lists(ring->dev));
2427 i915_gem_retire_requests(struct drm_device *dev)
2429 drm_i915_private_t *dev_priv = dev->dev_private;
2430 struct intel_ring_buffer *ring;
2433 for_each_ring(ring, dev_priv, i)
2434 i915_gem_retire_requests_ring(ring);
2438 i915_gem_retire_work_handler(struct work_struct *work)
2440 drm_i915_private_t *dev_priv;
2441 struct drm_device *dev;
2442 struct intel_ring_buffer *ring;
2446 dev_priv = container_of(work, drm_i915_private_t,
2447 mm.retire_work.work);
2448 dev = dev_priv->dev;
2450 /* Come back later if the device is busy... */
2451 if (!mutex_trylock(&dev->struct_mutex)) {
2452 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2453 round_jiffies_up_relative(HZ));
2457 i915_gem_retire_requests(dev);
2459 /* Send a periodic flush down the ring so we don't hold onto GEM
2460 * objects indefinitely.
2463 for_each_ring(ring, dev_priv, i) {
2464 if (ring->gpu_caches_dirty)
2465 i915_add_request(ring, NULL);
2467 idle &= list_empty(&ring->request_list);
2470 if (!dev_priv->ums.mm_suspended && !idle)
2471 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2472 round_jiffies_up_relative(HZ));
2474 intel_mark_idle(dev);
2476 mutex_unlock(&dev->struct_mutex);
2480 * Ensures that an object will eventually get non-busy by flushing any required
2481 * write domains, emitting any outstanding lazy request and retiring and
2482 * completed requests.
2485 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2490 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2494 i915_gem_retire_requests_ring(obj->ring);
2501 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2502 * @DRM_IOCTL_ARGS: standard ioctl arguments
2504 * Returns 0 if successful, else an error is returned with the remaining time in
2505 * the timeout parameter.
2506 * -ETIME: object is still busy after timeout
2507 * -ERESTARTSYS: signal interrupted the wait
2508 * -ENONENT: object doesn't exist
2509 * Also possible, but rare:
2510 * -EAGAIN: GPU wedged
2512 * -ENODEV: Internal IRQ fail
2513 * -E?: The add request failed
2515 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2516 * non-zero timeout parameter the wait ioctl will wait for the given number of
2517 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2518 * without holding struct_mutex the object may become re-busied before this
2519 * function completes. A similar but shorter * race condition exists in the busy
2523 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2525 drm_i915_private_t *dev_priv = dev->dev_private;
2526 struct drm_i915_gem_wait *args = data;
2527 struct drm_i915_gem_object *obj;
2528 struct intel_ring_buffer *ring = NULL;
2529 struct timespec timeout_stack, *timeout = NULL;
2530 unsigned reset_counter;
2534 if (args->timeout_ns >= 0) {
2535 timeout_stack = ns_to_timespec(args->timeout_ns);
2536 timeout = &timeout_stack;
2539 ret = i915_mutex_lock_interruptible(dev);
2543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2544 if (&obj->base == NULL) {
2545 mutex_unlock(&dev->struct_mutex);
2549 /* Need to make sure the object gets inactive eventually. */
2550 ret = i915_gem_object_flush_active(obj);
2555 seqno = obj->last_read_seqno;
2562 /* Do this after OLR check to make sure we make forward progress polling
2563 * on this IOCTL with a 0 timeout (like busy ioctl)
2565 if (!args->timeout_ns) {
2570 drm_gem_object_unreference(&obj->base);
2571 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2572 mutex_unlock(&dev->struct_mutex);
2574 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2576 args->timeout_ns = timespec_to_ns(timeout);
2580 drm_gem_object_unreference(&obj->base);
2581 mutex_unlock(&dev->struct_mutex);
2586 * i915_gem_object_sync - sync an object to a ring.
2588 * @obj: object which may be in use on another ring.
2589 * @to: ring we wish to use the object on. May be NULL.
2591 * This code is meant to abstract object synchronization with the GPU.
2592 * Calling with NULL implies synchronizing the object with the CPU
2593 * rather than a particular GPU ring.
2595 * Returns 0 if successful, else propagates up the lower layer error.
2598 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2599 struct intel_ring_buffer *to)
2601 struct intel_ring_buffer *from = obj->ring;
2605 if (from == NULL || to == from)
2608 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2609 return i915_gem_object_wait_rendering(obj, false);
2611 idx = intel_ring_sync_index(from, to);
2613 seqno = obj->last_read_seqno;
2614 if (seqno <= from->sync_seqno[idx])
2617 ret = i915_gem_check_olr(obj->ring, seqno);
2621 ret = to->sync_to(to, from, seqno);
2623 /* We use last_read_seqno because sync_to()
2624 * might have just caused seqno wrap under
2627 from->sync_seqno[idx] = obj->last_read_seqno;
2632 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2634 u32 old_write_domain, old_read_domains;
2636 /* Force a pagefault for domain tracking on next user access */
2637 i915_gem_release_mmap(obj);
2639 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2642 /* Wait for any direct GTT access to complete */
2645 old_read_domains = obj->base.read_domains;
2646 old_write_domain = obj->base.write_domain;
2648 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2649 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2651 trace_i915_gem_object_change_domain(obj,
2656 int i915_vma_unbind(struct i915_vma *vma)
2658 struct drm_i915_gem_object *obj = vma->obj;
2659 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2662 /* For now we only ever use 1 vma per object */
2663 WARN_ON(!list_is_singular(&obj->vma_list));
2665 if (list_empty(&vma->vma_link))
2668 if (!drm_mm_node_allocated(&vma->node)) {
2669 i915_gem_vma_destroy(vma);
2677 BUG_ON(obj->pages == NULL);
2679 ret = i915_gem_object_finish_gpu(obj);
2682 /* Continue on if we fail due to EIO, the GPU is hung so we
2683 * should be safe and we need to cleanup or else we might
2684 * cause memory corruption through use-after-free.
2687 i915_gem_object_finish_gtt(obj);
2689 /* release the fence reg _after_ flushing */
2690 ret = i915_gem_object_put_fence(obj);
2694 trace_i915_vma_unbind(vma);
2696 if (obj->has_global_gtt_mapping)
2697 i915_gem_gtt_unbind_object(obj);
2698 if (obj->has_aliasing_ppgtt_mapping) {
2699 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2700 obj->has_aliasing_ppgtt_mapping = 0;
2702 i915_gem_gtt_finish_object(obj);
2703 i915_gem_object_unpin_pages(obj);
2705 list_del(&vma->mm_list);
2706 /* Avoid an unnecessary call to unbind on rebind. */
2707 if (i915_is_ggtt(vma->vm))
2708 obj->map_and_fenceable = true;
2710 drm_mm_remove_node(&vma->node);
2712 i915_gem_vma_destroy(vma);
2714 /* Since the unbound list is global, only move to that list if
2715 * no more VMAs exist. */
2716 if (list_empty(&obj->vma_list))
2717 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2723 * Unbinds an object from the global GTT aperture.
2726 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2728 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2729 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2731 if (!i915_gem_obj_ggtt_bound(obj))
2737 BUG_ON(obj->pages == NULL);
2739 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2742 int i915_gpu_idle(struct drm_device *dev)
2744 drm_i915_private_t *dev_priv = dev->dev_private;
2745 struct intel_ring_buffer *ring;
2748 /* Flush everything onto the inactive list. */
2749 for_each_ring(ring, dev_priv, i) {
2750 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2754 ret = intel_ring_idle(ring);
2762 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2763 struct drm_i915_gem_object *obj)
2765 drm_i915_private_t *dev_priv = dev->dev_private;
2767 int fence_pitch_shift;
2769 if (INTEL_INFO(dev)->gen >= 6) {
2770 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2771 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2773 fence_reg = FENCE_REG_965_0;
2774 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2777 fence_reg += reg * 8;
2779 /* To w/a incoherency with non-atomic 64-bit register updates,
2780 * we split the 64-bit update into two 32-bit writes. In order
2781 * for a partial fence not to be evaluated between writes, we
2782 * precede the update with write to turn off the fence register,
2783 * and only enable the fence as the last step.
2785 * For extra levels of paranoia, we make sure each step lands
2786 * before applying the next step.
2788 I915_WRITE(fence_reg, 0);
2789 POSTING_READ(fence_reg);
2792 u32 size = i915_gem_obj_ggtt_size(obj);
2795 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2797 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2798 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2799 if (obj->tiling_mode == I915_TILING_Y)
2800 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2801 val |= I965_FENCE_REG_VALID;
2803 I915_WRITE(fence_reg + 4, val >> 32);
2804 POSTING_READ(fence_reg + 4);
2806 I915_WRITE(fence_reg + 0, val);
2807 POSTING_READ(fence_reg);
2809 I915_WRITE(fence_reg + 4, 0);
2810 POSTING_READ(fence_reg + 4);
2814 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2815 struct drm_i915_gem_object *obj)
2817 drm_i915_private_t *dev_priv = dev->dev_private;
2821 u32 size = i915_gem_obj_ggtt_size(obj);
2825 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2826 (size & -size) != size ||
2827 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2828 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2829 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2831 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2836 /* Note: pitch better be a power of two tile widths */
2837 pitch_val = obj->stride / tile_width;
2838 pitch_val = ffs(pitch_val) - 1;
2840 val = i915_gem_obj_ggtt_offset(obj);
2841 if (obj->tiling_mode == I915_TILING_Y)
2842 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2843 val |= I915_FENCE_SIZE_BITS(size);
2844 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2845 val |= I830_FENCE_REG_VALID;
2850 reg = FENCE_REG_830_0 + reg * 4;
2852 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2854 I915_WRITE(reg, val);
2858 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2859 struct drm_i915_gem_object *obj)
2861 drm_i915_private_t *dev_priv = dev->dev_private;
2865 u32 size = i915_gem_obj_ggtt_size(obj);
2868 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2869 (size & -size) != size ||
2870 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2871 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2872 i915_gem_obj_ggtt_offset(obj), size);
2874 pitch_val = obj->stride / 128;
2875 pitch_val = ffs(pitch_val) - 1;
2877 val = i915_gem_obj_ggtt_offset(obj);
2878 if (obj->tiling_mode == I915_TILING_Y)
2879 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2880 val |= I830_FENCE_SIZE_BITS(size);
2881 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2882 val |= I830_FENCE_REG_VALID;
2886 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2887 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2890 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2892 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2895 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2896 struct drm_i915_gem_object *obj)
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2900 /* Ensure that all CPU reads are completed before installing a fence
2901 * and all writes before removing the fence.
2903 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2906 WARN(obj && (!obj->stride || !obj->tiling_mode),
2907 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2908 obj->stride, obj->tiling_mode);
2910 switch (INTEL_INFO(dev)->gen) {
2914 case 4: i965_write_fence_reg(dev, reg, obj); break;
2915 case 3: i915_write_fence_reg(dev, reg, obj); break;
2916 case 2: i830_write_fence_reg(dev, reg, obj); break;
2920 /* And similarly be paranoid that no direct access to this region
2921 * is reordered to before the fence is installed.
2923 if (i915_gem_object_needs_mb(obj))
2927 static inline int fence_number(struct drm_i915_private *dev_priv,
2928 struct drm_i915_fence_reg *fence)
2930 return fence - dev_priv->fence_regs;
2933 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2934 struct drm_i915_fence_reg *fence,
2937 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2938 int reg = fence_number(dev_priv, fence);
2940 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2943 obj->fence_reg = reg;
2945 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2947 obj->fence_reg = I915_FENCE_REG_NONE;
2949 list_del_init(&fence->lru_list);
2951 obj->fence_dirty = false;
2955 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2957 if (obj->last_fenced_seqno) {
2958 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2962 obj->last_fenced_seqno = 0;
2965 obj->fenced_gpu_access = false;
2970 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2972 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2973 struct drm_i915_fence_reg *fence;
2976 ret = i915_gem_object_wait_fence(obj);
2980 if (obj->fence_reg == I915_FENCE_REG_NONE)
2983 fence = &dev_priv->fence_regs[obj->fence_reg];
2985 i915_gem_object_fence_lost(obj);
2986 i915_gem_object_update_fence(obj, fence, false);
2991 static struct drm_i915_fence_reg *
2992 i915_find_fence_reg(struct drm_device *dev)
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 struct drm_i915_fence_reg *reg, *avail;
2998 /* First try to find a free reg */
3000 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3001 reg = &dev_priv->fence_regs[i];
3005 if (!reg->pin_count)
3012 /* None available, try to steal one or wait for a user to finish */
3013 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3024 * i915_gem_object_get_fence - set up fencing for an object
3025 * @obj: object to map through a fence reg
3027 * When mapping objects through the GTT, userspace wants to be able to write
3028 * to them without having to worry about swizzling if the object is tiled.
3029 * This function walks the fence regs looking for a free one for @obj,
3030 * stealing one if it can't find any.
3032 * It then sets up the reg based on the object's properties: address, pitch
3033 * and tiling format.
3035 * For an untiled surface, this removes any existing fence.
3038 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3040 struct drm_device *dev = obj->base.dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 bool enable = obj->tiling_mode != I915_TILING_NONE;
3043 struct drm_i915_fence_reg *reg;
3046 /* Have we updated the tiling parameters upon the object and so
3047 * will need to serialise the write to the associated fence register?
3049 if (obj->fence_dirty) {
3050 ret = i915_gem_object_wait_fence(obj);
3055 /* Just update our place in the LRU if our fence is getting reused. */
3056 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3057 reg = &dev_priv->fence_regs[obj->fence_reg];
3058 if (!obj->fence_dirty) {
3059 list_move_tail(®->lru_list,
3060 &dev_priv->mm.fence_list);
3063 } else if (enable) {
3064 reg = i915_find_fence_reg(dev);
3069 struct drm_i915_gem_object *old = reg->obj;
3071 ret = i915_gem_object_wait_fence(old);
3075 i915_gem_object_fence_lost(old);
3080 i915_gem_object_update_fence(obj, reg, enable);
3085 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3086 struct drm_mm_node *gtt_space,
3087 unsigned long cache_level)
3089 struct drm_mm_node *other;
3091 /* On non-LLC machines we have to be careful when putting differing
3092 * types of snoopable memory together to avoid the prefetcher
3093 * crossing memory domains and dying.
3098 if (!drm_mm_node_allocated(gtt_space))
3101 if (list_empty(>t_space->node_list))
3104 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3105 if (other->allocated && !other->hole_follows && other->color != cache_level)
3108 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3109 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3115 static void i915_gem_verify_gtt(struct drm_device *dev)
3118 struct drm_i915_private *dev_priv = dev->dev_private;
3119 struct drm_i915_gem_object *obj;
3122 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3123 if (obj->gtt_space == NULL) {
3124 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3129 if (obj->cache_level != obj->gtt_space->color) {
3130 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3131 i915_gem_obj_ggtt_offset(obj),
3132 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3134 obj->gtt_space->color);
3139 if (!i915_gem_valid_gtt_space(dev,
3141 obj->cache_level)) {
3142 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3143 i915_gem_obj_ggtt_offset(obj),
3144 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3156 * Finds free space in the GTT aperture and binds the object there.
3159 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3160 struct i915_address_space *vm,
3162 bool map_and_fenceable,
3165 struct drm_device *dev = obj->base.dev;
3166 drm_i915_private_t *dev_priv = dev->dev_private;
3167 u32 size, fence_size, fence_alignment, unfenced_alignment;
3169 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3170 struct i915_vma *vma;
3173 fence_size = i915_gem_get_gtt_size(dev,
3176 fence_alignment = i915_gem_get_gtt_alignment(dev,
3178 obj->tiling_mode, true);
3179 unfenced_alignment =
3180 i915_gem_get_gtt_alignment(dev,
3182 obj->tiling_mode, false);
3185 alignment = map_and_fenceable ? fence_alignment :
3187 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3188 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3192 size = map_and_fenceable ? fence_size : obj->base.size;
3194 /* If the object is bigger than the entire aperture, reject it early
3195 * before evicting everything in a vain attempt to find space.
3197 if (obj->base.size > gtt_max) {
3198 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3200 map_and_fenceable ? "mappable" : "total",
3205 ret = i915_gem_object_get_pages(obj);
3209 i915_gem_object_pin_pages(obj);
3211 BUG_ON(!i915_is_ggtt(vm));
3213 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3219 /* For now we only ever use 1 vma per object */
3220 WARN_ON(!list_is_singular(&obj->vma_list));
3223 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3225 obj->cache_level, 0, gtt_max,
3226 DRM_MM_SEARCH_DEFAULT);
3228 ret = i915_gem_evict_something(dev, vm, size, alignment,
3237 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3238 obj->cache_level))) {
3240 goto err_remove_node;
3243 ret = i915_gem_gtt_prepare_object(obj);
3245 goto err_remove_node;
3247 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3248 list_add_tail(&vma->mm_list, &vm->inactive_list);
3250 if (i915_is_ggtt(vm)) {
3251 bool mappable, fenceable;
3253 fenceable = (vma->node.size == fence_size &&
3254 (vma->node.start & (fence_alignment - 1)) == 0);
3256 mappable = (vma->node.start + obj->base.size <=
3257 dev_priv->gtt.mappable_end);
3259 obj->map_and_fenceable = mappable && fenceable;
3262 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3264 trace_i915_vma_bind(vma, map_and_fenceable);
3265 i915_gem_verify_gtt(dev);
3269 drm_mm_remove_node(&vma->node);
3271 i915_gem_vma_destroy(vma);
3273 i915_gem_object_unpin_pages(obj);
3278 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3281 /* If we don't have a page list set up, then we're not pinned
3282 * to GPU, and we can ignore the cache flush because it'll happen
3283 * again at bind time.
3285 if (obj->pages == NULL)
3289 * Stolen memory is always coherent with the GPU as it is explicitly
3290 * marked as wc by the system, or the system is cache-coherent.
3295 /* If the GPU is snooping the contents of the CPU cache,
3296 * we do not need to manually clear the CPU cache lines. However,
3297 * the caches are only snooped when the render cache is
3298 * flushed/invalidated. As we always have to emit invalidations
3299 * and flushes when moving into and out of the RENDER domain, correct
3300 * snooping behaviour occurs naturally as the result of our domain
3303 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3306 trace_i915_gem_object_clflush(obj);
3307 drm_clflush_sg(obj->pages);
3312 /** Flushes the GTT write domain for the object if it's dirty. */
3314 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3316 uint32_t old_write_domain;
3318 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3321 /* No actual flushing is required for the GTT write domain. Writes
3322 * to it immediately go to main memory as far as we know, so there's
3323 * no chipset flush. It also doesn't land in render cache.
3325 * However, we do have to enforce the order so that all writes through
3326 * the GTT land before any writes to the device, such as updates to
3331 old_write_domain = obj->base.write_domain;
3332 obj->base.write_domain = 0;
3334 trace_i915_gem_object_change_domain(obj,
3335 obj->base.read_domains,
3339 /** Flushes the CPU write domain for the object if it's dirty. */
3341 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3344 uint32_t old_write_domain;
3346 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3349 if (i915_gem_clflush_object(obj, force))
3350 i915_gem_chipset_flush(obj->base.dev);
3352 old_write_domain = obj->base.write_domain;
3353 obj->base.write_domain = 0;
3355 trace_i915_gem_object_change_domain(obj,
3356 obj->base.read_domains,
3361 * Moves a single object to the GTT read, and possibly write domain.
3363 * This function returns when the move is complete, including waiting on
3367 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3369 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3370 uint32_t old_write_domain, old_read_domains;
3373 /* Not valid to be called on unbound objects. */
3374 if (!i915_gem_obj_bound_any(obj))
3377 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3380 ret = i915_gem_object_wait_rendering(obj, !write);
3384 i915_gem_object_flush_cpu_write_domain(obj, false);
3386 /* Serialise direct access to this object with the barriers for
3387 * coherent writes from the GPU, by effectively invalidating the
3388 * GTT domain upon first access.
3390 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3393 old_write_domain = obj->base.write_domain;
3394 old_read_domains = obj->base.read_domains;
3396 /* It should now be out of any other write domains, and we can update
3397 * the domain values for our changes.
3399 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3400 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3402 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3403 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3407 trace_i915_gem_object_change_domain(obj,
3411 /* And bump the LRU for this access */
3412 if (i915_gem_object_is_inactive(obj)) {
3413 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3414 &dev_priv->gtt.base);
3416 list_move_tail(&vma->mm_list,
3417 &dev_priv->gtt.base.inactive_list);
3424 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3425 enum i915_cache_level cache_level)
3427 struct drm_device *dev = obj->base.dev;
3428 drm_i915_private_t *dev_priv = dev->dev_private;
3429 struct i915_vma *vma;
3432 if (obj->cache_level == cache_level)
3435 if (obj->pin_count) {
3436 DRM_DEBUG("can not change the cache level of pinned objects\n");
3440 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3441 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3442 ret = i915_vma_unbind(vma);
3450 if (i915_gem_obj_bound_any(obj)) {
3451 ret = i915_gem_object_finish_gpu(obj);
3455 i915_gem_object_finish_gtt(obj);
3457 /* Before SandyBridge, you could not use tiling or fence
3458 * registers with snooped memory, so relinquish any fences
3459 * currently pointing to our region in the aperture.
3461 if (INTEL_INFO(dev)->gen < 6) {
3462 ret = i915_gem_object_put_fence(obj);
3467 if (obj->has_global_gtt_mapping)
3468 i915_gem_gtt_bind_object(obj, cache_level);
3469 if (obj->has_aliasing_ppgtt_mapping)
3470 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3474 list_for_each_entry(vma, &obj->vma_list, vma_link)
3475 vma->node.color = cache_level;
3476 obj->cache_level = cache_level;
3478 if (cpu_write_needs_clflush(obj)) {
3479 u32 old_read_domains, old_write_domain;
3481 /* If we're coming from LLC cached, then we haven't
3482 * actually been tracking whether the data is in the
3483 * CPU cache or not, since we only allow one bit set
3484 * in obj->write_domain and have been skipping the clflushes.
3485 * Just set it to the CPU cache for now.
3487 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3489 old_read_domains = obj->base.read_domains;
3490 old_write_domain = obj->base.write_domain;
3492 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3493 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3495 trace_i915_gem_object_change_domain(obj,
3500 i915_gem_verify_gtt(dev);
3504 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3505 struct drm_file *file)
3507 struct drm_i915_gem_caching *args = data;
3508 struct drm_i915_gem_object *obj;
3511 ret = i915_mutex_lock_interruptible(dev);
3515 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3516 if (&obj->base == NULL) {
3521 switch (obj->cache_level) {
3522 case I915_CACHE_LLC:
3523 case I915_CACHE_L3_LLC:
3524 args->caching = I915_CACHING_CACHED;
3528 args->caching = I915_CACHING_DISPLAY;
3532 args->caching = I915_CACHING_NONE;
3536 drm_gem_object_unreference(&obj->base);
3538 mutex_unlock(&dev->struct_mutex);
3542 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3543 struct drm_file *file)
3545 struct drm_i915_gem_caching *args = data;
3546 struct drm_i915_gem_object *obj;
3547 enum i915_cache_level level;
3550 switch (args->caching) {
3551 case I915_CACHING_NONE:
3552 level = I915_CACHE_NONE;
3554 case I915_CACHING_CACHED:
3555 level = I915_CACHE_LLC;
3557 case I915_CACHING_DISPLAY:
3558 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3564 ret = i915_mutex_lock_interruptible(dev);
3568 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3569 if (&obj->base == NULL) {
3574 ret = i915_gem_object_set_cache_level(obj, level);
3576 drm_gem_object_unreference(&obj->base);
3578 mutex_unlock(&dev->struct_mutex);
3582 static bool is_pin_display(struct drm_i915_gem_object *obj)
3584 /* There are 3 sources that pin objects:
3585 * 1. The display engine (scanouts, sprites, cursors);
3586 * 2. Reservations for execbuffer;
3589 * We can ignore reservations as we hold the struct_mutex and
3590 * are only called outside of the reservation path. The user
3591 * can only increment pin_count once, and so if after
3592 * subtracting the potential reference by the user, any pin_count
3593 * remains, it must be due to another use by the display engine.
3595 return obj->pin_count - !!obj->user_pin_count;
3599 * Prepare buffer for display plane (scanout, cursors, etc).
3600 * Can be called from an uninterruptible phase (modesetting) and allows
3601 * any flushes to be pipelined (for pageflips).
3604 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3606 struct intel_ring_buffer *pipelined)
3608 u32 old_read_domains, old_write_domain;
3611 if (pipelined != obj->ring) {
3612 ret = i915_gem_object_sync(obj, pipelined);
3617 /* Mark the pin_display early so that we account for the
3618 * display coherency whilst setting up the cache domains.
3620 obj->pin_display = true;
3622 /* The display engine is not coherent with the LLC cache on gen6. As
3623 * a result, we make sure that the pinning that is about to occur is
3624 * done with uncached PTEs. This is lowest common denominator for all
3627 * However for gen6+, we could do better by using the GFDT bit instead
3628 * of uncaching, which would allow us to flush all the LLC-cached data
3629 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3631 ret = i915_gem_object_set_cache_level(obj,
3632 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3634 goto err_unpin_display;
3636 /* As the user may map the buffer once pinned in the display plane
3637 * (e.g. libkms for the bootup splash), we have to ensure that we
3638 * always use map_and_fenceable for all scanout buffers.
3640 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3642 goto err_unpin_display;
3644 i915_gem_object_flush_cpu_write_domain(obj, true);
3646 old_write_domain = obj->base.write_domain;
3647 old_read_domains = obj->base.read_domains;
3649 /* It should now be out of any other write domains, and we can update
3650 * the domain values for our changes.
3652 obj->base.write_domain = 0;
3653 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3655 trace_i915_gem_object_change_domain(obj,
3662 obj->pin_display = is_pin_display(obj);
3667 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3669 i915_gem_object_unpin(obj);
3670 obj->pin_display = is_pin_display(obj);
3674 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3678 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3681 ret = i915_gem_object_wait_rendering(obj, false);
3685 /* Ensure that we invalidate the GPU's caches and TLBs. */
3686 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3691 * Moves a single object to the CPU read, and possibly write domain.
3693 * This function returns when the move is complete, including waiting on
3697 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3699 uint32_t old_write_domain, old_read_domains;
3702 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3705 ret = i915_gem_object_wait_rendering(obj, !write);
3709 i915_gem_object_flush_gtt_write_domain(obj);
3711 old_write_domain = obj->base.write_domain;
3712 old_read_domains = obj->base.read_domains;
3714 /* Flush the CPU cache if it's still invalid. */
3715 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3716 i915_gem_clflush_object(obj, false);
3718 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3721 /* It should now be out of any other write domains, and we can update
3722 * the domain values for our changes.
3724 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3726 /* If we're writing through the CPU, then the GPU read domains will
3727 * need to be invalidated at next use.
3730 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3731 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3734 trace_i915_gem_object_change_domain(obj,
3741 /* Throttle our rendering by waiting until the ring has completed our requests
3742 * emitted over 20 msec ago.
3744 * Note that if we were to use the current jiffies each time around the loop,
3745 * we wouldn't escape the function with any frames outstanding if the time to
3746 * render a frame was over 20ms.
3748 * This should get us reasonable parallelism between CPU and GPU but also
3749 * relatively low latency when blocking on a particular request to finish.
3752 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3754 struct drm_i915_private *dev_priv = dev->dev_private;
3755 struct drm_i915_file_private *file_priv = file->driver_priv;
3756 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3757 struct drm_i915_gem_request *request;
3758 struct intel_ring_buffer *ring = NULL;
3759 unsigned reset_counter;
3763 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3767 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3771 spin_lock(&file_priv->mm.lock);
3772 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3773 if (time_after_eq(request->emitted_jiffies, recent_enough))
3776 ring = request->ring;
3777 seqno = request->seqno;
3779 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3780 spin_unlock(&file_priv->mm.lock);
3785 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3787 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3793 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3794 struct i915_address_space *vm,
3796 bool map_and_fenceable,
3799 struct i915_vma *vma;
3802 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3805 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3807 vma = i915_gem_obj_to_vma(obj, vm);
3811 vma->node.start & (alignment - 1)) ||
3812 (map_and_fenceable && !obj->map_and_fenceable)) {
3813 WARN(obj->pin_count,
3814 "bo is already pinned with incorrect alignment:"
3815 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3816 " obj->map_and_fenceable=%d\n",
3817 i915_gem_obj_offset(obj, vm), alignment,
3819 obj->map_and_fenceable);
3820 ret = i915_vma_unbind(vma);
3826 if (!i915_gem_obj_bound(obj, vm)) {
3827 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3829 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3835 if (!dev_priv->mm.aliasing_ppgtt)
3836 i915_gem_gtt_bind_object(obj, obj->cache_level);
3839 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3840 i915_gem_gtt_bind_object(obj, obj->cache_level);
3843 obj->pin_mappable |= map_and_fenceable;
3849 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3851 BUG_ON(obj->pin_count == 0);
3852 BUG_ON(!i915_gem_obj_bound_any(obj));
3854 if (--obj->pin_count == 0)
3855 obj->pin_mappable = false;
3859 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3860 struct drm_file *file)
3862 struct drm_i915_gem_pin *args = data;
3863 struct drm_i915_gem_object *obj;
3866 ret = i915_mutex_lock_interruptible(dev);
3870 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3871 if (&obj->base == NULL) {
3876 if (obj->madv != I915_MADV_WILLNEED) {
3877 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3882 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3883 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3889 if (obj->user_pin_count == 0) {
3890 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3895 obj->user_pin_count++;
3896 obj->pin_filp = file;
3898 args->offset = i915_gem_obj_ggtt_offset(obj);
3900 drm_gem_object_unreference(&obj->base);
3902 mutex_unlock(&dev->struct_mutex);
3907 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3908 struct drm_file *file)
3910 struct drm_i915_gem_pin *args = data;
3911 struct drm_i915_gem_object *obj;
3914 ret = i915_mutex_lock_interruptible(dev);
3918 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3919 if (&obj->base == NULL) {
3924 if (obj->pin_filp != file) {
3925 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3930 obj->user_pin_count--;
3931 if (obj->user_pin_count == 0) {
3932 obj->pin_filp = NULL;
3933 i915_gem_object_unpin(obj);
3937 drm_gem_object_unreference(&obj->base);
3939 mutex_unlock(&dev->struct_mutex);
3944 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3945 struct drm_file *file)
3947 struct drm_i915_gem_busy *args = data;
3948 struct drm_i915_gem_object *obj;
3951 ret = i915_mutex_lock_interruptible(dev);
3955 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3956 if (&obj->base == NULL) {
3961 /* Count all active objects as busy, even if they are currently not used
3962 * by the gpu. Users of this interface expect objects to eventually
3963 * become non-busy without any further actions, therefore emit any
3964 * necessary flushes here.
3966 ret = i915_gem_object_flush_active(obj);
3968 args->busy = obj->active;
3970 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3971 args->busy |= intel_ring_flag(obj->ring) << 16;
3974 drm_gem_object_unreference(&obj->base);
3976 mutex_unlock(&dev->struct_mutex);
3981 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3982 struct drm_file *file_priv)
3984 return i915_gem_ring_throttle(dev, file_priv);
3988 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3989 struct drm_file *file_priv)
3991 struct drm_i915_gem_madvise *args = data;
3992 struct drm_i915_gem_object *obj;
3995 switch (args->madv) {
3996 case I915_MADV_DONTNEED:
3997 case I915_MADV_WILLNEED:
4003 ret = i915_mutex_lock_interruptible(dev);
4007 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4008 if (&obj->base == NULL) {
4013 if (obj->pin_count) {
4018 if (obj->madv != __I915_MADV_PURGED)
4019 obj->madv = args->madv;
4021 /* if the object is no longer attached, discard its backing storage */
4022 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4023 i915_gem_object_truncate(obj);
4025 args->retained = obj->madv != __I915_MADV_PURGED;
4028 drm_gem_object_unreference(&obj->base);
4030 mutex_unlock(&dev->struct_mutex);
4034 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4035 const struct drm_i915_gem_object_ops *ops)
4037 INIT_LIST_HEAD(&obj->global_list);
4038 INIT_LIST_HEAD(&obj->ring_list);
4039 INIT_LIST_HEAD(&obj->obj_exec_link);
4040 INIT_LIST_HEAD(&obj->vma_list);
4044 obj->fence_reg = I915_FENCE_REG_NONE;
4045 obj->madv = I915_MADV_WILLNEED;
4046 /* Avoid an unnecessary call to unbind on the first bind. */
4047 obj->map_and_fenceable = true;
4049 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4052 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4053 .get_pages = i915_gem_object_get_pages_gtt,
4054 .put_pages = i915_gem_object_put_pages_gtt,
4057 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4060 struct drm_i915_gem_object *obj;
4061 struct address_space *mapping;
4064 obj = i915_gem_object_alloc(dev);
4068 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4069 i915_gem_object_free(obj);
4073 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4074 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4075 /* 965gm cannot relocate objects above 4GiB. */
4076 mask &= ~__GFP_HIGHMEM;
4077 mask |= __GFP_DMA32;
4080 mapping = file_inode(obj->base.filp)->i_mapping;
4081 mapping_set_gfp_mask(mapping, mask);
4083 i915_gem_object_init(obj, &i915_gem_object_ops);
4085 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4086 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4089 /* On some devices, we can have the GPU use the LLC (the CPU
4090 * cache) for about a 10% performance improvement
4091 * compared to uncached. Graphics requests other than
4092 * display scanout are coherent with the CPU in
4093 * accessing this cache. This means in this mode we
4094 * don't need to clflush on the CPU side, and on the
4095 * GPU side we only need to flush internal caches to
4096 * get data visible to the CPU.
4098 * However, we maintain the display planes as UC, and so
4099 * need to rebind when first used as such.
4101 obj->cache_level = I915_CACHE_LLC;
4103 obj->cache_level = I915_CACHE_NONE;
4105 trace_i915_gem_object_create(obj);
4110 int i915_gem_init_object(struct drm_gem_object *obj)
4117 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4119 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4120 struct drm_device *dev = obj->base.dev;
4121 drm_i915_private_t *dev_priv = dev->dev_private;
4122 struct i915_vma *vma, *next;
4124 trace_i915_gem_object_destroy(obj);
4127 i915_gem_detach_phys_object(dev, obj);
4130 /* NB: 0 or 1 elements */
4131 WARN_ON(!list_empty(&obj->vma_list) &&
4132 !list_is_singular(&obj->vma_list));
4133 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4134 int ret = i915_vma_unbind(vma);
4135 if (WARN_ON(ret == -ERESTARTSYS)) {
4136 bool was_interruptible;
4138 was_interruptible = dev_priv->mm.interruptible;
4139 dev_priv->mm.interruptible = false;
4141 WARN_ON(i915_vma_unbind(vma));
4143 dev_priv->mm.interruptible = was_interruptible;
4147 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4148 * before progressing. */
4150 i915_gem_object_unpin_pages(obj);
4152 if (WARN_ON(obj->pages_pin_count))
4153 obj->pages_pin_count = 0;
4154 i915_gem_object_put_pages(obj);
4155 i915_gem_object_free_mmap_offset(obj);
4156 i915_gem_object_release_stolen(obj);
4160 if (obj->base.import_attach)
4161 drm_prime_gem_destroy(&obj->base, NULL);
4163 drm_gem_object_release(&obj->base);
4164 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4167 i915_gem_object_free(obj);
4170 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4171 struct i915_address_space *vm)
4173 struct i915_vma *vma;
4174 list_for_each_entry(vma, &obj->vma_list, vma_link)
4181 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4182 struct i915_address_space *vm)
4184 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4186 return ERR_PTR(-ENOMEM);
4188 INIT_LIST_HEAD(&vma->vma_link);
4189 INIT_LIST_HEAD(&vma->mm_list);
4190 INIT_LIST_HEAD(&vma->exec_list);
4194 /* Keep GGTT vmas first to make debug easier */
4195 if (i915_is_ggtt(vm))
4196 list_add(&vma->vma_link, &obj->vma_list);
4198 list_add_tail(&vma->vma_link, &obj->vma_list);
4204 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4205 struct i915_address_space *vm)
4207 struct i915_vma *vma;
4209 vma = i915_gem_obj_to_vma(obj, vm);
4211 vma = __i915_gem_vma_create(obj, vm);
4216 void i915_gem_vma_destroy(struct i915_vma *vma)
4218 WARN_ON(vma->node.allocated);
4220 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4221 if (!list_empty(&vma->exec_list))
4224 list_del(&vma->vma_link);
4230 i915_gem_idle(struct drm_device *dev)
4232 drm_i915_private_t *dev_priv = dev->dev_private;
4235 if (dev_priv->ums.mm_suspended) {
4236 mutex_unlock(&dev->struct_mutex);
4240 ret = i915_gpu_idle(dev);
4242 mutex_unlock(&dev->struct_mutex);
4245 i915_gem_retire_requests(dev);
4247 /* Under UMS, be paranoid and evict. */
4248 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4249 i915_gem_evict_everything(dev);
4251 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4253 i915_kernel_lost_context(dev);
4254 i915_gem_cleanup_ringbuffer(dev);
4256 /* Cancel the retire work handler, which should be idle now. */
4257 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4262 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4264 struct drm_device *dev = ring->dev;
4265 drm_i915_private_t *dev_priv = dev->dev_private;
4266 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4267 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4270 if (!HAS_L3_DPF(dev) || !remap_info)
4273 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4278 * Note: We do not worry about the concurrent register cacheline hang
4279 * here because no other code should access these registers other than
4280 * at initialization time.
4282 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4283 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4284 intel_ring_emit(ring, reg_base + i);
4285 intel_ring_emit(ring, remap_info[i/4]);
4288 intel_ring_advance(ring);
4293 void i915_gem_init_swizzling(struct drm_device *dev)
4295 drm_i915_private_t *dev_priv = dev->dev_private;
4297 if (INTEL_INFO(dev)->gen < 5 ||
4298 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4301 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4302 DISP_TILE_SURFACE_SWIZZLING);
4307 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4309 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4310 else if (IS_GEN7(dev))
4311 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4317 intel_enable_blt(struct drm_device *dev)
4322 /* The blitter was dysfunctional on early prototypes */
4323 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4324 DRM_INFO("BLT not supported on this pre-production hardware;"
4325 " graphics performance will be degraded.\n");
4332 static int i915_gem_init_rings(struct drm_device *dev)
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4337 ret = intel_init_render_ring_buffer(dev);
4342 ret = intel_init_bsd_ring_buffer(dev);
4344 goto cleanup_render_ring;
4347 if (intel_enable_blt(dev)) {
4348 ret = intel_init_blt_ring_buffer(dev);
4350 goto cleanup_bsd_ring;
4353 if (HAS_VEBOX(dev)) {
4354 ret = intel_init_vebox_ring_buffer(dev);
4356 goto cleanup_blt_ring;
4360 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4362 goto cleanup_vebox_ring;
4367 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4369 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4371 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4372 cleanup_render_ring:
4373 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4379 i915_gem_init_hw(struct drm_device *dev)
4381 drm_i915_private_t *dev_priv = dev->dev_private;
4384 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4387 if (dev_priv->ellc_size)
4388 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4390 if (IS_HSW_GT3(dev))
4391 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
4393 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
4395 if (HAS_PCH_NOP(dev)) {
4396 u32 temp = I915_READ(GEN7_MSG_CTL);
4397 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4398 I915_WRITE(GEN7_MSG_CTL, temp);
4401 i915_gem_init_swizzling(dev);
4403 ret = i915_gem_init_rings(dev);
4407 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4408 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4411 * XXX: There was some w/a described somewhere suggesting loading
4412 * contexts before PPGTT.
4414 i915_gem_context_init(dev);
4415 if (dev_priv->mm.aliasing_ppgtt) {
4416 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4418 i915_gem_cleanup_aliasing_ppgtt(dev);
4419 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4426 int i915_gem_init(struct drm_device *dev)
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4431 mutex_lock(&dev->struct_mutex);
4433 if (IS_VALLEYVIEW(dev)) {
4434 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4435 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4436 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4437 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4440 i915_gem_init_global_gtt(dev);
4442 ret = i915_gem_init_hw(dev);
4443 mutex_unlock(&dev->struct_mutex);
4445 i915_gem_cleanup_aliasing_ppgtt(dev);
4449 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4450 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4451 dev_priv->dri1.allow_batchbuffer = 1;
4456 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4458 drm_i915_private_t *dev_priv = dev->dev_private;
4459 struct intel_ring_buffer *ring;
4462 for_each_ring(ring, dev_priv, i)
4463 intel_cleanup_ring_buffer(ring);
4467 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4468 struct drm_file *file_priv)
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4473 if (drm_core_check_feature(dev, DRIVER_MODESET))
4476 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4477 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4478 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4481 mutex_lock(&dev->struct_mutex);
4482 dev_priv->ums.mm_suspended = 0;
4484 ret = i915_gem_init_hw(dev);
4486 mutex_unlock(&dev->struct_mutex);
4490 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4491 mutex_unlock(&dev->struct_mutex);
4493 ret = drm_irq_install(dev);
4495 goto cleanup_ringbuffer;
4500 mutex_lock(&dev->struct_mutex);
4501 i915_gem_cleanup_ringbuffer(dev);
4502 dev_priv->ums.mm_suspended = 1;
4503 mutex_unlock(&dev->struct_mutex);
4509 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4510 struct drm_file *file_priv)
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4515 if (drm_core_check_feature(dev, DRIVER_MODESET))
4518 drm_irq_uninstall(dev);
4520 mutex_lock(&dev->struct_mutex);
4521 ret = i915_gem_idle(dev);
4523 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4524 * We need to replace this with a semaphore, or something.
4525 * And not confound ums.mm_suspended!
4528 dev_priv->ums.mm_suspended = 1;
4529 mutex_unlock(&dev->struct_mutex);
4535 i915_gem_lastclose(struct drm_device *dev)
4539 if (drm_core_check_feature(dev, DRIVER_MODESET))
4542 mutex_lock(&dev->struct_mutex);
4543 ret = i915_gem_idle(dev);
4545 DRM_ERROR("failed to idle hardware: %d\n", ret);
4546 mutex_unlock(&dev->struct_mutex);
4550 init_ring_lists(struct intel_ring_buffer *ring)
4552 INIT_LIST_HEAD(&ring->active_list);
4553 INIT_LIST_HEAD(&ring->request_list);
4556 static void i915_init_vm(struct drm_i915_private *dev_priv,
4557 struct i915_address_space *vm)
4559 vm->dev = dev_priv->dev;
4560 INIT_LIST_HEAD(&vm->active_list);
4561 INIT_LIST_HEAD(&vm->inactive_list);
4562 INIT_LIST_HEAD(&vm->global_link);
4563 list_add(&vm->global_link, &dev_priv->vm_list);
4567 i915_gem_load(struct drm_device *dev)
4569 drm_i915_private_t *dev_priv = dev->dev_private;
4573 kmem_cache_create("i915_gem_object",
4574 sizeof(struct drm_i915_gem_object), 0,
4578 INIT_LIST_HEAD(&dev_priv->vm_list);
4579 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4581 INIT_LIST_HEAD(&dev_priv->context_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4583 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4584 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4585 for (i = 0; i < I915_NUM_RINGS; i++)
4586 init_ring_lists(&dev_priv->ring[i]);
4587 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4588 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4589 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4590 i915_gem_retire_work_handler);
4591 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4593 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4595 I915_WRITE(MI_ARB_STATE,
4596 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4599 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4601 /* Old X drivers will take 0-2 for front, back, depth buffers */
4602 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4603 dev_priv->fence_reg_start = 3;
4605 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4606 dev_priv->num_fence_regs = 32;
4607 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4608 dev_priv->num_fence_regs = 16;
4610 dev_priv->num_fence_regs = 8;
4612 /* Initialize fence registers to zero */
4613 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4614 i915_gem_restore_fences(dev);
4616 i915_gem_detect_bit_6_swizzle(dev);
4617 init_waitqueue_head(&dev_priv->pending_flip_queue);
4619 dev_priv->mm.interruptible = true;
4621 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4622 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4623 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4624 register_shrinker(&dev_priv->mm.inactive_shrinker);
4628 * Create a physically contiguous memory object for this object
4629 * e.g. for cursor + overlay regs
4631 static int i915_gem_init_phys_object(struct drm_device *dev,
4632 int id, int size, int align)
4634 drm_i915_private_t *dev_priv = dev->dev_private;
4635 struct drm_i915_gem_phys_object *phys_obj;
4638 if (dev_priv->mm.phys_objs[id - 1] || !size)
4641 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4647 phys_obj->handle = drm_pci_alloc(dev, size, align);
4648 if (!phys_obj->handle) {
4653 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4656 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4664 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4666 drm_i915_private_t *dev_priv = dev->dev_private;
4667 struct drm_i915_gem_phys_object *phys_obj;
4669 if (!dev_priv->mm.phys_objs[id - 1])
4672 phys_obj = dev_priv->mm.phys_objs[id - 1];
4673 if (phys_obj->cur_obj) {
4674 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4678 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4680 drm_pci_free(dev, phys_obj->handle);
4682 dev_priv->mm.phys_objs[id - 1] = NULL;
4685 void i915_gem_free_all_phys_object(struct drm_device *dev)
4689 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4690 i915_gem_free_phys_object(dev, i);
4693 void i915_gem_detach_phys_object(struct drm_device *dev,
4694 struct drm_i915_gem_object *obj)
4696 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4703 vaddr = obj->phys_obj->handle->vaddr;
4705 page_count = obj->base.size / PAGE_SIZE;
4706 for (i = 0; i < page_count; i++) {
4707 struct page *page = shmem_read_mapping_page(mapping, i);
4708 if (!IS_ERR(page)) {
4709 char *dst = kmap_atomic(page);
4710 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4713 drm_clflush_pages(&page, 1);
4715 set_page_dirty(page);
4716 mark_page_accessed(page);
4717 page_cache_release(page);
4720 i915_gem_chipset_flush(dev);
4722 obj->phys_obj->cur_obj = NULL;
4723 obj->phys_obj = NULL;
4727 i915_gem_attach_phys_object(struct drm_device *dev,
4728 struct drm_i915_gem_object *obj,
4732 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4733 drm_i915_private_t *dev_priv = dev->dev_private;
4738 if (id > I915_MAX_PHYS_OBJECT)
4741 if (obj->phys_obj) {
4742 if (obj->phys_obj->id == id)
4744 i915_gem_detach_phys_object(dev, obj);
4747 /* create a new object */
4748 if (!dev_priv->mm.phys_objs[id - 1]) {
4749 ret = i915_gem_init_phys_object(dev, id,
4750 obj->base.size, align);
4752 DRM_ERROR("failed to init phys object %d size: %zu\n",
4753 id, obj->base.size);
4758 /* bind to the object */
4759 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4760 obj->phys_obj->cur_obj = obj;
4762 page_count = obj->base.size / PAGE_SIZE;
4764 for (i = 0; i < page_count; i++) {
4768 page = shmem_read_mapping_page(mapping, i);
4770 return PTR_ERR(page);
4772 src = kmap_atomic(page);
4773 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4774 memcpy(dst, src, PAGE_SIZE);
4777 mark_page_accessed(page);
4778 page_cache_release(page);
4785 i915_gem_phys_pwrite(struct drm_device *dev,
4786 struct drm_i915_gem_object *obj,
4787 struct drm_i915_gem_pwrite *args,
4788 struct drm_file *file_priv)
4790 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4791 char __user *user_data = to_user_ptr(args->data_ptr);
4793 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4794 unsigned long unwritten;
4796 /* The physical object once assigned is fixed for the lifetime
4797 * of the obj, so we can safely drop the lock and continue
4800 mutex_unlock(&dev->struct_mutex);
4801 unwritten = copy_from_user(vaddr, user_data, args->size);
4802 mutex_lock(&dev->struct_mutex);
4807 i915_gem_chipset_flush(dev);
4811 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4813 struct drm_i915_file_private *file_priv = file->driver_priv;
4815 /* Clean up our request list when the client is going away, so that
4816 * later retire_requests won't dereference our soon-to-be-gone
4819 spin_lock(&file_priv->mm.lock);
4820 while (!list_empty(&file_priv->mm.request_list)) {
4821 struct drm_i915_gem_request *request;
4823 request = list_first_entry(&file_priv->mm.request_list,
4824 struct drm_i915_gem_request,
4826 list_del(&request->client_list);
4827 request->file_priv = NULL;
4829 spin_unlock(&file_priv->mm.lock);
4832 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4834 if (!mutex_is_locked(mutex))
4837 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4838 return mutex->owner == task;
4840 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4845 static unsigned long
4846 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4848 struct drm_i915_private *dev_priv =
4849 container_of(shrinker,
4850 struct drm_i915_private,
4851 mm.inactive_shrinker);
4852 struct drm_device *dev = dev_priv->dev;
4853 struct drm_i915_gem_object *obj;
4855 unsigned long count;
4857 if (!mutex_trylock(&dev->struct_mutex)) {
4858 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4861 if (dev_priv->mm.shrinker_no_lock_stealing)
4868 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4869 if (obj->pages_pin_count == 0)
4870 count += obj->base.size >> PAGE_SHIFT;
4872 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4876 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4877 count += obj->base.size >> PAGE_SHIFT;
4881 mutex_unlock(&dev->struct_mutex);
4885 /* All the new VM stuff */
4886 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4887 struct i915_address_space *vm)
4889 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4890 struct i915_vma *vma;
4892 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4893 vm = &dev_priv->gtt.base;
4895 BUG_ON(list_empty(&o->vma_list));
4896 list_for_each_entry(vma, &o->vma_list, vma_link) {
4898 return vma->node.start;
4904 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4905 struct i915_address_space *vm)
4907 struct i915_vma *vma;
4909 list_for_each_entry(vma, &o->vma_list, vma_link)
4910 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4916 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4918 struct i915_vma *vma;
4920 list_for_each_entry(vma, &o->vma_list, vma_link)
4921 if (drm_mm_node_allocated(&vma->node))
4927 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4928 struct i915_address_space *vm)
4930 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4931 struct i915_vma *vma;
4933 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4934 vm = &dev_priv->gtt.base;
4936 BUG_ON(list_empty(&o->vma_list));
4938 list_for_each_entry(vma, &o->vma_list, vma_link)
4940 return vma->node.size;
4945 static unsigned long
4946 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
4948 struct drm_i915_private *dev_priv =
4949 container_of(shrinker,
4950 struct drm_i915_private,
4951 mm.inactive_shrinker);
4952 struct drm_device *dev = dev_priv->dev;
4953 int nr_to_scan = sc->nr_to_scan;
4954 unsigned long freed;
4957 if (!mutex_trylock(&dev->struct_mutex)) {
4958 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4961 if (dev_priv->mm.shrinker_no_lock_stealing)
4967 freed = i915_gem_purge(dev_priv, nr_to_scan);
4968 if (freed < nr_to_scan)
4969 freed += __i915_gem_shrink(dev_priv, nr_to_scan,
4971 if (freed < nr_to_scan)
4972 freed += i915_gem_shrink_all(dev_priv);
4975 mutex_unlock(&dev->struct_mutex);