drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct drm_device *dev)
  91 {
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct completion *x = &dev_priv->error_completion;
  94         unsigned long flags;
  95         int ret;
  96
  97         if (!atomic_read(&dev_priv->mm.wedged))
  98                 return 0;
  99
 100         /*
 101          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 102          * userspace. If it takes that long something really bad is going on and
 103          * we should simply try to bail out and fail as gracefully as possible.
 104          */
 105         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
 106         if (ret == 0) {
 107                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 108                 return -EIO;
 109         } else if (ret < 0) {
 110                 return ret;
 111         }
 112
 113         if (atomic_read(&dev_priv->mm.wedged)) {
 114                 /* GPU is hung, bump the completion count to account for
 115                  * the token we just consumed so that we never hit zero and
 116                  * end up waiting upon a subsequent completion event that
 117                  * will never happen.
 118                  */
 119                 spin_lock_irqsave(&x->wait.lock, flags);
 120                 x->done++;
 121                 spin_unlock_irqrestore(&x->wait.lock, flags);
 122         }
 123         return 0;
 124 }
 125
 126 int i915_mutex_lock_interruptible(struct drm_device *dev)
 127 {
 128         int ret;
 129
 130         ret = i915_gem_wait_for_error(dev);
 131         if (ret)
 132                 return ret;
 133
 134         ret = mutex_lock_interruptible(&dev->struct_mutex);
 135         if (ret)
 136                 return ret;
 137
 138         WARN_ON(i915_verify_lists(dev));
 139         return 0;
 140 }
 141
 142 static inline bool
 143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 144 {
 145         return obj->gtt_space && !obj->active;
 146 }
 147
 148 int
 149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 150                     struct drm_file *file)
 151 {
 152         struct drm_i915_gem_init *args = data;
 153
 154         if (drm_core_check_feature(dev, DRIVER_MODESET))
 155                 return -ENODEV;
 156
 157         if (args->gtt_start >= args->gtt_end ||
 158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 159                 return -EINVAL;
 160
 161         /* GEM with user mode setting was never supported on ilk and later. */
 162         if (INTEL_INFO(dev)->gen >= 5)
 163                 return -ENODEV;
 164
 165         mutex_lock(&dev->struct_mutex);
 166         i915_gem_init_global_gtt(dev, args->gtt_start,
 167                                  args->gtt_end, args->gtt_end);
 168         mutex_unlock(&dev->struct_mutex);
 169
 170         return 0;
 171 }
 172
 173 int
 174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 175                             struct drm_file *file)
 176 {
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         struct drm_i915_gem_get_aperture *args = data;
 179         struct drm_i915_gem_object *obj;
 180         size_t pinned;
 181
 182         pinned = 0;
 183         mutex_lock(&dev->struct_mutex);
 184         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
 185                 if (obj->pin_count)
 186                         pinned += obj->gtt_space->size;
 187         mutex_unlock(&dev->struct_mutex);
 188
 189         args->aper_size = dev_priv->mm.gtt_total;
 190         args->aper_available_size = args->aper_size - pinned;
 191
 192         return 0;
 193 }
 194
 195 static int
 196 i915_gem_create(struct drm_file *file,
 197                 struct drm_device *dev,
 198                 uint64_t size,
 199                 uint32_t *handle_p)
 200 {
 201         struct drm_i915_gem_object *obj;
 202         int ret;
 203         u32 handle;
 204
 205         size = roundup(size, PAGE_SIZE);
 206         if (size == 0)
 207                 return -EINVAL;
 208
 209         /* Allocate the new object */
 210         obj = i915_gem_alloc_object(dev, size);
 211         if (obj == NULL)
 212                 return -ENOMEM;
 213
 214         ret = drm_gem_handle_create(file, &obj->base, &handle);
 215         if (ret) {
 216                 drm_gem_object_release(&obj->base);
 217                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 218                 kfree(obj);
 219                 return ret;
 220         }
 221
 222         /* drop reference from allocate - handle holds it now */
 223         drm_gem_object_unreference(&obj->base);
 224         trace_i915_gem_object_create(obj);
 225
 226         *handle_p = handle;
 227         return 0;
 228 }
 229
 230 int
 231 i915_gem_dumb_create(struct drm_file *file,
 232                      struct drm_device *dev,
 233                      struct drm_mode_create_dumb *args)
 234 {
 235         /* have to work out size/pitch and return them */
 236         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 237         args->size = args->pitch * args->height;
 238         return i915_gem_create(file, dev,
 239                                args->size, &args->handle);
 240 }
 241
 242 int i915_gem_dumb_destroy(struct drm_file *file,
 243                           struct drm_device *dev,
 244                           uint32_t handle)
 245 {
 246         return drm_gem_handle_delete(file, handle);
 247 }
 248
 249 /**
 250  * Creates a new mm object and returns a handle to it.
 251  */
 252 int
 253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 254                       struct drm_file *file)
 255 {
 256         struct drm_i915_gem_create *args = data;
 257
 258         return i915_gem_create(file, dev,
 259                                args->size, &args->handle);
 260 }
 261
 262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 263 {
 264         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 265
 266         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 267                 obj->tiling_mode != I915_TILING_NONE;
 268 }
 269
 270 static inline int
 271 __copy_to_user_swizzled(char __user *cpu_vaddr,
 272                         const char *gpu_vaddr, int gpu_offset,
 273                         int length)
 274 {
 275         int ret, cpu_offset = 0;
 276
 277         while (length > 0) {
 278                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 279                 int this_length = min(cacheline_end - gpu_offset, length);
 280                 int swizzled_gpu_offset = gpu_offset ^ 64;
 281
 282                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 283                                      gpu_vaddr + swizzled_gpu_offset,
 284                                      this_length);
 285                 if (ret)
 286                         return ret + length;
 287
 288                 cpu_offset += this_length;
 289                 gpu_offset += this_length;
 290                 length -= this_length;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static inline int
 297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 298                           const char __user *cpu_vaddr,
 299                           int length)
 300 {
 301         int ret, cpu_offset = 0;
 302
 303         while (length > 0) {
 304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 305                 int this_length = min(cacheline_end - gpu_offset, length);
 306                 int swizzled_gpu_offset = gpu_offset ^ 64;
 307
 308                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 309                                        cpu_vaddr + cpu_offset,
 310                                        this_length);
 311                 if (ret)
 312                         return ret + length;
 313
 314                 cpu_offset += this_length;
 315                 gpu_offset += this_length;
 316                 length -= this_length;
 317         }
 318
 319         return 0;
 320 }
 321
 322 /* Per-page copy function for the shmem pread fastpath.
 323  * Flushes invalid cachelines before reading the target if
 324  * needs_clflush is set. */
 325 static int
 326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 327                  char __user *user_data,
 328                  bool page_do_bit17_swizzling, bool needs_clflush)
 329 {
 330         char *vaddr;
 331         int ret;
 332
 333         if (unlikely(page_do_bit17_swizzling))
 334                 return -EINVAL;
 335
 336         vaddr = kmap_atomic(page);
 337         if (needs_clflush)
 338                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 339                                        page_length);
 340         ret = __copy_to_user_inatomic(user_data,
 341                                       vaddr + shmem_page_offset,
 342                                       page_length);
 343         kunmap_atomic(vaddr);
 344
 345         return ret ? -EFAULT : 0;
 346 }
 347
 348 static void
 349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 350                              bool swizzled)
 351 {
 352         if (unlikely(swizzled)) {
 353                 unsigned long start = (unsigned long) addr;
 354                 unsigned long end = (unsigned long) addr + length;
 355
 356                 /* For swizzling simply ensure that we always flush both
 357                  * channels. Lame, but simple and it works. Swizzled
 358                  * pwrite/pread is far from a hotpath - current userspace
 359                  * doesn't use it at all. */
 360                 start = round_down(start, 128);
 361                 end = round_up(end, 128);
 362
 363                 drm_clflush_virt_range((void *)start, end - start);
 364         } else {
 365                 drm_clflush_virt_range(addr, length);
 366         }
 367
 368 }
 369
 370 /* Only difference to the fast-path function is that this can handle bit17
 371  * and uses non-atomic copy and kmap functions. */
 372 static int
 373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 374                  char __user *user_data,
 375                  bool page_do_bit17_swizzling, bool needs_clflush)
 376 {
 377         char *vaddr;
 378         int ret;
 379
 380         vaddr = kmap(page);
 381         if (needs_clflush)
 382                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 383                                              page_length,
 384                                              page_do_bit17_swizzling);
 385
 386         if (page_do_bit17_swizzling)
 387                 ret = __copy_to_user_swizzled(user_data,
 388                                               vaddr, shmem_page_offset,
 389                                               page_length);
 390         else
 391                 ret = __copy_to_user(user_data,
 392                                      vaddr + shmem_page_offset,
 393                                      page_length);
 394         kunmap(page);
 395
 396         return ret ? - EFAULT : 0;
 397 }
 398
 399 static int
 400 i915_gem_shmem_pread(struct drm_device *dev,
 401                      struct drm_i915_gem_object *obj,
 402                      struct drm_i915_gem_pread *args,
 403                      struct drm_file *file)
 404 {
 405         char __user *user_data;
 406         ssize_t remain;
 407         loff_t offset;
 408         int shmem_page_offset, page_length, ret = 0;
 409         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 410         int hit_slowpath = 0;
 411         int prefaulted = 0;
 412         int needs_clflush = 0;
 413         struct scatterlist *sg;
 414         int i;
 415
 416         user_data = (char __user *) (uintptr_t) args->data_ptr;
 417         remain = args->size;
 418
 419         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 420
 421         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 422                 /* If we're not in the cpu read domain, set ourself into the gtt
 423                  * read domain and manually flush cachelines (if required). This
 424                  * optimizes for the case when the gpu will dirty the data
 425                  * anyway again before the next pread happens. */
 426                 if (obj->cache_level == I915_CACHE_NONE)
 427                         needs_clflush = 1;
 428                 if (obj->gtt_space) {
 429                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 430                         if (ret)
 431                                 return ret;
 432                 }
 433         }
 434
 435         ret = i915_gem_object_get_pages(obj);
 436         if (ret)
 437                 return ret;
 438
 439         i915_gem_object_pin_pages(obj);
 440
 441         offset = args->offset;
 442
 443         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 444                 struct page *page;
 445
 446                 if (i < offset >> PAGE_SHIFT)
 447                         continue;
 448
 449                 if (remain <= 0)
 450                         break;
 451
 452                 /* Operation in this page
 453                  *
 454                  * shmem_page_offset = offset within page in shmem file
 455                  * page_length = bytes to copy for this page
 456                  */
 457                 shmem_page_offset = offset_in_page(offset);
 458                 page_length = remain;
 459                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 460                         page_length = PAGE_SIZE - shmem_page_offset;
 461
 462                 page = sg_page(sg);
 463                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 464                         (page_to_phys(page) & (1 << 17)) != 0;
 465
 466                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 467                                        user_data, page_do_bit17_swizzling,
 468                                        needs_clflush);
 469                 if (ret == 0)
 470                         goto next_page;
 471
 472                 hit_slowpath = 1;
 473                 mutex_unlock(&dev->struct_mutex);
 474
 475                 if (!prefaulted) {
 476                         ret = fault_in_multipages_writeable(user_data, remain);
 477                         /* Userspace is tricking us, but we've already clobbered
 478                          * its pages with the prefault and promised to write the
 479                          * data up to the first fault. Hence ignore any errors
 480                          * and just continue. */
 481                         (void)ret;
 482                         prefaulted = 1;
 483                 }
 484
 485                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 486                                        user_data, page_do_bit17_swizzling,
 487                                        needs_clflush);
 488
 489                 mutex_lock(&dev->struct_mutex);
 490
 491 next_page:
 492                 mark_page_accessed(page);
 493
 494                 if (ret)
 495                         goto out;
 496
 497                 remain -= page_length;
 498                 user_data += page_length;
 499                 offset += page_length;
 500         }
 501
 502 out:
 503         i915_gem_object_unpin_pages(obj);
 504
 505         if (hit_slowpath) {
 506                 /* Fixup: Kill any reinstated backing storage pages */
 507                 if (obj->madv == __I915_MADV_PURGED)
 508                         i915_gem_object_truncate(obj);
 509         }
 510
 511         return ret;
 512 }
 513
 514 /**
 515  * Reads data from the object referenced by handle.
 516  *
 517  * On error, the contents of *data are undefined.
 518  */
 519 int
 520 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 521                      struct drm_file *file)
 522 {
 523         struct drm_i915_gem_pread *args = data;
 524         struct drm_i915_gem_object *obj;
 525         int ret = 0;
 526
 527         if (args->size == 0)
 528                 return 0;
 529
 530         if (!access_ok(VERIFY_WRITE,
 531                        (char __user *)(uintptr_t)args->data_ptr,
 532                        args->size))
 533                 return -EFAULT;
 534
 535         ret = i915_mutex_lock_interruptible(dev);
 536         if (ret)
 537                 return ret;
 538
 539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 540         if (&obj->base == NULL) {
 541                 ret = -ENOENT;
 542                 goto unlock;
 543         }
 544
 545         /* Bounds check source.  */
 546         if (args->offset > obj->base.size ||
 547             args->size > obj->base.size - args->offset) {
 548                 ret = -EINVAL;
 549                 goto out;
 550         }
 551
 552         /* prime objects have no backing filp to GEM pread/pwrite
 553          * pages from.
 554          */
 555         if (!obj->base.filp) {
 556                 ret = -EINVAL;
 557                 goto out;
 558         }
 559
 560         trace_i915_gem_object_pread(obj, args->offset, args->size);
 561
 562         ret = i915_gem_shmem_pread(dev, obj, args, file);
 563
 564 out:
 565         drm_gem_object_unreference(&obj->base);
 566 unlock:
 567         mutex_unlock(&dev->struct_mutex);
 568         return ret;
 569 }
 570
 571 /* This is the fast write path which cannot handle
 572  * page faults in the source data
 573  */
 574
 575 static inline int
 576 fast_user_write(struct io_mapping *mapping,
 577                 loff_t page_base, int page_offset,
 578                 char __user *user_data,
 579                 int length)
 580 {
 581         void __iomem *vaddr_atomic;
 582         void *vaddr;
 583         unsigned long unwritten;
 584
 585         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 586         /* We can use the cpu mem copy function because this is X86. */
 587         vaddr = (void __force*)vaddr_atomic + page_offset;
 588         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 589                                                       user_data, length);
 590         io_mapping_unmap_atomic(vaddr_atomic);
 591         return unwritten;
 592 }
 593
 594 /**
 595  * This is the fast pwrite path, where we copy the data directly from the
 596  * user into the GTT, uncached.
 597  */
 598 static int
 599 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 600                          struct drm_i915_gem_object *obj,
 601                          struct drm_i915_gem_pwrite *args,
 602                          struct drm_file *file)
 603 {
 604         drm_i915_private_t *dev_priv = dev->dev_private;
 605         ssize_t remain;
 606         loff_t offset, page_base;
 607         char __user *user_data;
 608         int page_offset, page_length, ret;
 609
 610         ret = i915_gem_object_pin(obj, 0, true, true);
 611         if (ret)
 612                 goto out;
 613
 614         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 615         if (ret)
 616                 goto out_unpin;
 617
 618         ret = i915_gem_object_put_fence(obj);
 619         if (ret)
 620                 goto out_unpin;
 621
 622         user_data = (char __user *) (uintptr_t) args->data_ptr;
 623         remain = args->size;
 624
 625         offset = obj->gtt_offset + args->offset;
 626
 627         while (remain > 0) {
 628                 /* Operation in this page
 629                  *
 630                  * page_base = page offset within aperture
 631                  * page_offset = offset within page
 632                  * page_length = bytes to copy for this page
 633                  */
 634                 page_base = offset & PAGE_MASK;
 635                 page_offset = offset_in_page(offset);
 636                 page_length = remain;
 637                 if ((page_offset + remain) > PAGE_SIZE)
 638                         page_length = PAGE_SIZE - page_offset;
 639
 640                 /* If we get a fault while copying data, then (presumably) our
 641                  * source page isn't available.  Return the error and we'll
 642                  * retry in the slow path.
 643                  */
 644                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 645                                     page_offset, user_data, page_length)) {
 646                         ret = -EFAULT;
 647                         goto out_unpin;
 648                 }
 649
 650                 remain -= page_length;
 651                 user_data += page_length;
 652                 offset += page_length;
 653         }
 654
 655 out_unpin:
 656         i915_gem_object_unpin(obj);
 657 out:
 658         return ret;
 659 }
 660
 661 /* Per-page copy function for the shmem pwrite fastpath.
 662  * Flushes invalid cachelines before writing to the target if
 663  * needs_clflush_before is set and flushes out any written cachelines after
 664  * writing if needs_clflush is set. */
 665 static int
 666 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 667                   char __user *user_data,
 668                   bool page_do_bit17_swizzling,
 669                   bool needs_clflush_before,
 670                   bool needs_clflush_after)
 671 {
 672         char *vaddr;
 673         int ret;
 674
 675         if (unlikely(page_do_bit17_swizzling))
 676                 return -EINVAL;
 677
 678         vaddr = kmap_atomic(page);
 679         if (needs_clflush_before)
 680                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 681                                        page_length);
 682         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 683                                                 user_data,
 684                                                 page_length);
 685         if (needs_clflush_after)
 686                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 687                                        page_length);
 688         kunmap_atomic(vaddr);
 689
 690         return ret ? -EFAULT : 0;
 691 }
 692
 693 /* Only difference to the fast-path function is that this can handle bit17
 694  * and uses non-atomic copy and kmap functions. */
 695 static int
 696 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 697                   char __user *user_data,
 698                   bool page_do_bit17_swizzling,
 699                   bool needs_clflush_before,
 700                   bool needs_clflush_after)
 701 {
 702         char *vaddr;
 703         int ret;
 704
 705         vaddr = kmap(page);
 706         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 707                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 708                                              page_length,
 709                                              page_do_bit17_swizzling);
 710         if (page_do_bit17_swizzling)
 711                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 712                                                 user_data,
 713                                                 page_length);
 714         else
 715                 ret = __copy_from_user(vaddr + shmem_page_offset,
 716                                        user_data,
 717                                        page_length);
 718         if (needs_clflush_after)
 719                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 720                                              page_length,
 721                                              page_do_bit17_swizzling);
 722         kunmap(page);
 723
 724         return ret ? -EFAULT : 0;
 725 }
 726
 727 static int
 728 i915_gem_shmem_pwrite(struct drm_device *dev,
 729                       struct drm_i915_gem_object *obj,
 730                       struct drm_i915_gem_pwrite *args,
 731                       struct drm_file *file)
 732 {
 733         ssize_t remain;
 734         loff_t offset;
 735         char __user *user_data;
 736         int shmem_page_offset, page_length, ret = 0;
 737         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 738         int hit_slowpath = 0;
 739         int needs_clflush_after = 0;
 740         int needs_clflush_before = 0;
 741         int i;
 742         struct scatterlist *sg;
 743
 744         user_data = (char __user *) (uintptr_t) args->data_ptr;
 745         remain = args->size;
 746
 747         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 748
 749         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 750                 /* If we're not in the cpu write domain, set ourself into the gtt
 751                  * write domain and manually flush cachelines (if required). This
 752                  * optimizes for the case when the gpu will use the data
 753                  * right away and we therefore have to clflush anyway. */
 754                 if (obj->cache_level == I915_CACHE_NONE)
 755                         needs_clflush_after = 1;
 756                 if (obj->gtt_space) {
 757                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 758                         if (ret)
 759                                 return ret;
 760                 }
 761         }
 762         /* Same trick applies for invalidate partially written cachelines before
 763          * writing.  */
 764         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 765             && obj->cache_level == I915_CACHE_NONE)
 766                 needs_clflush_before = 1;
 767
 768         ret = i915_gem_object_get_pages(obj);
 769         if (ret)
 770                 return ret;
 771
 772         i915_gem_object_pin_pages(obj);
 773
 774         offset = args->offset;
 775         obj->dirty = 1;
 776
 777         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 778                 struct page *page;
 779                 int partial_cacheline_write;
 780
 781                 if (i < offset >> PAGE_SHIFT)
 782                         continue;
 783
 784                 if (remain <= 0)
 785                         break;
 786
 787                 /* Operation in this page
 788                  *
 789                  * shmem_page_offset = offset within page in shmem file
 790                  * page_length = bytes to copy for this page
 791                  */
 792                 shmem_page_offset = offset_in_page(offset);
 793
 794                 page_length = remain;
 795                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 796                         page_length = PAGE_SIZE - shmem_page_offset;
 797
 798                 /* If we don't overwrite a cacheline completely we need to be
 799                  * careful to have up-to-date data by first clflushing. Don't
 800                  * overcomplicate things and flush the entire patch. */
 801                 partial_cacheline_write = needs_clflush_before &&
 802                         ((shmem_page_offset | page_length)
 803                                 & (boot_cpu_data.x86_clflush_size - 1));
 804
 805                 page = sg_page(sg);
 806                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 807                         (page_to_phys(page) & (1 << 17)) != 0;
 808
 809                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 810                                         user_data, page_do_bit17_swizzling,
 811                                         partial_cacheline_write,
 812                                         needs_clflush_after);
 813                 if (ret == 0)
 814                         goto next_page;
 815
 816                 hit_slowpath = 1;
 817                 mutex_unlock(&dev->struct_mutex);
 818                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 819                                         user_data, page_do_bit17_swizzling,
 820                                         partial_cacheline_write,
 821                                         needs_clflush_after);
 822
 823                 mutex_lock(&dev->struct_mutex);
 824
 825 next_page:
 826                 set_page_dirty(page);
 827                 mark_page_accessed(page);
 828
 829                 if (ret)
 830                         goto out;
 831
 832                 remain -= page_length;
 833                 user_data += page_length;
 834                 offset += page_length;
 835         }
 836
 837 out:
 838         i915_gem_object_unpin_pages(obj);
 839
 840         if (hit_slowpath) {
 841                 /* Fixup: Kill any reinstated backing storage pages */
 842                 if (obj->madv == __I915_MADV_PURGED)
 843                         i915_gem_object_truncate(obj);
 844                 /* and flush dirty cachelines in case the object isn't in the cpu write
 845                  * domain anymore. */
 846                 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 847                         i915_gem_clflush_object(obj);
 848                         i915_gem_chipset_flush(dev);
 849                 }
 850         }
 851
 852         if (needs_clflush_after)
 853                 i915_gem_chipset_flush(dev);
 854
 855         return ret;
 856 }
 857
 858 /**
 859  * Writes data to the object referenced by handle.
 860  *
 861  * On error, the contents of the buffer that were to be modified are undefined.
 862  */
 863 int
 864 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 865                       struct drm_file *file)
 866 {
 867         struct drm_i915_gem_pwrite *args = data;
 868         struct drm_i915_gem_object *obj;
 869         int ret;
 870
 871         if (args->size == 0)
 872                 return 0;
 873
 874         if (!access_ok(VERIFY_READ,
 875                        (char __user *)(uintptr_t)args->data_ptr,
 876                        args->size))
 877                 return -EFAULT;
 878
 879         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
 880                                            args->size);
 881         if (ret)
 882                 return -EFAULT;
 883
 884         ret = i915_mutex_lock_interruptible(dev);
 885         if (ret)
 886                 return ret;
 887
 888         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 889         if (&obj->base == NULL) {
 890                 ret = -ENOENT;
 891                 goto unlock;
 892         }
 893
 894         /* Bounds check destination. */
 895         if (args->offset > obj->base.size ||
 896             args->size > obj->base.size - args->offset) {
 897                 ret = -EINVAL;
 898                 goto out;
 899         }
 900
 901         /* prime objects have no backing filp to GEM pread/pwrite
 902          * pages from.
 903          */
 904         if (!obj->base.filp) {
 905                 ret = -EINVAL;
 906                 goto out;
 907         }
 908
 909         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 910
 911         ret = -EFAULT;
 912         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 913          * it would end up going through the fenced access, and we'll get
 914          * different detiling behavior between reading and writing.
 915          * pread/pwrite currently are reading and writing from the CPU
 916          * perspective, requiring manual detiling by the client.
 917          */
 918         if (obj->phys_obj) {
 919                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 920                 goto out;
 921         }
 922
 923         if (obj->cache_level == I915_CACHE_NONE &&
 924             obj->tiling_mode == I915_TILING_NONE &&
 925             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 926                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 927                 /* Note that the gtt paths might fail with non-page-backed user
 928                  * pointers (e.g. gtt mappings when moving data between
 929                  * textures). Fallback to the shmem path in that case. */
 930         }
 931
 932         if (ret == -EFAULT || ret == -ENOSPC)
 933                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 934
 935 out:
 936         drm_gem_object_unreference(&obj->base);
 937 unlock:
 938         mutex_unlock(&dev->struct_mutex);
 939         return ret;
 940 }
 941
 942 int
 943 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
 944                      bool interruptible)
 945 {
 946         if (atomic_read(&dev_priv->mm.wedged)) {
 947                 struct completion *x = &dev_priv->error_completion;
 948                 bool recovery_complete;
 949                 unsigned long flags;
 950
 951                 /* Give the error handler a chance to run. */
 952                 spin_lock_irqsave(&x->wait.lock, flags);
 953                 recovery_complete = x->done > 0;
 954                 spin_unlock_irqrestore(&x->wait.lock, flags);
 955
 956                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 957                  * -EIO unconditionally for these. */
 958                 if (!interruptible)
 959                         return -EIO;
 960
 961                 /* Recovery complete, but still wedged means reset failure. */
 962                 if (recovery_complete)
 963                         return -EIO;
 964
 965                 return -EAGAIN;
 966         }
 967
 968         return 0;
 969 }
 970
 971 /*
 972  * Compare seqno against outstanding lazy request. Emit a request if they are
 973  * equal.
 974  */
 975 static int
 976 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 977 {
 978         int ret;
 979
 980         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 981
 982         ret = 0;
 983         if (seqno == ring->outstanding_lazy_request)
 984                 ret = i915_add_request(ring, NULL, NULL);
 985
 986         return ret;
 987 }
 988
 989 /**
 990  * __wait_seqno - wait until execution of seqno has finished
 991  * @ring: the ring expected to report seqno
 992  * @seqno: duh!
 993  * @interruptible: do an interruptible wait (normally yes)
 994  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 995  *
 996  * Returns 0 if the seqno was found within the alloted time. Else returns the
 997  * errno with remaining time filled in timeout argument.
 998  */
 999 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1000                         bool interruptible, struct timespec *timeout)
1001 {
1002         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1003         struct timespec before, now, wait_time={1,0};
1004         unsigned long timeout_jiffies;
1005         long end;
1006         bool wait_forever = true;
1007         int ret;
1008
1009         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1010                 return 0;
1011
1012         trace_i915_gem_request_wait_begin(ring, seqno);
1013
1014         if (timeout != NULL) {
1015                 wait_time = *timeout;
1016                 wait_forever = false;
1017         }
1018
1019         timeout_jiffies = timespec_to_jiffies(&wait_time);
1020
1021         if (WARN_ON(!ring->irq_get(ring)))
1022                 return -ENODEV;
1023
1024         /* Record current time in case interrupted by signal, or wedged * */
1025         getrawmonotonic(&before);
1026
1027 #define EXIT_COND \
1028         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029         atomic_read(&dev_priv->mm.wedged))
1030         do {
1031                 if (interruptible)
1032                         end = wait_event_interruptible_timeout(ring->irq_queue,
1033                                                                EXIT_COND,
1034                                                                timeout_jiffies);
1035                 else
1036                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1037                                                  timeout_jiffies);
1038
1039                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1040                 if (ret)
1041                         end = ret;
1042         } while (end == 0 && wait_forever);
1043
1044         getrawmonotonic(&now);
1045
1046         ring->irq_put(ring);
1047         trace_i915_gem_request_wait_end(ring, seqno);
1048 #undef EXIT_COND
1049
1050         if (timeout) {
1051                 struct timespec sleep_time = timespec_sub(now, before);
1052                 *timeout = timespec_sub(*timeout, sleep_time);
1053         }
1054
1055         switch (end) {
1056         case -EIO:
1057         case -EAGAIN: /* Wedged */
1058         case -ERESTARTSYS: /* Signal */
1059                 return (int)end;
1060         case 0: /* Timeout */
1061                 if (timeout)
1062                         set_normalized_timespec(timeout, 0, 0);
1063                 return -ETIME;
1064         default: /* Completed */
1065                 WARN_ON(end < 0); /* We're not aware of other errors */
1066                 return 0;
1067         }
1068 }
1069
1070 /**
1071  * Waits for a sequence number to be signaled, and cleans up the
1072  * request and object lists appropriately for that event.
1073  */
1074 int
1075 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1076 {
1077         struct drm_device *dev = ring->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         bool interruptible = dev_priv->mm.interruptible;
1080         int ret;
1081
1082         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1083         BUG_ON(seqno == 0);
1084
1085         ret = i915_gem_check_wedge(dev_priv, interruptible);
1086         if (ret)
1087                 return ret;
1088
1089         ret = i915_gem_check_olr(ring, seqno);
1090         if (ret)
1091                 return ret;
1092
1093         return __wait_seqno(ring, seqno, interruptible, NULL);
1094 }
1095
1096 /**
1097  * Ensures that all rendering to the object has completed and the object is
1098  * safe to unbind from the GTT or access from the CPU.
1099  */
1100 static __must_check int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102                                bool readonly)
1103 {
1104         struct intel_ring_buffer *ring = obj->ring;
1105         u32 seqno;
1106         int ret;
1107
1108         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109         if (seqno == 0)
1110                 return 0;
1111
1112         ret = i915_wait_seqno(ring, seqno);
1113         if (ret)
1114                 return ret;
1115
1116         i915_gem_retire_requests_ring(ring);
1117
1118         /* Manually manage the write flush as we may have not yet
1119          * retired the buffer.
1120          */
1121         if (obj->last_write_seqno &&
1122             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1123                 obj->last_write_seqno = 0;
1124                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131  * as the object state may change during this call.
1132  */
1133 static __must_check int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1135                                             bool readonly)
1136 {
1137         struct drm_device *dev = obj->base.dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct intel_ring_buffer *ring = obj->ring;
1140         u32 seqno;
1141         int ret;
1142
1143         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1144         BUG_ON(!dev_priv->mm.interruptible);
1145
1146         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147         if (seqno == 0)
1148                 return 0;
1149
1150         ret = i915_gem_check_wedge(dev_priv, true);
1151         if (ret)
1152                 return ret;
1153
1154         ret = i915_gem_check_olr(ring, seqno);
1155         if (ret)
1156                 return ret;
1157
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161
1162         i915_gem_retire_requests_ring(ring);
1163
1164         /* Manually manage the write flush as we may have not yet
1165          * retired the buffer.
1166          */
1167         if (obj->last_write_seqno &&
1168             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1169                 obj->last_write_seqno = 0;
1170                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1171         }
1172
1173         return ret;
1174 }
1175
1176 /**
1177  * Called when user space prepares to use an object with the CPU, either
1178  * through the mmap ioctl's mapping or a GTT mapping.
1179  */
1180 int
1181 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182                           struct drm_file *file)
1183 {
1184         struct drm_i915_gem_set_domain *args = data;
1185         struct drm_i915_gem_object *obj;
1186         uint32_t read_domains = args->read_domains;
1187         uint32_t write_domain = args->write_domain;
1188         int ret;
1189
1190         /* Only handle setting domains to types used by the CPU. */
1191         if (write_domain & I915_GEM_GPU_DOMAINS)
1192                 return -EINVAL;
1193
1194         if (read_domains & I915_GEM_GPU_DOMAINS)
1195                 return -EINVAL;
1196
1197         /* Having something in the write domain implies it's in the read
1198          * domain, and only that read domain.  Enforce that in the request.
1199          */
1200         if (write_domain != 0 && read_domains != write_domain)
1201                 return -EINVAL;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 return ret;
1206
1207         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208         if (&obj->base == NULL) {
1209                 ret = -ENOENT;
1210                 goto unlock;
1211         }
1212
1213         /* Try to flush the object off the GPU without holding the lock.
1214          * We will repeat the flush holding the lock in the normal manner
1215          * to catch cases where we are gazumped.
1216          */
1217         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218         if (ret)
1219                 goto unref;
1220
1221         if (read_domains & I915_GEM_DOMAIN_GTT) {
1222                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223
1224                 /* Silently promote "you're not bound, there was nothing to do"
1225                  * to success, since the client was just asking us to
1226                  * make sure everything was done.
1227                  */
1228                 if (ret == -EINVAL)
1229                         ret = 0;
1230         } else {
1231                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232         }
1233
1234 unref:
1235         drm_gem_object_unreference(&obj->base);
1236 unlock:
1237         mutex_unlock(&dev->struct_mutex);
1238         return ret;
1239 }
1240
1241 /**
1242  * Called when user space has done writes to this buffer
1243  */
1244 int
1245 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246                          struct drm_file *file)
1247 {
1248         struct drm_i915_gem_sw_finish *args = data;
1249         struct drm_i915_gem_object *obj;
1250         int ret = 0;
1251
1252         ret = i915_mutex_lock_interruptible(dev);
1253         if (ret)
1254                 return ret;
1255
1256         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257         if (&obj->base == NULL) {
1258                 ret = -ENOENT;
1259                 goto unlock;
1260         }
1261
1262         /* Pinned buffers may be scanout, so flush the cache */
1263         if (obj->pin_count)
1264                 i915_gem_object_flush_cpu_write_domain(obj);
1265
1266         drm_gem_object_unreference(&obj->base);
1267 unlock:
1268         mutex_unlock(&dev->struct_mutex);
1269         return ret;
1270 }
1271
1272 /**
1273  * Maps the contents of an object, returning the address it is mapped
1274  * into.
1275  *
1276  * While the mapping holds a reference on the contents of the object, it doesn't
1277  * imply a ref on the object itself.
1278  */
1279 int
1280 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281                     struct drm_file *file)
1282 {
1283         struct drm_i915_gem_mmap *args = data;
1284         struct drm_gem_object *obj;
1285         unsigned long addr;
1286
1287         obj = drm_gem_object_lookup(dev, file, args->handle);
1288         if (obj == NULL)
1289                 return -ENOENT;
1290
1291         /* prime objects have no backing filp to GEM mmap
1292          * pages from.
1293          */
1294         if (!obj->filp) {
1295                 drm_gem_object_unreference_unlocked(obj);
1296                 return -EINVAL;
1297         }
1298
1299         addr = vm_mmap(obj->filp, 0, args->size,
1300                        PROT_READ | PROT_WRITE, MAP_SHARED,
1301                        args->offset);
1302         drm_gem_object_unreference_unlocked(obj);
1303         if (IS_ERR((void *)addr))
1304                 return addr;
1305
1306         args->addr_ptr = (uint64_t) addr;
1307
1308         return 0;
1309 }
1310
1311 /**
1312  * i915_gem_fault - fault a page into the GTT
1313  * vma: VMA in question
1314  * vmf: fault info
1315  *
1316  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317  * from userspace.  The fault handler takes care of binding the object to
1318  * the GTT (if needed), allocating and programming a fence register (again,
1319  * only if needed based on whether the old reg is still valid or the object
1320  * is tiled) and inserting a new PTE into the faulting process.
1321  *
1322  * Note that the faulting process may involve evicting existing objects
1323  * from the GTT and/or fence registers to make room.  So performance may
1324  * suffer if the GTT working set is large or there are few fence registers
1325  * left.
1326  */
1327 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1328 {
1329         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1330         struct drm_device *dev = obj->base.dev;
1331         drm_i915_private_t *dev_priv = dev->dev_private;
1332         pgoff_t page_offset;
1333         unsigned long pfn;
1334         int ret = 0;
1335         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336
1337         /* We don't use vmf->pgoff since that has the fake offset */
1338         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1339                 PAGE_SHIFT;
1340
1341         ret = i915_mutex_lock_interruptible(dev);
1342         if (ret)
1343                 goto out;
1344
1345         trace_i915_gem_object_fault(obj, page_offset, true, write);
1346
1347         /* Now bind it into the GTT if needed */
1348         ret = i915_gem_object_pin(obj, 0, true, false);
1349         if (ret)
1350                 goto unlock;
1351
1352         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1353         if (ret)
1354                 goto unpin;
1355
1356         ret = i915_gem_object_get_fence(obj);
1357         if (ret)
1358                 goto unpin;
1359
1360         obj->fault_mappable = true;
1361
1362         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1363                 page_offset;
1364
1365         /* Finally, remap it using the new GTT offset */
1366         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1367 unpin:
1368         i915_gem_object_unpin(obj);
1369 unlock:
1370         mutex_unlock(&dev->struct_mutex);
1371 out:
1372         switch (ret) {
1373         case -EIO:
1374                 /* If this -EIO is due to a gpu hang, give the reset code a
1375                  * chance to clean up the mess. Otherwise return the proper
1376                  * SIGBUS. */
1377                 if (!atomic_read(&dev_priv->mm.wedged))
1378                         return VM_FAULT_SIGBUS;
1379         case -EAGAIN:
1380                 /* Give the error handler a chance to run and move the
1381                  * objects off the GPU active list. Next time we service the
1382                  * fault, we should be able to transition the page into the
1383                  * GTT without touching the GPU (and so avoid further
1384                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1385                  * with coherency, just lost writes.
1386                  */
1387                 set_need_resched();
1388         case 0:
1389         case -ERESTARTSYS:
1390         case -EINTR:
1391         case -EBUSY:
1392                 /*
1393                  * EBUSY is ok: this just means that another thread
1394                  * already did the job.
1395                  */
1396                 return VM_FAULT_NOPAGE;
1397         case -ENOMEM:
1398                 return VM_FAULT_OOM;
1399         case -ENOSPC:
1400                 return VM_FAULT_SIGBUS;
1401         default:
1402                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1403                 return VM_FAULT_SIGBUS;
1404         }
1405 }
1406
1407 /**
1408  * i915_gem_release_mmap - remove physical page mappings
1409  * @obj: obj in question
1410  *
1411  * Preserve the reservation of the mmapping with the DRM core code, but
1412  * relinquish ownership of the pages back to the system.
1413  *
1414  * It is vital that we remove the page mapping if we have mapped a tiled
1415  * object through the GTT and then lose the fence register due to
1416  * resource pressure. Similarly if the object has been moved out of the
1417  * aperture, than pages mapped into userspace must be revoked. Removing the
1418  * mapping will then trigger a page fault on the next user access, allowing
1419  * fixup by i915_gem_fault().
1420  */
1421 void
1422 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1423 {
1424         if (!obj->fault_mappable)
1425                 return;
1426
1427         if (obj->base.dev->dev_mapping)
1428                 unmap_mapping_range(obj->base.dev->dev_mapping,
1429                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1430                                     obj->base.size, 1);
1431
1432         obj->fault_mappable = false;
1433 }
1434
1435 static uint32_t
1436 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1437 {
1438         uint32_t gtt_size;
1439
1440         if (INTEL_INFO(dev)->gen >= 4 ||
1441             tiling_mode == I915_TILING_NONE)
1442                 return size;
1443
1444         /* Previous chips need a power-of-two fence region when tiling */
1445         if (INTEL_INFO(dev)->gen == 3)
1446                 gtt_size = 1024*1024;
1447         else
1448                 gtt_size = 512*1024;
1449
1450         while (gtt_size < size)
1451                 gtt_size <<= 1;
1452
1453         return gtt_size;
1454 }
1455
1456 /**
1457  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458  * @obj: object to check
1459  *
1460  * Return the required GTT alignment for an object, taking into account
1461  * potential fence register mapping.
1462  */
1463 static uint32_t
1464 i915_gem_get_gtt_alignment(struct drm_device *dev,
1465                            uint32_t size,
1466                            int tiling_mode)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 /**
1484  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1485  *                                       unfenced object
1486  * @dev: the device
1487  * @size: size of the object
1488  * @tiling_mode: tiling mode of the object
1489  *
1490  * Return the required GTT alignment for an object, only taking into account
1491  * unfenced tiled surface requirements.
1492  */
1493 uint32_t
1494 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1495                                     uint32_t size,
1496                                     int tiling_mode)
1497 {
1498         /*
1499          * Minimum alignment is 4k (GTT page size) for sane hw.
1500          */
1501         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1502             tiling_mode == I915_TILING_NONE)
1503                 return 4096;
1504
1505         /* Previous hardware however needs to be aligned to a power-of-two
1506          * tile height. The simplest method for determining this is to reuse
1507          * the power-of-tile object size.
1508          */
1509         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1510 }
1511
1512 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1513 {
1514         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1515         int ret;
1516
1517         if (obj->base.map_list.map)
1518                 return 0;
1519
1520         ret = drm_gem_create_mmap_offset(&obj->base);
1521         if (ret != -ENOSPC)
1522                 return ret;
1523
1524         /* Badly fragmented mmap space? The only way we can recover
1525          * space is by destroying unwanted objects. We can't randomly release
1526          * mmap_offsets as userspace expects them to be persistent for the
1527          * lifetime of the objects. The closest we can is to release the
1528          * offsets on purgeable objects by truncating it and marking it purged,
1529          * which prevents userspace from ever using that object again.
1530          */
1531         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1532         ret = drm_gem_create_mmap_offset(&obj->base);
1533         if (ret != -ENOSPC)
1534                 return ret;
1535
1536         i915_gem_shrink_all(dev_priv);
1537         return drm_gem_create_mmap_offset(&obj->base);
1538 }
1539
1540 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1541 {
1542         if (!obj->base.map_list.map)
1543                 return;
1544
1545         drm_gem_free_mmap_offset(&obj->base);
1546 }
1547
1548 int
1549 i915_gem_mmap_gtt(struct drm_file *file,
1550                   struct drm_device *dev,
1551                   uint32_t handle,
1552                   uint64_t *offset)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_i915_gem_object *obj;
1556         int ret;
1557
1558         ret = i915_mutex_lock_interruptible(dev);
1559         if (ret)
1560                 return ret;
1561
1562         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1563         if (&obj->base == NULL) {
1564                 ret = -ENOENT;
1565                 goto unlock;
1566         }
1567
1568         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1569                 ret = -E2BIG;
1570                 goto out;
1571         }
1572
1573         if (obj->madv != I915_MADV_WILLNEED) {
1574                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1575                 ret = -EINVAL;
1576                 goto out;
1577         }
1578
1579         ret = i915_gem_object_create_mmap_offset(obj);
1580         if (ret)
1581                 goto out;
1582
1583         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1584
1585 out:
1586         drm_gem_object_unreference(&obj->base);
1587 unlock:
1588         mutex_unlock(&dev->struct_mutex);
1589         return ret;
1590 }
1591
1592 /**
1593  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1594  * @dev: DRM device
1595  * @data: GTT mapping ioctl data
1596  * @file: GEM object info
1597  *
1598  * Simply returns the fake offset to userspace so it can mmap it.
1599  * The mmap call will end up in drm_gem_mmap(), which will set things
1600  * up so we can get faults in the handler above.
1601  *
1602  * The fault handler will take care of binding the object into the GTT
1603  * (since it may have been evicted to make room for something), allocating
1604  * a fence register, and mapping the appropriate aperture address into
1605  * userspace.
1606  */
1607 int
1608 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1609                         struct drm_file *file)
1610 {
1611         struct drm_i915_gem_mmap_gtt *args = data;
1612
1613         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1614 }
1615
1616 /* Immediately discard the backing storage */
1617 static void
1618 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1619 {
1620         struct inode *inode;
1621
1622         i915_gem_object_free_mmap_offset(obj);
1623
1624         if (obj->base.filp == NULL)
1625                 return;
1626
1627         /* Our goal here is to return as much of the memory as
1628          * is possible back to the system as we are called from OOM.
1629          * To do this we must instruct the shmfs to drop all of its
1630          * backing pages, *now*.
1631          */
1632         inode = obj->base.filp->f_path.dentry->d_inode;
1633         shmem_truncate_range(inode, 0, (loff_t)-1);
1634
1635         obj->madv = __I915_MADV_PURGED;
1636 }
1637
1638 static inline int
1639 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1640 {
1641         return obj->madv == I915_MADV_DONTNEED;
1642 }
1643
1644 static void
1645 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1646 {
1647         int page_count = obj->base.size / PAGE_SIZE;
1648         struct scatterlist *sg;
1649         int ret, i;
1650
1651         BUG_ON(obj->madv == __I915_MADV_PURGED);
1652
1653         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1654         if (ret) {
1655                 /* In the event of a disaster, abandon all caches and
1656                  * hope for the best.
1657                  */
1658                 WARN_ON(ret != -EIO);
1659                 i915_gem_clflush_object(obj);
1660                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1661         }
1662
1663         if (i915_gem_object_needs_bit17_swizzle(obj))
1664                 i915_gem_object_save_bit_17_swizzle(obj);
1665
1666         if (obj->madv == I915_MADV_DONTNEED)
1667                 obj->dirty = 0;
1668
1669         for_each_sg(obj->pages->sgl, sg, page_count, i) {
1670                 struct page *page = sg_page(sg);
1671
1672                 if (obj->dirty)
1673                         set_page_dirty(page);
1674
1675                 if (obj->madv == I915_MADV_WILLNEED)
1676                         mark_page_accessed(page);
1677
1678                 page_cache_release(page);
1679         }
1680         obj->dirty = 0;
1681
1682         sg_free_table(obj->pages);
1683         kfree(obj->pages);
1684 }
1685
1686 static int
1687 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1688 {
1689         const struct drm_i915_gem_object_ops *ops = obj->ops;
1690
1691         if (obj->pages == NULL)
1692                 return 0;
1693
1694         BUG_ON(obj->gtt_space);
1695
1696         if (obj->pages_pin_count)
1697                 return -EBUSY;
1698
1699         /* ->put_pages might need to allocate memory for the bit17 swizzle
1700          * array, hence protect them from being reaped by removing them from gtt
1701          * lists early. */
1702         list_del(&obj->gtt_list);
1703
1704         ops->put_pages(obj);
1705         obj->pages = NULL;
1706
1707         if (i915_gem_object_is_purgeable(obj))
1708                 i915_gem_object_truncate(obj);
1709
1710         return 0;
1711 }
1712
1713 static long
1714 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1715 {
1716         struct drm_i915_gem_object *obj, *next;
1717         long count = 0;
1718
1719         list_for_each_entry_safe(obj, next,
1720                                  &dev_priv->mm.unbound_list,
1721                                  gtt_list) {
1722                 if (i915_gem_object_is_purgeable(obj) &&
1723                     i915_gem_object_put_pages(obj) == 0) {
1724                         count += obj->base.size >> PAGE_SHIFT;
1725                         if (count >= target)
1726                                 return count;
1727                 }
1728         }
1729
1730         list_for_each_entry_safe(obj, next,
1731                                  &dev_priv->mm.inactive_list,
1732                                  mm_list) {
1733                 if (i915_gem_object_is_purgeable(obj) &&
1734                     i915_gem_object_unbind(obj) == 0 &&
1735                     i915_gem_object_put_pages(obj) == 0) {
1736                         count += obj->base.size >> PAGE_SHIFT;
1737                         if (count >= target)
1738                                 return count;
1739                 }
1740         }
1741
1742         return count;
1743 }
1744
1745 static void
1746 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1747 {
1748         struct drm_i915_gem_object *obj, *next;
1749
1750         i915_gem_evict_everything(dev_priv->dev);
1751
1752         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1753                 i915_gem_object_put_pages(obj);
1754 }
1755
1756 static int
1757 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1758 {
1759         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1760         int page_count, i;
1761         struct address_space *mapping;
1762         struct sg_table *st;
1763         struct scatterlist *sg;
1764         struct page *page;
1765         gfp_t gfp;
1766
1767         /* Assert that the object is not currently in any GPU domain. As it
1768          * wasn't in the GTT, there shouldn't be any way it could have been in
1769          * a GPU cache
1770          */
1771         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1772         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1773
1774         st = kmalloc(sizeof(*st), GFP_KERNEL);
1775         if (st == NULL)
1776                 return -ENOMEM;
1777
1778         page_count = obj->base.size / PAGE_SIZE;
1779         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1780                 sg_free_table(st);
1781                 kfree(st);
1782                 return -ENOMEM;
1783         }
1784
1785         /* Get the list of pages out of our struct file.  They'll be pinned
1786          * at this point until we release them.
1787          *
1788          * Fail silently without starting the shrinker
1789          */
1790         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1791         gfp = mapping_gfp_mask(mapping);
1792         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1793         gfp &= ~(__GFP_IO | __GFP_WAIT);
1794         for_each_sg(st->sgl, sg, page_count, i) {
1795                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1796                 if (IS_ERR(page)) {
1797                         i915_gem_purge(dev_priv, page_count);
1798                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1799                 }
1800                 if (IS_ERR(page)) {
1801                         /* We've tried hard to allocate the memory by reaping
1802                          * our own buffer, now let the real VM do its job and
1803                          * go down in flames if truly OOM.
1804                          */
1805                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1806                         gfp |= __GFP_IO | __GFP_WAIT;
1807
1808                         i915_gem_shrink_all(dev_priv);
1809                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1810                         if (IS_ERR(page))
1811                                 goto err_pages;
1812
1813                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1814                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1815                 }
1816
1817                 sg_set_page(sg, page, PAGE_SIZE, 0);
1818         }
1819
1820         obj->pages = st;
1821
1822         if (i915_gem_object_needs_bit17_swizzle(obj))
1823                 i915_gem_object_do_bit_17_swizzle(obj);
1824
1825         return 0;
1826
1827 err_pages:
1828         for_each_sg(st->sgl, sg, i, page_count)
1829                 page_cache_release(sg_page(sg));
1830         sg_free_table(st);
1831         kfree(st);
1832         return PTR_ERR(page);
1833 }
1834
1835 /* Ensure that the associated pages are gathered from the backing storage
1836  * and pinned into our object. i915_gem_object_get_pages() may be called
1837  * multiple times before they are released by a single call to
1838  * i915_gem_object_put_pages() - once the pages are no longer referenced
1839  * either as a result of memory pressure (reaping pages under the shrinker)
1840  * or as the object is itself released.
1841  */
1842 int
1843 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1844 {
1845         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1846         const struct drm_i915_gem_object_ops *ops = obj->ops;
1847         int ret;
1848
1849         if (obj->pages)
1850                 return 0;
1851
1852         BUG_ON(obj->pages_pin_count);
1853
1854         ret = ops->get_pages(obj);
1855         if (ret)
1856                 return ret;
1857
1858         list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1859         return 0;
1860 }
1861
1862 void
1863 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1864                                struct intel_ring_buffer *ring)
1865 {
1866         struct drm_device *dev = obj->base.dev;
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         u32 seqno = intel_ring_get_seqno(ring);
1869
1870         BUG_ON(ring == NULL);
1871         obj->ring = ring;
1872
1873         /* Add a reference if we're newly entering the active list. */
1874         if (!obj->active) {
1875                 drm_gem_object_reference(&obj->base);
1876                 obj->active = 1;
1877         }
1878
1879         /* Move from whatever list we were on to the tail of execution. */
1880         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1881         list_move_tail(&obj->ring_list, &ring->active_list);
1882
1883         obj->last_read_seqno = seqno;
1884
1885         if (obj->fenced_gpu_access) {
1886                 obj->last_fenced_seqno = seqno;
1887
1888                 /* Bump MRU to take account of the delayed flush */
1889                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1890                         struct drm_i915_fence_reg *reg;
1891
1892                         reg = &dev_priv->fence_regs[obj->fence_reg];
1893                         list_move_tail(&reg->lru_list,
1894                                        &dev_priv->mm.fence_list);
1895                 }
1896         }
1897 }
1898
1899 static void
1900 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1901 {
1902         struct drm_device *dev = obj->base.dev;
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904
1905         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1906         BUG_ON(!obj->active);
1907
1908         if (obj->pin_count) /* are we a framebuffer? */
1909                 intel_mark_fb_idle(obj);
1910
1911         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1912
1913         list_del_init(&obj->ring_list);
1914         obj->ring = NULL;
1915
1916         obj->last_read_seqno = 0;
1917         obj->last_write_seqno = 0;
1918         obj->base.write_domain = 0;
1919
1920         obj->last_fenced_seqno = 0;
1921         obj->fenced_gpu_access = false;
1922
1923         obj->active = 0;
1924         drm_gem_object_unreference(&obj->base);
1925
1926         WARN_ON(i915_verify_lists(dev));
1927 }
1928
1929 static int
1930 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1931 {
1932         struct drm_i915_private *dev_priv = dev->dev_private;
1933         struct intel_ring_buffer *ring;
1934         int ret, i, j;
1935
1936         /* The hardware uses various monotonic 32-bit counters, if we
1937          * detect that they will wraparound we need to idle the GPU
1938          * and reset those counters.
1939          */
1940         ret = 0;
1941         for_each_ring(ring, dev_priv, i) {
1942                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1943                         ret |= ring->sync_seqno[j] != 0;
1944         }
1945         if (ret == 0)
1946                 return ret;
1947
1948         ret = i915_gpu_idle(dev);
1949         if (ret)
1950                 return ret;
1951
1952         i915_gem_retire_requests(dev);
1953         for_each_ring(ring, dev_priv, i) {
1954                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1955                         ring->sync_seqno[j] = 0;
1956         }
1957
1958         return 0;
1959 }
1960
1961 int
1962 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1963 {
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965
1966         /* reserve 0 for non-seqno */
1967         if (dev_priv->next_seqno == 0) {
1968                 int ret = i915_gem_handle_seqno_wrap(dev);
1969                 if (ret)
1970                         return ret;
1971
1972                 dev_priv->next_seqno = 1;
1973         }
1974
1975         *seqno = dev_priv->next_seqno++;
1976         return 0;
1977 }
1978
1979 int
1980 i915_add_request(struct intel_ring_buffer *ring,
1981                  struct drm_file *file,
1982                  u32 *out_seqno)
1983 {
1984         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1985         struct drm_i915_gem_request *request;
1986         u32 request_ring_position;
1987         int was_empty;
1988         int ret;
1989
1990         /*
1991          * Emit any outstanding flushes - execbuf can fail to emit the flush
1992          * after having emitted the batchbuffer command. Hence we need to fix
1993          * things up similar to emitting the lazy request. The difference here
1994          * is that the flush _must_ happen before the next request, no matter
1995          * what.
1996          */
1997         ret = intel_ring_flush_all_caches(ring);
1998         if (ret)
1999                 return ret;
2000
2001         request = kmalloc(sizeof(*request), GFP_KERNEL);
2002         if (request == NULL)
2003                 return -ENOMEM;
2004
2005
2006         /* Record the position of the start of the request so that
2007          * should we detect the updated seqno part-way through the
2008          * GPU processing the request, we never over-estimate the
2009          * position of the head.
2010          */
2011         request_ring_position = intel_ring_get_tail(ring);
2012
2013         ret = ring->add_request(ring);
2014         if (ret) {
2015                 kfree(request);
2016                 return ret;
2017         }
2018
2019         request->seqno = intel_ring_get_seqno(ring);
2020         request->ring = ring;
2021         request->tail = request_ring_position;
2022         request->emitted_jiffies = jiffies;
2023         was_empty = list_empty(&ring->request_list);
2024         list_add_tail(&request->list, &ring->request_list);
2025         request->file_priv = NULL;
2026
2027         if (file) {
2028                 struct drm_i915_file_private *file_priv = file->driver_priv;
2029
2030                 spin_lock(&file_priv->mm.lock);
2031                 request->file_priv = file_priv;
2032                 list_add_tail(&request->client_list,
2033                               &file_priv->mm.request_list);
2034                 spin_unlock(&file_priv->mm.lock);
2035         }
2036
2037         trace_i915_gem_request_add(ring, request->seqno);
2038         ring->outstanding_lazy_request = 0;
2039
2040         if (!dev_priv->mm.suspended) {
2041                 if (i915_enable_hangcheck) {
2042                         mod_timer(&dev_priv->hangcheck_timer,
2043                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2044                 }
2045                 if (was_empty) {
2046                         queue_delayed_work(dev_priv->wq,
2047                                            &dev_priv->mm.retire_work,
2048                                            round_jiffies_up_relative(HZ));
2049                         intel_mark_busy(dev_priv->dev);
2050                 }
2051         }
2052
2053         if (out_seqno)
2054                 *out_seqno = request->seqno;
2055         return 0;
2056 }
2057
2058 static inline void
2059 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2060 {
2061         struct drm_i915_file_private *file_priv = request->file_priv;
2062
2063         if (!file_priv)
2064                 return;
2065
2066         spin_lock(&file_priv->mm.lock);
2067         if (request->file_priv) {
2068                 list_del(&request->client_list);
2069                 request->file_priv = NULL;
2070         }
2071         spin_unlock(&file_priv->mm.lock);
2072 }
2073
2074 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2075                                       struct intel_ring_buffer *ring)
2076 {
2077         while (!list_empty(&ring->request_list)) {
2078                 struct drm_i915_gem_request *request;
2079
2080                 request = list_first_entry(&ring->request_list,
2081                                            struct drm_i915_gem_request,
2082                                            list);
2083
2084                 list_del(&request->list);
2085                 i915_gem_request_remove_from_client(request);
2086                 kfree(request);
2087         }
2088
2089         while (!list_empty(&ring->active_list)) {
2090                 struct drm_i915_gem_object *obj;
2091
2092                 obj = list_first_entry(&ring->active_list,
2093                                        struct drm_i915_gem_object,
2094                                        ring_list);
2095
2096                 i915_gem_object_move_to_inactive(obj);
2097         }
2098 }
2099
2100 static void i915_gem_reset_fences(struct drm_device *dev)
2101 {
2102         struct drm_i915_private *dev_priv = dev->dev_private;
2103         int i;
2104
2105         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2106                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2107
2108                 i915_gem_write_fence(dev, i, NULL);
2109
2110                 if (reg->obj)
2111                         i915_gem_object_fence_lost(reg->obj);
2112
2113                 reg->pin_count = 0;
2114                 reg->obj = NULL;
2115                 INIT_LIST_HEAD(&reg->lru_list);
2116         }
2117
2118         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2119 }
2120
2121 void i915_gem_reset(struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct drm_i915_gem_object *obj;
2125         struct intel_ring_buffer *ring;
2126         int i;
2127
2128         for_each_ring(ring, dev_priv, i)
2129                 i915_gem_reset_ring_lists(dev_priv, ring);
2130
2131         /* Move everything out of the GPU domains to ensure we do any
2132          * necessary invalidation upon reuse.
2133          */
2134         list_for_each_entry(obj,
2135                             &dev_priv->mm.inactive_list,
2136                             mm_list)
2137         {
2138                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2139         }
2140
2141         /* The fence registers are invalidated so clear them out */
2142         i915_gem_reset_fences(dev);
2143 }
2144
2145 /**
2146  * This function clears the request list as sequence numbers are passed.
2147  */
2148 void
2149 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2150 {
2151         uint32_t seqno;
2152
2153         if (list_empty(&ring->request_list))
2154                 return;
2155
2156         WARN_ON(i915_verify_lists(ring->dev));
2157
2158         seqno = ring->get_seqno(ring, true);
2159
2160         while (!list_empty(&ring->request_list)) {
2161                 struct drm_i915_gem_request *request;
2162
2163                 request = list_first_entry(&ring->request_list,
2164                                            struct drm_i915_gem_request,
2165                                            list);
2166
2167                 if (!i915_seqno_passed(seqno, request->seqno))
2168                         break;
2169
2170                 trace_i915_gem_request_retire(ring, request->seqno);
2171                 /* We know the GPU must have read the request to have
2172                  * sent us the seqno + interrupt, so use the position
2173                  * of tail of the request to update the last known position
2174                  * of the GPU head.
2175                  */
2176                 ring->last_retired_head = request->tail;
2177
2178                 list_del(&request->list);
2179                 i915_gem_request_remove_from_client(request);
2180                 kfree(request);
2181         }
2182
2183         /* Move any buffers on the active list that are no longer referenced
2184          * by the ringbuffer to the flushing/inactive lists as appropriate.
2185          */
2186         while (!list_empty(&ring->active_list)) {
2187                 struct drm_i915_gem_object *obj;
2188
2189                 obj = list_first_entry(&ring->active_list,
2190                                       struct drm_i915_gem_object,
2191                                       ring_list);
2192
2193                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2194                         break;
2195
2196                 i915_gem_object_move_to_inactive(obj);
2197         }
2198
2199         if (unlikely(ring->trace_irq_seqno &&
2200                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2201                 ring->irq_put(ring);
2202                 ring->trace_irq_seqno = 0;
2203         }
2204
2205         WARN_ON(i915_verify_lists(ring->dev));
2206 }
2207
2208 void
2209 i915_gem_retire_requests(struct drm_device *dev)
2210 {
2211         drm_i915_private_t *dev_priv = dev->dev_private;
2212         struct intel_ring_buffer *ring;
2213         int i;
2214
2215         for_each_ring(ring, dev_priv, i)
2216                 i915_gem_retire_requests_ring(ring);
2217 }
2218
2219 static void
2220 i915_gem_retire_work_handler(struct work_struct *work)
2221 {
2222         drm_i915_private_t *dev_priv;
2223         struct drm_device *dev;
2224         struct intel_ring_buffer *ring;
2225         bool idle;
2226         int i;
2227
2228         dev_priv = container_of(work, drm_i915_private_t,
2229                                 mm.retire_work.work);
2230         dev = dev_priv->dev;
2231
2232         /* Come back later if the device is busy... */
2233         if (!mutex_trylock(&dev->struct_mutex)) {
2234                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2235                                    round_jiffies_up_relative(HZ));
2236                 return;
2237         }
2238
2239         i915_gem_retire_requests(dev);
2240
2241         /* Send a periodic flush down the ring so we don't hold onto GEM
2242          * objects indefinitely.
2243          */
2244         idle = true;
2245         for_each_ring(ring, dev_priv, i) {
2246                 if (ring->gpu_caches_dirty)
2247                         i915_add_request(ring, NULL, NULL);
2248
2249                 idle &= list_empty(&ring->request_list);
2250         }
2251
2252         if (!dev_priv->mm.suspended && !idle)
2253                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2254                                    round_jiffies_up_relative(HZ));
2255         if (idle)
2256                 intel_mark_idle(dev);
2257
2258         mutex_unlock(&dev->struct_mutex);
2259 }
2260
2261 /**
2262  * Ensures that an object will eventually get non-busy by flushing any required
2263  * write domains, emitting any outstanding lazy request and retiring and
2264  * completed requests.
2265  */
2266 static int
2267 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2268 {
2269         int ret;
2270
2271         if (obj->active) {
2272                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2273                 if (ret)
2274                         return ret;
2275
2276                 i915_gem_retire_requests_ring(obj->ring);
2277         }
2278
2279         return 0;
2280 }
2281
2282 /**
2283  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2284  * @DRM_IOCTL_ARGS: standard ioctl arguments
2285  *
2286  * Returns 0 if successful, else an error is returned with the remaining time in
2287  * the timeout parameter.
2288  *  -ETIME: object is still busy after timeout
2289  *  -ERESTARTSYS: signal interrupted the wait
2290  *  -ENONENT: object doesn't exist
2291  * Also possible, but rare:
2292  *  -EAGAIN: GPU wedged
2293  *  -ENOMEM: damn
2294  *  -ENODEV: Internal IRQ fail
2295  *  -E?: The add request failed
2296  *
2297  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2298  * non-zero timeout parameter the wait ioctl will wait for the given number of
2299  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2300  * without holding struct_mutex the object may become re-busied before this
2301  * function completes. A similar but shorter * race condition exists in the busy
2302  * ioctl
2303  */
2304 int
2305 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2306 {
2307         struct drm_i915_gem_wait *args = data;
2308         struct drm_i915_gem_object *obj;
2309         struct intel_ring_buffer *ring = NULL;
2310         struct timespec timeout_stack, *timeout = NULL;
2311         u32 seqno = 0;
2312         int ret = 0;
2313
2314         if (args->timeout_ns >= 0) {
2315                 timeout_stack = ns_to_timespec(args->timeout_ns);
2316                 timeout = &timeout_stack;
2317         }
2318
2319         ret = i915_mutex_lock_interruptible(dev);
2320         if (ret)
2321                 return ret;
2322
2323         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2324         if (&obj->base == NULL) {
2325                 mutex_unlock(&dev->struct_mutex);
2326                 return -ENOENT;
2327         }
2328
2329         /* Need to make sure the object gets inactive eventually. */
2330         ret = i915_gem_object_flush_active(obj);
2331         if (ret)
2332                 goto out;
2333
2334         if (obj->active) {
2335                 seqno = obj->last_read_seqno;
2336                 ring = obj->ring;
2337         }
2338
2339         if (seqno == 0)
2340                  goto out;
2341
2342         /* Do this after OLR check to make sure we make forward progress polling
2343          * on this IOCTL with a 0 timeout (like busy ioctl)
2344          */
2345         if (!args->timeout_ns) {
2346                 ret = -ETIME;
2347                 goto out;
2348         }
2349
2350         drm_gem_object_unreference(&obj->base);
2351         mutex_unlock(&dev->struct_mutex);
2352
2353         ret = __wait_seqno(ring, seqno, true, timeout);
2354         if (timeout) {
2355                 WARN_ON(!timespec_valid(timeout));
2356                 args->timeout_ns = timespec_to_ns(timeout);
2357         }
2358         return ret;
2359
2360 out:
2361         drm_gem_object_unreference(&obj->base);
2362         mutex_unlock(&dev->struct_mutex);
2363         return ret;
2364 }
2365
2366 /**
2367  * i915_gem_object_sync - sync an object to a ring.
2368  *
2369  * @obj: object which may be in use on another ring.
2370  * @to: ring we wish to use the object on. May be NULL.
2371  *
2372  * This code is meant to abstract object synchronization with the GPU.
2373  * Calling with NULL implies synchronizing the object with the CPU
2374  * rather than a particular GPU ring.
2375  *
2376  * Returns 0 if successful, else propagates up the lower layer error.
2377  */
2378 int
2379 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2380                      struct intel_ring_buffer *to)
2381 {
2382         struct intel_ring_buffer *from = obj->ring;
2383         u32 seqno;
2384         int ret, idx;
2385
2386         if (from == NULL || to == from)
2387                 return 0;
2388
2389         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2390                 return i915_gem_object_wait_rendering(obj, false);
2391
2392         idx = intel_ring_sync_index(from, to);
2393
2394         seqno = obj->last_read_seqno;
2395         if (seqno <= from->sync_seqno[idx])
2396                 return 0;
2397
2398         ret = i915_gem_check_olr(obj->ring, seqno);
2399         if (ret)
2400                 return ret;
2401
2402         ret = to->sync_to(to, from, seqno);
2403         if (!ret)
2404                 /* We use last_read_seqno because sync_to()
2405                  * might have just caused seqno wrap under
2406                  * the radar.
2407                  */
2408                 from->sync_seqno[idx] = obj->last_read_seqno;
2409
2410         return ret;
2411 }
2412
2413 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2414 {
2415         u32 old_write_domain, old_read_domains;
2416
2417         /* Act a barrier for all accesses through the GTT */
2418         mb();
2419
2420         /* Force a pagefault for domain tracking on next user access */
2421         i915_gem_release_mmap(obj);
2422
2423         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2424                 return;
2425
2426         old_read_domains = obj->base.read_domains;
2427         old_write_domain = obj->base.write_domain;
2428
2429         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2430         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2431
2432         trace_i915_gem_object_change_domain(obj,
2433                                             old_read_domains,
2434                                             old_write_domain);
2435 }
2436
2437 /**
2438  * Unbinds an object from the GTT aperture.
2439  */
2440 int
2441 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2442 {
2443         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2444         int ret = 0;
2445
2446         if (obj->gtt_space == NULL)
2447                 return 0;
2448
2449         if (obj->pin_count)
2450                 return -EBUSY;
2451
2452         BUG_ON(obj->pages == NULL);
2453
2454         ret = i915_gem_object_finish_gpu(obj);
2455         if (ret)
2456                 return ret;
2457         /* Continue on if we fail due to EIO, the GPU is hung so we
2458          * should be safe and we need to cleanup or else we might
2459          * cause memory corruption through use-after-free.
2460          */
2461
2462         i915_gem_object_finish_gtt(obj);
2463
2464         /* release the fence reg _after_ flushing */
2465         ret = i915_gem_object_put_fence(obj);
2466         if (ret)
2467                 return ret;
2468
2469         trace_i915_gem_object_unbind(obj);
2470
2471         if (obj->has_global_gtt_mapping)
2472                 i915_gem_gtt_unbind_object(obj);
2473         if (obj->has_aliasing_ppgtt_mapping) {
2474                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2475                 obj->has_aliasing_ppgtt_mapping = 0;
2476         }
2477         i915_gem_gtt_finish_object(obj);
2478
2479         list_del(&obj->mm_list);
2480         list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2481         /* Avoid an unnecessary call to unbind on rebind. */
2482         obj->map_and_fenceable = true;
2483
2484         drm_mm_put_block(obj->gtt_space);
2485         obj->gtt_space = NULL;
2486         obj->gtt_offset = 0;
2487
2488         return 0;
2489 }
2490
2491 int i915_gpu_idle(struct drm_device *dev)
2492 {
2493         drm_i915_private_t *dev_priv = dev->dev_private;
2494         struct intel_ring_buffer *ring;
2495         int ret, i;
2496
2497         /* Flush everything onto the inactive list. */
2498         for_each_ring(ring, dev_priv, i) {
2499                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2500                 if (ret)
2501                         return ret;
2502
2503                 ret = intel_ring_idle(ring);
2504                 if (ret)
2505                         return ret;
2506         }
2507
2508         return 0;
2509 }
2510
2511 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2512                                         struct drm_i915_gem_object *obj)
2513 {
2514         drm_i915_private_t *dev_priv = dev->dev_private;
2515         uint64_t val;
2516
2517         if (obj) {
2518                 u32 size = obj->gtt_space->size;
2519
2520                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2521                                  0xfffff000) << 32;
2522                 val |= obj->gtt_offset & 0xfffff000;
2523                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2524                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2525
2526                 if (obj->tiling_mode == I915_TILING_Y)
2527                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2528                 val |= I965_FENCE_REG_VALID;
2529         } else
2530                 val = 0;
2531
2532         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2533         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2534 }
2535
2536 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2537                                  struct drm_i915_gem_object *obj)
2538 {
2539         drm_i915_private_t *dev_priv = dev->dev_private;
2540         uint64_t val;
2541
2542         if (obj) {
2543                 u32 size = obj->gtt_space->size;
2544
2545                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2546                                  0xfffff000) << 32;
2547                 val |= obj->gtt_offset & 0xfffff000;
2548                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2549                 if (obj->tiling_mode == I915_TILING_Y)
2550                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2551                 val |= I965_FENCE_REG_VALID;
2552         } else
2553                 val = 0;
2554
2555         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2556         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2557 }
2558
2559 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2560                                  struct drm_i915_gem_object *obj)
2561 {
2562         drm_i915_private_t *dev_priv = dev->dev_private;
2563         u32 val;
2564
2565         if (obj) {
2566                 u32 size = obj->gtt_space->size;
2567                 int pitch_val;
2568                 int tile_width;
2569
2570                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2571                      (size & -size) != size ||
2572                      (obj->gtt_offset & (size - 1)),
2573                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2574                      obj->gtt_offset, obj->map_and_fenceable, size);
2575
2576                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2577                         tile_width = 128;
2578                 else
2579                         tile_width = 512;
2580
2581                 /* Note: pitch better be a power of two tile widths */
2582                 pitch_val = obj->stride / tile_width;
2583                 pitch_val = ffs(pitch_val) - 1;
2584
2585                 val = obj->gtt_offset;
2586                 if (obj->tiling_mode == I915_TILING_Y)
2587                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2588                 val |= I915_FENCE_SIZE_BITS(size);
2589                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2590                 val |= I830_FENCE_REG_VALID;
2591         } else
2592                 val = 0;
2593
2594         if (reg < 8)
2595                 reg = FENCE_REG_830_0 + reg * 4;
2596         else
2597                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2598
2599         I915_WRITE(reg, val);
2600         POSTING_READ(reg);
2601 }
2602
2603 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2604                                 struct drm_i915_gem_object *obj)
2605 {
2606         drm_i915_private_t *dev_priv = dev->dev_private;
2607         uint32_t val;
2608
2609         if (obj) {
2610                 u32 size = obj->gtt_space->size;
2611                 uint32_t pitch_val;
2612
2613                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2614                      (size & -size) != size ||
2615                      (obj->gtt_offset & (size - 1)),
2616                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2617                      obj->gtt_offset, size);
2618
2619                 pitch_val = obj->stride / 128;
2620                 pitch_val = ffs(pitch_val) - 1;
2621
2622                 val = obj->gtt_offset;
2623                 if (obj->tiling_mode == I915_TILING_Y)
2624                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2625                 val |= I830_FENCE_SIZE_BITS(size);
2626                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2627                 val |= I830_FENCE_REG_VALID;
2628         } else
2629                 val = 0;
2630
2631         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2632         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2633 }
2634
2635 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2636                                  struct drm_i915_gem_object *obj)
2637 {
2638         switch (INTEL_INFO(dev)->gen) {
2639         case 7:
2640         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2641         case 5:
2642         case 4: i965_write_fence_reg(dev, reg, obj); break;
2643         case 3: i915_write_fence_reg(dev, reg, obj); break;
2644         case 2: i830_write_fence_reg(dev, reg, obj); break;
2645         default: break;
2646         }
2647 }
2648
2649 static inline int fence_number(struct drm_i915_private *dev_priv,
2650                                struct drm_i915_fence_reg *fence)
2651 {
2652         return fence - dev_priv->fence_regs;
2653 }
2654
2655 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2656                                          struct drm_i915_fence_reg *fence,
2657                                          bool enable)
2658 {
2659         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2660         int reg = fence_number(dev_priv, fence);
2661
2662         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2663
2664         if (enable) {
2665                 obj->fence_reg = reg;
2666                 fence->obj = obj;
2667                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2668         } else {
2669                 obj->fence_reg = I915_FENCE_REG_NONE;
2670                 fence->obj = NULL;
2671                 list_del_init(&fence->lru_list);
2672         }
2673 }
2674
2675 static int
2676 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2677 {
2678         if (obj->last_fenced_seqno) {
2679                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2680                 if (ret)
2681                         return ret;
2682
2683                 obj->last_fenced_seqno = 0;
2684         }
2685
2686         /* Ensure that all CPU reads are completed before installing a fence
2687          * and all writes before removing the fence.
2688          */
2689         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2690                 mb();
2691
2692         obj->fenced_gpu_access = false;
2693         return 0;
2694 }
2695
2696 int
2697 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2698 {
2699         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2700         int ret;
2701
2702         ret = i915_gem_object_flush_fence(obj);
2703         if (ret)
2704                 return ret;
2705
2706         if (obj->fence_reg == I915_FENCE_REG_NONE)
2707                 return 0;
2708
2709         i915_gem_object_update_fence(obj,
2710                                      &dev_priv->fence_regs[obj->fence_reg],
2711                                      false);
2712         i915_gem_object_fence_lost(obj);
2713
2714         return 0;
2715 }
2716
2717 static struct drm_i915_fence_reg *
2718 i915_find_fence_reg(struct drm_device *dev)
2719 {
2720         struct drm_i915_private *dev_priv = dev->dev_private;
2721         struct drm_i915_fence_reg *reg, *avail;
2722         int i;
2723
2724         /* First try to find a free reg */
2725         avail = NULL;
2726         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2727                 reg = &dev_priv->fence_regs[i];
2728                 if (!reg->obj)
2729                         return reg;
2730
2731                 if (!reg->pin_count)
2732                         avail = reg;
2733         }
2734
2735         if (avail == NULL)
2736                 return NULL;
2737
2738         /* None available, try to steal one or wait for a user to finish */
2739         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2740                 if (reg->pin_count)
2741                         continue;
2742
2743                 return reg;
2744         }
2745
2746         return NULL;
2747 }
2748
2749 /**
2750  * i915_gem_object_get_fence - set up fencing for an object
2751  * @obj: object to map through a fence reg
2752  *
2753  * When mapping objects through the GTT, userspace wants to be able to write
2754  * to them without having to worry about swizzling if the object is tiled.
2755  * This function walks the fence regs looking for a free one for @obj,
2756  * stealing one if it can't find any.
2757  *
2758  * It then sets up the reg based on the object's properties: address, pitch
2759  * and tiling format.
2760  *
2761  * For an untiled surface, this removes any existing fence.
2762  */
2763 int
2764 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2765 {
2766         struct drm_device *dev = obj->base.dev;
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         bool enable = obj->tiling_mode != I915_TILING_NONE;
2769         struct drm_i915_fence_reg *reg;
2770         int ret;
2771
2772         /* Have we updated the tiling parameters upon the object and so
2773          * will need to serialise the write to the associated fence register?
2774          */
2775         if (obj->fence_dirty) {
2776                 ret = i915_gem_object_flush_fence(obj);
2777                 if (ret)
2778                         return ret;
2779         }
2780
2781         /* Just update our place in the LRU if our fence is getting reused. */
2782         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2783                 reg = &dev_priv->fence_regs[obj->fence_reg];
2784                 if (!obj->fence_dirty) {
2785                         list_move_tail(&reg->lru_list,
2786                                        &dev_priv->mm.fence_list);
2787                         return 0;
2788                 }
2789         } else if (enable) {
2790                 reg = i915_find_fence_reg(dev);
2791                 if (reg == NULL)
2792                         return -EDEADLK;
2793
2794                 if (reg->obj) {
2795                         struct drm_i915_gem_object *old = reg->obj;
2796
2797                         ret = i915_gem_object_flush_fence(old);
2798                         if (ret)
2799                                 return ret;
2800
2801                         i915_gem_object_fence_lost(old);
2802                 }
2803         } else
2804                 return 0;
2805
2806         i915_gem_object_update_fence(obj, reg, enable);
2807         obj->fence_dirty = false;
2808
2809         return 0;
2810 }
2811
2812 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2813                                      struct drm_mm_node *gtt_space,
2814                                      unsigned long cache_level)
2815 {
2816         struct drm_mm_node *other;
2817
2818         /* On non-LLC machines we have to be careful when putting differing
2819          * types of snoopable memory together to avoid the prefetcher
2820          * crossing memory domains and dieing.
2821          */
2822         if (HAS_LLC(dev))
2823                 return true;
2824
2825         if (gtt_space == NULL)
2826                 return true;
2827
2828         if (list_empty(&gtt_space->node_list))
2829                 return true;
2830
2831         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2832         if (other->allocated && !other->hole_follows && other->color != cache_level)
2833                 return false;
2834
2835         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2836         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2837                 return false;
2838
2839         return true;
2840 }
2841
2842 static void i915_gem_verify_gtt(struct drm_device *dev)
2843 {
2844 #if WATCH_GTT
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct drm_i915_gem_object *obj;
2847         int err = 0;
2848
2849         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2850                 if (obj->gtt_space == NULL) {
2851                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
2852                         err++;
2853                         continue;
2854                 }
2855
2856                 if (obj->cache_level != obj->gtt_space->color) {
2857                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2858                                obj->gtt_space->start,
2859                                obj->gtt_space->start + obj->gtt_space->size,
2860                                obj->cache_level,
2861                                obj->gtt_space->color);
2862                         err++;
2863                         continue;
2864                 }
2865
2866                 if (!i915_gem_valid_gtt_space(dev,
2867                                               obj->gtt_space,
2868                                               obj->cache_level)) {
2869                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2870                                obj->gtt_space->start,
2871                                obj->gtt_space->start + obj->gtt_space->size,
2872                                obj->cache_level);
2873                         err++;
2874                         continue;
2875                 }
2876         }
2877
2878         WARN_ON(err);
2879 #endif
2880 }
2881
2882 /**
2883  * Finds free space in the GTT aperture and binds the object there.
2884  */
2885 static int
2886 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2887                             unsigned alignment,
2888                             bool map_and_fenceable,
2889                             bool nonblocking)
2890 {
2891         struct drm_device *dev = obj->base.dev;
2892         drm_i915_private_t *dev_priv = dev->dev_private;
2893         struct drm_mm_node *free_space;
2894         u32 size, fence_size, fence_alignment, unfenced_alignment;
2895         bool mappable, fenceable;
2896         int ret;
2897
2898         if (obj->madv != I915_MADV_WILLNEED) {
2899                 DRM_ERROR("Attempting to bind a purgeable object\n");
2900                 return -EINVAL;
2901         }
2902
2903         fence_size = i915_gem_get_gtt_size(dev,
2904                                            obj->base.size,
2905                                            obj->tiling_mode);
2906         fence_alignment = i915_gem_get_gtt_alignment(dev,
2907                                                      obj->base.size,
2908                                                      obj->tiling_mode);
2909         unfenced_alignment =
2910                 i915_gem_get_unfenced_gtt_alignment(dev,
2911                                                     obj->base.size,
2912                                                     obj->tiling_mode);
2913
2914         if (alignment == 0)
2915                 alignment = map_and_fenceable ? fence_alignment :
2916                                                 unfenced_alignment;
2917         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2918                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2919                 return -EINVAL;
2920         }
2921
2922         size = map_and_fenceable ? fence_size : obj->base.size;
2923
2924         /* If the object is bigger than the entire aperture, reject it early
2925          * before evicting everything in a vain attempt to find space.
2926          */
2927         if (obj->base.size >
2928             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2929                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2930                 return -E2BIG;
2931         }
2932
2933         ret = i915_gem_object_get_pages(obj);
2934         if (ret)
2935                 return ret;
2936
2937         i915_gem_object_pin_pages(obj);
2938
2939  search_free:
2940         if (map_and_fenceable)
2941                 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2942                                                                size, alignment, obj->cache_level,
2943                                                                0, dev_priv->mm.gtt_mappable_end,
2944                                                                false);
2945         else
2946                 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2947                                                       size, alignment, obj->cache_level,
2948                                                       false);
2949
2950         if (free_space != NULL) {
2951                 if (map_and_fenceable)
2952                         free_space =
2953                                 drm_mm_get_block_range_generic(free_space,
2954                                                                size, alignment, obj->cache_level,
2955                                                                0, dev_priv->mm.gtt_mappable_end,
2956                                                                false);
2957                 else
2958                         free_space =
2959                                 drm_mm_get_block_generic(free_space,
2960                                                          size, alignment, obj->cache_level,
2961                                                          false);
2962         }
2963         if (free_space == NULL) {
2964                 ret = i915_gem_evict_something(dev, size, alignment,
2965                                                obj->cache_level,
2966                                                map_and_fenceable,
2967                                                nonblocking);
2968                 if (ret) {
2969                         i915_gem_object_unpin_pages(obj);
2970                         return ret;
2971                 }
2972
2973                 goto search_free;
2974         }
2975         if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2976                                               free_space,
2977                                               obj->cache_level))) {
2978                 i915_gem_object_unpin_pages(obj);
2979                 drm_mm_put_block(free_space);
2980                 return -EINVAL;
2981         }
2982
2983         ret = i915_gem_gtt_prepare_object(obj);
2984         if (ret) {
2985                 i915_gem_object_unpin_pages(obj);
2986                 drm_mm_put_block(free_space);
2987                 return ret;
2988         }
2989
2990         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2991         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2992
2993         obj->gtt_space = free_space;
2994         obj->gtt_offset = free_space->start;
2995
2996         fenceable =
2997                 free_space->size == fence_size &&
2998                 (free_space->start & (fence_alignment - 1)) == 0;
2999
3000         mappable =
3001                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3002
3003         obj->map_and_fenceable = mappable && fenceable;
3004
3005         i915_gem_object_unpin_pages(obj);
3006         trace_i915_gem_object_bind(obj, map_and_fenceable);
3007         i915_gem_verify_gtt(dev);
3008         return 0;
3009 }
3010
3011 void
3012 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3013 {
3014         /* If we don't have a page list set up, then we're not pinned
3015          * to GPU, and we can ignore the cache flush because it'll happen
3016          * again at bind time.
3017          */
3018         if (obj->pages == NULL)
3019                 return;
3020
3021         /* If the GPU is snooping the contents of the CPU cache,
3022          * we do not need to manually clear the CPU cache lines.  However,
3023          * the caches are only snooped when the render cache is
3024          * flushed/invalidated.  As we always have to emit invalidations
3025          * and flushes when moving into and out of the RENDER domain, correct
3026          * snooping behaviour occurs naturally as the result of our domain
3027          * tracking.
3028          */
3029         if (obj->cache_level != I915_CACHE_NONE)
3030                 return;
3031
3032         trace_i915_gem_object_clflush(obj);
3033
3034         drm_clflush_sg(obj->pages);
3035 }
3036
3037 /** Flushes the GTT write domain for the object if it's dirty. */
3038 static void
3039 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3040 {
3041         uint32_t old_write_domain;
3042
3043         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3044                 return;
3045
3046         /* No actual flushing is required for the GTT write domain.  Writes
3047          * to it immediately go to main memory as far as we know, so there's
3048          * no chipset flush.  It also doesn't land in render cache.
3049          *
3050          * However, we do have to enforce the order so that all writes through
3051          * the GTT land before any writes to the device, such as updates to
3052          * the GATT itself.
3053          */
3054         wmb();
3055
3056         old_write_domain = obj->base.write_domain;
3057         obj->base.write_domain = 0;
3058
3059         trace_i915_gem_object_change_domain(obj,
3060                                             obj->base.read_domains,
3061                                             old_write_domain);
3062 }
3063
3064 /** Flushes the CPU write domain for the object if it's dirty. */
3065 static void
3066 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3067 {
3068         uint32_t old_write_domain;
3069
3070         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3071                 return;
3072
3073         i915_gem_clflush_object(obj);
3074         i915_gem_chipset_flush(obj->base.dev);
3075         old_write_domain = obj->base.write_domain;
3076         obj->base.write_domain = 0;
3077
3078         trace_i915_gem_object_change_domain(obj,
3079                                             obj->base.read_domains,
3080                                             old_write_domain);
3081 }
3082
3083 /**
3084  * Moves a single object to the GTT read, and possibly write domain.
3085  *
3086  * This function returns when the move is complete, including waiting on
3087  * flushes to occur.
3088  */
3089 int
3090 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3091 {
3092         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3093         uint32_t old_write_domain, old_read_domains;
3094         int ret;
3095
3096         /* Not valid to be called on unbound objects. */
3097         if (obj->gtt_space == NULL)
3098                 return -EINVAL;
3099
3100         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3101                 return 0;
3102
3103         ret = i915_gem_object_wait_rendering(obj, !write);
3104         if (ret)
3105                 return ret;
3106
3107         i915_gem_object_flush_cpu_write_domain(obj);
3108
3109         old_write_domain = obj->base.write_domain;
3110         old_read_domains = obj->base.read_domains;
3111
3112         /* It should now be out of any other write domains, and we can update
3113          * the domain values for our changes.
3114          */
3115         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3116         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3117         if (write) {
3118                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3119                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3120                 obj->dirty = 1;
3121         }
3122
3123         trace_i915_gem_object_change_domain(obj,
3124                                             old_read_domains,
3125                                             old_write_domain);
3126
3127         /* And bump the LRU for this access */
3128         if (i915_gem_object_is_inactive(obj))
3129                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3130
3131         return 0;
3132 }
3133
3134 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3135                                     enum i915_cache_level cache_level)
3136 {
3137         struct drm_device *dev = obj->base.dev;
3138         drm_i915_private_t *dev_priv = dev->dev_private;
3139         int ret;
3140
3141         if (obj->cache_level == cache_level)
3142                 return 0;
3143
3144         if (obj->pin_count) {
3145                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3146                 return -EBUSY;
3147         }
3148
3149         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3150                 ret = i915_gem_object_unbind(obj);
3151                 if (ret)
3152                         return ret;
3153         }
3154
3155         if (obj->gtt_space) {
3156                 ret = i915_gem_object_finish_gpu(obj);
3157                 if (ret)
3158                         return ret;
3159
3160                 i915_gem_object_finish_gtt(obj);
3161
3162                 /* Before SandyBridge, you could not use tiling or fence
3163                  * registers with snooped memory, so relinquish any fences
3164                  * currently pointing to our region in the aperture.
3165                  */
3166                 if (INTEL_INFO(dev)->gen < 6) {
3167                         ret = i915_gem_object_put_fence(obj);
3168                         if (ret)
3169                                 return ret;
3170                 }
3171
3172                 if (obj->has_global_gtt_mapping)
3173                         i915_gem_gtt_bind_object(obj, cache_level);
3174                 if (obj->has_aliasing_ppgtt_mapping)
3175                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3176                                                obj, cache_level);
3177
3178                 obj->gtt_space->color = cache_level;
3179         }
3180
3181         if (cache_level == I915_CACHE_NONE) {
3182                 u32 old_read_domains, old_write_domain;
3183
3184                 /* If we're coming from LLC cached, then we haven't
3185                  * actually been tracking whether the data is in the
3186                  * CPU cache or not, since we only allow one bit set
3187                  * in obj->write_domain and have been skipping the clflushes.
3188                  * Just set it to the CPU cache for now.
3189                  */
3190                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3191                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3192
3193                 old_read_domains = obj->base.read_domains;
3194                 old_write_domain = obj->base.write_domain;
3195
3196                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3197                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3198
3199                 trace_i915_gem_object_change_domain(obj,
3200                                                     old_read_domains,
3201                                                     old_write_domain);
3202         }
3203
3204         obj->cache_level = cache_level;
3205         i915_gem_verify_gtt(dev);
3206         return 0;
3207 }
3208
3209 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3210                                struct drm_file *file)
3211 {
3212         struct drm_i915_gem_caching *args = data;
3213         struct drm_i915_gem_object *obj;
3214         int ret;
3215
3216         ret = i915_mutex_lock_interruptible(dev);
3217         if (ret)
3218                 return ret;
3219
3220         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3221         if (&obj->base == NULL) {
3222                 ret = -ENOENT;
3223                 goto unlock;
3224         }
3225
3226         args->caching = obj->cache_level != I915_CACHE_NONE;
3227
3228         drm_gem_object_unreference(&obj->base);
3229 unlock:
3230         mutex_unlock(&dev->struct_mutex);
3231         return ret;
3232 }
3233
3234 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3235                                struct drm_file *file)
3236 {
3237         struct drm_i915_gem_caching *args = data;
3238         struct drm_i915_gem_object *obj;
3239         enum i915_cache_level level;
3240         int ret;
3241
3242         switch (args->caching) {
3243         case I915_CACHING_NONE:
3244                 level = I915_CACHE_NONE;
3245                 break;
3246         case I915_CACHING_CACHED:
3247                 level = I915_CACHE_LLC;
3248                 break;
3249         default:
3250                 return -EINVAL;
3251         }
3252
3253         ret = i915_mutex_lock_interruptible(dev);
3254         if (ret)
3255                 return ret;
3256
3257         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3258         if (&obj->base == NULL) {
3259                 ret = -ENOENT;
3260                 goto unlock;
3261         }
3262
3263         ret = i915_gem_object_set_cache_level(obj, level);
3264
3265         drm_gem_object_unreference(&obj->base);
3266 unlock:
3267         mutex_unlock(&dev->struct_mutex);
3268         return ret;
3269 }
3270
3271 /*
3272  * Prepare buffer for display plane (scanout, cursors, etc).
3273  * Can be called from an uninterruptible phase (modesetting) and allows
3274  * any flushes to be pipelined (for pageflips).
3275  */
3276 int
3277 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3278                                      u32 alignment,
3279                                      struct intel_ring_buffer *pipelined)
3280 {
3281         u32 old_read_domains, old_write_domain;
3282         int ret;
3283
3284         if (pipelined != obj->ring) {
3285                 ret = i915_gem_object_sync(obj, pipelined);
3286                 if (ret)
3287                         return ret;
3288         }
3289
3290         /* The display engine is not coherent with the LLC cache on gen6.  As
3291          * a result, we make sure that the pinning that is about to occur is
3292          * done with uncached PTEs. This is lowest common denominator for all
3293          * chipsets.
3294          *
3295          * However for gen6+, we could do better by using the GFDT bit instead
3296          * of uncaching, which would allow us to flush all the LLC-cached data
3297          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3298          */
3299         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3300         if (ret)
3301                 return ret;
3302
3303         /* As the user may map the buffer once pinned in the display plane
3304          * (e.g. libkms for the bootup splash), we have to ensure that we
3305          * always use map_and_fenceable for all scanout buffers.
3306          */
3307         ret = i915_gem_object_pin(obj, alignment, true, false);
3308         if (ret)
3309                 return ret;
3310
3311         i915_gem_object_flush_cpu_write_domain(obj);
3312
3313         old_write_domain = obj->base.write_domain;
3314         old_read_domains = obj->base.read_domains;
3315
3316         /* It should now be out of any other write domains, and we can update
3317          * the domain values for our changes.
3318          */
3319         obj->base.write_domain = 0;
3320         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3321
3322         trace_i915_gem_object_change_domain(obj,
3323                                             old_read_domains,
3324                                             old_write_domain);
3325
3326         return 0;
3327 }
3328
3329 int
3330 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3331 {
3332         int ret;
3333
3334         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3335                 return 0;
3336
3337         ret = i915_gem_object_wait_rendering(obj, false);
3338         if (ret)
3339                 return ret;
3340
3341         /* Ensure that we invalidate the GPU's caches and TLBs. */
3342         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3343         return 0;
3344 }
3345
3346 /**
3347  * Moves a single object to the CPU read, and possibly write domain.
3348  *
3349  * This function returns when the move is complete, including waiting on
3350  * flushes to occur.
3351  */
3352 int
3353 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3354 {
3355         uint32_t old_write_domain, old_read_domains;
3356         int ret;
3357
3358         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3359                 return 0;
3360
3361         ret = i915_gem_object_wait_rendering(obj, !write);
3362         if (ret)
3363                 return ret;
3364
3365         i915_gem_object_flush_gtt_write_domain(obj);
3366
3367         old_write_domain = obj->base.write_domain;
3368         old_read_domains = obj->base.read_domains;
3369
3370         /* Flush the CPU cache if it's still invalid. */
3371         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3372                 i915_gem_clflush_object(obj);
3373
3374                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3375         }
3376
3377         /* It should now be out of any other write domains, and we can update
3378          * the domain values for our changes.
3379          */
3380         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3381
3382         /* If we're writing through the CPU, then the GPU read domains will
3383          * need to be invalidated at next use.
3384          */
3385         if (write) {
3386                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3387                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3388         }
3389
3390         trace_i915_gem_object_change_domain(obj,
3391                                             old_read_domains,
3392                                             old_write_domain);
3393
3394         return 0;
3395 }
3396
3397 /* Throttle our rendering by waiting until the ring has completed our requests
3398  * emitted over 20 msec ago.
3399  *
3400  * Note that if we were to use the current jiffies each time around the loop,
3401  * we wouldn't escape the function with any frames outstanding if the time to
3402  * render a frame was over 20ms.
3403  *
3404  * This should get us reasonable parallelism between CPU and GPU but also
3405  * relatively low latency when blocking on a particular request to finish.
3406  */
3407 static int
3408 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         struct drm_i915_file_private *file_priv = file->driver_priv;
3412         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3413         struct drm_i915_gem_request *request;
3414         struct intel_ring_buffer *ring = NULL;
3415         u32 seqno = 0;
3416         int ret;
3417
3418         if (atomic_read(&dev_priv->mm.wedged))
3419                 return -EIO;
3420
3421         spin_lock(&file_priv->mm.lock);
3422         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3423                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3424                         break;
3425
3426                 ring = request->ring;
3427                 seqno = request->seqno;
3428         }
3429         spin_unlock(&file_priv->mm.lock);
3430
3431         if (seqno == 0)
3432                 return 0;
3433
3434         ret = __wait_seqno(ring, seqno, true, NULL);
3435         if (ret == 0)
3436                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3437
3438         return ret;
3439 }
3440
3441 int
3442 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3443                     uint32_t alignment,
3444                     bool map_and_fenceable,
3445                     bool nonblocking)
3446 {
3447         int ret;
3448
3449         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3450                 return -EBUSY;
3451
3452         if (obj->gtt_space != NULL) {
3453                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3454                     (map_and_fenceable && !obj->map_and_fenceable)) {
3455                         WARN(obj->pin_count,
3456                              "bo is already pinned with incorrect alignment:"
3457                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3458                              " obj->map_and_fenceable=%d\n",
3459                              obj->gtt_offset, alignment,
3460                              map_and_fenceable,
3461                              obj->map_and_fenceable);
3462                         ret = i915_gem_object_unbind(obj);
3463                         if (ret)
3464                                 return ret;
3465                 }
3466         }
3467
3468         if (obj->gtt_space == NULL) {
3469                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3470
3471                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3472                                                   map_and_fenceable,
3473                                                   nonblocking);
3474                 if (ret)
3475                         return ret;
3476
3477                 if (!dev_priv->mm.aliasing_ppgtt)
3478                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3479         }
3480
3481         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3482                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3483
3484         obj->pin_count++;
3485         obj->pin_mappable |= map_and_fenceable;
3486
3487         return 0;
3488 }
3489
3490 void
3491 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3492 {
3493         BUG_ON(obj->pin_count == 0);
3494         BUG_ON(obj->gtt_space == NULL);
3495
3496         if (--obj->pin_count == 0)
3497                 obj->pin_mappable = false;
3498 }
3499
3500 int
3501 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3502                    struct drm_file *file)
3503 {
3504         struct drm_i915_gem_pin *args = data;
3505         struct drm_i915_gem_object *obj;
3506         int ret;
3507
3508         ret = i915_mutex_lock_interruptible(dev);
3509         if (ret)
3510                 return ret;
3511
3512         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3513         if (&obj->base == NULL) {
3514                 ret = -ENOENT;
3515                 goto unlock;
3516         }
3517
3518         if (obj->madv != I915_MADV_WILLNEED) {
3519                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3520                 ret = -EINVAL;
3521                 goto out;
3522         }
3523
3524         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3525                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3526                           args->handle);
3527                 ret = -EINVAL;
3528                 goto out;
3529         }
3530
3531         obj->user_pin_count++;
3532         obj->pin_filp = file;
3533         if (obj->user_pin_count == 1) {
3534                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3535                 if (ret)
3536                         goto out;
3537         }
3538
3539         /* XXX - flush the CPU caches for pinned objects
3540          * as the X server doesn't manage domains yet
3541          */
3542         i915_gem_object_flush_cpu_write_domain(obj);
3543         args->offset = obj->gtt_offset;
3544 out:
3545         drm_gem_object_unreference(&obj->base);
3546 unlock:
3547         mutex_unlock(&dev->struct_mutex);
3548         return ret;
3549 }
3550
3551 int
3552 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3553                      struct drm_file *file)
3554 {
3555         struct drm_i915_gem_pin *args = data;
3556         struct drm_i915_gem_object *obj;
3557         int ret;
3558
3559         ret = i915_mutex_lock_interruptible(dev);
3560         if (ret)
3561                 return ret;
3562
3563         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3564         if (&obj->base == NULL) {
3565                 ret = -ENOENT;
3566                 goto unlock;
3567         }
3568
3569         if (obj->pin_filp != file) {
3570                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3571                           args->handle);
3572                 ret = -EINVAL;
3573                 goto out;
3574         }
3575         obj->user_pin_count--;
3576         if (obj->user_pin_count == 0) {
3577                 obj->pin_filp = NULL;
3578                 i915_gem_object_unpin(obj);
3579         }
3580
3581 out:
3582         drm_gem_object_unreference(&obj->base);
3583 unlock:
3584         mutex_unlock(&dev->struct_mutex);
3585         return ret;
3586 }
3587
3588 int
3589 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3590                     struct drm_file *file)
3591 {
3592         struct drm_i915_gem_busy *args = data;
3593         struct drm_i915_gem_object *obj;
3594         int ret;
3595
3596         ret = i915_mutex_lock_interruptible(dev);
3597         if (ret)
3598                 return ret;
3599
3600         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3601         if (&obj->base == NULL) {
3602                 ret = -ENOENT;
3603                 goto unlock;
3604         }
3605
3606         /* Count all active objects as busy, even if they are currently not used
3607          * by the gpu. Users of this interface expect objects to eventually
3608          * become non-busy without any further actions, therefore emit any
3609          * necessary flushes here.
3610          */
3611         ret = i915_gem_object_flush_active(obj);
3612
3613         args->busy = obj->active;
3614         if (obj->ring) {
3615                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3616                 args->busy |= intel_ring_flag(obj->ring) << 16;
3617         }
3618
3619         drm_gem_object_unreference(&obj->base);
3620 unlock:
3621         mutex_unlock(&dev->struct_mutex);
3622         return ret;
3623 }
3624
3625 int
3626 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3627                         struct drm_file *file_priv)
3628 {
3629         return i915_gem_ring_throttle(dev, file_priv);
3630 }
3631
3632 int
3633 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3634                        struct drm_file *file_priv)
3635 {
3636         struct drm_i915_gem_madvise *args = data;
3637         struct drm_i915_gem_object *obj;
3638         int ret;
3639
3640         switch (args->madv) {
3641         case I915_MADV_DONTNEED:
3642         case I915_MADV_WILLNEED:
3643             break;
3644         default:
3645             return -EINVAL;
3646         }
3647
3648         ret = i915_mutex_lock_interruptible(dev);
3649         if (ret)
3650                 return ret;
3651
3652         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3653         if (&obj->base == NULL) {
3654                 ret = -ENOENT;
3655                 goto unlock;
3656         }
3657
3658         if (obj->pin_count) {
3659                 ret = -EINVAL;
3660                 goto out;
3661         }
3662
3663         if (obj->madv != __I915_MADV_PURGED)
3664                 obj->madv = args->madv;
3665
3666         /* if the object is no longer attached, discard its backing storage */
3667         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3668                 i915_gem_object_truncate(obj);
3669
3670         args->retained = obj->madv != __I915_MADV_PURGED;
3671
3672 out:
3673         drm_gem_object_unreference(&obj->base);
3674 unlock:
3675         mutex_unlock(&dev->struct_mutex);
3676         return ret;
3677 }
3678
3679 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3680                           const struct drm_i915_gem_object_ops *ops)
3681 {
3682         INIT_LIST_HEAD(&obj->mm_list);
3683         INIT_LIST_HEAD(&obj->gtt_list);
3684         INIT_LIST_HEAD(&obj->ring_list);
3685         INIT_LIST_HEAD(&obj->exec_list);
3686
3687         obj->ops = ops;
3688
3689         obj->fence_reg = I915_FENCE_REG_NONE;
3690         obj->madv = I915_MADV_WILLNEED;
3691         /* Avoid an unnecessary call to unbind on the first bind. */
3692         obj->map_and_fenceable = true;
3693
3694         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3695 }
3696
3697 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3698         .get_pages = i915_gem_object_get_pages_gtt,
3699         .put_pages = i915_gem_object_put_pages_gtt,
3700 };
3701
3702 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3703                                                   size_t size)
3704 {
3705         struct drm_i915_gem_object *obj;
3706         struct address_space *mapping;
3707         u32 mask;
3708
3709         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3710         if (obj == NULL)
3711                 return NULL;
3712
3713         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3714                 kfree(obj);
3715                 return NULL;
3716         }
3717
3718         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3719         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3720                 /* 965gm cannot relocate objects above 4GiB. */
3721                 mask &= ~__GFP_HIGHMEM;
3722                 mask |= __GFP_DMA32;
3723         }
3724
3725         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3726         mapping_set_gfp_mask(mapping, mask);
3727
3728         i915_gem_object_init(obj, &i915_gem_object_ops);
3729
3730         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3731         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3732
3733         if (HAS_LLC(dev)) {
3734                 /* On some devices, we can have the GPU use the LLC (the CPU
3735                  * cache) for about a 10% performance improvement
3736                  * compared to uncached.  Graphics requests other than
3737                  * display scanout are coherent with the CPU in
3738                  * accessing this cache.  This means in this mode we
3739                  * don't need to clflush on the CPU side, and on the
3740                  * GPU side we only need to flush internal caches to
3741                  * get data visible to the CPU.
3742                  *
3743                  * However, we maintain the display planes as UC, and so
3744                  * need to rebind when first used as such.
3745                  */
3746                 obj->cache_level = I915_CACHE_LLC;
3747         } else
3748                 obj->cache_level = I915_CACHE_NONE;
3749
3750         return obj;
3751 }
3752
3753 int i915_gem_init_object(struct drm_gem_object *obj)
3754 {
3755         BUG();
3756
3757         return 0;
3758 }
3759
3760 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3761 {
3762         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3763         struct drm_device *dev = obj->base.dev;
3764         drm_i915_private_t *dev_priv = dev->dev_private;
3765
3766         trace_i915_gem_object_destroy(obj);
3767
3768         if (obj->phys_obj)
3769                 i915_gem_detach_phys_object(dev, obj);
3770
3771         obj->pin_count = 0;
3772         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3773                 bool was_interruptible;
3774
3775                 was_interruptible = dev_priv->mm.interruptible;
3776                 dev_priv->mm.interruptible = false;
3777
3778                 WARN_ON(i915_gem_object_unbind(obj));
3779
3780                 dev_priv->mm.interruptible = was_interruptible;
3781         }
3782
3783         obj->pages_pin_count = 0;
3784         i915_gem_object_put_pages(obj);
3785         i915_gem_object_free_mmap_offset(obj);
3786
3787         BUG_ON(obj->pages);
3788
3789         if (obj->base.import_attach)
3790                 drm_prime_gem_destroy(&obj->base, NULL);
3791
3792         drm_gem_object_release(&obj->base);
3793         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3794
3795         kfree(obj->bit_17);
3796         kfree(obj);
3797 }
3798
3799 int
3800 i915_gem_idle(struct drm_device *dev)
3801 {
3802         drm_i915_private_t *dev_priv = dev->dev_private;
3803         int ret;
3804
3805         mutex_lock(&dev->struct_mutex);
3806
3807         if (dev_priv->mm.suspended) {
3808                 mutex_unlock(&dev->struct_mutex);
3809                 return 0;
3810         }
3811
3812         ret = i915_gpu_idle(dev);
3813         if (ret) {
3814                 mutex_unlock(&dev->struct_mutex);
3815                 return ret;
3816         }
3817         i915_gem_retire_requests(dev);
3818
3819         /* Under UMS, be paranoid and evict. */
3820         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3821                 i915_gem_evict_everything(dev);
3822
3823         i915_gem_reset_fences(dev);
3824
3825         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3826          * We need to replace this with a semaphore, or something.
3827          * And not confound mm.suspended!
3828          */
3829         dev_priv->mm.suspended = 1;
3830         del_timer_sync(&dev_priv->hangcheck_timer);
3831
3832         i915_kernel_lost_context(dev);
3833         i915_gem_cleanup_ringbuffer(dev);
3834
3835         mutex_unlock(&dev->struct_mutex);
3836
3837         /* Cancel the retire work handler, which should be idle now. */
3838         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3839
3840         return 0;
3841 }
3842
3843 void i915_gem_l3_remap(struct drm_device *dev)
3844 {
3845         drm_i915_private_t *dev_priv = dev->dev_private;
3846         u32 misccpctl;
3847         int i;
3848
3849         if (!IS_IVYBRIDGE(dev))
3850                 return;
3851
3852         if (!dev_priv->l3_parity.remap_info)
3853                 return;
3854
3855         misccpctl = I915_READ(GEN7_MISCCPCTL);
3856         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3857         POSTING_READ(GEN7_MISCCPCTL);
3858
3859         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3860                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3861                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3862                         DRM_DEBUG("0x%x was already programmed to %x\n",
3863                                   GEN7_L3LOG_BASE + i, remap);
3864                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3865                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
3866                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3867         }
3868
3869         /* Make sure all the writes land before disabling dop clock gating */
3870         POSTING_READ(GEN7_L3LOG_BASE);
3871
3872         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3873 }
3874
3875 void i915_gem_init_swizzling(struct drm_device *dev)
3876 {
3877         drm_i915_private_t *dev_priv = dev->dev_private;
3878
3879         if (INTEL_INFO(dev)->gen < 5 ||
3880             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3881                 return;
3882
3883         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3884                                  DISP_TILE_SURFACE_SWIZZLING);
3885
3886         if (IS_GEN5(dev))
3887                 return;
3888
3889         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3890         if (IS_GEN6(dev))
3891                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3892         else
3893                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3894 }
3895
3896 static bool
3897 intel_enable_blt(struct drm_device *dev)
3898 {
3899         if (!HAS_BLT(dev))
3900                 return false;
3901
3902         /* The blitter was dysfunctional on early prototypes */
3903         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3904                 DRM_INFO("BLT not supported on this pre-production hardware;"
3905                          " graphics performance will be degraded.\n");
3906                 return false;
3907         }
3908
3909         return true;
3910 }
3911
3912 int
3913 i915_gem_init_hw(struct drm_device *dev)
3914 {
3915         drm_i915_private_t *dev_priv = dev->dev_private;
3916         int ret;
3917
3918         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3919                 return -EIO;
3920
3921         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3922                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3923
3924         i915_gem_l3_remap(dev);
3925
3926         i915_gem_init_swizzling(dev);
3927
3928         ret = intel_init_render_ring_buffer(dev);
3929         if (ret)
3930                 return ret;
3931
3932         if (HAS_BSD(dev)) {
3933                 ret = intel_init_bsd_ring_buffer(dev);
3934                 if (ret)
3935                         goto cleanup_render_ring;
3936         }
3937
3938         if (intel_enable_blt(dev)) {
3939                 ret = intel_init_blt_ring_buffer(dev);
3940                 if (ret)
3941                         goto cleanup_bsd_ring;
3942         }
3943
3944         dev_priv->next_seqno = 1;
3945
3946         /*
3947          * XXX: There was some w/a described somewhere suggesting loading
3948          * contexts before PPGTT.
3949          */
3950         i915_gem_context_init(dev);
3951         i915_gem_init_ppgtt(dev);
3952
3953         return 0;
3954
3955 cleanup_bsd_ring:
3956         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3957 cleanup_render_ring:
3958         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3959         return ret;
3960 }
3961
3962 static bool
3963 intel_enable_ppgtt(struct drm_device *dev)
3964 {
3965         if (i915_enable_ppgtt >= 0)
3966                 return i915_enable_ppgtt;
3967
3968 #ifdef CONFIG_INTEL_IOMMU
3969         /* Disable ppgtt on SNB if VT-d is on. */
3970         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3971                 return false;
3972 #endif
3973
3974         return true;
3975 }
3976
3977 int i915_gem_init(struct drm_device *dev)
3978 {
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980         unsigned long gtt_size, mappable_size;
3981         int ret;
3982
3983         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3984         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3985
3986         mutex_lock(&dev->struct_mutex);
3987         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3988                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3989                  * aperture accordingly when using aliasing ppgtt. */
3990                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3991
3992                 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3993
3994                 ret = i915_gem_init_aliasing_ppgtt(dev);
3995                 if (ret) {
3996                         mutex_unlock(&dev->struct_mutex);
3997                         return ret;
3998                 }
3999         } else {
4000                 /* Let GEM Manage all of the aperture.
4001                  *
4002                  * However, leave one page at the end still bound to the scratch
4003                  * page.  There are a number of places where the hardware
4004                  * apparently prefetches past the end of the object, and we've
4005                  * seen multiple hangs with the GPU head pointer stuck in a
4006                  * batchbuffer bound at the last page of the aperture.  One page
4007                  * should be enough to keep any prefetching inside of the
4008                  * aperture.
4009                  */
4010                 i915_gem_init_global_gtt(dev, 0, mappable_size,
4011                                          gtt_size);
4012         }
4013
4014         ret = i915_gem_init_hw(dev);
4015         mutex_unlock(&dev->struct_mutex);
4016         if (ret) {
4017                 i915_gem_cleanup_aliasing_ppgtt(dev);
4018                 return ret;
4019         }
4020
4021         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4022         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4023                 dev_priv->dri1.allow_batchbuffer = 1;
4024         return 0;
4025 }
4026
4027 void
4028 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4029 {
4030         drm_i915_private_t *dev_priv = dev->dev_private;
4031         struct intel_ring_buffer *ring;
4032         int i;
4033
4034         for_each_ring(ring, dev_priv, i)
4035                 intel_cleanup_ring_buffer(ring);
4036 }
4037
4038 int
4039 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4040                        struct drm_file *file_priv)
4041 {
4042         drm_i915_private_t *dev_priv = dev->dev_private;
4043         int ret;
4044
4045         if (drm_core_check_feature(dev, DRIVER_MODESET))
4046                 return 0;
4047
4048         if (atomic_read(&dev_priv->mm.wedged)) {
4049                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4050                 atomic_set(&dev_priv->mm.wedged, 0);
4051         }
4052
4053         mutex_lock(&dev->struct_mutex);
4054         dev_priv->mm.suspended = 0;
4055
4056         ret = i915_gem_init_hw(dev);
4057         if (ret != 0) {
4058                 mutex_unlock(&dev->struct_mutex);
4059                 return ret;
4060         }
4061
4062         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4063         mutex_unlock(&dev->struct_mutex);
4064
4065         ret = drm_irq_install(dev);
4066         if (ret)
4067                 goto cleanup_ringbuffer;
4068
4069         return 0;
4070
4071 cleanup_ringbuffer:
4072         mutex_lock(&dev->struct_mutex);
4073         i915_gem_cleanup_ringbuffer(dev);
4074         dev_priv->mm.suspended = 1;
4075         mutex_unlock(&dev->struct_mutex);
4076
4077         return ret;
4078 }
4079
4080 int
4081 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4082                        struct drm_file *file_priv)
4083 {
4084         if (drm_core_check_feature(dev, DRIVER_MODESET))
4085                 return 0;
4086
4087         drm_irq_uninstall(dev);
4088         return i915_gem_idle(dev);
4089 }
4090
4091 void
4092 i915_gem_lastclose(struct drm_device *dev)
4093 {
4094         int ret;
4095
4096         if (drm_core_check_feature(dev, DRIVER_MODESET))
4097                 return;
4098
4099         ret = i915_gem_idle(dev);
4100         if (ret)
4101                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4102 }
4103
4104 static void
4105 init_ring_lists(struct intel_ring_buffer *ring)
4106 {
4107         INIT_LIST_HEAD(&ring->active_list);
4108         INIT_LIST_HEAD(&ring->request_list);
4109 }
4110
4111 void
4112 i915_gem_load(struct drm_device *dev)
4113 {
4114         int i;
4115         drm_i915_private_t *dev_priv = dev->dev_private;
4116
4117         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4118         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4119         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4120         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4121         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4122         for (i = 0; i < I915_NUM_RINGS; i++)
4123                 init_ring_lists(&dev_priv->ring[i]);
4124         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4125                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4126         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4127                           i915_gem_retire_work_handler);
4128         init_completion(&dev_priv->error_completion);
4129
4130         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4131         if (IS_GEN3(dev)) {
4132                 I915_WRITE(MI_ARB_STATE,
4133                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4134         }
4135
4136         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4137
4138         /* Old X drivers will take 0-2 for front, back, depth buffers */
4139         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4140                 dev_priv->fence_reg_start = 3;
4141
4142         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4143                 dev_priv->num_fence_regs = 16;
4144         else
4145                 dev_priv->num_fence_regs = 8;
4146
4147         /* Initialize fence registers to zero */
4148         i915_gem_reset_fences(dev);
4149
4150         i915_gem_detect_bit_6_swizzle(dev);
4151         init_waitqueue_head(&dev_priv->pending_flip_queue);
4152
4153         dev_priv->mm.interruptible = true;
4154
4155         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4156         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4157         register_shrinker(&dev_priv->mm.inactive_shrinker);
4158 }
4159
4160 /*
4161  * Create a physically contiguous memory object for this object
4162  * e.g. for cursor + overlay regs
4163  */
4164 static int i915_gem_init_phys_object(struct drm_device *dev,
4165                                      int id, int size, int align)
4166 {
4167         drm_i915_private_t *dev_priv = dev->dev_private;
4168         struct drm_i915_gem_phys_object *phys_obj;
4169         int ret;
4170
4171         if (dev_priv->mm.phys_objs[id - 1] || !size)
4172                 return 0;
4173
4174         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4175         if (!phys_obj)
4176                 return -ENOMEM;
4177
4178         phys_obj->id = id;
4179
4180         phys_obj->handle = drm_pci_alloc(dev, size, align);
4181         if (!phys_obj->handle) {
4182                 ret = -ENOMEM;
4183                 goto kfree_obj;
4184         }
4185 #ifdef CONFIG_X86
4186         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4187 #endif
4188
4189         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4190
4191         return 0;
4192 kfree_obj:
4193         kfree(phys_obj);
4194         return ret;
4195 }
4196
4197 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4198 {
4199         drm_i915_private_t *dev_priv = dev->dev_private;
4200         struct drm_i915_gem_phys_object *phys_obj;
4201
4202         if (!dev_priv->mm.phys_objs[id - 1])
4203                 return;
4204
4205         phys_obj = dev_priv->mm.phys_objs[id - 1];
4206         if (phys_obj->cur_obj) {
4207                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4208         }
4209
4210 #ifdef CONFIG_X86
4211         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4212 #endif
4213         drm_pci_free(dev, phys_obj->handle);
4214         kfree(phys_obj);
4215         dev_priv->mm.phys_objs[id - 1] = NULL;
4216 }
4217
4218 void i915_gem_free_all_phys_object(struct drm_device *dev)
4219 {
4220         int i;
4221
4222         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4223                 i915_gem_free_phys_object(dev, i);
4224 }
4225
4226 void i915_gem_detach_phys_object(struct drm_device *dev,
4227                                  struct drm_i915_gem_object *obj)
4228 {
4229         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4230         char *vaddr;
4231         int i;
4232         int page_count;
4233
4234         if (!obj->phys_obj)
4235                 return;
4236         vaddr = obj->phys_obj->handle->vaddr;
4237
4238         page_count = obj->base.size / PAGE_SIZE;
4239         for (i = 0; i < page_count; i++) {
4240                 struct page *page = shmem_read_mapping_page(mapping, i);
4241                 if (!IS_ERR(page)) {
4242                         char *dst = kmap_atomic(page);
4243                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4244                         kunmap_atomic(dst);
4245
4246                         drm_clflush_pages(&page, 1);
4247
4248                         set_page_dirty(page);
4249                         mark_page_accessed(page);
4250                         page_cache_release(page);
4251                 }
4252         }
4253         i915_gem_chipset_flush(dev);
4254
4255         obj->phys_obj->cur_obj = NULL;
4256         obj->phys_obj = NULL;
4257 }
4258
4259 int
4260 i915_gem_attach_phys_object(struct drm_device *dev,
4261                             struct drm_i915_gem_object *obj,
4262                             int id,
4263                             int align)
4264 {
4265         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4266         drm_i915_private_t *dev_priv = dev->dev_private;
4267         int ret = 0;
4268         int page_count;
4269         int i;
4270
4271         if (id > I915_MAX_PHYS_OBJECT)
4272                 return -EINVAL;
4273
4274         if (obj->phys_obj) {
4275                 if (obj->phys_obj->id == id)
4276                         return 0;
4277                 i915_gem_detach_phys_object(dev, obj);
4278         }
4279
4280         /* create a new object */
4281         if (!dev_priv->mm.phys_objs[id - 1]) {
4282                 ret = i915_gem_init_phys_object(dev, id,
4283                                                 obj->base.size, align);
4284                 if (ret) {
4285                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4286                                   id, obj->base.size);
4287                         return ret;
4288                 }
4289         }
4290
4291         /* bind to the object */
4292         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4293         obj->phys_obj->cur_obj = obj;
4294
4295         page_count = obj->base.size / PAGE_SIZE;
4296
4297         for (i = 0; i < page_count; i++) {
4298                 struct page *page;
4299                 char *dst, *src;
4300
4301                 page = shmem_read_mapping_page(mapping, i);
4302                 if (IS_ERR(page))
4303                         return PTR_ERR(page);
4304
4305                 src = kmap_atomic(page);
4306                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4307                 memcpy(dst, src, PAGE_SIZE);
4308                 kunmap_atomic(src);
4309
4310                 mark_page_accessed(page);
4311                 page_cache_release(page);
4312         }
4313
4314         return 0;
4315 }
4316
4317 static int
4318 i915_gem_phys_pwrite(struct drm_device *dev,
4319                      struct drm_i915_gem_object *obj,
4320                      struct drm_i915_gem_pwrite *args,
4321                      struct drm_file *file_priv)
4322 {
4323         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4324         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4325
4326         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4327                 unsigned long unwritten;
4328
4329                 /* The physical object once assigned is fixed for the lifetime
4330                  * of the obj, so we can safely drop the lock and continue
4331                  * to access vaddr.
4332                  */
4333                 mutex_unlock(&dev->struct_mutex);
4334                 unwritten = copy_from_user(vaddr, user_data, args->size);
4335                 mutex_lock(&dev->struct_mutex);
4336                 if (unwritten)
4337                         return -EFAULT;
4338         }
4339
4340         i915_gem_chipset_flush(dev);
4341         return 0;
4342 }
4343
4344 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4345 {
4346         struct drm_i915_file_private *file_priv = file->driver_priv;
4347
4348         /* Clean up our request list when the client is going away, so that
4349          * later retire_requests won't dereference our soon-to-be-gone
4350          * file_priv.
4351          */
4352         spin_lock(&file_priv->mm.lock);
4353         while (!list_empty(&file_priv->mm.request_list)) {
4354                 struct drm_i915_gem_request *request;
4355
4356                 request = list_first_entry(&file_priv->mm.request_list,
4357                                            struct drm_i915_gem_request,
4358                                            client_list);
4359                 list_del(&request->client_list);
4360                 request->file_priv = NULL;
4361         }
4362         spin_unlock(&file_priv->mm.lock);
4363 }
4364
4365 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4366 {
4367         if (!mutex_is_locked(mutex))
4368                 return false;
4369
4370 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4371         return mutex->owner == task;
4372 #else
4373         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4374         return false;
4375 #endif
4376 }
4377
4378 static int
4379 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4380 {
4381         struct drm_i915_private *dev_priv =
4382                 container_of(shrinker,
4383                              struct drm_i915_private,
4384                              mm.inactive_shrinker);
4385         struct drm_device *dev = dev_priv->dev;
4386         struct drm_i915_gem_object *obj;
4387         int nr_to_scan = sc->nr_to_scan;
4388         bool unlock = true;
4389         int cnt;
4390
4391         if (!mutex_trylock(&dev->struct_mutex)) {
4392                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4393                         return 0;
4394
4395                 unlock = false;
4396         }
4397
4398         if (nr_to_scan) {
4399                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4400                 if (nr_to_scan > 0)
4401                         i915_gem_shrink_all(dev_priv);
4402         }
4403
4404         cnt = 0;
4405         list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4406                 if (obj->pages_pin_count == 0)
4407                         cnt += obj->base.size >> PAGE_SHIFT;
4408         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4409                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4410                         cnt += obj->base.size >> PAGE_SHIFT;
4411
4412         if (unlock)
4413                 mutex_unlock(&dev->struct_mutex);
4414         return cnt;
4415 }