2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct completion *x = &dev_priv->error_completion;
97 if (!atomic_read(&dev_priv->mm.wedged))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret < 0) {
113 if (atomic_read(&dev_priv->mm.wedged)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x->wait.lock, flags);
121 spin_unlock_irqrestore(&x->wait.lock, flags);
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
130 ret = i915_gem_wait_for_error(dev);
134 ret = mutex_lock_interruptible(&dev->struct_mutex);
138 WARN_ON(i915_verify_lists(dev));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
145 return obj->gtt_space && !obj->active;
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
168 mutex_unlock(&dev->struct_mutex);
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175 struct drm_file *file)
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct drm_i915_gem_get_aperture *args = data;
179 struct drm_i915_gem_object *obj;
183 mutex_lock(&dev->struct_mutex);
184 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
186 pinned += obj->gtt_space->size;
187 mutex_unlock(&dev->struct_mutex);
189 args->aper_size = dev_priv->mm.gtt_total;
190 args->aper_available_size = args->aper_size - pinned;
195 void *i915_gem_object_alloc(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
201 void i915_gem_object_free(struct drm_i915_gem_object *obj)
203 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
204 kmem_cache_free(dev_priv->slab, obj);
208 i915_gem_create(struct drm_file *file,
209 struct drm_device *dev,
213 struct drm_i915_gem_object *obj;
217 size = roundup(size, PAGE_SIZE);
221 /* Allocate the new object */
222 obj = i915_gem_alloc_object(dev, size);
226 ret = drm_gem_handle_create(file, &obj->base, &handle);
228 drm_gem_object_release(&obj->base);
229 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
230 i915_gem_object_free(obj);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference(&obj->base);
236 trace_i915_gem_object_create(obj);
243 i915_gem_dumb_create(struct drm_file *file,
244 struct drm_device *dev,
245 struct drm_mode_create_dumb *args)
247 /* have to work out size/pitch and return them */
248 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
249 args->size = args->pitch * args->height;
250 return i915_gem_create(file, dev,
251 args->size, &args->handle);
254 int i915_gem_dumb_destroy(struct drm_file *file,
255 struct drm_device *dev,
258 return drm_gem_handle_delete(file, handle);
262 * Creates a new mm object and returns a handle to it.
265 i915_gem_create_ioctl(struct drm_device *dev, void *data,
266 struct drm_file *file)
268 struct drm_i915_gem_create *args = data;
270 return i915_gem_create(file, dev,
271 args->size, &args->handle);
275 __copy_to_user_swizzled(char __user *cpu_vaddr,
276 const char *gpu_vaddr, int gpu_offset,
279 int ret, cpu_offset = 0;
282 int cacheline_end = ALIGN(gpu_offset + 1, 64);
283 int this_length = min(cacheline_end - gpu_offset, length);
284 int swizzled_gpu_offset = gpu_offset ^ 64;
286 ret = __copy_to_user(cpu_vaddr + cpu_offset,
287 gpu_vaddr + swizzled_gpu_offset,
292 cpu_offset += this_length;
293 gpu_offset += this_length;
294 length -= this_length;
301 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
302 const char __user *cpu_vaddr,
305 int ret, cpu_offset = 0;
308 int cacheline_end = ALIGN(gpu_offset + 1, 64);
309 int this_length = min(cacheline_end - gpu_offset, length);
310 int swizzled_gpu_offset = gpu_offset ^ 64;
312 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
313 cpu_vaddr + cpu_offset,
318 cpu_offset += this_length;
319 gpu_offset += this_length;
320 length -= this_length;
326 /* Per-page copy function for the shmem pread fastpath.
327 * Flushes invalid cachelines before reading the target if
328 * needs_clflush is set. */
330 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
331 char __user *user_data,
332 bool page_do_bit17_swizzling, bool needs_clflush)
337 if (unlikely(page_do_bit17_swizzling))
340 vaddr = kmap_atomic(page);
342 drm_clflush_virt_range(vaddr + shmem_page_offset,
344 ret = __copy_to_user_inatomic(user_data,
345 vaddr + shmem_page_offset,
347 kunmap_atomic(vaddr);
349 return ret ? -EFAULT : 0;
353 shmem_clflush_swizzled_range(char *addr, unsigned long length,
356 if (unlikely(swizzled)) {
357 unsigned long start = (unsigned long) addr;
358 unsigned long end = (unsigned long) addr + length;
360 /* For swizzling simply ensure that we always flush both
361 * channels. Lame, but simple and it works. Swizzled
362 * pwrite/pread is far from a hotpath - current userspace
363 * doesn't use it at all. */
364 start = round_down(start, 128);
365 end = round_up(end, 128);
367 drm_clflush_virt_range((void *)start, end - start);
369 drm_clflush_virt_range(addr, length);
374 /* Only difference to the fast-path function is that this can handle bit17
375 * and uses non-atomic copy and kmap functions. */
377 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
378 char __user *user_data,
379 bool page_do_bit17_swizzling, bool needs_clflush)
386 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
388 page_do_bit17_swizzling);
390 if (page_do_bit17_swizzling)
391 ret = __copy_to_user_swizzled(user_data,
392 vaddr, shmem_page_offset,
395 ret = __copy_to_user(user_data,
396 vaddr + shmem_page_offset,
400 return ret ? - EFAULT : 0;
404 i915_gem_shmem_pread(struct drm_device *dev,
405 struct drm_i915_gem_object *obj,
406 struct drm_i915_gem_pread *args,
407 struct drm_file *file)
409 char __user *user_data;
412 int shmem_page_offset, page_length, ret = 0;
413 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
415 int needs_clflush = 0;
416 struct scatterlist *sg;
419 user_data = (char __user *) (uintptr_t) args->data_ptr;
422 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
424 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
425 /* If we're not in the cpu read domain, set ourself into the gtt
426 * read domain and manually flush cachelines (if required). This
427 * optimizes for the case when the gpu will dirty the data
428 * anyway again before the next pread happens. */
429 if (obj->cache_level == I915_CACHE_NONE)
431 if (obj->gtt_space) {
432 ret = i915_gem_object_set_to_gtt_domain(obj, false);
438 ret = i915_gem_object_get_pages(obj);
442 i915_gem_object_pin_pages(obj);
444 offset = args->offset;
446 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
449 if (i < offset >> PAGE_SHIFT)
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset = offset_in_page(offset);
461 page_length = remain;
462 if ((shmem_page_offset + page_length) > PAGE_SIZE)
463 page_length = PAGE_SIZE - shmem_page_offset;
466 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
467 (page_to_phys(page) & (1 << 17)) != 0;
469 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
470 user_data, page_do_bit17_swizzling,
475 mutex_unlock(&dev->struct_mutex);
478 ret = fault_in_multipages_writeable(user_data, remain);
479 /* Userspace is tricking us, but we've already clobbered
480 * its pages with the prefault and promised to write the
481 * data up to the first fault. Hence ignore any errors
482 * and just continue. */
487 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
488 user_data, page_do_bit17_swizzling,
491 mutex_lock(&dev->struct_mutex);
494 mark_page_accessed(page);
499 remain -= page_length;
500 user_data += page_length;
501 offset += page_length;
505 i915_gem_object_unpin_pages(obj);
511 * Reads data from the object referenced by handle.
513 * On error, the contents of *data are undefined.
516 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
517 struct drm_file *file)
519 struct drm_i915_gem_pread *args = data;
520 struct drm_i915_gem_object *obj;
526 if (!access_ok(VERIFY_WRITE,
527 (char __user *)(uintptr_t)args->data_ptr,
531 ret = i915_mutex_lock_interruptible(dev);
535 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
536 if (&obj->base == NULL) {
541 /* Bounds check source. */
542 if (args->offset > obj->base.size ||
543 args->size > obj->base.size - args->offset) {
548 /* prime objects have no backing filp to GEM pread/pwrite
551 if (!obj->base.filp) {
556 trace_i915_gem_object_pread(obj, args->offset, args->size);
558 ret = i915_gem_shmem_pread(dev, obj, args, file);
561 drm_gem_object_unreference(&obj->base);
563 mutex_unlock(&dev->struct_mutex);
567 /* This is the fast write path which cannot handle
568 * page faults in the source data
572 fast_user_write(struct io_mapping *mapping,
573 loff_t page_base, int page_offset,
574 char __user *user_data,
577 void __iomem *vaddr_atomic;
579 unsigned long unwritten;
581 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
582 /* We can use the cpu mem copy function because this is X86. */
583 vaddr = (void __force*)vaddr_atomic + page_offset;
584 unwritten = __copy_from_user_inatomic_nocache(vaddr,
586 io_mapping_unmap_atomic(vaddr_atomic);
591 * This is the fast pwrite path, where we copy the data directly from the
592 * user into the GTT, uncached.
595 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
596 struct drm_i915_gem_object *obj,
597 struct drm_i915_gem_pwrite *args,
598 struct drm_file *file)
600 drm_i915_private_t *dev_priv = dev->dev_private;
602 loff_t offset, page_base;
603 char __user *user_data;
604 int page_offset, page_length, ret;
606 ret = i915_gem_object_pin(obj, 0, true, true);
610 ret = i915_gem_object_set_to_gtt_domain(obj, true);
614 ret = i915_gem_object_put_fence(obj);
618 user_data = (char __user *) (uintptr_t) args->data_ptr;
621 offset = obj->gtt_offset + args->offset;
624 /* Operation in this page
626 * page_base = page offset within aperture
627 * page_offset = offset within page
628 * page_length = bytes to copy for this page
630 page_base = offset & PAGE_MASK;
631 page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((page_offset + remain) > PAGE_SIZE)
634 page_length = PAGE_SIZE - page_offset;
636 /* If we get a fault while copying data, then (presumably) our
637 * source page isn't available. Return the error and we'll
638 * retry in the slow path.
640 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
641 page_offset, user_data, page_length)) {
646 remain -= page_length;
647 user_data += page_length;
648 offset += page_length;
652 i915_gem_object_unpin(obj);
657 /* Per-page copy function for the shmem pwrite fastpath.
658 * Flushes invalid cachelines before writing to the target if
659 * needs_clflush_before is set and flushes out any written cachelines after
660 * writing if needs_clflush is set. */
662 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
663 char __user *user_data,
664 bool page_do_bit17_swizzling,
665 bool needs_clflush_before,
666 bool needs_clflush_after)
671 if (unlikely(page_do_bit17_swizzling))
674 vaddr = kmap_atomic(page);
675 if (needs_clflush_before)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
678 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
681 if (needs_clflush_after)
682 drm_clflush_virt_range(vaddr + shmem_page_offset,
684 kunmap_atomic(vaddr);
686 return ret ? -EFAULT : 0;
689 /* Only difference to the fast-path function is that this can handle bit17
690 * and uses non-atomic copy and kmap functions. */
692 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
693 char __user *user_data,
694 bool page_do_bit17_swizzling,
695 bool needs_clflush_before,
696 bool needs_clflush_after)
702 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
703 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
705 page_do_bit17_swizzling);
706 if (page_do_bit17_swizzling)
707 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
711 ret = __copy_from_user(vaddr + shmem_page_offset,
714 if (needs_clflush_after)
715 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
717 page_do_bit17_swizzling);
720 return ret ? -EFAULT : 0;
724 i915_gem_shmem_pwrite(struct drm_device *dev,
725 struct drm_i915_gem_object *obj,
726 struct drm_i915_gem_pwrite *args,
727 struct drm_file *file)
731 char __user *user_data;
732 int shmem_page_offset, page_length, ret = 0;
733 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
734 int hit_slowpath = 0;
735 int needs_clflush_after = 0;
736 int needs_clflush_before = 0;
738 struct scatterlist *sg;
740 user_data = (char __user *) (uintptr_t) args->data_ptr;
743 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
745 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
746 /* If we're not in the cpu write domain, set ourself into the gtt
747 * write domain and manually flush cachelines (if required). This
748 * optimizes for the case when the gpu will use the data
749 * right away and we therefore have to clflush anyway. */
750 if (obj->cache_level == I915_CACHE_NONE)
751 needs_clflush_after = 1;
752 if (obj->gtt_space) {
753 ret = i915_gem_object_set_to_gtt_domain(obj, true);
758 /* Same trick applies for invalidate partially written cachelines before
760 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
761 && obj->cache_level == I915_CACHE_NONE)
762 needs_clflush_before = 1;
764 ret = i915_gem_object_get_pages(obj);
768 i915_gem_object_pin_pages(obj);
770 offset = args->offset;
773 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
775 int partial_cacheline_write;
777 if (i < offset >> PAGE_SHIFT)
783 /* Operation in this page
785 * shmem_page_offset = offset within page in shmem file
786 * page_length = bytes to copy for this page
788 shmem_page_offset = offset_in_page(offset);
790 page_length = remain;
791 if ((shmem_page_offset + page_length) > PAGE_SIZE)
792 page_length = PAGE_SIZE - shmem_page_offset;
794 /* If we don't overwrite a cacheline completely we need to be
795 * careful to have up-to-date data by first clflushing. Don't
796 * overcomplicate things and flush the entire patch. */
797 partial_cacheline_write = needs_clflush_before &&
798 ((shmem_page_offset | page_length)
799 & (boot_cpu_data.x86_clflush_size - 1));
802 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
803 (page_to_phys(page) & (1 << 17)) != 0;
805 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
806 user_data, page_do_bit17_swizzling,
807 partial_cacheline_write,
808 needs_clflush_after);
813 mutex_unlock(&dev->struct_mutex);
814 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
815 user_data, page_do_bit17_swizzling,
816 partial_cacheline_write,
817 needs_clflush_after);
819 mutex_lock(&dev->struct_mutex);
822 set_page_dirty(page);
823 mark_page_accessed(page);
828 remain -= page_length;
829 user_data += page_length;
830 offset += page_length;
834 i915_gem_object_unpin_pages(obj);
838 * Fixup: Flush cpu caches in case we didn't flush the dirty
839 * cachelines in-line while writing and the object moved
840 * out of the cpu write domain while we've dropped the lock.
842 if (!needs_clflush_after &&
843 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
844 i915_gem_clflush_object(obj);
845 i915_gem_chipset_flush(dev);
849 if (needs_clflush_after)
850 i915_gem_chipset_flush(dev);
856 * Writes data to the object referenced by handle.
858 * On error, the contents of the buffer that were to be modified are undefined.
861 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file)
864 struct drm_i915_gem_pwrite *args = data;
865 struct drm_i915_gem_object *obj;
871 if (!access_ok(VERIFY_READ,
872 (char __user *)(uintptr_t)args->data_ptr,
876 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
881 ret = i915_mutex_lock_interruptible(dev);
885 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
886 if (&obj->base == NULL) {
891 /* Bounds check destination. */
892 if (args->offset > obj->base.size ||
893 args->size > obj->base.size - args->offset) {
898 /* prime objects have no backing filp to GEM pread/pwrite
901 if (!obj->base.filp) {
906 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
909 /* We can only do the GTT pwrite on untiled buffers, as otherwise
910 * it would end up going through the fenced access, and we'll get
911 * different detiling behavior between reading and writing.
912 * pread/pwrite currently are reading and writing from the CPU
913 * perspective, requiring manual detiling by the client.
916 ret = i915_gem_phys_pwrite(dev, obj, args, file);
920 if (obj->cache_level == I915_CACHE_NONE &&
921 obj->tiling_mode == I915_TILING_NONE &&
922 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
923 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
924 /* Note that the gtt paths might fail with non-page-backed user
925 * pointers (e.g. gtt mappings when moving data between
926 * textures). Fallback to the shmem path in that case. */
929 if (ret == -EFAULT || ret == -ENOSPC)
930 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
933 drm_gem_object_unreference(&obj->base);
935 mutex_unlock(&dev->struct_mutex);
940 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
943 if (atomic_read(&dev_priv->mm.wedged)) {
944 struct completion *x = &dev_priv->error_completion;
945 bool recovery_complete;
948 /* Give the error handler a chance to run. */
949 spin_lock_irqsave(&x->wait.lock, flags);
950 recovery_complete = x->done > 0;
951 spin_unlock_irqrestore(&x->wait.lock, flags);
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but still wedged means reset failure. */
959 if (recovery_complete)
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
980 if (seqno == ring->outstanding_lazy_request)
981 ret = i915_add_request(ring, NULL, NULL);
987 * __wait_seqno - wait until execution of seqno has finished
988 * @ring: the ring expected to report seqno
990 * @interruptible: do an interruptible wait (normally yes)
991 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
993 * Returns 0 if the seqno was found within the alloted time. Else returns the
994 * errno with remaining time filled in timeout argument.
996 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
997 bool interruptible, struct timespec *timeout)
999 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1000 struct timespec before, now, wait_time={1,0};
1001 unsigned long timeout_jiffies;
1003 bool wait_forever = true;
1006 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1009 trace_i915_gem_request_wait_begin(ring, seqno);
1011 if (timeout != NULL) {
1012 wait_time = *timeout;
1013 wait_forever = false;
1016 timeout_jiffies = timespec_to_jiffies(&wait_time);
1018 if (WARN_ON(!ring->irq_get(ring)))
1021 /* Record current time in case interrupted by signal, or wedged * */
1022 getrawmonotonic(&before);
1025 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026 atomic_read(&dev_priv->mm.wedged))
1029 end = wait_event_interruptible_timeout(ring->irq_queue,
1033 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1036 ret = i915_gem_check_wedge(dev_priv, interruptible);
1039 } while (end == 0 && wait_forever);
1041 getrawmonotonic(&now);
1043 ring->irq_put(ring);
1044 trace_i915_gem_request_wait_end(ring, seqno);
1048 struct timespec sleep_time = timespec_sub(now, before);
1049 *timeout = timespec_sub(*timeout, sleep_time);
1054 case -EAGAIN: /* Wedged */
1055 case -ERESTARTSYS: /* Signal */
1057 case 0: /* Timeout */
1059 set_normalized_timespec(timeout, 0, 0);
1061 default: /* Completed */
1062 WARN_ON(end < 0); /* We're not aware of other errors */
1068 * Waits for a sequence number to be signaled, and cleans up the
1069 * request and object lists appropriately for that event.
1072 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1074 struct drm_device *dev = ring->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 bool interruptible = dev_priv->mm.interruptible;
1079 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1082 ret = i915_gem_check_wedge(dev_priv, interruptible);
1086 ret = i915_gem_check_olr(ring, seqno);
1090 return __wait_seqno(ring, seqno, interruptible, NULL);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1101 struct intel_ring_buffer *ring = obj->ring;
1105 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109 ret = i915_wait_seqno(ring, seqno);
1113 i915_gem_retire_requests_ring(ring);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj->last_write_seqno &&
1119 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1120 obj->last_write_seqno = 0;
1121 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1134 struct drm_device *dev = obj->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 struct intel_ring_buffer *ring = obj->ring;
1140 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1141 BUG_ON(!dev_priv->mm.interruptible);
1143 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147 ret = i915_gem_check_wedge(dev_priv, true);
1151 ret = i915_gem_check_olr(ring, seqno);
1155 mutex_unlock(&dev->struct_mutex);
1156 ret = __wait_seqno(ring, seqno, true, NULL);
1157 mutex_lock(&dev->struct_mutex);
1159 i915_gem_retire_requests_ring(ring);
1161 /* Manually manage the write flush as we may have not yet
1162 * retired the buffer.
1164 if (obj->last_write_seqno &&
1165 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1166 obj->last_write_seqno = 0;
1167 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1350 /* Now bind it into the GTT if needed */
1351 ret = i915_gem_object_pin(obj, 0, true, false);
1355 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359 ret = i915_gem_object_get_fence(obj);
1363 obj->fault_mappable = true;
1365 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1368 /* Finally, remap it using the new GTT offset */
1369 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1371 i915_gem_object_unpin(obj);
1373 mutex_unlock(&dev->struct_mutex);
1377 /* If this -EIO is due to a gpu hang, give the reset code a
1378 * chance to clean up the mess. Otherwise return the proper
1380 if (!atomic_read(&dev_priv->mm.wedged))
1381 return VM_FAULT_SIGBUS;
1383 /* Give the error handler a chance to run and move the
1384 * objects off the GPU active list. Next time we service the
1385 * fault, we should be able to transition the page into the
1386 * GTT without touching the GPU (and so avoid further
1387 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1388 * with coherency, just lost writes.
1396 * EBUSY is ok: this just means that another thread
1397 * already did the job.
1399 return VM_FAULT_NOPAGE;
1401 return VM_FAULT_OOM;
1403 return VM_FAULT_SIGBUS;
1405 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1406 return VM_FAULT_SIGBUS;
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1427 if (!obj->fault_mappable)
1430 if (obj->base.dev->dev_mapping)
1431 unmap_mapping_range(obj->base.dev->dev_mapping,
1432 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1435 obj->fault_mappable = false;
1439 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1443 if (INTEL_INFO(dev)->gen >= 4 ||
1444 tiling_mode == I915_TILING_NONE)
1447 /* Previous chips need a power-of-two fence region when tiling */
1448 if (INTEL_INFO(dev)->gen == 3)
1449 gtt_size = 1024*1024;
1451 gtt_size = 512*1024;
1453 while (gtt_size < size)
1460 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1461 * @obj: object to check
1463 * Return the required GTT alignment for an object, taking into account
1464 * potential fence register mapping.
1467 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1468 int tiling_mode, bool fenced)
1471 * Minimum alignment is 4k (GTT page size), but might be greater
1472 * if a fence register is needed for the object.
1474 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1475 tiling_mode == I915_TILING_NONE)
1479 * Previous chips need to be aligned to the size of the smallest
1480 * fence register that can contain the object.
1482 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1485 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1487 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1490 if (obj->base.map_list.map)
1493 dev_priv->mm.shrinker_no_lock_stealing = true;
1495 ret = drm_gem_create_mmap_offset(&obj->base);
1499 /* Badly fragmented mmap space? The only way we can recover
1500 * space is by destroying unwanted objects. We can't randomly release
1501 * mmap_offsets as userspace expects them to be persistent for the
1502 * lifetime of the objects. The closest we can is to release the
1503 * offsets on purgeable objects by truncating it and marking it purged,
1504 * which prevents userspace from ever using that object again.
1506 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1507 ret = drm_gem_create_mmap_offset(&obj->base);
1511 i915_gem_shrink_all(dev_priv);
1512 ret = drm_gem_create_mmap_offset(&obj->base);
1514 dev_priv->mm.shrinker_no_lock_stealing = false;
1519 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1521 if (!obj->base.map_list.map)
1524 drm_gem_free_mmap_offset(&obj->base);
1528 i915_gem_mmap_gtt(struct drm_file *file,
1529 struct drm_device *dev,
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 struct drm_i915_gem_object *obj;
1537 ret = i915_mutex_lock_interruptible(dev);
1541 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1542 if (&obj->base == NULL) {
1547 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1552 if (obj->madv != I915_MADV_WILLNEED) {
1553 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1558 ret = i915_gem_object_create_mmap_offset(obj);
1562 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1565 drm_gem_object_unreference(&obj->base);
1567 mutex_unlock(&dev->struct_mutex);
1572 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1574 * @data: GTT mapping ioctl data
1575 * @file: GEM object info
1577 * Simply returns the fake offset to userspace so it can mmap it.
1578 * The mmap call will end up in drm_gem_mmap(), which will set things
1579 * up so we can get faults in the handler above.
1581 * The fault handler will take care of binding the object into the GTT
1582 * (since it may have been evicted to make room for something), allocating
1583 * a fence register, and mapping the appropriate aperture address into
1587 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1588 struct drm_file *file)
1590 struct drm_i915_gem_mmap_gtt *args = data;
1592 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1595 /* Immediately discard the backing storage */
1597 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1599 struct inode *inode;
1601 i915_gem_object_free_mmap_offset(obj);
1603 if (obj->base.filp == NULL)
1606 /* Our goal here is to return as much of the memory as
1607 * is possible back to the system as we are called from OOM.
1608 * To do this we must instruct the shmfs to drop all of its
1609 * backing pages, *now*.
1611 inode = obj->base.filp->f_path.dentry->d_inode;
1612 shmem_truncate_range(inode, 0, (loff_t)-1);
1614 obj->madv = __I915_MADV_PURGED;
1618 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1620 return obj->madv == I915_MADV_DONTNEED;
1624 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1626 int page_count = obj->base.size / PAGE_SIZE;
1627 struct scatterlist *sg;
1630 BUG_ON(obj->madv == __I915_MADV_PURGED);
1632 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1634 /* In the event of a disaster, abandon all caches and
1635 * hope for the best.
1637 WARN_ON(ret != -EIO);
1638 i915_gem_clflush_object(obj);
1639 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1642 if (i915_gem_object_needs_bit17_swizzle(obj))
1643 i915_gem_object_save_bit_17_swizzle(obj);
1645 if (obj->madv == I915_MADV_DONTNEED)
1648 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1649 struct page *page = sg_page(sg);
1652 set_page_dirty(page);
1654 if (obj->madv == I915_MADV_WILLNEED)
1655 mark_page_accessed(page);
1657 page_cache_release(page);
1661 sg_free_table(obj->pages);
1666 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1668 const struct drm_i915_gem_object_ops *ops = obj->ops;
1670 if (obj->pages == NULL)
1673 BUG_ON(obj->gtt_space);
1675 if (obj->pages_pin_count)
1678 /* ->put_pages might need to allocate memory for the bit17 swizzle
1679 * array, hence protect them from being reaped by removing them from gtt
1681 list_del(&obj->gtt_list);
1683 ops->put_pages(obj);
1686 if (i915_gem_object_is_purgeable(obj))
1687 i915_gem_object_truncate(obj);
1693 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1695 struct drm_i915_gem_object *obj, *next;
1698 list_for_each_entry_safe(obj, next,
1699 &dev_priv->mm.unbound_list,
1701 if (i915_gem_object_is_purgeable(obj) &&
1702 i915_gem_object_put_pages(obj) == 0) {
1703 count += obj->base.size >> PAGE_SHIFT;
1704 if (count >= target)
1709 list_for_each_entry_safe(obj, next,
1710 &dev_priv->mm.inactive_list,
1712 if (i915_gem_object_is_purgeable(obj) &&
1713 i915_gem_object_unbind(obj) == 0 &&
1714 i915_gem_object_put_pages(obj) == 0) {
1715 count += obj->base.size >> PAGE_SHIFT;
1716 if (count >= target)
1725 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1727 struct drm_i915_gem_object *obj, *next;
1729 i915_gem_evict_everything(dev_priv->dev);
1731 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1732 i915_gem_object_put_pages(obj);
1736 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1738 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1740 struct address_space *mapping;
1741 struct sg_table *st;
1742 struct scatterlist *sg;
1746 /* Assert that the object is not currently in any GPU domain. As it
1747 * wasn't in the GTT, there shouldn't be any way it could have been in
1750 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1751 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1753 st = kmalloc(sizeof(*st), GFP_KERNEL);
1757 page_count = obj->base.size / PAGE_SIZE;
1758 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1764 /* Get the list of pages out of our struct file. They'll be pinned
1765 * at this point until we release them.
1767 * Fail silently without starting the shrinker
1769 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1770 gfp = mapping_gfp_mask(mapping);
1771 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1772 gfp &= ~(__GFP_IO | __GFP_WAIT);
1773 for_each_sg(st->sgl, sg, page_count, i) {
1774 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1776 i915_gem_purge(dev_priv, page_count);
1777 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1780 /* We've tried hard to allocate the memory by reaping
1781 * our own buffer, now let the real VM do its job and
1782 * go down in flames if truly OOM.
1784 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1785 gfp |= __GFP_IO | __GFP_WAIT;
1787 i915_gem_shrink_all(dev_priv);
1788 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1792 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1793 gfp &= ~(__GFP_IO | __GFP_WAIT);
1796 sg_set_page(sg, page, PAGE_SIZE, 0);
1801 if (i915_gem_object_needs_bit17_swizzle(obj))
1802 i915_gem_object_do_bit_17_swizzle(obj);
1807 for_each_sg(st->sgl, sg, i, page_count)
1808 page_cache_release(sg_page(sg));
1811 return PTR_ERR(page);
1814 /* Ensure that the associated pages are gathered from the backing storage
1815 * and pinned into our object. i915_gem_object_get_pages() may be called
1816 * multiple times before they are released by a single call to
1817 * i915_gem_object_put_pages() - once the pages are no longer referenced
1818 * either as a result of memory pressure (reaping pages under the shrinker)
1819 * or as the object is itself released.
1822 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1824 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1825 const struct drm_i915_gem_object_ops *ops = obj->ops;
1831 BUG_ON(obj->pages_pin_count);
1833 ret = ops->get_pages(obj);
1837 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1842 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1843 struct intel_ring_buffer *ring)
1845 struct drm_device *dev = obj->base.dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 u32 seqno = intel_ring_get_seqno(ring);
1849 BUG_ON(ring == NULL);
1852 /* Add a reference if we're newly entering the active list. */
1854 drm_gem_object_reference(&obj->base);
1858 /* Move from whatever list we were on to the tail of execution. */
1859 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1860 list_move_tail(&obj->ring_list, &ring->active_list);
1862 obj->last_read_seqno = seqno;
1864 if (obj->fenced_gpu_access) {
1865 obj->last_fenced_seqno = seqno;
1867 /* Bump MRU to take account of the delayed flush */
1868 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1869 struct drm_i915_fence_reg *reg;
1871 reg = &dev_priv->fence_regs[obj->fence_reg];
1872 list_move_tail(®->lru_list,
1873 &dev_priv->mm.fence_list);
1879 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1881 struct drm_device *dev = obj->base.dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1884 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1885 BUG_ON(!obj->active);
1887 if (obj->pin_count) /* are we a framebuffer? */
1888 intel_mark_fb_idle(obj);
1890 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1892 list_del_init(&obj->ring_list);
1895 obj->last_read_seqno = 0;
1896 obj->last_write_seqno = 0;
1897 obj->base.write_domain = 0;
1899 obj->last_fenced_seqno = 0;
1900 obj->fenced_gpu_access = false;
1903 drm_gem_object_unreference(&obj->base);
1905 WARN_ON(i915_verify_lists(dev));
1909 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_ring_buffer *ring;
1915 /* Carefully retire all requests without writing to the rings */
1916 for_each_ring(ring, dev_priv, i) {
1917 ret = intel_ring_idle(ring);
1921 i915_gem_retire_requests(dev);
1923 /* Finally reset hw state */
1924 for_each_ring(ring, dev_priv, i) {
1925 intel_ring_init_seqno(ring, seqno);
1927 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1928 ring->sync_seqno[j] = 0;
1934 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1942 /* HWS page needs to be set less than what we
1943 * will inject to ring
1945 ret = i915_gem_init_seqno(dev, seqno - 1);
1949 /* Carefully set the last_seqno value so that wrap
1950 * detection still works
1952 dev_priv->next_seqno = seqno;
1953 dev_priv->last_seqno = seqno - 1;
1954 if (dev_priv->last_seqno == 0)
1955 dev_priv->last_seqno--;
1961 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1965 /* reserve 0 for non-seqno */
1966 if (dev_priv->next_seqno == 0) {
1967 int ret = i915_gem_init_seqno(dev, 0);
1971 dev_priv->next_seqno = 1;
1974 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1979 i915_add_request(struct intel_ring_buffer *ring,
1980 struct drm_file *file,
1983 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1984 struct drm_i915_gem_request *request;
1985 u32 request_ring_position;
1990 * Emit any outstanding flushes - execbuf can fail to emit the flush
1991 * after having emitted the batchbuffer command. Hence we need to fix
1992 * things up similar to emitting the lazy request. The difference here
1993 * is that the flush _must_ happen before the next request, no matter
1996 ret = intel_ring_flush_all_caches(ring);
2000 request = kmalloc(sizeof(*request), GFP_KERNEL);
2001 if (request == NULL)
2005 /* Record the position of the start of the request so that
2006 * should we detect the updated seqno part-way through the
2007 * GPU processing the request, we never over-estimate the
2008 * position of the head.
2010 request_ring_position = intel_ring_get_tail(ring);
2012 ret = ring->add_request(ring);
2018 request->seqno = intel_ring_get_seqno(ring);
2019 request->ring = ring;
2020 request->tail = request_ring_position;
2021 request->emitted_jiffies = jiffies;
2022 was_empty = list_empty(&ring->request_list);
2023 list_add_tail(&request->list, &ring->request_list);
2024 request->file_priv = NULL;
2027 struct drm_i915_file_private *file_priv = file->driver_priv;
2029 spin_lock(&file_priv->mm.lock);
2030 request->file_priv = file_priv;
2031 list_add_tail(&request->client_list,
2032 &file_priv->mm.request_list);
2033 spin_unlock(&file_priv->mm.lock);
2036 trace_i915_gem_request_add(ring, request->seqno);
2037 ring->outstanding_lazy_request = 0;
2039 if (!dev_priv->mm.suspended) {
2040 if (i915_enable_hangcheck) {
2041 mod_timer(&dev_priv->hangcheck_timer,
2042 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2045 queue_delayed_work(dev_priv->wq,
2046 &dev_priv->mm.retire_work,
2047 round_jiffies_up_relative(HZ));
2048 intel_mark_busy(dev_priv->dev);
2053 *out_seqno = request->seqno;
2058 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2060 struct drm_i915_file_private *file_priv = request->file_priv;
2065 spin_lock(&file_priv->mm.lock);
2066 if (request->file_priv) {
2067 list_del(&request->client_list);
2068 request->file_priv = NULL;
2070 spin_unlock(&file_priv->mm.lock);
2073 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2074 struct intel_ring_buffer *ring)
2076 while (!list_empty(&ring->request_list)) {
2077 struct drm_i915_gem_request *request;
2079 request = list_first_entry(&ring->request_list,
2080 struct drm_i915_gem_request,
2083 list_del(&request->list);
2084 i915_gem_request_remove_from_client(request);
2088 while (!list_empty(&ring->active_list)) {
2089 struct drm_i915_gem_object *obj;
2091 obj = list_first_entry(&ring->active_list,
2092 struct drm_i915_gem_object,
2095 i915_gem_object_move_to_inactive(obj);
2099 static void i915_gem_reset_fences(struct drm_device *dev)
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2104 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2105 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2107 i915_gem_write_fence(dev, i, NULL);
2110 i915_gem_object_fence_lost(reg->obj);
2114 INIT_LIST_HEAD(®->lru_list);
2117 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2120 void i915_gem_reset(struct drm_device *dev)
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 struct drm_i915_gem_object *obj;
2124 struct intel_ring_buffer *ring;
2127 for_each_ring(ring, dev_priv, i)
2128 i915_gem_reset_ring_lists(dev_priv, ring);
2130 /* Move everything out of the GPU domains to ensure we do any
2131 * necessary invalidation upon reuse.
2133 list_for_each_entry(obj,
2134 &dev_priv->mm.inactive_list,
2137 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2140 /* The fence registers are invalidated so clear them out */
2141 i915_gem_reset_fences(dev);
2145 * This function clears the request list as sequence numbers are passed.
2148 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2152 if (list_empty(&ring->request_list))
2155 WARN_ON(i915_verify_lists(ring->dev));
2157 seqno = ring->get_seqno(ring, true);
2159 while (!list_empty(&ring->request_list)) {
2160 struct drm_i915_gem_request *request;
2162 request = list_first_entry(&ring->request_list,
2163 struct drm_i915_gem_request,
2166 if (!i915_seqno_passed(seqno, request->seqno))
2169 trace_i915_gem_request_retire(ring, request->seqno);
2170 /* We know the GPU must have read the request to have
2171 * sent us the seqno + interrupt, so use the position
2172 * of tail of the request to update the last known position
2175 ring->last_retired_head = request->tail;
2177 list_del(&request->list);
2178 i915_gem_request_remove_from_client(request);
2182 /* Move any buffers on the active list that are no longer referenced
2183 * by the ringbuffer to the flushing/inactive lists as appropriate.
2185 while (!list_empty(&ring->active_list)) {
2186 struct drm_i915_gem_object *obj;
2188 obj = list_first_entry(&ring->active_list,
2189 struct drm_i915_gem_object,
2192 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2195 i915_gem_object_move_to_inactive(obj);
2198 if (unlikely(ring->trace_irq_seqno &&
2199 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2200 ring->irq_put(ring);
2201 ring->trace_irq_seqno = 0;
2204 WARN_ON(i915_verify_lists(ring->dev));
2208 i915_gem_retire_requests(struct drm_device *dev)
2210 drm_i915_private_t *dev_priv = dev->dev_private;
2211 struct intel_ring_buffer *ring;
2214 for_each_ring(ring, dev_priv, i)
2215 i915_gem_retire_requests_ring(ring);
2219 i915_gem_retire_work_handler(struct work_struct *work)
2221 drm_i915_private_t *dev_priv;
2222 struct drm_device *dev;
2223 struct intel_ring_buffer *ring;
2227 dev_priv = container_of(work, drm_i915_private_t,
2228 mm.retire_work.work);
2229 dev = dev_priv->dev;
2231 /* Come back later if the device is busy... */
2232 if (!mutex_trylock(&dev->struct_mutex)) {
2233 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2234 round_jiffies_up_relative(HZ));
2238 i915_gem_retire_requests(dev);
2240 /* Send a periodic flush down the ring so we don't hold onto GEM
2241 * objects indefinitely.
2244 for_each_ring(ring, dev_priv, i) {
2245 if (ring->gpu_caches_dirty)
2246 i915_add_request(ring, NULL, NULL);
2248 idle &= list_empty(&ring->request_list);
2251 if (!dev_priv->mm.suspended && !idle)
2252 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2253 round_jiffies_up_relative(HZ));
2255 intel_mark_idle(dev);
2257 mutex_unlock(&dev->struct_mutex);
2261 * Ensures that an object will eventually get non-busy by flushing any required
2262 * write domains, emitting any outstanding lazy request and retiring and
2263 * completed requests.
2266 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2271 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2275 i915_gem_retire_requests_ring(obj->ring);
2282 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2283 * @DRM_IOCTL_ARGS: standard ioctl arguments
2285 * Returns 0 if successful, else an error is returned with the remaining time in
2286 * the timeout parameter.
2287 * -ETIME: object is still busy after timeout
2288 * -ERESTARTSYS: signal interrupted the wait
2289 * -ENONENT: object doesn't exist
2290 * Also possible, but rare:
2291 * -EAGAIN: GPU wedged
2293 * -ENODEV: Internal IRQ fail
2294 * -E?: The add request failed
2296 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2297 * non-zero timeout parameter the wait ioctl will wait for the given number of
2298 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2299 * without holding struct_mutex the object may become re-busied before this
2300 * function completes. A similar but shorter * race condition exists in the busy
2304 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2306 struct drm_i915_gem_wait *args = data;
2307 struct drm_i915_gem_object *obj;
2308 struct intel_ring_buffer *ring = NULL;
2309 struct timespec timeout_stack, *timeout = NULL;
2313 if (args->timeout_ns >= 0) {
2314 timeout_stack = ns_to_timespec(args->timeout_ns);
2315 timeout = &timeout_stack;
2318 ret = i915_mutex_lock_interruptible(dev);
2322 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2323 if (&obj->base == NULL) {
2324 mutex_unlock(&dev->struct_mutex);
2328 /* Need to make sure the object gets inactive eventually. */
2329 ret = i915_gem_object_flush_active(obj);
2334 seqno = obj->last_read_seqno;
2341 /* Do this after OLR check to make sure we make forward progress polling
2342 * on this IOCTL with a 0 timeout (like busy ioctl)
2344 if (!args->timeout_ns) {
2349 drm_gem_object_unreference(&obj->base);
2350 mutex_unlock(&dev->struct_mutex);
2352 ret = __wait_seqno(ring, seqno, true, timeout);
2354 WARN_ON(!timespec_valid(timeout));
2355 args->timeout_ns = timespec_to_ns(timeout);
2360 drm_gem_object_unreference(&obj->base);
2361 mutex_unlock(&dev->struct_mutex);
2366 * i915_gem_object_sync - sync an object to a ring.
2368 * @obj: object which may be in use on another ring.
2369 * @to: ring we wish to use the object on. May be NULL.
2371 * This code is meant to abstract object synchronization with the GPU.
2372 * Calling with NULL implies synchronizing the object with the CPU
2373 * rather than a particular GPU ring.
2375 * Returns 0 if successful, else propagates up the lower layer error.
2378 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2379 struct intel_ring_buffer *to)
2381 struct intel_ring_buffer *from = obj->ring;
2385 if (from == NULL || to == from)
2388 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2389 return i915_gem_object_wait_rendering(obj, false);
2391 idx = intel_ring_sync_index(from, to);
2393 seqno = obj->last_read_seqno;
2394 if (seqno <= from->sync_seqno[idx])
2397 ret = i915_gem_check_olr(obj->ring, seqno);
2401 ret = to->sync_to(to, from, seqno);
2403 /* We use last_read_seqno because sync_to()
2404 * might have just caused seqno wrap under
2407 from->sync_seqno[idx] = obj->last_read_seqno;
2412 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2414 u32 old_write_domain, old_read_domains;
2416 /* Act a barrier for all accesses through the GTT */
2419 /* Force a pagefault for domain tracking on next user access */
2420 i915_gem_release_mmap(obj);
2422 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2425 old_read_domains = obj->base.read_domains;
2426 old_write_domain = obj->base.write_domain;
2428 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2429 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2431 trace_i915_gem_object_change_domain(obj,
2437 * Unbinds an object from the GTT aperture.
2440 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2442 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2445 if (obj->gtt_space == NULL)
2451 BUG_ON(obj->pages == NULL);
2453 ret = i915_gem_object_finish_gpu(obj);
2456 /* Continue on if we fail due to EIO, the GPU is hung so we
2457 * should be safe and we need to cleanup or else we might
2458 * cause memory corruption through use-after-free.
2461 i915_gem_object_finish_gtt(obj);
2463 /* release the fence reg _after_ flushing */
2464 ret = i915_gem_object_put_fence(obj);
2468 trace_i915_gem_object_unbind(obj);
2470 if (obj->has_global_gtt_mapping)
2471 i915_gem_gtt_unbind_object(obj);
2472 if (obj->has_aliasing_ppgtt_mapping) {
2473 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2474 obj->has_aliasing_ppgtt_mapping = 0;
2476 i915_gem_gtt_finish_object(obj);
2478 list_del(&obj->mm_list);
2479 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2480 /* Avoid an unnecessary call to unbind on rebind. */
2481 obj->map_and_fenceable = true;
2483 drm_mm_put_block(obj->gtt_space);
2484 obj->gtt_space = NULL;
2485 obj->gtt_offset = 0;
2490 int i915_gpu_idle(struct drm_device *dev)
2492 drm_i915_private_t *dev_priv = dev->dev_private;
2493 struct intel_ring_buffer *ring;
2496 /* Flush everything onto the inactive list. */
2497 for_each_ring(ring, dev_priv, i) {
2498 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2502 ret = intel_ring_idle(ring);
2510 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2511 struct drm_i915_gem_object *obj)
2513 drm_i915_private_t *dev_priv = dev->dev_private;
2515 int fence_pitch_shift;
2518 if (INTEL_INFO(dev)->gen >= 6) {
2519 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2520 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2522 fence_reg = FENCE_REG_965_0;
2523 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2527 u32 size = obj->gtt_space->size;
2529 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2531 val |= obj->gtt_offset & 0xfffff000;
2532 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2533 if (obj->tiling_mode == I915_TILING_Y)
2534 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2535 val |= I965_FENCE_REG_VALID;
2539 fence_reg += reg * 8;
2540 I915_WRITE64(fence_reg, val);
2541 POSTING_READ(fence_reg);
2544 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2545 struct drm_i915_gem_object *obj)
2547 drm_i915_private_t *dev_priv = dev->dev_private;
2551 u32 size = obj->gtt_space->size;
2555 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2556 (size & -size) != size ||
2557 (obj->gtt_offset & (size - 1)),
2558 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2559 obj->gtt_offset, obj->map_and_fenceable, size);
2561 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2566 /* Note: pitch better be a power of two tile widths */
2567 pitch_val = obj->stride / tile_width;
2568 pitch_val = ffs(pitch_val) - 1;
2570 val = obj->gtt_offset;
2571 if (obj->tiling_mode == I915_TILING_Y)
2572 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2573 val |= I915_FENCE_SIZE_BITS(size);
2574 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2575 val |= I830_FENCE_REG_VALID;
2580 reg = FENCE_REG_830_0 + reg * 4;
2582 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2584 I915_WRITE(reg, val);
2588 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2589 struct drm_i915_gem_object *obj)
2591 drm_i915_private_t *dev_priv = dev->dev_private;
2595 u32 size = obj->gtt_space->size;
2598 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2599 (size & -size) != size ||
2600 (obj->gtt_offset & (size - 1)),
2601 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2602 obj->gtt_offset, size);
2604 pitch_val = obj->stride / 128;
2605 pitch_val = ffs(pitch_val) - 1;
2607 val = obj->gtt_offset;
2608 if (obj->tiling_mode == I915_TILING_Y)
2609 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2610 val |= I830_FENCE_SIZE_BITS(size);
2611 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2612 val |= I830_FENCE_REG_VALID;
2616 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2617 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2620 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2621 struct drm_i915_gem_object *obj)
2623 switch (INTEL_INFO(dev)->gen) {
2627 case 4: i965_write_fence_reg(dev, reg, obj); break;
2628 case 3: i915_write_fence_reg(dev, reg, obj); break;
2629 case 2: i830_write_fence_reg(dev, reg, obj); break;
2634 static inline int fence_number(struct drm_i915_private *dev_priv,
2635 struct drm_i915_fence_reg *fence)
2637 return fence - dev_priv->fence_regs;
2640 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2641 struct drm_i915_fence_reg *fence,
2644 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2645 int reg = fence_number(dev_priv, fence);
2647 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2650 obj->fence_reg = reg;
2652 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2654 obj->fence_reg = I915_FENCE_REG_NONE;
2656 list_del_init(&fence->lru_list);
2661 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2663 if (obj->last_fenced_seqno) {
2664 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2668 obj->last_fenced_seqno = 0;
2671 /* Ensure that all CPU reads are completed before installing a fence
2672 * and all writes before removing the fence.
2674 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2677 obj->fenced_gpu_access = false;
2682 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2684 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2687 ret = i915_gem_object_flush_fence(obj);
2691 if (obj->fence_reg == I915_FENCE_REG_NONE)
2694 i915_gem_object_update_fence(obj,
2695 &dev_priv->fence_regs[obj->fence_reg],
2697 i915_gem_object_fence_lost(obj);
2702 static struct drm_i915_fence_reg *
2703 i915_find_fence_reg(struct drm_device *dev)
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct drm_i915_fence_reg *reg, *avail;
2709 /* First try to find a free reg */
2711 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2712 reg = &dev_priv->fence_regs[i];
2716 if (!reg->pin_count)
2723 /* None available, try to steal one or wait for a user to finish */
2724 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2735 * i915_gem_object_get_fence - set up fencing for an object
2736 * @obj: object to map through a fence reg
2738 * When mapping objects through the GTT, userspace wants to be able to write
2739 * to them without having to worry about swizzling if the object is tiled.
2740 * This function walks the fence regs looking for a free one for @obj,
2741 * stealing one if it can't find any.
2743 * It then sets up the reg based on the object's properties: address, pitch
2744 * and tiling format.
2746 * For an untiled surface, this removes any existing fence.
2749 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2751 struct drm_device *dev = obj->base.dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 bool enable = obj->tiling_mode != I915_TILING_NONE;
2754 struct drm_i915_fence_reg *reg;
2757 /* Have we updated the tiling parameters upon the object and so
2758 * will need to serialise the write to the associated fence register?
2760 if (obj->fence_dirty) {
2761 ret = i915_gem_object_flush_fence(obj);
2766 /* Just update our place in the LRU if our fence is getting reused. */
2767 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2768 reg = &dev_priv->fence_regs[obj->fence_reg];
2769 if (!obj->fence_dirty) {
2770 list_move_tail(®->lru_list,
2771 &dev_priv->mm.fence_list);
2774 } else if (enable) {
2775 reg = i915_find_fence_reg(dev);
2780 struct drm_i915_gem_object *old = reg->obj;
2782 ret = i915_gem_object_flush_fence(old);
2786 i915_gem_object_fence_lost(old);
2791 i915_gem_object_update_fence(obj, reg, enable);
2792 obj->fence_dirty = false;
2797 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2798 struct drm_mm_node *gtt_space,
2799 unsigned long cache_level)
2801 struct drm_mm_node *other;
2803 /* On non-LLC machines we have to be careful when putting differing
2804 * types of snoopable memory together to avoid the prefetcher
2805 * crossing memory domains and dying.
2810 if (gtt_space == NULL)
2813 if (list_empty(>t_space->node_list))
2816 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2817 if (other->allocated && !other->hole_follows && other->color != cache_level)
2820 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2821 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2827 static void i915_gem_verify_gtt(struct drm_device *dev)
2830 struct drm_i915_private *dev_priv = dev->dev_private;
2831 struct drm_i915_gem_object *obj;
2834 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2835 if (obj->gtt_space == NULL) {
2836 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2841 if (obj->cache_level != obj->gtt_space->color) {
2842 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2843 obj->gtt_space->start,
2844 obj->gtt_space->start + obj->gtt_space->size,
2846 obj->gtt_space->color);
2851 if (!i915_gem_valid_gtt_space(dev,
2853 obj->cache_level)) {
2854 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2855 obj->gtt_space->start,
2856 obj->gtt_space->start + obj->gtt_space->size,
2868 * Finds free space in the GTT aperture and binds the object there.
2871 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2873 bool map_and_fenceable,
2876 struct drm_device *dev = obj->base.dev;
2877 drm_i915_private_t *dev_priv = dev->dev_private;
2878 struct drm_mm_node *node;
2879 u32 size, fence_size, fence_alignment, unfenced_alignment;
2880 bool mappable, fenceable;
2883 if (obj->madv != I915_MADV_WILLNEED) {
2884 DRM_ERROR("Attempting to bind a purgeable object\n");
2888 fence_size = i915_gem_get_gtt_size(dev,
2891 fence_alignment = i915_gem_get_gtt_alignment(dev,
2893 obj->tiling_mode, true);
2894 unfenced_alignment =
2895 i915_gem_get_gtt_alignment(dev,
2897 obj->tiling_mode, false);
2900 alignment = map_and_fenceable ? fence_alignment :
2902 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2903 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2907 size = map_and_fenceable ? fence_size : obj->base.size;
2909 /* If the object is bigger than the entire aperture, reject it early
2910 * before evicting everything in a vain attempt to find space.
2912 if (obj->base.size >
2913 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2914 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2918 ret = i915_gem_object_get_pages(obj);
2922 i915_gem_object_pin_pages(obj);
2924 node = kzalloc(sizeof(*node), GFP_KERNEL);
2926 i915_gem_object_unpin_pages(obj);
2931 if (map_and_fenceable)
2932 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
2933 size, alignment, obj->cache_level,
2934 0, dev_priv->mm.gtt_mappable_end);
2936 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
2937 size, alignment, obj->cache_level);
2939 ret = i915_gem_evict_something(dev, size, alignment,
2946 i915_gem_object_unpin_pages(obj);
2950 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
2951 i915_gem_object_unpin_pages(obj);
2952 drm_mm_put_block(node);
2956 ret = i915_gem_gtt_prepare_object(obj);
2958 i915_gem_object_unpin_pages(obj);
2959 drm_mm_put_block(node);
2963 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2964 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2966 obj->gtt_space = node;
2967 obj->gtt_offset = node->start;
2970 node->size == fence_size &&
2971 (node->start & (fence_alignment - 1)) == 0;
2974 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2976 obj->map_and_fenceable = mappable && fenceable;
2978 i915_gem_object_unpin_pages(obj);
2979 trace_i915_gem_object_bind(obj, map_and_fenceable);
2980 i915_gem_verify_gtt(dev);
2985 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2987 /* If we don't have a page list set up, then we're not pinned
2988 * to GPU, and we can ignore the cache flush because it'll happen
2989 * again at bind time.
2991 if (obj->pages == NULL)
2994 /* If the GPU is snooping the contents of the CPU cache,
2995 * we do not need to manually clear the CPU cache lines. However,
2996 * the caches are only snooped when the render cache is
2997 * flushed/invalidated. As we always have to emit invalidations
2998 * and flushes when moving into and out of the RENDER domain, correct
2999 * snooping behaviour occurs naturally as the result of our domain
3002 if (obj->cache_level != I915_CACHE_NONE)
3005 trace_i915_gem_object_clflush(obj);
3007 drm_clflush_sg(obj->pages);
3010 /** Flushes the GTT write domain for the object if it's dirty. */
3012 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3014 uint32_t old_write_domain;
3016 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3019 /* No actual flushing is required for the GTT write domain. Writes
3020 * to it immediately go to main memory as far as we know, so there's
3021 * no chipset flush. It also doesn't land in render cache.
3023 * However, we do have to enforce the order so that all writes through
3024 * the GTT land before any writes to the device, such as updates to
3029 old_write_domain = obj->base.write_domain;
3030 obj->base.write_domain = 0;
3032 trace_i915_gem_object_change_domain(obj,
3033 obj->base.read_domains,
3037 /** Flushes the CPU write domain for the object if it's dirty. */
3039 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3041 uint32_t old_write_domain;
3043 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3046 i915_gem_clflush_object(obj);
3047 i915_gem_chipset_flush(obj->base.dev);
3048 old_write_domain = obj->base.write_domain;
3049 obj->base.write_domain = 0;
3051 trace_i915_gem_object_change_domain(obj,
3052 obj->base.read_domains,
3057 * Moves a single object to the GTT read, and possibly write domain.
3059 * This function returns when the move is complete, including waiting on
3063 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3065 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3066 uint32_t old_write_domain, old_read_domains;
3069 /* Not valid to be called on unbound objects. */
3070 if (obj->gtt_space == NULL)
3073 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3076 ret = i915_gem_object_wait_rendering(obj, !write);
3080 i915_gem_object_flush_cpu_write_domain(obj);
3082 old_write_domain = obj->base.write_domain;
3083 old_read_domains = obj->base.read_domains;
3085 /* It should now be out of any other write domains, and we can update
3086 * the domain values for our changes.
3088 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3089 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3091 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3092 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3096 trace_i915_gem_object_change_domain(obj,
3100 /* And bump the LRU for this access */
3101 if (i915_gem_object_is_inactive(obj))
3102 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3107 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3108 enum i915_cache_level cache_level)
3110 struct drm_device *dev = obj->base.dev;
3111 drm_i915_private_t *dev_priv = dev->dev_private;
3114 if (obj->cache_level == cache_level)
3117 if (obj->pin_count) {
3118 DRM_DEBUG("can not change the cache level of pinned objects\n");
3122 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3123 ret = i915_gem_object_unbind(obj);
3128 if (obj->gtt_space) {
3129 ret = i915_gem_object_finish_gpu(obj);
3133 i915_gem_object_finish_gtt(obj);
3135 /* Before SandyBridge, you could not use tiling or fence
3136 * registers with snooped memory, so relinquish any fences
3137 * currently pointing to our region in the aperture.
3139 if (INTEL_INFO(dev)->gen < 6) {
3140 ret = i915_gem_object_put_fence(obj);
3145 if (obj->has_global_gtt_mapping)
3146 i915_gem_gtt_bind_object(obj, cache_level);
3147 if (obj->has_aliasing_ppgtt_mapping)
3148 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3151 obj->gtt_space->color = cache_level;
3154 if (cache_level == I915_CACHE_NONE) {
3155 u32 old_read_domains, old_write_domain;
3157 /* If we're coming from LLC cached, then we haven't
3158 * actually been tracking whether the data is in the
3159 * CPU cache or not, since we only allow one bit set
3160 * in obj->write_domain and have been skipping the clflushes.
3161 * Just set it to the CPU cache for now.
3163 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3164 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3166 old_read_domains = obj->base.read_domains;
3167 old_write_domain = obj->base.write_domain;
3169 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3170 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3172 trace_i915_gem_object_change_domain(obj,
3177 obj->cache_level = cache_level;
3178 i915_gem_verify_gtt(dev);
3182 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3183 struct drm_file *file)
3185 struct drm_i915_gem_caching *args = data;
3186 struct drm_i915_gem_object *obj;
3189 ret = i915_mutex_lock_interruptible(dev);
3193 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3194 if (&obj->base == NULL) {
3199 args->caching = obj->cache_level != I915_CACHE_NONE;
3201 drm_gem_object_unreference(&obj->base);
3203 mutex_unlock(&dev->struct_mutex);
3207 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3208 struct drm_file *file)
3210 struct drm_i915_gem_caching *args = data;
3211 struct drm_i915_gem_object *obj;
3212 enum i915_cache_level level;
3215 switch (args->caching) {
3216 case I915_CACHING_NONE:
3217 level = I915_CACHE_NONE;
3219 case I915_CACHING_CACHED:
3220 level = I915_CACHE_LLC;
3226 ret = i915_mutex_lock_interruptible(dev);
3230 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3231 if (&obj->base == NULL) {
3236 ret = i915_gem_object_set_cache_level(obj, level);
3238 drm_gem_object_unreference(&obj->base);
3240 mutex_unlock(&dev->struct_mutex);
3245 * Prepare buffer for display plane (scanout, cursors, etc).
3246 * Can be called from an uninterruptible phase (modesetting) and allows
3247 * any flushes to be pipelined (for pageflips).
3250 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3252 struct intel_ring_buffer *pipelined)
3254 u32 old_read_domains, old_write_domain;
3257 if (pipelined != obj->ring) {
3258 ret = i915_gem_object_sync(obj, pipelined);
3263 /* The display engine is not coherent with the LLC cache on gen6. As
3264 * a result, we make sure that the pinning that is about to occur is
3265 * done with uncached PTEs. This is lowest common denominator for all
3268 * However for gen6+, we could do better by using the GFDT bit instead
3269 * of uncaching, which would allow us to flush all the LLC-cached data
3270 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3272 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3276 /* As the user may map the buffer once pinned in the display plane
3277 * (e.g. libkms for the bootup splash), we have to ensure that we
3278 * always use map_and_fenceable for all scanout buffers.
3280 ret = i915_gem_object_pin(obj, alignment, true, false);
3284 i915_gem_object_flush_cpu_write_domain(obj);
3286 old_write_domain = obj->base.write_domain;
3287 old_read_domains = obj->base.read_domains;
3289 /* It should now be out of any other write domains, and we can update
3290 * the domain values for our changes.
3292 obj->base.write_domain = 0;
3293 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3295 trace_i915_gem_object_change_domain(obj,
3303 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3307 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3310 ret = i915_gem_object_wait_rendering(obj, false);
3314 /* Ensure that we invalidate the GPU's caches and TLBs. */
3315 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3320 * Moves a single object to the CPU read, and possibly write domain.
3322 * This function returns when the move is complete, including waiting on
3326 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3328 uint32_t old_write_domain, old_read_domains;
3331 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3334 ret = i915_gem_object_wait_rendering(obj, !write);
3338 i915_gem_object_flush_gtt_write_domain(obj);
3340 old_write_domain = obj->base.write_domain;
3341 old_read_domains = obj->base.read_domains;
3343 /* Flush the CPU cache if it's still invalid. */
3344 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3345 i915_gem_clflush_object(obj);
3347 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3350 /* It should now be out of any other write domains, and we can update
3351 * the domain values for our changes.
3353 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3355 /* If we're writing through the CPU, then the GPU read domains will
3356 * need to be invalidated at next use.
3359 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3360 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3363 trace_i915_gem_object_change_domain(obj,
3370 /* Throttle our rendering by waiting until the ring has completed our requests
3371 * emitted over 20 msec ago.
3373 * Note that if we were to use the current jiffies each time around the loop,
3374 * we wouldn't escape the function with any frames outstanding if the time to
3375 * render a frame was over 20ms.
3377 * This should get us reasonable parallelism between CPU and GPU but also
3378 * relatively low latency when blocking on a particular request to finish.
3381 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct drm_i915_file_private *file_priv = file->driver_priv;
3385 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3386 struct drm_i915_gem_request *request;
3387 struct intel_ring_buffer *ring = NULL;
3391 if (atomic_read(&dev_priv->mm.wedged))
3394 spin_lock(&file_priv->mm.lock);
3395 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3396 if (time_after_eq(request->emitted_jiffies, recent_enough))
3399 ring = request->ring;
3400 seqno = request->seqno;
3402 spin_unlock(&file_priv->mm.lock);
3407 ret = __wait_seqno(ring, seqno, true, NULL);
3409 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3415 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3417 bool map_and_fenceable,
3422 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3425 if (obj->gtt_space != NULL) {
3426 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3427 (map_and_fenceable && !obj->map_and_fenceable)) {
3428 WARN(obj->pin_count,
3429 "bo is already pinned with incorrect alignment:"
3430 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3431 " obj->map_and_fenceable=%d\n",
3432 obj->gtt_offset, alignment,
3434 obj->map_and_fenceable);
3435 ret = i915_gem_object_unbind(obj);
3441 if (obj->gtt_space == NULL) {
3442 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3444 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3450 if (!dev_priv->mm.aliasing_ppgtt)
3451 i915_gem_gtt_bind_object(obj, obj->cache_level);
3454 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3455 i915_gem_gtt_bind_object(obj, obj->cache_level);
3458 obj->pin_mappable |= map_and_fenceable;
3464 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3466 BUG_ON(obj->pin_count == 0);
3467 BUG_ON(obj->gtt_space == NULL);
3469 if (--obj->pin_count == 0)
3470 obj->pin_mappable = false;
3474 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3475 struct drm_file *file)
3477 struct drm_i915_gem_pin *args = data;
3478 struct drm_i915_gem_object *obj;
3481 ret = i915_mutex_lock_interruptible(dev);
3485 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3486 if (&obj->base == NULL) {
3491 if (obj->madv != I915_MADV_WILLNEED) {
3492 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3497 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3498 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3504 obj->user_pin_count++;
3505 obj->pin_filp = file;
3506 if (obj->user_pin_count == 1) {
3507 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3512 /* XXX - flush the CPU caches for pinned objects
3513 * as the X server doesn't manage domains yet
3515 i915_gem_object_flush_cpu_write_domain(obj);
3516 args->offset = obj->gtt_offset;
3518 drm_gem_object_unreference(&obj->base);
3520 mutex_unlock(&dev->struct_mutex);
3525 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3526 struct drm_file *file)
3528 struct drm_i915_gem_pin *args = data;
3529 struct drm_i915_gem_object *obj;
3532 ret = i915_mutex_lock_interruptible(dev);
3536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3537 if (&obj->base == NULL) {
3542 if (obj->pin_filp != file) {
3543 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3548 obj->user_pin_count--;
3549 if (obj->user_pin_count == 0) {
3550 obj->pin_filp = NULL;
3551 i915_gem_object_unpin(obj);
3555 drm_gem_object_unreference(&obj->base);
3557 mutex_unlock(&dev->struct_mutex);
3562 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3563 struct drm_file *file)
3565 struct drm_i915_gem_busy *args = data;
3566 struct drm_i915_gem_object *obj;
3569 ret = i915_mutex_lock_interruptible(dev);
3573 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3574 if (&obj->base == NULL) {
3579 /* Count all active objects as busy, even if they are currently not used
3580 * by the gpu. Users of this interface expect objects to eventually
3581 * become non-busy without any further actions, therefore emit any
3582 * necessary flushes here.
3584 ret = i915_gem_object_flush_active(obj);
3586 args->busy = obj->active;
3588 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3589 args->busy |= intel_ring_flag(obj->ring) << 16;
3592 drm_gem_object_unreference(&obj->base);
3594 mutex_unlock(&dev->struct_mutex);
3599 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3600 struct drm_file *file_priv)
3602 return i915_gem_ring_throttle(dev, file_priv);
3606 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3607 struct drm_file *file_priv)
3609 struct drm_i915_gem_madvise *args = data;
3610 struct drm_i915_gem_object *obj;
3613 switch (args->madv) {
3614 case I915_MADV_DONTNEED:
3615 case I915_MADV_WILLNEED:
3621 ret = i915_mutex_lock_interruptible(dev);
3625 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3626 if (&obj->base == NULL) {
3631 if (obj->pin_count) {
3636 if (obj->madv != __I915_MADV_PURGED)
3637 obj->madv = args->madv;
3639 /* if the object is no longer attached, discard its backing storage */
3640 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3641 i915_gem_object_truncate(obj);
3643 args->retained = obj->madv != __I915_MADV_PURGED;
3646 drm_gem_object_unreference(&obj->base);
3648 mutex_unlock(&dev->struct_mutex);
3652 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3653 const struct drm_i915_gem_object_ops *ops)
3655 INIT_LIST_HEAD(&obj->mm_list);
3656 INIT_LIST_HEAD(&obj->gtt_list);
3657 INIT_LIST_HEAD(&obj->ring_list);
3658 INIT_LIST_HEAD(&obj->exec_list);
3662 obj->fence_reg = I915_FENCE_REG_NONE;
3663 obj->madv = I915_MADV_WILLNEED;
3664 /* Avoid an unnecessary call to unbind on the first bind. */
3665 obj->map_and_fenceable = true;
3667 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3670 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3671 .get_pages = i915_gem_object_get_pages_gtt,
3672 .put_pages = i915_gem_object_put_pages_gtt,
3675 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3678 struct drm_i915_gem_object *obj;
3679 struct address_space *mapping;
3682 obj = i915_gem_object_alloc(dev);
3686 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3687 i915_gem_object_free(obj);
3691 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3692 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3693 /* 965gm cannot relocate objects above 4GiB. */
3694 mask &= ~__GFP_HIGHMEM;
3695 mask |= __GFP_DMA32;
3698 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3699 mapping_set_gfp_mask(mapping, mask);
3701 i915_gem_object_init(obj, &i915_gem_object_ops);
3703 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3704 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3707 /* On some devices, we can have the GPU use the LLC (the CPU
3708 * cache) for about a 10% performance improvement
3709 * compared to uncached. Graphics requests other than
3710 * display scanout are coherent with the CPU in
3711 * accessing this cache. This means in this mode we
3712 * don't need to clflush on the CPU side, and on the
3713 * GPU side we only need to flush internal caches to
3714 * get data visible to the CPU.
3716 * However, we maintain the display planes as UC, and so
3717 * need to rebind when first used as such.
3719 obj->cache_level = I915_CACHE_LLC;
3721 obj->cache_level = I915_CACHE_NONE;
3726 int i915_gem_init_object(struct drm_gem_object *obj)
3733 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3735 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3736 struct drm_device *dev = obj->base.dev;
3737 drm_i915_private_t *dev_priv = dev->dev_private;
3739 trace_i915_gem_object_destroy(obj);
3742 i915_gem_detach_phys_object(dev, obj);
3745 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3746 bool was_interruptible;
3748 was_interruptible = dev_priv->mm.interruptible;
3749 dev_priv->mm.interruptible = false;
3751 WARN_ON(i915_gem_object_unbind(obj));
3753 dev_priv->mm.interruptible = was_interruptible;
3756 obj->pages_pin_count = 0;
3757 i915_gem_object_put_pages(obj);
3758 i915_gem_object_free_mmap_offset(obj);
3759 i915_gem_object_release_stolen(obj);
3763 if (obj->base.import_attach)
3764 drm_prime_gem_destroy(&obj->base, NULL);
3766 drm_gem_object_release(&obj->base);
3767 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3770 i915_gem_object_free(obj);
3774 i915_gem_idle(struct drm_device *dev)
3776 drm_i915_private_t *dev_priv = dev->dev_private;
3779 mutex_lock(&dev->struct_mutex);
3781 if (dev_priv->mm.suspended) {
3782 mutex_unlock(&dev->struct_mutex);
3786 ret = i915_gpu_idle(dev);
3788 mutex_unlock(&dev->struct_mutex);
3791 i915_gem_retire_requests(dev);
3793 /* Under UMS, be paranoid and evict. */
3794 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3795 i915_gem_evict_everything(dev);
3797 i915_gem_reset_fences(dev);
3799 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3800 * We need to replace this with a semaphore, or something.
3801 * And not confound mm.suspended!
3803 dev_priv->mm.suspended = 1;
3804 del_timer_sync(&dev_priv->hangcheck_timer);
3806 i915_kernel_lost_context(dev);
3807 i915_gem_cleanup_ringbuffer(dev);
3809 mutex_unlock(&dev->struct_mutex);
3811 /* Cancel the retire work handler, which should be idle now. */
3812 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3817 void i915_gem_l3_remap(struct drm_device *dev)
3819 drm_i915_private_t *dev_priv = dev->dev_private;
3823 if (!IS_IVYBRIDGE(dev))
3826 if (!dev_priv->l3_parity.remap_info)
3829 misccpctl = I915_READ(GEN7_MISCCPCTL);
3830 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3831 POSTING_READ(GEN7_MISCCPCTL);
3833 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3834 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3835 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3836 DRM_DEBUG("0x%x was already programmed to %x\n",
3837 GEN7_L3LOG_BASE + i, remap);
3838 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3839 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3840 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3843 /* Make sure all the writes land before disabling dop clock gating */
3844 POSTING_READ(GEN7_L3LOG_BASE);
3846 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3849 void i915_gem_init_swizzling(struct drm_device *dev)
3851 drm_i915_private_t *dev_priv = dev->dev_private;
3853 if (INTEL_INFO(dev)->gen < 5 ||
3854 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3857 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3858 DISP_TILE_SURFACE_SWIZZLING);
3863 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3865 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3866 else if (IS_GEN7(dev))
3867 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3873 intel_enable_blt(struct drm_device *dev)
3878 /* The blitter was dysfunctional on early prototypes */
3879 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3880 DRM_INFO("BLT not supported on this pre-production hardware;"
3881 " graphics performance will be degraded.\n");
3889 i915_gem_init_hw(struct drm_device *dev)
3891 drm_i915_private_t *dev_priv = dev->dev_private;
3894 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3897 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3898 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3900 i915_gem_l3_remap(dev);
3902 i915_gem_init_swizzling(dev);
3904 dev_priv->next_seqno = dev_priv->last_seqno = (u32)~0 - 0x1000;
3906 ret = intel_init_render_ring_buffer(dev);
3911 ret = intel_init_bsd_ring_buffer(dev);
3913 goto cleanup_render_ring;
3916 if (intel_enable_blt(dev)) {
3917 ret = intel_init_blt_ring_buffer(dev);
3919 goto cleanup_bsd_ring;
3923 * XXX: There was some w/a described somewhere suggesting loading
3924 * contexts before PPGTT.
3926 i915_gem_context_init(dev);
3927 i915_gem_init_ppgtt(dev);
3932 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3933 cleanup_render_ring:
3934 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3938 int i915_gem_init(struct drm_device *dev)
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3943 mutex_lock(&dev->struct_mutex);
3944 i915_gem_init_global_gtt(dev);
3945 ret = i915_gem_init_hw(dev);
3946 mutex_unlock(&dev->struct_mutex);
3948 i915_gem_cleanup_aliasing_ppgtt(dev);
3952 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3953 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3954 dev_priv->dri1.allow_batchbuffer = 1;
3959 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3961 drm_i915_private_t *dev_priv = dev->dev_private;
3962 struct intel_ring_buffer *ring;
3965 for_each_ring(ring, dev_priv, i)
3966 intel_cleanup_ring_buffer(ring);
3970 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3971 struct drm_file *file_priv)
3973 drm_i915_private_t *dev_priv = dev->dev_private;
3976 if (drm_core_check_feature(dev, DRIVER_MODESET))
3979 if (atomic_read(&dev_priv->mm.wedged)) {
3980 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3981 atomic_set(&dev_priv->mm.wedged, 0);
3984 mutex_lock(&dev->struct_mutex);
3985 dev_priv->mm.suspended = 0;
3987 ret = i915_gem_init_hw(dev);
3989 mutex_unlock(&dev->struct_mutex);
3993 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3994 mutex_unlock(&dev->struct_mutex);
3996 ret = drm_irq_install(dev);
3998 goto cleanup_ringbuffer;
4003 mutex_lock(&dev->struct_mutex);
4004 i915_gem_cleanup_ringbuffer(dev);
4005 dev_priv->mm.suspended = 1;
4006 mutex_unlock(&dev->struct_mutex);
4012 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4013 struct drm_file *file_priv)
4015 if (drm_core_check_feature(dev, DRIVER_MODESET))
4018 drm_irq_uninstall(dev);
4019 return i915_gem_idle(dev);
4023 i915_gem_lastclose(struct drm_device *dev)
4027 if (drm_core_check_feature(dev, DRIVER_MODESET))
4030 ret = i915_gem_idle(dev);
4032 DRM_ERROR("failed to idle hardware: %d\n", ret);
4036 init_ring_lists(struct intel_ring_buffer *ring)
4038 INIT_LIST_HEAD(&ring->active_list);
4039 INIT_LIST_HEAD(&ring->request_list);
4043 i915_gem_load(struct drm_device *dev)
4045 drm_i915_private_t *dev_priv = dev->dev_private;
4049 kmem_cache_create("i915_gem_object",
4050 sizeof(struct drm_i915_gem_object), 0,
4054 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4055 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4056 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4057 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4058 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4059 for (i = 0; i < I915_NUM_RINGS; i++)
4060 init_ring_lists(&dev_priv->ring[i]);
4061 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4062 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4063 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4064 i915_gem_retire_work_handler);
4065 init_completion(&dev_priv->error_completion);
4067 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4069 I915_WRITE(MI_ARB_STATE,
4070 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4073 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4075 /* Old X drivers will take 0-2 for front, back, depth buffers */
4076 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4077 dev_priv->fence_reg_start = 3;
4079 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4080 dev_priv->num_fence_regs = 16;
4082 dev_priv->num_fence_regs = 8;
4084 /* Initialize fence registers to zero */
4085 i915_gem_reset_fences(dev);
4087 i915_gem_detect_bit_6_swizzle(dev);
4088 init_waitqueue_head(&dev_priv->pending_flip_queue);
4090 dev_priv->mm.interruptible = true;
4092 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4093 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4094 register_shrinker(&dev_priv->mm.inactive_shrinker);
4098 * Create a physically contiguous memory object for this object
4099 * e.g. for cursor + overlay regs
4101 static int i915_gem_init_phys_object(struct drm_device *dev,
4102 int id, int size, int align)
4104 drm_i915_private_t *dev_priv = dev->dev_private;
4105 struct drm_i915_gem_phys_object *phys_obj;
4108 if (dev_priv->mm.phys_objs[id - 1] || !size)
4111 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4117 phys_obj->handle = drm_pci_alloc(dev, size, align);
4118 if (!phys_obj->handle) {
4123 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4126 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4134 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4136 drm_i915_private_t *dev_priv = dev->dev_private;
4137 struct drm_i915_gem_phys_object *phys_obj;
4139 if (!dev_priv->mm.phys_objs[id - 1])
4142 phys_obj = dev_priv->mm.phys_objs[id - 1];
4143 if (phys_obj->cur_obj) {
4144 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4148 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4150 drm_pci_free(dev, phys_obj->handle);
4152 dev_priv->mm.phys_objs[id - 1] = NULL;
4155 void i915_gem_free_all_phys_object(struct drm_device *dev)
4159 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4160 i915_gem_free_phys_object(dev, i);
4163 void i915_gem_detach_phys_object(struct drm_device *dev,
4164 struct drm_i915_gem_object *obj)
4166 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4173 vaddr = obj->phys_obj->handle->vaddr;
4175 page_count = obj->base.size / PAGE_SIZE;
4176 for (i = 0; i < page_count; i++) {
4177 struct page *page = shmem_read_mapping_page(mapping, i);
4178 if (!IS_ERR(page)) {
4179 char *dst = kmap_atomic(page);
4180 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4183 drm_clflush_pages(&page, 1);
4185 set_page_dirty(page);
4186 mark_page_accessed(page);
4187 page_cache_release(page);
4190 i915_gem_chipset_flush(dev);
4192 obj->phys_obj->cur_obj = NULL;
4193 obj->phys_obj = NULL;
4197 i915_gem_attach_phys_object(struct drm_device *dev,
4198 struct drm_i915_gem_object *obj,
4202 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4203 drm_i915_private_t *dev_priv = dev->dev_private;
4208 if (id > I915_MAX_PHYS_OBJECT)
4211 if (obj->phys_obj) {
4212 if (obj->phys_obj->id == id)
4214 i915_gem_detach_phys_object(dev, obj);
4217 /* create a new object */
4218 if (!dev_priv->mm.phys_objs[id - 1]) {
4219 ret = i915_gem_init_phys_object(dev, id,
4220 obj->base.size, align);
4222 DRM_ERROR("failed to init phys object %d size: %zu\n",
4223 id, obj->base.size);
4228 /* bind to the object */
4229 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4230 obj->phys_obj->cur_obj = obj;
4232 page_count = obj->base.size / PAGE_SIZE;
4234 for (i = 0; i < page_count; i++) {
4238 page = shmem_read_mapping_page(mapping, i);
4240 return PTR_ERR(page);
4242 src = kmap_atomic(page);
4243 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4244 memcpy(dst, src, PAGE_SIZE);
4247 mark_page_accessed(page);
4248 page_cache_release(page);
4255 i915_gem_phys_pwrite(struct drm_device *dev,
4256 struct drm_i915_gem_object *obj,
4257 struct drm_i915_gem_pwrite *args,
4258 struct drm_file *file_priv)
4260 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4261 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4263 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4264 unsigned long unwritten;
4266 /* The physical object once assigned is fixed for the lifetime
4267 * of the obj, so we can safely drop the lock and continue
4270 mutex_unlock(&dev->struct_mutex);
4271 unwritten = copy_from_user(vaddr, user_data, args->size);
4272 mutex_lock(&dev->struct_mutex);
4277 i915_gem_chipset_flush(dev);
4281 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4283 struct drm_i915_file_private *file_priv = file->driver_priv;
4285 /* Clean up our request list when the client is going away, so that
4286 * later retire_requests won't dereference our soon-to-be-gone
4289 spin_lock(&file_priv->mm.lock);
4290 while (!list_empty(&file_priv->mm.request_list)) {
4291 struct drm_i915_gem_request *request;
4293 request = list_first_entry(&file_priv->mm.request_list,
4294 struct drm_i915_gem_request,
4296 list_del(&request->client_list);
4297 request->file_priv = NULL;
4299 spin_unlock(&file_priv->mm.lock);
4302 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4304 if (!mutex_is_locked(mutex))
4307 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4308 return mutex->owner == task;
4310 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4316 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4318 struct drm_i915_private *dev_priv =
4319 container_of(shrinker,
4320 struct drm_i915_private,
4321 mm.inactive_shrinker);
4322 struct drm_device *dev = dev_priv->dev;
4323 struct drm_i915_gem_object *obj;
4324 int nr_to_scan = sc->nr_to_scan;
4328 if (!mutex_trylock(&dev->struct_mutex)) {
4329 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4332 if (dev_priv->mm.shrinker_no_lock_stealing)
4339 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4341 i915_gem_shrink_all(dev_priv);
4345 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4346 if (obj->pages_pin_count == 0)
4347 cnt += obj->base.size >> PAGE_SHIFT;
4348 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4349 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4350 cnt += obj->base.size >> PAGE_SHIFT;
4353 mutex_unlock(&dev->struct_mutex);