2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915_prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915_prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
974 static void fake_irq(unsigned long data)
976 wake_up_process((struct task_struct *)data);
979 static bool missed_irq(struct drm_i915_private *dev_priv,
980 struct intel_ring_buffer *ring)
982 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
985 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
987 if (file_priv == NULL)
990 return !atomic_xchg(&file_priv->rps_wait_boost, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1012 unsigned reset_counter,
1014 struct timespec *timeout,
1015 struct drm_i915_file_private *file_priv)
1017 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1018 struct timespec before, now;
1020 unsigned long timeout_expire;
1023 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1025 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1028 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1030 if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
1031 gen6_rps_boost(dev_priv);
1033 mod_delayed_work(dev_priv->wq,
1034 &file_priv->mm.idle_work,
1035 msecs_to_jiffies(100));
1038 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) &&
1039 WARN_ON(!ring->irq_get(ring)))
1042 /* Record current time in case interrupted by signal, or wedged */
1043 trace_i915_gem_request_wait_begin(ring, seqno);
1044 getrawmonotonic(&before);
1046 struct timer_list timer;
1048 prepare_to_wait(&ring->irq_queue, &wait,
1049 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1051 /* We need to check whether any gpu reset happened in between
1052 * the caller grabbing the seqno and now ... */
1053 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1054 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1055 * is truely gone. */
1056 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1062 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1067 if (interruptible && signal_pending(current)) {
1072 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1077 timer.function = NULL;
1078 if (timeout || missed_irq(dev_priv, ring)) {
1079 unsigned long expire;
1081 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1082 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1083 mod_timer(&timer, expire);
1088 if (timer.function) {
1089 del_singleshot_timer_sync(&timer);
1090 destroy_timer_on_stack(&timer);
1093 getrawmonotonic(&now);
1094 trace_i915_gem_request_wait_end(ring, seqno);
1096 ring->irq_put(ring);
1098 finish_wait(&ring->irq_queue, &wait);
1101 struct timespec sleep_time = timespec_sub(now, before);
1102 *timeout = timespec_sub(*timeout, sleep_time);
1103 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1104 set_normalized_timespec(timeout, 0, 0);
1111 * Waits for a sequence number to be signaled, and cleans up the
1112 * request and object lists appropriately for that event.
1115 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1117 struct drm_device *dev = ring->dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 bool interruptible = dev_priv->mm.interruptible;
1122 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1125 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1129 ret = i915_gem_check_olr(ring, seqno);
1133 return __wait_seqno(ring, seqno,
1134 atomic_read(&dev_priv->gpu_error.reset_counter),
1135 interruptible, NULL, NULL);
1139 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1140 struct intel_ring_buffer *ring)
1142 i915_gem_retire_requests_ring(ring);
1144 /* Manually manage the write flush as we may have not yet
1145 * retired the buffer.
1147 * Note that the last_write_seqno is always the earlier of
1148 * the two (read/write) seqno, so if we haved successfully waited,
1149 * we know we have passed the last write.
1151 obj->last_write_seqno = 0;
1152 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1158 * Ensures that all rendering to the object has completed and the object is
1159 * safe to unbind from the GTT or access from the CPU.
1161 static __must_check int
1162 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1165 struct intel_ring_buffer *ring = obj->ring;
1169 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1173 ret = i915_wait_seqno(ring, seqno);
1177 return i915_gem_object_wait_rendering__tail(obj, ring);
1180 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1181 * as the object state may change during this call.
1183 static __must_check int
1184 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1185 struct drm_file *file,
1188 struct drm_device *dev = obj->base.dev;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 struct intel_ring_buffer *ring = obj->ring;
1191 unsigned reset_counter;
1195 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1196 BUG_ON(!dev_priv->mm.interruptible);
1198 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1202 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1206 ret = i915_gem_check_olr(ring, seqno);
1210 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1211 mutex_unlock(&dev->struct_mutex);
1212 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv);
1213 mutex_lock(&dev->struct_mutex);
1217 return i915_gem_object_wait_rendering__tail(obj, ring);
1221 * Called when user space prepares to use an object with the CPU, either
1222 * through the mmap ioctl's mapping or a GTT mapping.
1225 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1226 struct drm_file *file)
1228 struct drm_i915_gem_set_domain *args = data;
1229 struct drm_i915_gem_object *obj;
1230 uint32_t read_domains = args->read_domains;
1231 uint32_t write_domain = args->write_domain;
1234 /* Only handle setting domains to types used by the CPU. */
1235 if (write_domain & I915_GEM_GPU_DOMAINS)
1238 if (read_domains & I915_GEM_GPU_DOMAINS)
1241 /* Having something in the write domain implies it's in the read
1242 * domain, and only that read domain. Enforce that in the request.
1244 if (write_domain != 0 && read_domains != write_domain)
1247 ret = i915_mutex_lock_interruptible(dev);
1251 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252 if (&obj->base == NULL) {
1257 /* Try to flush the object off the GPU without holding the lock.
1258 * We will repeat the flush holding the lock in the normal manner
1259 * to catch cases where we are gazumped.
1261 ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain);
1265 if (read_domains & I915_GEM_DOMAIN_GTT) {
1266 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1268 /* Silently promote "you're not bound, there was nothing to do"
1269 * to success, since the client was just asking us to
1270 * make sure everything was done.
1275 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1279 drm_gem_object_unreference(&obj->base);
1281 mutex_unlock(&dev->struct_mutex);
1286 * Called when user space has done writes to this buffer
1289 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1290 struct drm_file *file)
1292 struct drm_i915_gem_sw_finish *args = data;
1293 struct drm_i915_gem_object *obj;
1296 ret = i915_mutex_lock_interruptible(dev);
1300 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1301 if (&obj->base == NULL) {
1306 /* Pinned buffers may be scanout, so flush the cache */
1307 if (obj->pin_display)
1308 i915_gem_object_flush_cpu_write_domain(obj, true);
1310 drm_gem_object_unreference(&obj->base);
1312 mutex_unlock(&dev->struct_mutex);
1317 * Maps the contents of an object, returning the address it is mapped
1320 * While the mapping holds a reference on the contents of the object, it doesn't
1321 * imply a ref on the object itself.
1324 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1325 struct drm_file *file)
1327 struct drm_i915_gem_mmap *args = data;
1328 struct drm_gem_object *obj;
1331 obj = drm_gem_object_lookup(dev, file, args->handle);
1335 /* prime objects have no backing filp to GEM mmap
1339 drm_gem_object_unreference_unlocked(obj);
1343 addr = vm_mmap(obj->filp, 0, args->size,
1344 PROT_READ | PROT_WRITE, MAP_SHARED,
1346 drm_gem_object_unreference_unlocked(obj);
1347 if (IS_ERR((void *)addr))
1350 args->addr_ptr = (uint64_t) addr;
1356 * i915_gem_fault - fault a page into the GTT
1357 * vma: VMA in question
1360 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1361 * from userspace. The fault handler takes care of binding the object to
1362 * the GTT (if needed), allocating and programming a fence register (again,
1363 * only if needed based on whether the old reg is still valid or the object
1364 * is tiled) and inserting a new PTE into the faulting process.
1366 * Note that the faulting process may involve evicting existing objects
1367 * from the GTT and/or fence registers to make room. So performance may
1368 * suffer if the GTT working set is large or there are few fence registers
1371 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1373 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1374 struct drm_device *dev = obj->base.dev;
1375 drm_i915_private_t *dev_priv = dev->dev_private;
1376 pgoff_t page_offset;
1379 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1381 intel_runtime_pm_get(dev_priv);
1383 /* We don't use vmf->pgoff since that has the fake offset */
1384 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1387 ret = i915_mutex_lock_interruptible(dev);
1391 trace_i915_gem_object_fault(obj, page_offset, true, write);
1393 /* Access to snoopable pages through the GTT is incoherent. */
1394 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1399 /* Now bind it into the GTT if needed */
1400 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1404 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1408 ret = i915_gem_object_get_fence(obj);
1412 obj->fault_mappable = true;
1414 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1418 /* Finally, remap it using the new GTT offset */
1419 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1421 i915_gem_object_unpin(obj);
1423 mutex_unlock(&dev->struct_mutex);
1427 /* If this -EIO is due to a gpu hang, give the reset code a
1428 * chance to clean up the mess. Otherwise return the proper
1430 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1431 ret = VM_FAULT_SIGBUS;
1436 * EAGAIN means the gpu is hung and we'll wait for the error
1437 * handler to reset everything when re-faulting in
1438 * i915_mutex_lock_interruptible.
1445 * EBUSY is ok: this just means that another thread
1446 * already did the job.
1448 ret = VM_FAULT_NOPAGE;
1454 ret = VM_FAULT_SIGBUS;
1457 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1458 ret = VM_FAULT_SIGBUS;
1462 intel_runtime_pm_put(dev_priv);
1467 * i915_gem_release_mmap - remove physical page mappings
1468 * @obj: obj in question
1470 * Preserve the reservation of the mmapping with the DRM core code, but
1471 * relinquish ownership of the pages back to the system.
1473 * It is vital that we remove the page mapping if we have mapped a tiled
1474 * object through the GTT and then lose the fence register due to
1475 * resource pressure. Similarly if the object has been moved out of the
1476 * aperture, than pages mapped into userspace must be revoked. Removing the
1477 * mapping will then trigger a page fault on the next user access, allowing
1478 * fixup by i915_gem_fault().
1481 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1483 if (!obj->fault_mappable)
1486 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1487 obj->fault_mappable = false;
1491 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1495 if (INTEL_INFO(dev)->gen >= 4 ||
1496 tiling_mode == I915_TILING_NONE)
1499 /* Previous chips need a power-of-two fence region when tiling */
1500 if (INTEL_INFO(dev)->gen == 3)
1501 gtt_size = 1024*1024;
1503 gtt_size = 512*1024;
1505 while (gtt_size < size)
1512 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1513 * @obj: object to check
1515 * Return the required GTT alignment for an object, taking into account
1516 * potential fence register mapping.
1519 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1520 int tiling_mode, bool fenced)
1523 * Minimum alignment is 4k (GTT page size), but might be greater
1524 * if a fence register is needed for the object.
1526 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1527 tiling_mode == I915_TILING_NONE)
1531 * Previous chips need to be aligned to the size of the smallest
1532 * fence register that can contain the object.
1534 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1537 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1539 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1542 if (drm_vma_node_has_offset(&obj->base.vma_node))
1545 dev_priv->mm.shrinker_no_lock_stealing = true;
1547 ret = drm_gem_create_mmap_offset(&obj->base);
1551 /* Badly fragmented mmap space? The only way we can recover
1552 * space is by destroying unwanted objects. We can't randomly release
1553 * mmap_offsets as userspace expects them to be persistent for the
1554 * lifetime of the objects. The closest we can is to release the
1555 * offsets on purgeable objects by truncating it and marking it purged,
1556 * which prevents userspace from ever using that object again.
1558 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1559 ret = drm_gem_create_mmap_offset(&obj->base);
1563 i915_gem_shrink_all(dev_priv);
1564 ret = drm_gem_create_mmap_offset(&obj->base);
1566 dev_priv->mm.shrinker_no_lock_stealing = false;
1571 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1573 drm_gem_free_mmap_offset(&obj->base);
1577 i915_gem_mmap_gtt(struct drm_file *file,
1578 struct drm_device *dev,
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 struct drm_i915_gem_object *obj;
1586 ret = i915_mutex_lock_interruptible(dev);
1590 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1591 if (&obj->base == NULL) {
1596 if (obj->base.size > dev_priv->gtt.mappable_end) {
1601 if (obj->madv != I915_MADV_WILLNEED) {
1602 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1607 ret = i915_gem_object_create_mmap_offset(obj);
1611 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1614 drm_gem_object_unreference(&obj->base);
1616 mutex_unlock(&dev->struct_mutex);
1621 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1623 * @data: GTT mapping ioctl data
1624 * @file: GEM object info
1626 * Simply returns the fake offset to userspace so it can mmap it.
1627 * The mmap call will end up in drm_gem_mmap(), which will set things
1628 * up so we can get faults in the handler above.
1630 * The fault handler will take care of binding the object into the GTT
1631 * (since it may have been evicted to make room for something), allocating
1632 * a fence register, and mapping the appropriate aperture address into
1636 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1637 struct drm_file *file)
1639 struct drm_i915_gem_mmap_gtt *args = data;
1641 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1644 /* Immediately discard the backing storage */
1646 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1648 struct inode *inode;
1650 i915_gem_object_free_mmap_offset(obj);
1652 if (obj->base.filp == NULL)
1655 /* Our goal here is to return as much of the memory as
1656 * is possible back to the system as we are called from OOM.
1657 * To do this we must instruct the shmfs to drop all of its
1658 * backing pages, *now*.
1660 inode = file_inode(obj->base.filp);
1661 shmem_truncate_range(inode, 0, (loff_t)-1);
1663 obj->madv = __I915_MADV_PURGED;
1667 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1669 return obj->madv == I915_MADV_DONTNEED;
1673 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1675 struct sg_page_iter sg_iter;
1678 BUG_ON(obj->madv == __I915_MADV_PURGED);
1680 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1682 /* In the event of a disaster, abandon all caches and
1683 * hope for the best.
1685 WARN_ON(ret != -EIO);
1686 i915_gem_clflush_object(obj, true);
1687 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1690 if (i915_gem_object_needs_bit17_swizzle(obj))
1691 i915_gem_object_save_bit_17_swizzle(obj);
1693 if (obj->madv == I915_MADV_DONTNEED)
1696 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1697 struct page *page = sg_page_iter_page(&sg_iter);
1700 set_page_dirty(page);
1702 if (obj->madv == I915_MADV_WILLNEED)
1703 mark_page_accessed(page);
1705 page_cache_release(page);
1709 sg_free_table(obj->pages);
1714 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1716 const struct drm_i915_gem_object_ops *ops = obj->ops;
1718 if (obj->pages == NULL)
1721 if (obj->pages_pin_count)
1724 BUG_ON(i915_gem_obj_bound_any(obj));
1726 /* ->put_pages might need to allocate memory for the bit17 swizzle
1727 * array, hence protect them from being reaped by removing them from gtt
1729 list_del(&obj->global_list);
1731 ops->put_pages(obj);
1734 if (i915_gem_object_is_purgeable(obj))
1735 i915_gem_object_truncate(obj);
1740 static unsigned long
1741 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1742 bool purgeable_only)
1744 struct list_head still_bound_list;
1745 struct drm_i915_gem_object *obj, *next;
1746 unsigned long count = 0;
1748 list_for_each_entry_safe(obj, next,
1749 &dev_priv->mm.unbound_list,
1751 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1752 i915_gem_object_put_pages(obj) == 0) {
1753 count += obj->base.size >> PAGE_SHIFT;
1754 if (count >= target)
1760 * As we may completely rewrite the bound list whilst unbinding
1761 * (due to retiring requests) we have to strictly process only
1762 * one element of the list at the time, and recheck the list
1763 * on every iteration.
1765 INIT_LIST_HEAD(&still_bound_list);
1766 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1767 struct i915_vma *vma, *v;
1769 obj = list_first_entry(&dev_priv->mm.bound_list,
1770 typeof(*obj), global_list);
1771 list_move_tail(&obj->global_list, &still_bound_list);
1773 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1777 * Hold a reference whilst we unbind this object, as we may
1778 * end up waiting for and retiring requests. This might
1779 * release the final reference (held by the active list)
1780 * and result in the object being freed from under us.
1781 * in this object being freed.
1783 * Note 1: Shrinking the bound list is special since only active
1784 * (and hence bound objects) can contain such limbo objects, so
1785 * we don't need special tricks for shrinking the unbound list.
1786 * The only other place where we have to be careful with active
1787 * objects suddenly disappearing due to retiring requests is the
1790 * Note 2: Even though the bound list doesn't hold a reference
1791 * to the object we can safely grab one here: The final object
1792 * unreferencing and the bound_list are both protected by the
1793 * dev->struct_mutex and so we won't ever be able to observe an
1794 * object on the bound_list with a reference count equals 0.
1796 drm_gem_object_reference(&obj->base);
1798 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1799 if (i915_vma_unbind(vma))
1802 if (i915_gem_object_put_pages(obj) == 0)
1803 count += obj->base.size >> PAGE_SHIFT;
1805 drm_gem_object_unreference(&obj->base);
1807 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1812 static unsigned long
1813 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1815 return __i915_gem_shrink(dev_priv, target, true);
1818 static unsigned long
1819 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1821 struct drm_i915_gem_object *obj, *next;
1824 i915_gem_evict_everything(dev_priv->dev);
1826 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1828 if (i915_gem_object_put_pages(obj) == 0)
1829 freed += obj->base.size >> PAGE_SHIFT;
1835 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1837 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1839 struct address_space *mapping;
1840 struct sg_table *st;
1841 struct scatterlist *sg;
1842 struct sg_page_iter sg_iter;
1844 unsigned long last_pfn = 0; /* suppress gcc warning */
1847 /* Assert that the object is not currently in any GPU domain. As it
1848 * wasn't in the GTT, there shouldn't be any way it could have been in
1851 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1852 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1854 st = kmalloc(sizeof(*st), GFP_KERNEL);
1858 page_count = obj->base.size / PAGE_SIZE;
1859 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1864 /* Get the list of pages out of our struct file. They'll be pinned
1865 * at this point until we release them.
1867 * Fail silently without starting the shrinker
1869 mapping = file_inode(obj->base.filp)->i_mapping;
1870 gfp = mapping_gfp_mask(mapping);
1871 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1872 gfp &= ~(__GFP_IO | __GFP_WAIT);
1875 for (i = 0; i < page_count; i++) {
1876 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1878 i915_gem_purge(dev_priv, page_count);
1879 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1882 /* We've tried hard to allocate the memory by reaping
1883 * our own buffer, now let the real VM do its job and
1884 * go down in flames if truly OOM.
1886 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1887 gfp |= __GFP_IO | __GFP_WAIT;
1889 i915_gem_shrink_all(dev_priv);
1890 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1894 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1895 gfp &= ~(__GFP_IO | __GFP_WAIT);
1897 #ifdef CONFIG_SWIOTLB
1898 if (swiotlb_nr_tbl()) {
1900 sg_set_page(sg, page, PAGE_SIZE, 0);
1905 if (!i || page_to_pfn(page) != last_pfn + 1) {
1909 sg_set_page(sg, page, PAGE_SIZE, 0);
1911 sg->length += PAGE_SIZE;
1913 last_pfn = page_to_pfn(page);
1915 /* Check that the i965g/gm workaround works. */
1916 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1918 #ifdef CONFIG_SWIOTLB
1919 if (!swiotlb_nr_tbl())
1924 if (i915_gem_object_needs_bit17_swizzle(obj))
1925 i915_gem_object_do_bit_17_swizzle(obj);
1931 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1932 page_cache_release(sg_page_iter_page(&sg_iter));
1935 return PTR_ERR(page);
1938 /* Ensure that the associated pages are gathered from the backing storage
1939 * and pinned into our object. i915_gem_object_get_pages() may be called
1940 * multiple times before they are released by a single call to
1941 * i915_gem_object_put_pages() - once the pages are no longer referenced
1942 * either as a result of memory pressure (reaping pages under the shrinker)
1943 * or as the object is itself released.
1946 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1948 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1949 const struct drm_i915_gem_object_ops *ops = obj->ops;
1955 if (obj->madv != I915_MADV_WILLNEED) {
1956 DRM_ERROR("Attempting to obtain a purgeable object\n");
1960 BUG_ON(obj->pages_pin_count);
1962 ret = ops->get_pages(obj);
1966 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1971 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1972 struct intel_ring_buffer *ring)
1974 struct drm_device *dev = obj->base.dev;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 u32 seqno = intel_ring_get_seqno(ring);
1978 BUG_ON(ring == NULL);
1979 if (obj->ring != ring && obj->last_write_seqno) {
1980 /* Keep the seqno relative to the current ring */
1981 obj->last_write_seqno = seqno;
1985 /* Add a reference if we're newly entering the active list. */
1987 drm_gem_object_reference(&obj->base);
1991 list_move_tail(&obj->ring_list, &ring->active_list);
1993 obj->last_read_seqno = seqno;
1995 if (obj->fenced_gpu_access) {
1996 obj->last_fenced_seqno = seqno;
1998 /* Bump MRU to take account of the delayed flush */
1999 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2000 struct drm_i915_fence_reg *reg;
2002 reg = &dev_priv->fence_regs[obj->fence_reg];
2003 list_move_tail(®->lru_list,
2004 &dev_priv->mm.fence_list);
2009 void i915_vma_move_to_active(struct i915_vma *vma,
2010 struct intel_ring_buffer *ring)
2012 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2013 return i915_gem_object_move_to_active(vma->obj, ring);
2017 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2019 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2020 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2021 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2023 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2024 BUG_ON(!obj->active);
2026 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2028 list_del_init(&obj->ring_list);
2031 obj->last_read_seqno = 0;
2032 obj->last_write_seqno = 0;
2033 obj->base.write_domain = 0;
2035 obj->last_fenced_seqno = 0;
2036 obj->fenced_gpu_access = false;
2039 drm_gem_object_unreference(&obj->base);
2041 WARN_ON(i915_verify_lists(dev));
2045 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_ring_buffer *ring;
2051 /* Carefully retire all requests without writing to the rings */
2052 for_each_ring(ring, dev_priv, i) {
2053 ret = intel_ring_idle(ring);
2057 i915_gem_retire_requests(dev);
2059 /* Finally reset hw state */
2060 for_each_ring(ring, dev_priv, i) {
2061 intel_ring_init_seqno(ring, seqno);
2063 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2064 ring->sync_seqno[j] = 0;
2070 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2078 /* HWS page needs to be set less than what we
2079 * will inject to ring
2081 ret = i915_gem_init_seqno(dev, seqno - 1);
2085 /* Carefully set the last_seqno value so that wrap
2086 * detection still works
2088 dev_priv->next_seqno = seqno;
2089 dev_priv->last_seqno = seqno - 1;
2090 if (dev_priv->last_seqno == 0)
2091 dev_priv->last_seqno--;
2097 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2101 /* reserve 0 for non-seqno */
2102 if (dev_priv->next_seqno == 0) {
2103 int ret = i915_gem_init_seqno(dev, 0);
2107 dev_priv->next_seqno = 1;
2110 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2114 int __i915_add_request(struct intel_ring_buffer *ring,
2115 struct drm_file *file,
2116 struct drm_i915_gem_object *obj,
2119 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2120 struct drm_i915_gem_request *request;
2121 u32 request_ring_position, request_start;
2125 request_start = intel_ring_get_tail(ring);
2127 * Emit any outstanding flushes - execbuf can fail to emit the flush
2128 * after having emitted the batchbuffer command. Hence we need to fix
2129 * things up similar to emitting the lazy request. The difference here
2130 * is that the flush _must_ happen before the next request, no matter
2133 ret = intel_ring_flush_all_caches(ring);
2137 request = ring->preallocated_lazy_request;
2138 if (WARN_ON(request == NULL))
2141 /* Record the position of the start of the request so that
2142 * should we detect the updated seqno part-way through the
2143 * GPU processing the request, we never over-estimate the
2144 * position of the head.
2146 request_ring_position = intel_ring_get_tail(ring);
2148 ret = ring->add_request(ring);
2152 request->seqno = intel_ring_get_seqno(ring);
2153 request->ring = ring;
2154 request->head = request_start;
2155 request->tail = request_ring_position;
2157 /* Whilst this request exists, batch_obj will be on the
2158 * active_list, and so will hold the active reference. Only when this
2159 * request is retired will the the batch_obj be moved onto the
2160 * inactive_list and lose its active reference. Hence we do not need
2161 * to explicitly hold another reference here.
2163 request->batch_obj = obj;
2165 /* Hold a reference to the current context so that we can inspect
2166 * it later in case a hangcheck error event fires.
2168 request->ctx = ring->last_context;
2170 i915_gem_context_reference(request->ctx);
2172 request->emitted_jiffies = jiffies;
2173 was_empty = list_empty(&ring->request_list);
2174 list_add_tail(&request->list, &ring->request_list);
2175 request->file_priv = NULL;
2178 struct drm_i915_file_private *file_priv = file->driver_priv;
2180 spin_lock(&file_priv->mm.lock);
2181 request->file_priv = file_priv;
2182 list_add_tail(&request->client_list,
2183 &file_priv->mm.request_list);
2184 spin_unlock(&file_priv->mm.lock);
2187 trace_i915_gem_request_add(ring, request->seqno);
2188 ring->outstanding_lazy_seqno = 0;
2189 ring->preallocated_lazy_request = NULL;
2191 if (!dev_priv->ums.mm_suspended) {
2192 i915_queue_hangcheck(ring->dev);
2195 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2196 queue_delayed_work(dev_priv->wq,
2197 &dev_priv->mm.retire_work,
2198 round_jiffies_up_relative(HZ));
2199 intel_mark_busy(dev_priv->dev);
2204 *out_seqno = request->seqno;
2209 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2211 struct drm_i915_file_private *file_priv = request->file_priv;
2216 spin_lock(&file_priv->mm.lock);
2217 list_del(&request->client_list);
2218 request->file_priv = NULL;
2219 spin_unlock(&file_priv->mm.lock);
2222 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2223 struct i915_address_space *vm)
2225 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2226 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2232 static bool i915_head_inside_request(const u32 acthd_unmasked,
2233 const u32 request_start,
2234 const u32 request_end)
2236 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2238 if (request_start < request_end) {
2239 if (acthd >= request_start && acthd < request_end)
2241 } else if (request_start > request_end) {
2242 if (acthd >= request_start || acthd < request_end)
2249 static struct i915_address_space *
2250 request_to_vm(struct drm_i915_gem_request *request)
2252 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2253 struct i915_address_space *vm;
2255 vm = &dev_priv->gtt.base;
2260 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2261 const u32 acthd, bool *inside)
2263 /* There is a possibility that unmasked head address
2264 * pointing inside the ring, matches the batch_obj address range.
2265 * However this is extremely unlikely.
2267 if (request->batch_obj) {
2268 if (i915_head_inside_object(acthd, request->batch_obj,
2269 request_to_vm(request))) {
2275 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2283 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2285 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2290 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2291 DRM_ERROR("context hanging too fast, declaring banned!\n");
2298 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2299 struct drm_i915_gem_request *request,
2302 struct i915_ctx_hang_stats *hs = NULL;
2303 bool inside, guilty;
2304 unsigned long offset = 0;
2306 /* Innocent until proven guilty */
2309 if (request->batch_obj)
2310 offset = i915_gem_obj_offset(request->batch_obj,
2311 request_to_vm(request));
2313 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2314 i915_request_guilty(request, acthd, &inside)) {
2315 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2317 inside ? "inside" : "flushing",
2319 request->ctx ? request->ctx->id : 0,
2325 /* If contexts are disabled or this is the default context, use
2326 * file_priv->reset_state
2328 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2329 hs = &request->ctx->hang_stats;
2330 else if (request->file_priv)
2331 hs = &request->file_priv->hang_stats;
2335 hs->banned = i915_context_is_banned(hs);
2337 hs->guilty_ts = get_seconds();
2339 hs->batch_pending++;
2344 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2346 list_del(&request->list);
2347 i915_gem_request_remove_from_client(request);
2350 i915_gem_context_unreference(request->ctx);
2355 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2356 struct intel_ring_buffer *ring)
2358 u32 completed_seqno;
2361 acthd = intel_ring_get_active_head(ring);
2362 completed_seqno = ring->get_seqno(ring, false);
2364 while (!list_empty(&ring->request_list)) {
2365 struct drm_i915_gem_request *request;
2367 request = list_first_entry(&ring->request_list,
2368 struct drm_i915_gem_request,
2371 if (request->seqno > completed_seqno)
2372 i915_set_reset_status(ring, request, acthd);
2374 i915_gem_free_request(request);
2377 while (!list_empty(&ring->active_list)) {
2378 struct drm_i915_gem_object *obj;
2380 obj = list_first_entry(&ring->active_list,
2381 struct drm_i915_gem_object,
2384 i915_gem_object_move_to_inactive(obj);
2388 void i915_gem_restore_fences(struct drm_device *dev)
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2393 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2394 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2397 * Commit delayed tiling changes if we have an object still
2398 * attached to the fence, otherwise just clear the fence.
2401 i915_gem_object_update_fence(reg->obj, reg,
2402 reg->obj->tiling_mode);
2404 i915_gem_write_fence(dev, i, NULL);
2409 void i915_gem_reset(struct drm_device *dev)
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct intel_ring_buffer *ring;
2415 for_each_ring(ring, dev_priv, i)
2416 i915_gem_reset_ring_lists(dev_priv, ring);
2418 i915_gem_cleanup_ringbuffer(dev);
2420 i915_gem_restore_fences(dev);
2424 * This function clears the request list as sequence numbers are passed.
2427 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2431 if (list_empty(&ring->request_list))
2434 WARN_ON(i915_verify_lists(ring->dev));
2436 seqno = ring->get_seqno(ring, true);
2438 while (!list_empty(&ring->request_list)) {
2439 struct drm_i915_gem_request *request;
2441 request = list_first_entry(&ring->request_list,
2442 struct drm_i915_gem_request,
2445 if (!i915_seqno_passed(seqno, request->seqno))
2448 trace_i915_gem_request_retire(ring, request->seqno);
2449 /* We know the GPU must have read the request to have
2450 * sent us the seqno + interrupt, so use the position
2451 * of tail of the request to update the last known position
2454 ring->last_retired_head = request->tail;
2456 i915_gem_free_request(request);
2459 /* Move any buffers on the active list that are no longer referenced
2460 * by the ringbuffer to the flushing/inactive lists as appropriate.
2462 while (!list_empty(&ring->active_list)) {
2463 struct drm_i915_gem_object *obj;
2465 obj = list_first_entry(&ring->active_list,
2466 struct drm_i915_gem_object,
2469 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2472 i915_gem_object_move_to_inactive(obj);
2475 if (unlikely(ring->trace_irq_seqno &&
2476 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2477 ring->irq_put(ring);
2478 ring->trace_irq_seqno = 0;
2481 WARN_ON(i915_verify_lists(ring->dev));
2485 i915_gem_retire_requests(struct drm_device *dev)
2487 drm_i915_private_t *dev_priv = dev->dev_private;
2488 struct intel_ring_buffer *ring;
2492 for_each_ring(ring, dev_priv, i) {
2493 i915_gem_retire_requests_ring(ring);
2494 idle &= list_empty(&ring->request_list);
2498 mod_delayed_work(dev_priv->wq,
2499 &dev_priv->mm.idle_work,
2500 msecs_to_jiffies(100));
2506 i915_gem_retire_work_handler(struct work_struct *work)
2508 struct drm_i915_private *dev_priv =
2509 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2510 struct drm_device *dev = dev_priv->dev;
2513 /* Come back later if the device is busy... */
2515 if (mutex_trylock(&dev->struct_mutex)) {
2516 idle = i915_gem_retire_requests(dev);
2517 mutex_unlock(&dev->struct_mutex);
2520 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2521 round_jiffies_up_relative(HZ));
2525 i915_gem_idle_work_handler(struct work_struct *work)
2527 struct drm_i915_private *dev_priv =
2528 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2530 intel_mark_idle(dev_priv->dev);
2534 * Ensures that an object will eventually get non-busy by flushing any required
2535 * write domains, emitting any outstanding lazy request and retiring and
2536 * completed requests.
2539 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2544 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2548 i915_gem_retire_requests_ring(obj->ring);
2555 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2556 * @DRM_IOCTL_ARGS: standard ioctl arguments
2558 * Returns 0 if successful, else an error is returned with the remaining time in
2559 * the timeout parameter.
2560 * -ETIME: object is still busy after timeout
2561 * -ERESTARTSYS: signal interrupted the wait
2562 * -ENONENT: object doesn't exist
2563 * Also possible, but rare:
2564 * -EAGAIN: GPU wedged
2566 * -ENODEV: Internal IRQ fail
2567 * -E?: The add request failed
2569 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2570 * non-zero timeout parameter the wait ioctl will wait for the given number of
2571 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2572 * without holding struct_mutex the object may become re-busied before this
2573 * function completes. A similar but shorter * race condition exists in the busy
2577 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2579 drm_i915_private_t *dev_priv = dev->dev_private;
2580 struct drm_i915_gem_wait *args = data;
2581 struct drm_i915_gem_object *obj;
2582 struct intel_ring_buffer *ring = NULL;
2583 struct timespec timeout_stack, *timeout = NULL;
2584 unsigned reset_counter;
2588 if (args->timeout_ns >= 0) {
2589 timeout_stack = ns_to_timespec(args->timeout_ns);
2590 timeout = &timeout_stack;
2593 ret = i915_mutex_lock_interruptible(dev);
2597 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2598 if (&obj->base == NULL) {
2599 mutex_unlock(&dev->struct_mutex);
2603 /* Need to make sure the object gets inactive eventually. */
2604 ret = i915_gem_object_flush_active(obj);
2609 seqno = obj->last_read_seqno;
2616 /* Do this after OLR check to make sure we make forward progress polling
2617 * on this IOCTL with a 0 timeout (like busy ioctl)
2619 if (!args->timeout_ns) {
2624 drm_gem_object_unreference(&obj->base);
2625 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2626 mutex_unlock(&dev->struct_mutex);
2628 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2630 args->timeout_ns = timespec_to_ns(timeout);
2634 drm_gem_object_unreference(&obj->base);
2635 mutex_unlock(&dev->struct_mutex);
2640 * i915_gem_object_sync - sync an object to a ring.
2642 * @obj: object which may be in use on another ring.
2643 * @to: ring we wish to use the object on. May be NULL.
2645 * This code is meant to abstract object synchronization with the GPU.
2646 * Calling with NULL implies synchronizing the object with the CPU
2647 * rather than a particular GPU ring.
2649 * Returns 0 if successful, else propagates up the lower layer error.
2652 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2653 struct intel_ring_buffer *to)
2655 struct intel_ring_buffer *from = obj->ring;
2659 if (from == NULL || to == from)
2662 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2663 return i915_gem_object_wait_rendering(obj, false);
2665 idx = intel_ring_sync_index(from, to);
2667 seqno = obj->last_read_seqno;
2668 if (seqno <= from->sync_seqno[idx])
2671 ret = i915_gem_check_olr(obj->ring, seqno);
2675 trace_i915_gem_ring_sync_to(from, to, seqno);
2676 ret = to->sync_to(to, from, seqno);
2678 /* We use last_read_seqno because sync_to()
2679 * might have just caused seqno wrap under
2682 from->sync_seqno[idx] = obj->last_read_seqno;
2687 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2689 u32 old_write_domain, old_read_domains;
2691 /* Force a pagefault for domain tracking on next user access */
2692 i915_gem_release_mmap(obj);
2694 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2697 /* Wait for any direct GTT access to complete */
2700 old_read_domains = obj->base.read_domains;
2701 old_write_domain = obj->base.write_domain;
2703 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2704 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2706 trace_i915_gem_object_change_domain(obj,
2711 int i915_vma_unbind(struct i915_vma *vma)
2713 struct drm_i915_gem_object *obj = vma->obj;
2714 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2717 /* For now we only ever use 1 vma per object */
2718 WARN_ON(!list_is_singular(&obj->vma_list));
2720 if (list_empty(&vma->vma_link))
2723 if (!drm_mm_node_allocated(&vma->node)) {
2724 i915_gem_vma_destroy(vma);
2732 BUG_ON(obj->pages == NULL);
2734 ret = i915_gem_object_finish_gpu(obj);
2737 /* Continue on if we fail due to EIO, the GPU is hung so we
2738 * should be safe and we need to cleanup or else we might
2739 * cause memory corruption through use-after-free.
2742 i915_gem_object_finish_gtt(obj);
2744 /* release the fence reg _after_ flushing */
2745 ret = i915_gem_object_put_fence(obj);
2749 trace_i915_vma_unbind(vma);
2751 if (obj->has_global_gtt_mapping)
2752 i915_gem_gtt_unbind_object(obj);
2753 if (obj->has_aliasing_ppgtt_mapping) {
2754 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2755 obj->has_aliasing_ppgtt_mapping = 0;
2757 i915_gem_gtt_finish_object(obj);
2759 list_del(&vma->mm_list);
2760 /* Avoid an unnecessary call to unbind on rebind. */
2761 if (i915_is_ggtt(vma->vm))
2762 obj->map_and_fenceable = true;
2764 drm_mm_remove_node(&vma->node);
2765 i915_gem_vma_destroy(vma);
2767 /* Since the unbound list is global, only move to that list if
2768 * no more VMAs exist. */
2769 if (list_empty(&obj->vma_list))
2770 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2772 /* And finally now the object is completely decoupled from this vma,
2773 * we can drop its hold on the backing storage and allow it to be
2774 * reaped by the shrinker.
2776 i915_gem_object_unpin_pages(obj);
2782 * Unbinds an object from the global GTT aperture.
2785 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2787 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2788 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2790 if (!i915_gem_obj_ggtt_bound(obj))
2796 BUG_ON(obj->pages == NULL);
2798 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2801 int i915_gpu_idle(struct drm_device *dev)
2803 drm_i915_private_t *dev_priv = dev->dev_private;
2804 struct intel_ring_buffer *ring;
2807 /* Flush everything onto the inactive list. */
2808 for_each_ring(ring, dev_priv, i) {
2809 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2813 ret = intel_ring_idle(ring);
2821 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2822 struct drm_i915_gem_object *obj)
2824 drm_i915_private_t *dev_priv = dev->dev_private;
2826 int fence_pitch_shift;
2828 if (INTEL_INFO(dev)->gen >= 6) {
2829 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2830 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2832 fence_reg = FENCE_REG_965_0;
2833 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2836 fence_reg += reg * 8;
2838 /* To w/a incoherency with non-atomic 64-bit register updates,
2839 * we split the 64-bit update into two 32-bit writes. In order
2840 * for a partial fence not to be evaluated between writes, we
2841 * precede the update with write to turn off the fence register,
2842 * and only enable the fence as the last step.
2844 * For extra levels of paranoia, we make sure each step lands
2845 * before applying the next step.
2847 I915_WRITE(fence_reg, 0);
2848 POSTING_READ(fence_reg);
2851 u32 size = i915_gem_obj_ggtt_size(obj);
2854 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2856 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2857 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2858 if (obj->tiling_mode == I915_TILING_Y)
2859 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2860 val |= I965_FENCE_REG_VALID;
2862 I915_WRITE(fence_reg + 4, val >> 32);
2863 POSTING_READ(fence_reg + 4);
2865 I915_WRITE(fence_reg + 0, val);
2866 POSTING_READ(fence_reg);
2868 I915_WRITE(fence_reg + 4, 0);
2869 POSTING_READ(fence_reg + 4);
2873 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2874 struct drm_i915_gem_object *obj)
2876 drm_i915_private_t *dev_priv = dev->dev_private;
2880 u32 size = i915_gem_obj_ggtt_size(obj);
2884 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2885 (size & -size) != size ||
2886 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2887 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2888 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2890 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2895 /* Note: pitch better be a power of two tile widths */
2896 pitch_val = obj->stride / tile_width;
2897 pitch_val = ffs(pitch_val) - 1;
2899 val = i915_gem_obj_ggtt_offset(obj);
2900 if (obj->tiling_mode == I915_TILING_Y)
2901 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2902 val |= I915_FENCE_SIZE_BITS(size);
2903 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2904 val |= I830_FENCE_REG_VALID;
2909 reg = FENCE_REG_830_0 + reg * 4;
2911 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2913 I915_WRITE(reg, val);
2917 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2918 struct drm_i915_gem_object *obj)
2920 drm_i915_private_t *dev_priv = dev->dev_private;
2924 u32 size = i915_gem_obj_ggtt_size(obj);
2927 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2928 (size & -size) != size ||
2929 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2930 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2931 i915_gem_obj_ggtt_offset(obj), size);
2933 pitch_val = obj->stride / 128;
2934 pitch_val = ffs(pitch_val) - 1;
2936 val = i915_gem_obj_ggtt_offset(obj);
2937 if (obj->tiling_mode == I915_TILING_Y)
2938 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2939 val |= I830_FENCE_SIZE_BITS(size);
2940 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2941 val |= I830_FENCE_REG_VALID;
2945 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2946 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2949 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2951 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2954 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2955 struct drm_i915_gem_object *obj)
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2959 /* Ensure that all CPU reads are completed before installing a fence
2960 * and all writes before removing the fence.
2962 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2965 WARN(obj && (!obj->stride || !obj->tiling_mode),
2966 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2967 obj->stride, obj->tiling_mode);
2969 switch (INTEL_INFO(dev)->gen) {
2974 case 4: i965_write_fence_reg(dev, reg, obj); break;
2975 case 3: i915_write_fence_reg(dev, reg, obj); break;
2976 case 2: i830_write_fence_reg(dev, reg, obj); break;
2980 /* And similarly be paranoid that no direct access to this region
2981 * is reordered to before the fence is installed.
2983 if (i915_gem_object_needs_mb(obj))
2987 static inline int fence_number(struct drm_i915_private *dev_priv,
2988 struct drm_i915_fence_reg *fence)
2990 return fence - dev_priv->fence_regs;
2993 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2994 struct drm_i915_fence_reg *fence,
2997 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2998 int reg = fence_number(dev_priv, fence);
3000 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3003 obj->fence_reg = reg;
3005 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3007 obj->fence_reg = I915_FENCE_REG_NONE;
3009 list_del_init(&fence->lru_list);
3011 obj->fence_dirty = false;
3015 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3017 if (obj->last_fenced_seqno) {
3018 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3022 obj->last_fenced_seqno = 0;
3025 obj->fenced_gpu_access = false;
3030 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3032 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3033 struct drm_i915_fence_reg *fence;
3036 ret = i915_gem_object_wait_fence(obj);
3040 if (obj->fence_reg == I915_FENCE_REG_NONE)
3043 fence = &dev_priv->fence_regs[obj->fence_reg];
3045 i915_gem_object_fence_lost(obj);
3046 i915_gem_object_update_fence(obj, fence, false);
3051 static struct drm_i915_fence_reg *
3052 i915_find_fence_reg(struct drm_device *dev)
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct drm_i915_fence_reg *reg, *avail;
3058 /* First try to find a free reg */
3060 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3061 reg = &dev_priv->fence_regs[i];
3065 if (!reg->pin_count)
3072 /* None available, try to steal one or wait for a user to finish */
3073 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3084 * i915_gem_object_get_fence - set up fencing for an object
3085 * @obj: object to map through a fence reg
3087 * When mapping objects through the GTT, userspace wants to be able to write
3088 * to them without having to worry about swizzling if the object is tiled.
3089 * This function walks the fence regs looking for a free one for @obj,
3090 * stealing one if it can't find any.
3092 * It then sets up the reg based on the object's properties: address, pitch
3093 * and tiling format.
3095 * For an untiled surface, this removes any existing fence.
3098 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3100 struct drm_device *dev = obj->base.dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 bool enable = obj->tiling_mode != I915_TILING_NONE;
3103 struct drm_i915_fence_reg *reg;
3106 /* Have we updated the tiling parameters upon the object and so
3107 * will need to serialise the write to the associated fence register?
3109 if (obj->fence_dirty) {
3110 ret = i915_gem_object_wait_fence(obj);
3115 /* Just update our place in the LRU if our fence is getting reused. */
3116 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3117 reg = &dev_priv->fence_regs[obj->fence_reg];
3118 if (!obj->fence_dirty) {
3119 list_move_tail(®->lru_list,
3120 &dev_priv->mm.fence_list);
3123 } else if (enable) {
3124 reg = i915_find_fence_reg(dev);
3129 struct drm_i915_gem_object *old = reg->obj;
3131 ret = i915_gem_object_wait_fence(old);
3135 i915_gem_object_fence_lost(old);
3140 i915_gem_object_update_fence(obj, reg, enable);
3145 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3146 struct drm_mm_node *gtt_space,
3147 unsigned long cache_level)
3149 struct drm_mm_node *other;
3151 /* On non-LLC machines we have to be careful when putting differing
3152 * types of snoopable memory together to avoid the prefetcher
3153 * crossing memory domains and dying.
3158 if (!drm_mm_node_allocated(gtt_space))
3161 if (list_empty(>t_space->node_list))
3164 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3165 if (other->allocated && !other->hole_follows && other->color != cache_level)
3168 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3169 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3175 static void i915_gem_verify_gtt(struct drm_device *dev)
3178 struct drm_i915_private *dev_priv = dev->dev_private;
3179 struct drm_i915_gem_object *obj;
3182 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3183 if (obj->gtt_space == NULL) {
3184 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3189 if (obj->cache_level != obj->gtt_space->color) {
3190 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3191 i915_gem_obj_ggtt_offset(obj),
3192 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3194 obj->gtt_space->color);
3199 if (!i915_gem_valid_gtt_space(dev,
3201 obj->cache_level)) {
3202 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3203 i915_gem_obj_ggtt_offset(obj),
3204 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3216 * Finds free space in the GTT aperture and binds the object there.
3219 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3220 struct i915_address_space *vm,
3222 bool map_and_fenceable,
3225 struct drm_device *dev = obj->base.dev;
3226 drm_i915_private_t *dev_priv = dev->dev_private;
3227 u32 size, fence_size, fence_alignment, unfenced_alignment;
3229 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3230 struct i915_vma *vma;
3233 fence_size = i915_gem_get_gtt_size(dev,
3236 fence_alignment = i915_gem_get_gtt_alignment(dev,
3238 obj->tiling_mode, true);
3239 unfenced_alignment =
3240 i915_gem_get_gtt_alignment(dev,
3242 obj->tiling_mode, false);
3245 alignment = map_and_fenceable ? fence_alignment :
3247 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3248 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3252 size = map_and_fenceable ? fence_size : obj->base.size;
3254 /* If the object is bigger than the entire aperture, reject it early
3255 * before evicting everything in a vain attempt to find space.
3257 if (obj->base.size > gtt_max) {
3258 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3260 map_and_fenceable ? "mappable" : "total",
3265 ret = i915_gem_object_get_pages(obj);
3269 i915_gem_object_pin_pages(obj);
3271 BUG_ON(!i915_is_ggtt(vm));
3273 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3279 /* For now we only ever use 1 vma per object */
3280 WARN_ON(!list_is_singular(&obj->vma_list));
3283 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3285 obj->cache_level, 0, gtt_max,
3286 DRM_MM_SEARCH_DEFAULT);
3288 ret = i915_gem_evict_something(dev, vm, size, alignment,
3297 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3298 obj->cache_level))) {
3300 goto err_remove_node;
3303 ret = i915_gem_gtt_prepare_object(obj);
3305 goto err_remove_node;
3307 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3308 list_add_tail(&vma->mm_list, &vm->inactive_list);
3310 if (i915_is_ggtt(vm)) {
3311 bool mappable, fenceable;
3313 fenceable = (vma->node.size == fence_size &&
3314 (vma->node.start & (fence_alignment - 1)) == 0);
3316 mappable = (vma->node.start + obj->base.size <=
3317 dev_priv->gtt.mappable_end);
3319 obj->map_and_fenceable = mappable && fenceable;
3322 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3324 trace_i915_vma_bind(vma, map_and_fenceable);
3325 i915_gem_verify_gtt(dev);
3329 drm_mm_remove_node(&vma->node);
3331 i915_gem_vma_destroy(vma);
3333 i915_gem_object_unpin_pages(obj);
3338 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3341 /* If we don't have a page list set up, then we're not pinned
3342 * to GPU, and we can ignore the cache flush because it'll happen
3343 * again at bind time.
3345 if (obj->pages == NULL)
3349 * Stolen memory is always coherent with the GPU as it is explicitly
3350 * marked as wc by the system, or the system is cache-coherent.
3355 /* If the GPU is snooping the contents of the CPU cache,
3356 * we do not need to manually clear the CPU cache lines. However,
3357 * the caches are only snooped when the render cache is
3358 * flushed/invalidated. As we always have to emit invalidations
3359 * and flushes when moving into and out of the RENDER domain, correct
3360 * snooping behaviour occurs naturally as the result of our domain
3363 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3366 trace_i915_gem_object_clflush(obj);
3367 drm_clflush_sg(obj->pages);
3372 /** Flushes the GTT write domain for the object if it's dirty. */
3374 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3376 uint32_t old_write_domain;
3378 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3381 /* No actual flushing is required for the GTT write domain. Writes
3382 * to it immediately go to main memory as far as we know, so there's
3383 * no chipset flush. It also doesn't land in render cache.
3385 * However, we do have to enforce the order so that all writes through
3386 * the GTT land before any writes to the device, such as updates to
3391 old_write_domain = obj->base.write_domain;
3392 obj->base.write_domain = 0;
3394 trace_i915_gem_object_change_domain(obj,
3395 obj->base.read_domains,
3399 /** Flushes the CPU write domain for the object if it's dirty. */
3401 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3404 uint32_t old_write_domain;
3406 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3409 if (i915_gem_clflush_object(obj, force))
3410 i915_gem_chipset_flush(obj->base.dev);
3412 old_write_domain = obj->base.write_domain;
3413 obj->base.write_domain = 0;
3415 trace_i915_gem_object_change_domain(obj,
3416 obj->base.read_domains,
3421 * Moves a single object to the GTT read, and possibly write domain.
3423 * This function returns when the move is complete, including waiting on
3427 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3429 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3430 uint32_t old_write_domain, old_read_domains;
3433 /* Not valid to be called on unbound objects. */
3434 if (!i915_gem_obj_bound_any(obj))
3437 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3440 ret = i915_gem_object_wait_rendering(obj, !write);
3444 i915_gem_object_flush_cpu_write_domain(obj, false);
3446 /* Serialise direct access to this object with the barriers for
3447 * coherent writes from the GPU, by effectively invalidating the
3448 * GTT domain upon first access.
3450 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3453 old_write_domain = obj->base.write_domain;
3454 old_read_domains = obj->base.read_domains;
3456 /* It should now be out of any other write domains, and we can update
3457 * the domain values for our changes.
3459 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3460 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3462 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3463 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3467 trace_i915_gem_object_change_domain(obj,
3471 /* And bump the LRU for this access */
3472 if (i915_gem_object_is_inactive(obj)) {
3473 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3475 list_move_tail(&vma->mm_list,
3476 &dev_priv->gtt.base.inactive_list);
3483 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3484 enum i915_cache_level cache_level)
3486 struct drm_device *dev = obj->base.dev;
3487 drm_i915_private_t *dev_priv = dev->dev_private;
3488 struct i915_vma *vma;
3491 if (obj->cache_level == cache_level)
3494 if (obj->pin_count) {
3495 DRM_DEBUG("can not change the cache level of pinned objects\n");
3499 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3500 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3501 ret = i915_vma_unbind(vma);
3509 if (i915_gem_obj_bound_any(obj)) {
3510 ret = i915_gem_object_finish_gpu(obj);
3514 i915_gem_object_finish_gtt(obj);
3516 /* Before SandyBridge, you could not use tiling or fence
3517 * registers with snooped memory, so relinquish any fences
3518 * currently pointing to our region in the aperture.
3520 if (INTEL_INFO(dev)->gen < 6) {
3521 ret = i915_gem_object_put_fence(obj);
3526 if (obj->has_global_gtt_mapping)
3527 i915_gem_gtt_bind_object(obj, cache_level);
3528 if (obj->has_aliasing_ppgtt_mapping)
3529 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3533 list_for_each_entry(vma, &obj->vma_list, vma_link)
3534 vma->node.color = cache_level;
3535 obj->cache_level = cache_level;
3537 if (cpu_write_needs_clflush(obj)) {
3538 u32 old_read_domains, old_write_domain;
3540 /* If we're coming from LLC cached, then we haven't
3541 * actually been tracking whether the data is in the
3542 * CPU cache or not, since we only allow one bit set
3543 * in obj->write_domain and have been skipping the clflushes.
3544 * Just set it to the CPU cache for now.
3546 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3548 old_read_domains = obj->base.read_domains;
3549 old_write_domain = obj->base.write_domain;
3551 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3552 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3554 trace_i915_gem_object_change_domain(obj,
3559 i915_gem_verify_gtt(dev);
3563 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3564 struct drm_file *file)
3566 struct drm_i915_gem_caching *args = data;
3567 struct drm_i915_gem_object *obj;
3570 ret = i915_mutex_lock_interruptible(dev);
3574 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3575 if (&obj->base == NULL) {
3580 switch (obj->cache_level) {
3581 case I915_CACHE_LLC:
3582 case I915_CACHE_L3_LLC:
3583 args->caching = I915_CACHING_CACHED;
3587 args->caching = I915_CACHING_DISPLAY;
3591 args->caching = I915_CACHING_NONE;
3595 drm_gem_object_unreference(&obj->base);
3597 mutex_unlock(&dev->struct_mutex);
3601 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3602 struct drm_file *file)
3604 struct drm_i915_gem_caching *args = data;
3605 struct drm_i915_gem_object *obj;
3606 enum i915_cache_level level;
3609 switch (args->caching) {
3610 case I915_CACHING_NONE:
3611 level = I915_CACHE_NONE;
3613 case I915_CACHING_CACHED:
3614 level = I915_CACHE_LLC;
3616 case I915_CACHING_DISPLAY:
3617 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3623 ret = i915_mutex_lock_interruptible(dev);
3627 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3628 if (&obj->base == NULL) {
3633 ret = i915_gem_object_set_cache_level(obj, level);
3635 drm_gem_object_unreference(&obj->base);
3637 mutex_unlock(&dev->struct_mutex);
3641 static bool is_pin_display(struct drm_i915_gem_object *obj)
3643 /* There are 3 sources that pin objects:
3644 * 1. The display engine (scanouts, sprites, cursors);
3645 * 2. Reservations for execbuffer;
3648 * We can ignore reservations as we hold the struct_mutex and
3649 * are only called outside of the reservation path. The user
3650 * can only increment pin_count once, and so if after
3651 * subtracting the potential reference by the user, any pin_count
3652 * remains, it must be due to another use by the display engine.
3654 return obj->pin_count - !!obj->user_pin_count;
3658 * Prepare buffer for display plane (scanout, cursors, etc).
3659 * Can be called from an uninterruptible phase (modesetting) and allows
3660 * any flushes to be pipelined (for pageflips).
3663 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3665 struct intel_ring_buffer *pipelined)
3667 u32 old_read_domains, old_write_domain;
3670 if (pipelined != obj->ring) {
3671 ret = i915_gem_object_sync(obj, pipelined);
3676 /* Mark the pin_display early so that we account for the
3677 * display coherency whilst setting up the cache domains.
3679 obj->pin_display = true;
3681 /* The display engine is not coherent with the LLC cache on gen6. As
3682 * a result, we make sure that the pinning that is about to occur is
3683 * done with uncached PTEs. This is lowest common denominator for all
3686 * However for gen6+, we could do better by using the GFDT bit instead
3687 * of uncaching, which would allow us to flush all the LLC-cached data
3688 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3690 ret = i915_gem_object_set_cache_level(obj,
3691 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3693 goto err_unpin_display;
3695 /* As the user may map the buffer once pinned in the display plane
3696 * (e.g. libkms for the bootup splash), we have to ensure that we
3697 * always use map_and_fenceable for all scanout buffers.
3699 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3701 goto err_unpin_display;
3703 i915_gem_object_flush_cpu_write_domain(obj, true);
3705 old_write_domain = obj->base.write_domain;
3706 old_read_domains = obj->base.read_domains;
3708 /* It should now be out of any other write domains, and we can update
3709 * the domain values for our changes.
3711 obj->base.write_domain = 0;
3712 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3714 trace_i915_gem_object_change_domain(obj,
3721 obj->pin_display = is_pin_display(obj);
3726 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3728 i915_gem_object_unpin(obj);
3729 obj->pin_display = is_pin_display(obj);
3733 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3737 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3740 ret = i915_gem_object_wait_rendering(obj, false);
3744 /* Ensure that we invalidate the GPU's caches and TLBs. */
3745 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3750 * Moves a single object to the CPU read, and possibly write domain.
3752 * This function returns when the move is complete, including waiting on
3756 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3758 uint32_t old_write_domain, old_read_domains;
3761 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3764 ret = i915_gem_object_wait_rendering(obj, !write);
3768 i915_gem_object_flush_gtt_write_domain(obj);
3770 old_write_domain = obj->base.write_domain;
3771 old_read_domains = obj->base.read_domains;
3773 /* Flush the CPU cache if it's still invalid. */
3774 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3775 i915_gem_clflush_object(obj, false);
3777 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3780 /* It should now be out of any other write domains, and we can update
3781 * the domain values for our changes.
3783 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3785 /* If we're writing through the CPU, then the GPU read domains will
3786 * need to be invalidated at next use.
3789 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3790 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3793 trace_i915_gem_object_change_domain(obj,
3800 /* Throttle our rendering by waiting until the ring has completed our requests
3801 * emitted over 20 msec ago.
3803 * Note that if we were to use the current jiffies each time around the loop,
3804 * we wouldn't escape the function with any frames outstanding if the time to
3805 * render a frame was over 20ms.
3807 * This should get us reasonable parallelism between CPU and GPU but also
3808 * relatively low latency when blocking on a particular request to finish.
3811 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct drm_i915_file_private *file_priv = file->driver_priv;
3815 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3816 struct drm_i915_gem_request *request;
3817 struct intel_ring_buffer *ring = NULL;
3818 unsigned reset_counter;
3822 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3826 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3830 spin_lock(&file_priv->mm.lock);
3831 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3832 if (time_after_eq(request->emitted_jiffies, recent_enough))
3835 ring = request->ring;
3836 seqno = request->seqno;
3838 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3839 spin_unlock(&file_priv->mm.lock);
3844 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3852 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3853 struct i915_address_space *vm,
3855 bool map_and_fenceable,
3858 struct i915_vma *vma;
3861 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3864 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3866 vma = i915_gem_obj_to_vma(obj, vm);
3870 vma->node.start & (alignment - 1)) ||
3871 (map_and_fenceable && !obj->map_and_fenceable)) {
3872 WARN(obj->pin_count,
3873 "bo is already pinned with incorrect alignment:"
3874 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3875 " obj->map_and_fenceable=%d\n",
3876 i915_gem_obj_offset(obj, vm), alignment,
3878 obj->map_and_fenceable);
3879 ret = i915_vma_unbind(vma);
3885 if (!i915_gem_obj_bound(obj, vm)) {
3886 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3888 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3894 if (!dev_priv->mm.aliasing_ppgtt)
3895 i915_gem_gtt_bind_object(obj, obj->cache_level);
3898 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3899 i915_gem_gtt_bind_object(obj, obj->cache_level);
3902 obj->pin_mappable |= map_and_fenceable;
3908 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3910 BUG_ON(obj->pin_count == 0);
3911 BUG_ON(!i915_gem_obj_bound_any(obj));
3913 if (--obj->pin_count == 0)
3914 obj->pin_mappable = false;
3918 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3919 struct drm_file *file)
3921 struct drm_i915_gem_pin *args = data;
3922 struct drm_i915_gem_object *obj;
3925 ret = i915_mutex_lock_interruptible(dev);
3929 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3930 if (&obj->base == NULL) {
3935 if (obj->madv != I915_MADV_WILLNEED) {
3936 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3941 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3942 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3948 if (obj->user_pin_count == ULONG_MAX) {
3953 if (obj->user_pin_count == 0) {
3954 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3959 obj->user_pin_count++;
3960 obj->pin_filp = file;
3962 args->offset = i915_gem_obj_ggtt_offset(obj);
3964 drm_gem_object_unreference(&obj->base);
3966 mutex_unlock(&dev->struct_mutex);
3971 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3972 struct drm_file *file)
3974 struct drm_i915_gem_pin *args = data;
3975 struct drm_i915_gem_object *obj;
3978 ret = i915_mutex_lock_interruptible(dev);
3982 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3983 if (&obj->base == NULL) {
3988 if (obj->pin_filp != file) {
3989 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3994 obj->user_pin_count--;
3995 if (obj->user_pin_count == 0) {
3996 obj->pin_filp = NULL;
3997 i915_gem_object_unpin(obj);
4001 drm_gem_object_unreference(&obj->base);
4003 mutex_unlock(&dev->struct_mutex);
4008 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4009 struct drm_file *file)
4011 struct drm_i915_gem_busy *args = data;
4012 struct drm_i915_gem_object *obj;
4015 ret = i915_mutex_lock_interruptible(dev);
4019 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4020 if (&obj->base == NULL) {
4025 /* Count all active objects as busy, even if they are currently not used
4026 * by the gpu. Users of this interface expect objects to eventually
4027 * become non-busy without any further actions, therefore emit any
4028 * necessary flushes here.
4030 ret = i915_gem_object_flush_active(obj);
4032 args->busy = obj->active;
4034 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4035 args->busy |= intel_ring_flag(obj->ring) << 16;
4038 drm_gem_object_unreference(&obj->base);
4040 mutex_unlock(&dev->struct_mutex);
4045 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4046 struct drm_file *file_priv)
4048 return i915_gem_ring_throttle(dev, file_priv);
4052 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4053 struct drm_file *file_priv)
4055 struct drm_i915_gem_madvise *args = data;
4056 struct drm_i915_gem_object *obj;
4059 switch (args->madv) {
4060 case I915_MADV_DONTNEED:
4061 case I915_MADV_WILLNEED:
4067 ret = i915_mutex_lock_interruptible(dev);
4071 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4072 if (&obj->base == NULL) {
4077 if (obj->pin_count) {
4082 if (obj->madv != __I915_MADV_PURGED)
4083 obj->madv = args->madv;
4085 /* if the object is no longer attached, discard its backing storage */
4086 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4087 i915_gem_object_truncate(obj);
4089 args->retained = obj->madv != __I915_MADV_PURGED;
4092 drm_gem_object_unreference(&obj->base);
4094 mutex_unlock(&dev->struct_mutex);
4098 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4099 const struct drm_i915_gem_object_ops *ops)
4101 INIT_LIST_HEAD(&obj->global_list);
4102 INIT_LIST_HEAD(&obj->ring_list);
4103 INIT_LIST_HEAD(&obj->obj_exec_link);
4104 INIT_LIST_HEAD(&obj->vma_list);
4108 obj->fence_reg = I915_FENCE_REG_NONE;
4109 obj->madv = I915_MADV_WILLNEED;
4110 /* Avoid an unnecessary call to unbind on the first bind. */
4111 obj->map_and_fenceable = true;
4113 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4116 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4117 .get_pages = i915_gem_object_get_pages_gtt,
4118 .put_pages = i915_gem_object_put_pages_gtt,
4121 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4124 struct drm_i915_gem_object *obj;
4125 struct address_space *mapping;
4128 obj = i915_gem_object_alloc(dev);
4132 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4133 i915_gem_object_free(obj);
4137 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4138 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4139 /* 965gm cannot relocate objects above 4GiB. */
4140 mask &= ~__GFP_HIGHMEM;
4141 mask |= __GFP_DMA32;
4144 mapping = file_inode(obj->base.filp)->i_mapping;
4145 mapping_set_gfp_mask(mapping, mask);
4147 i915_gem_object_init(obj, &i915_gem_object_ops);
4149 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4150 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4153 /* On some devices, we can have the GPU use the LLC (the CPU
4154 * cache) for about a 10% performance improvement
4155 * compared to uncached. Graphics requests other than
4156 * display scanout are coherent with the CPU in
4157 * accessing this cache. This means in this mode we
4158 * don't need to clflush on the CPU side, and on the
4159 * GPU side we only need to flush internal caches to
4160 * get data visible to the CPU.
4162 * However, we maintain the display planes as UC, and so
4163 * need to rebind when first used as such.
4165 obj->cache_level = I915_CACHE_LLC;
4167 obj->cache_level = I915_CACHE_NONE;
4169 trace_i915_gem_object_create(obj);
4174 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4176 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4177 struct drm_device *dev = obj->base.dev;
4178 drm_i915_private_t *dev_priv = dev->dev_private;
4179 struct i915_vma *vma, *next;
4181 intel_runtime_pm_get(dev_priv);
4183 trace_i915_gem_object_destroy(obj);
4186 i915_gem_detach_phys_object(dev, obj);
4189 /* NB: 0 or 1 elements */
4190 WARN_ON(!list_empty(&obj->vma_list) &&
4191 !list_is_singular(&obj->vma_list));
4192 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4193 int ret = i915_vma_unbind(vma);
4194 if (WARN_ON(ret == -ERESTARTSYS)) {
4195 bool was_interruptible;
4197 was_interruptible = dev_priv->mm.interruptible;
4198 dev_priv->mm.interruptible = false;
4200 WARN_ON(i915_vma_unbind(vma));
4202 dev_priv->mm.interruptible = was_interruptible;
4206 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4207 * before progressing. */
4209 i915_gem_object_unpin_pages(obj);
4211 if (WARN_ON(obj->pages_pin_count))
4212 obj->pages_pin_count = 0;
4213 i915_gem_object_put_pages(obj);
4214 i915_gem_object_free_mmap_offset(obj);
4215 i915_gem_object_release_stolen(obj);
4219 if (obj->base.import_attach)
4220 drm_prime_gem_destroy(&obj->base, NULL);
4222 drm_gem_object_release(&obj->base);
4223 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4226 i915_gem_object_free(obj);
4228 intel_runtime_pm_put(dev_priv);
4231 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4232 struct i915_address_space *vm)
4234 struct i915_vma *vma;
4235 list_for_each_entry(vma, &obj->vma_list, vma_link)
4242 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4243 struct i915_address_space *vm)
4245 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4247 return ERR_PTR(-ENOMEM);
4249 INIT_LIST_HEAD(&vma->vma_link);
4250 INIT_LIST_HEAD(&vma->mm_list);
4251 INIT_LIST_HEAD(&vma->exec_list);
4255 /* Keep GGTT vmas first to make debug easier */
4256 if (i915_is_ggtt(vm))
4257 list_add(&vma->vma_link, &obj->vma_list);
4259 list_add_tail(&vma->vma_link, &obj->vma_list);
4265 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4266 struct i915_address_space *vm)
4268 struct i915_vma *vma;
4270 vma = i915_gem_obj_to_vma(obj, vm);
4272 vma = __i915_gem_vma_create(obj, vm);
4277 void i915_gem_vma_destroy(struct i915_vma *vma)
4279 WARN_ON(vma->node.allocated);
4281 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4282 if (!list_empty(&vma->exec_list))
4285 list_del(&vma->vma_link);
4291 i915_gem_suspend(struct drm_device *dev)
4293 drm_i915_private_t *dev_priv = dev->dev_private;
4296 mutex_lock(&dev->struct_mutex);
4297 if (dev_priv->ums.mm_suspended)
4300 ret = i915_gpu_idle(dev);
4304 i915_gem_retire_requests(dev);
4306 /* Under UMS, be paranoid and evict. */
4307 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4308 i915_gem_evict_everything(dev);
4310 i915_kernel_lost_context(dev);
4311 i915_gem_cleanup_ringbuffer(dev);
4313 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4314 * We need to replace this with a semaphore, or something.
4315 * And not confound ums.mm_suspended!
4317 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4319 mutex_unlock(&dev->struct_mutex);
4321 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4322 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4323 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4328 mutex_unlock(&dev->struct_mutex);
4332 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4334 struct drm_device *dev = ring->dev;
4335 drm_i915_private_t *dev_priv = dev->dev_private;
4336 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4337 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4340 if (!HAS_L3_DPF(dev) || !remap_info)
4343 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4348 * Note: We do not worry about the concurrent register cacheline hang
4349 * here because no other code should access these registers other than
4350 * at initialization time.
4352 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4353 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4354 intel_ring_emit(ring, reg_base + i);
4355 intel_ring_emit(ring, remap_info[i/4]);
4358 intel_ring_advance(ring);
4363 void i915_gem_init_swizzling(struct drm_device *dev)
4365 drm_i915_private_t *dev_priv = dev->dev_private;
4367 if (INTEL_INFO(dev)->gen < 5 ||
4368 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4371 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4372 DISP_TILE_SURFACE_SWIZZLING);
4377 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4379 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4380 else if (IS_GEN7(dev))
4381 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4382 else if (IS_GEN8(dev))
4383 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4389 intel_enable_blt(struct drm_device *dev)
4394 /* The blitter was dysfunctional on early prototypes */
4395 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4396 DRM_INFO("BLT not supported on this pre-production hardware;"
4397 " graphics performance will be degraded.\n");
4404 static int i915_gem_init_rings(struct drm_device *dev)
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4409 ret = intel_init_render_ring_buffer(dev);
4414 ret = intel_init_bsd_ring_buffer(dev);
4416 goto cleanup_render_ring;
4419 if (intel_enable_blt(dev)) {
4420 ret = intel_init_blt_ring_buffer(dev);
4422 goto cleanup_bsd_ring;
4425 if (HAS_VEBOX(dev)) {
4426 ret = intel_init_vebox_ring_buffer(dev);
4428 goto cleanup_blt_ring;
4432 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4434 goto cleanup_vebox_ring;
4439 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4441 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4443 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4444 cleanup_render_ring:
4445 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4451 i915_gem_init_hw(struct drm_device *dev)
4453 drm_i915_private_t *dev_priv = dev->dev_private;
4456 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4459 if (dev_priv->ellc_size)
4460 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4462 if (IS_HSW_GT3(dev))
4463 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
4465 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
4467 if (HAS_PCH_NOP(dev)) {
4468 u32 temp = I915_READ(GEN7_MSG_CTL);
4469 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4470 I915_WRITE(GEN7_MSG_CTL, temp);
4473 i915_gem_init_swizzling(dev);
4475 ret = i915_gem_init_rings(dev);
4479 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4480 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4483 * XXX: There was some w/a described somewhere suggesting loading
4484 * contexts before PPGTT.
4486 ret = i915_gem_context_init(dev);
4488 i915_gem_cleanup_ringbuffer(dev);
4489 DRM_ERROR("Context initialization failed %d\n", ret);
4493 if (dev_priv->mm.aliasing_ppgtt) {
4494 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4496 i915_gem_cleanup_aliasing_ppgtt(dev);
4497 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4504 int i915_gem_init(struct drm_device *dev)
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4509 mutex_lock(&dev->struct_mutex);
4511 if (IS_VALLEYVIEW(dev)) {
4512 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4513 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4514 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4515 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4518 i915_gem_init_global_gtt(dev);
4520 ret = i915_gem_init_hw(dev);
4521 mutex_unlock(&dev->struct_mutex);
4523 i915_gem_cleanup_aliasing_ppgtt(dev);
4527 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4528 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4529 dev_priv->dri1.allow_batchbuffer = 1;
4534 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4536 drm_i915_private_t *dev_priv = dev->dev_private;
4537 struct intel_ring_buffer *ring;
4540 for_each_ring(ring, dev_priv, i)
4541 intel_cleanup_ring_buffer(ring);
4545 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4546 struct drm_file *file_priv)
4548 struct drm_i915_private *dev_priv = dev->dev_private;
4551 if (drm_core_check_feature(dev, DRIVER_MODESET))
4554 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4555 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4556 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4559 mutex_lock(&dev->struct_mutex);
4560 dev_priv->ums.mm_suspended = 0;
4562 ret = i915_gem_init_hw(dev);
4564 mutex_unlock(&dev->struct_mutex);
4568 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4569 mutex_unlock(&dev->struct_mutex);
4571 ret = drm_irq_install(dev);
4573 goto cleanup_ringbuffer;
4578 mutex_lock(&dev->struct_mutex);
4579 i915_gem_cleanup_ringbuffer(dev);
4580 dev_priv->ums.mm_suspended = 1;
4581 mutex_unlock(&dev->struct_mutex);
4587 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4588 struct drm_file *file_priv)
4590 if (drm_core_check_feature(dev, DRIVER_MODESET))
4593 drm_irq_uninstall(dev);
4595 return i915_gem_suspend(dev);
4599 i915_gem_lastclose(struct drm_device *dev)
4603 if (drm_core_check_feature(dev, DRIVER_MODESET))
4606 ret = i915_gem_suspend(dev);
4608 DRM_ERROR("failed to idle hardware: %d\n", ret);
4612 init_ring_lists(struct intel_ring_buffer *ring)
4614 INIT_LIST_HEAD(&ring->active_list);
4615 INIT_LIST_HEAD(&ring->request_list);
4618 static void i915_init_vm(struct drm_i915_private *dev_priv,
4619 struct i915_address_space *vm)
4621 vm->dev = dev_priv->dev;
4622 INIT_LIST_HEAD(&vm->active_list);
4623 INIT_LIST_HEAD(&vm->inactive_list);
4624 INIT_LIST_HEAD(&vm->global_link);
4625 list_add(&vm->global_link, &dev_priv->vm_list);
4629 i915_gem_load(struct drm_device *dev)
4631 drm_i915_private_t *dev_priv = dev->dev_private;
4635 kmem_cache_create("i915_gem_object",
4636 sizeof(struct drm_i915_gem_object), 0,
4640 INIT_LIST_HEAD(&dev_priv->vm_list);
4641 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4643 INIT_LIST_HEAD(&dev_priv->context_list);
4644 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4645 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4646 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4647 for (i = 0; i < I915_NUM_RINGS; i++)
4648 init_ring_lists(&dev_priv->ring[i]);
4649 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4650 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4651 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4652 i915_gem_retire_work_handler);
4653 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4654 i915_gem_idle_work_handler);
4655 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4657 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4659 I915_WRITE(MI_ARB_STATE,
4660 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4663 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4665 /* Old X drivers will take 0-2 for front, back, depth buffers */
4666 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4667 dev_priv->fence_reg_start = 3;
4669 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4670 dev_priv->num_fence_regs = 32;
4671 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4672 dev_priv->num_fence_regs = 16;
4674 dev_priv->num_fence_regs = 8;
4676 /* Initialize fence registers to zero */
4677 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4678 i915_gem_restore_fences(dev);
4680 i915_gem_detect_bit_6_swizzle(dev);
4681 init_waitqueue_head(&dev_priv->pending_flip_queue);
4683 dev_priv->mm.interruptible = true;
4685 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4686 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4687 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4688 register_shrinker(&dev_priv->mm.inactive_shrinker);
4692 * Create a physically contiguous memory object for this object
4693 * e.g. for cursor + overlay regs
4695 static int i915_gem_init_phys_object(struct drm_device *dev,
4696 int id, int size, int align)
4698 drm_i915_private_t *dev_priv = dev->dev_private;
4699 struct drm_i915_gem_phys_object *phys_obj;
4702 if (dev_priv->mm.phys_objs[id - 1] || !size)
4705 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4711 phys_obj->handle = drm_pci_alloc(dev, size, align);
4712 if (!phys_obj->handle) {
4717 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4720 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4728 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4730 drm_i915_private_t *dev_priv = dev->dev_private;
4731 struct drm_i915_gem_phys_object *phys_obj;
4733 if (!dev_priv->mm.phys_objs[id - 1])
4736 phys_obj = dev_priv->mm.phys_objs[id - 1];
4737 if (phys_obj->cur_obj) {
4738 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4742 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4744 drm_pci_free(dev, phys_obj->handle);
4746 dev_priv->mm.phys_objs[id - 1] = NULL;
4749 void i915_gem_free_all_phys_object(struct drm_device *dev)
4753 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4754 i915_gem_free_phys_object(dev, i);
4757 void i915_gem_detach_phys_object(struct drm_device *dev,
4758 struct drm_i915_gem_object *obj)
4760 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4767 vaddr = obj->phys_obj->handle->vaddr;
4769 page_count = obj->base.size / PAGE_SIZE;
4770 for (i = 0; i < page_count; i++) {
4771 struct page *page = shmem_read_mapping_page(mapping, i);
4772 if (!IS_ERR(page)) {
4773 char *dst = kmap_atomic(page);
4774 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4777 drm_clflush_pages(&page, 1);
4779 set_page_dirty(page);
4780 mark_page_accessed(page);
4781 page_cache_release(page);
4784 i915_gem_chipset_flush(dev);
4786 obj->phys_obj->cur_obj = NULL;
4787 obj->phys_obj = NULL;
4791 i915_gem_attach_phys_object(struct drm_device *dev,
4792 struct drm_i915_gem_object *obj,
4796 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4797 drm_i915_private_t *dev_priv = dev->dev_private;
4802 if (id > I915_MAX_PHYS_OBJECT)
4805 if (obj->phys_obj) {
4806 if (obj->phys_obj->id == id)
4808 i915_gem_detach_phys_object(dev, obj);
4811 /* create a new object */
4812 if (!dev_priv->mm.phys_objs[id - 1]) {
4813 ret = i915_gem_init_phys_object(dev, id,
4814 obj->base.size, align);
4816 DRM_ERROR("failed to init phys object %d size: %zu\n",
4817 id, obj->base.size);
4822 /* bind to the object */
4823 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4824 obj->phys_obj->cur_obj = obj;
4826 page_count = obj->base.size / PAGE_SIZE;
4828 for (i = 0; i < page_count; i++) {
4832 page = shmem_read_mapping_page(mapping, i);
4834 return PTR_ERR(page);
4836 src = kmap_atomic(page);
4837 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4838 memcpy(dst, src, PAGE_SIZE);
4841 mark_page_accessed(page);
4842 page_cache_release(page);
4849 i915_gem_phys_pwrite(struct drm_device *dev,
4850 struct drm_i915_gem_object *obj,
4851 struct drm_i915_gem_pwrite *args,
4852 struct drm_file *file_priv)
4854 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4855 char __user *user_data = to_user_ptr(args->data_ptr);
4857 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4858 unsigned long unwritten;
4860 /* The physical object once assigned is fixed for the lifetime
4861 * of the obj, so we can safely drop the lock and continue
4864 mutex_unlock(&dev->struct_mutex);
4865 unwritten = copy_from_user(vaddr, user_data, args->size);
4866 mutex_lock(&dev->struct_mutex);
4871 i915_gem_chipset_flush(dev);
4875 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4877 struct drm_i915_file_private *file_priv = file->driver_priv;
4879 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4881 /* Clean up our request list when the client is going away, so that
4882 * later retire_requests won't dereference our soon-to-be-gone
4885 spin_lock(&file_priv->mm.lock);
4886 while (!list_empty(&file_priv->mm.request_list)) {
4887 struct drm_i915_gem_request *request;
4889 request = list_first_entry(&file_priv->mm.request_list,
4890 struct drm_i915_gem_request,
4892 list_del(&request->client_list);
4893 request->file_priv = NULL;
4895 spin_unlock(&file_priv->mm.lock);
4899 i915_gem_file_idle_work_handler(struct work_struct *work)
4901 struct drm_i915_file_private *file_priv =
4902 container_of(work, typeof(*file_priv), mm.idle_work.work);
4904 atomic_set(&file_priv->rps_wait_boost, false);
4907 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4909 struct drm_i915_file_private *file_priv;
4911 DRM_DEBUG_DRIVER("\n");
4913 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4917 file->driver_priv = file_priv;
4918 file_priv->dev_priv = dev->dev_private;
4920 spin_lock_init(&file_priv->mm.lock);
4921 INIT_LIST_HEAD(&file_priv->mm.request_list);
4922 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4923 i915_gem_file_idle_work_handler);
4925 idr_init(&file_priv->context_idr);
4930 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4932 if (!mutex_is_locked(mutex))
4935 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4936 return mutex->owner == task;
4938 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4943 static unsigned long
4944 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4946 struct drm_i915_private *dev_priv =
4947 container_of(shrinker,
4948 struct drm_i915_private,
4949 mm.inactive_shrinker);
4950 struct drm_device *dev = dev_priv->dev;
4951 struct drm_i915_gem_object *obj;
4953 unsigned long count;
4955 if (!mutex_trylock(&dev->struct_mutex)) {
4956 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4959 if (dev_priv->mm.shrinker_no_lock_stealing)
4966 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4967 if (obj->pages_pin_count == 0)
4968 count += obj->base.size >> PAGE_SHIFT;
4970 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4974 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4975 count += obj->base.size >> PAGE_SHIFT;
4979 mutex_unlock(&dev->struct_mutex);
4984 /* All the new VM stuff */
4985 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4986 struct i915_address_space *vm)
4988 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4989 struct i915_vma *vma;
4991 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4992 vm = &dev_priv->gtt.base;
4994 BUG_ON(list_empty(&o->vma_list));
4995 list_for_each_entry(vma, &o->vma_list, vma_link) {
4997 return vma->node.start;
5003 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5004 struct i915_address_space *vm)
5006 struct i915_vma *vma;
5008 list_for_each_entry(vma, &o->vma_list, vma_link)
5009 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5015 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5017 struct i915_vma *vma;
5019 list_for_each_entry(vma, &o->vma_list, vma_link)
5020 if (drm_mm_node_allocated(&vma->node))
5026 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5027 struct i915_address_space *vm)
5029 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5030 struct i915_vma *vma;
5032 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5033 vm = &dev_priv->gtt.base;
5035 BUG_ON(list_empty(&o->vma_list));
5037 list_for_each_entry(vma, &o->vma_list, vma_link)
5039 return vma->node.size;
5044 static unsigned long
5045 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5047 struct drm_i915_private *dev_priv =
5048 container_of(shrinker,
5049 struct drm_i915_private,
5050 mm.inactive_shrinker);
5051 struct drm_device *dev = dev_priv->dev;
5052 unsigned long freed;
5055 if (!mutex_trylock(&dev->struct_mutex)) {
5056 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5059 if (dev_priv->mm.shrinker_no_lock_stealing)
5065 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5066 if (freed < sc->nr_to_scan)
5067 freed += __i915_gem_shrink(dev_priv,
5068 sc->nr_to_scan - freed,
5070 if (freed < sc->nr_to_scan)
5071 freed += i915_gem_shrink_all(dev_priv);
5074 mutex_unlock(&dev->struct_mutex);
5079 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5081 struct i915_vma *vma;
5083 if (WARN_ON(list_empty(&obj->vma_list)))
5086 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5087 if (WARN_ON(vma->vm != obj_to_ggtt(obj)))