drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hashtable.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/pm_qos.h>
  44 #include <linux/reservation.h>
  45 #include <linux/shmem_fs.h>
  46
  47 #include <drm/drmP.h>
  48 #include <drm/intel-gtt.h>
  49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  50 #include <drm/drm_gem.h>
  51 #include <drm/drm_auth.h>
  52 #include <drm/drm_cache.h>
  53
  54 #include "i915_params.h"
  55 #include "i915_reg.h"
  56 #include "i915_utils.h"
  57
  58 #include "intel_bios.h"
  59 #include "intel_dpll_mgr.h"
  60 #include "intel_uc.h"
  61 #include "intel_lrc.h"
  62 #include "intel_ringbuffer.h"
  63
  64 #include "i915_gem.h"
  65 #include "i915_gem_context.h"
  66 #include "i915_gem_fence_reg.h"
  67 #include "i915_gem_object.h"
  68 #include "i915_gem_gtt.h"
  69 #include "i915_gem_render_state.h"
  70 #include "i915_gem_request.h"
  71 #include "i915_gem_timeline.h"
  72
  73 #include "i915_vma.h"
  74
  75 #include "intel_gvt.h"
  76
  77 /* General customization:
  78  */
  79
  80 #define DRIVER_NAME             "i915"
  81 #define DRIVER_DESC             "Intel Graphics"
  82 #define DRIVER_DATE             "20170206"
  83 #define DRIVER_TIMESTAMP        1486372993
  84
  85 #undef WARN_ON
  86 /* Many gcc seem to no see through this and fall over :( */
  87 #if 0
  88 #define WARN_ON(x) ({ \
  89         bool __i915_warn_cond = (x); \
  90         if (__builtin_constant_p(__i915_warn_cond)) \
  91                 BUILD_BUG_ON(__i915_warn_cond); \
  92         WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
  93 #else
  94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
  95 #endif
  96
  97 #undef WARN_ON_ONCE
  98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
  99
 100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
 101                              (long) (x), __func__);
 102
 103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 104  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 105  * which may not necessarily be a user visible problem.  This will either
 106  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 107  * enable distros and users to tailor their preferred amount of i915 abrt
 108  * spam.
 109  */
 110 #define I915_STATE_WARN(condition, format...) ({                        \
 111         int __ret_warn_on = !!(condition);                              \
 112         if (unlikely(__ret_warn_on))                                    \
 113                 if (!WARN(i915.verbose_state_checks, format))           \
 114                         DRM_ERROR(format);                              \
 115         unlikely(__ret_warn_on);                                        \
 116 })
 117
 118 #define I915_STATE_WARN_ON(x)                                           \
 119         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 120
 121 bool __i915_inject_load_failure(const char *func, int line);
 122 #define i915_inject_load_failure() \
 123         __i915_inject_load_failure(__func__, __LINE__)
 124
 125 typedef struct {
 126         uint32_t val;
 127 } uint_fixed_16_16_t;
 128
 129 #define FP_16_16_MAX ({ \
 130         uint_fixed_16_16_t fp; \
 131         fp.val = UINT_MAX; \
 132         fp; \
 133 })
 134
 135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
 136 {
 137         uint_fixed_16_16_t fp;
 138
 139         WARN_ON(val >> 16);
 140
 141         fp.val = val << 16;
 142         return fp;
 143 }
 144
 145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
 146 {
 147         return DIV_ROUND_UP(fp.val, 1 << 16);
 148 }
 149
 150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
 151 {
 152         return fp.val >> 16;
 153 }
 154
 155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
 156                                                  uint_fixed_16_16_t min2)
 157 {
 158         uint_fixed_16_16_t min;
 159
 160         min.val = min(min1.val, min2.val);
 161         return min;
 162 }
 163
 164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
 165                                                  uint_fixed_16_16_t max2)
 166 {
 167         uint_fixed_16_16_t max;
 168
 169         max.val = max(max1.val, max2.val);
 170         return max;
 171 }
 172
 173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
 174                                                           uint32_t d)
 175 {
 176         uint_fixed_16_16_t fp, res;
 177
 178         fp = u32_to_fixed_16_16(val);
 179         res.val = DIV_ROUND_UP(fp.val, d);
 180         return res;
 181 }
 182
 183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
 184                                                               uint32_t d)
 185 {
 186         uint_fixed_16_16_t res;
 187         uint64_t interm_val;
 188
 189         interm_val = (uint64_t)val << 16;
 190         interm_val = DIV_ROUND_UP_ULL(interm_val, d);
 191         WARN_ON(interm_val >> 32);
 192         res.val = (uint32_t) interm_val;
 193
 194         return res;
 195 }
 196
 197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
 198                                                      uint_fixed_16_16_t mul)
 199 {
 200         uint64_t intermediate_val;
 201         uint_fixed_16_16_t fp;
 202
 203         intermediate_val = (uint64_t) val * mul.val;
 204         WARN_ON(intermediate_val >> 32);
 205         fp.val = (uint32_t) intermediate_val;
 206         return fp;
 207 }
 208
 209 static inline const char *yesno(bool v)
 210 {
 211         return v ? "yes" : "no";
 212 }
 213
 214 static inline const char *onoff(bool v)
 215 {
 216         return v ? "on" : "off";
 217 }
 218
 219 static inline const char *enableddisabled(bool v)
 220 {
 221         return v ? "enabled" : "disabled";
 222 }
 223
 224 enum pipe {
 225         INVALID_PIPE = -1,
 226         PIPE_A = 0,
 227         PIPE_B,
 228         PIPE_C,
 229         _PIPE_EDP,
 230         I915_MAX_PIPES = _PIPE_EDP
 231 };
 232 #define pipe_name(p) ((p) + 'A')
 233
 234 enum transcoder {
 235         TRANSCODER_A = 0,
 236         TRANSCODER_B,
 237         TRANSCODER_C,
 238         TRANSCODER_EDP,
 239         TRANSCODER_DSI_A,
 240         TRANSCODER_DSI_C,
 241         I915_MAX_TRANSCODERS
 242 };
 243
 244 static inline const char *transcoder_name(enum transcoder transcoder)
 245 {
 246         switch (transcoder) {
 247         case TRANSCODER_A:
 248                 return "A";
 249         case TRANSCODER_B:
 250                 return "B";
 251         case TRANSCODER_C:
 252                 return "C";
 253         case TRANSCODER_EDP:
 254                 return "EDP";
 255         case TRANSCODER_DSI_A:
 256                 return "DSI A";
 257         case TRANSCODER_DSI_C:
 258                 return "DSI C";
 259         default:
 260                 return "<invalid>";
 261         }
 262 }
 263
 264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 265 {
 266         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 267 }
 268
 269 /*
 270  * Global legacy plane identifier. Valid only for primary/sprite
 271  * planes on pre-g4x, and only for primary planes on g4x+.
 272  */
 273 enum plane {
 274         PLANE_A,
 275         PLANE_B,
 276         PLANE_C,
 277 };
 278 #define plane_name(p) ((p) + 'A')
 279
 280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 281
 282 /*
 283  * Per-pipe plane identifier.
 284  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 285  * number of planes per CRTC.  Not all platforms really have this many planes,
 286  * which means some arrays of size I915_MAX_PLANES may have unused entries
 287  * between the topmost sprite plane and the cursor plane.
 288  *
 289  * This is expected to be passed to various register macros
 290  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 291  */
 292 enum plane_id {
 293         PLANE_PRIMARY,
 294         PLANE_SPRITE0,
 295         PLANE_SPRITE1,
 296         PLANE_SPRITE2,
 297         PLANE_CURSOR,
 298         I915_MAX_PLANES,
 299 };
 300
 301 #define for_each_plane_id_on_crtc(__crtc, __p) \
 302         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 303                 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
 304
 305 enum port {
 306         PORT_NONE = -1,
 307         PORT_A = 0,
 308         PORT_B,
 309         PORT_C,
 310         PORT_D,
 311         PORT_E,
 312         I915_MAX_PORTS
 313 };
 314 #define port_name(p) ((p) + 'A')
 315
 316 #define I915_NUM_PHYS_VLV 2
 317
 318 enum dpio_channel {
 319         DPIO_CH0,
 320         DPIO_CH1
 321 };
 322
 323 enum dpio_phy {
 324         DPIO_PHY0,
 325         DPIO_PHY1,
 326         DPIO_PHY2,
 327 };
 328
 329 enum intel_display_power_domain {
 330         POWER_DOMAIN_PIPE_A,
 331         POWER_DOMAIN_PIPE_B,
 332         POWER_DOMAIN_PIPE_C,
 333         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 334         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 335         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 336         POWER_DOMAIN_TRANSCODER_A,
 337         POWER_DOMAIN_TRANSCODER_B,
 338         POWER_DOMAIN_TRANSCODER_C,
 339         POWER_DOMAIN_TRANSCODER_EDP,
 340         POWER_DOMAIN_TRANSCODER_DSI_A,
 341         POWER_DOMAIN_TRANSCODER_DSI_C,
 342         POWER_DOMAIN_PORT_DDI_A_LANES,
 343         POWER_DOMAIN_PORT_DDI_B_LANES,
 344         POWER_DOMAIN_PORT_DDI_C_LANES,
 345         POWER_DOMAIN_PORT_DDI_D_LANES,
 346         POWER_DOMAIN_PORT_DDI_E_LANES,
 347         POWER_DOMAIN_PORT_DDI_A_IO,
 348         POWER_DOMAIN_PORT_DDI_B_IO,
 349         POWER_DOMAIN_PORT_DDI_C_IO,
 350         POWER_DOMAIN_PORT_DDI_D_IO,
 351         POWER_DOMAIN_PORT_DDI_E_IO,
 352         POWER_DOMAIN_PORT_DSI,
 353         POWER_DOMAIN_PORT_CRT,
 354         POWER_DOMAIN_PORT_OTHER,
 355         POWER_DOMAIN_VGA,
 356         POWER_DOMAIN_AUDIO,
 357         POWER_DOMAIN_PLLS,
 358         POWER_DOMAIN_AUX_A,
 359         POWER_DOMAIN_AUX_B,
 360         POWER_DOMAIN_AUX_C,
 361         POWER_DOMAIN_AUX_D,
 362         POWER_DOMAIN_GMBUS,
 363         POWER_DOMAIN_MODESET,
 364         POWER_DOMAIN_INIT,
 365
 366         POWER_DOMAIN_NUM,
 367 };
 368
 369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 371                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 372 #define POWER_DOMAIN_TRANSCODER(tran) \
 373         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 374          (tran) + POWER_DOMAIN_TRANSCODER_A)
 375
 376 enum hpd_pin {
 377         HPD_NONE = 0,
 378         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 379         HPD_CRT,
 380         HPD_SDVO_B,
 381         HPD_SDVO_C,
 382         HPD_PORT_A,
 383         HPD_PORT_B,
 384         HPD_PORT_C,
 385         HPD_PORT_D,
 386         HPD_PORT_E,
 387         HPD_NUM_PINS
 388 };
 389
 390 #define for_each_hpd_pin(__pin) \
 391         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 392
 393 #define HPD_STORM_DEFAULT_THRESHOLD 5
 394
 395 struct i915_hotplug {
 396         struct work_struct hotplug_work;
 397
 398         struct {
 399                 unsigned long last_jiffies;
 400                 int count;
 401                 enum {
 402                         HPD_ENABLED = 0,
 403                         HPD_DISABLED = 1,
 404                         HPD_MARK_DISABLED = 2
 405                 } state;
 406         } stats[HPD_NUM_PINS];
 407         u32 event_bits;
 408         struct delayed_work reenable_work;
 409
 410         struct intel_digital_port *irq_port[I915_MAX_PORTS];
 411         u32 long_port_mask;
 412         u32 short_port_mask;
 413         struct work_struct dig_port_work;
 414
 415         struct work_struct poll_init_work;
 416         bool poll_enabled;
 417
 418         unsigned int hpd_storm_threshold;
 419
 420         /*
 421          * if we get a HPD irq from DP and a HPD irq from non-DP
 422          * the non-DP HPD could block the workqueue on a mode config
 423          * mutex getting, that userspace may have taken. However
 424          * userspace is waiting on the DP workqueue to run which is
 425          * blocked behind the non-DP one.
 426          */
 427         struct workqueue_struct *dp_wq;
 428 };
 429
 430 #define I915_GEM_GPU_DOMAINS \
 431         (I915_GEM_DOMAIN_RENDER | \
 432          I915_GEM_DOMAIN_SAMPLER | \
 433          I915_GEM_DOMAIN_COMMAND | \
 434          I915_GEM_DOMAIN_INSTRUCTION | \
 435          I915_GEM_DOMAIN_VERTEX)
 436
 437 #define for_each_pipe(__dev_priv, __p) \
 438         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 440         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 441                 for_each_if ((__mask) & (1 << (__p)))
 442 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 443         for ((__p) = 0;                                                 \
 444              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 445              (__p)++)
 446 #define for_each_sprite(__dev_priv, __p, __s)                           \
 447         for ((__s) = 0;                                                 \
 448              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 449              (__s)++)
 450
 451 #define for_each_port_masked(__port, __ports_mask) \
 452         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 453                 for_each_if ((__ports_mask) & (1 << (__port)))
 454
 455 #define for_each_crtc(dev, crtc) \
 456         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 457
 458 #define for_each_intel_plane(dev, intel_plane) \
 459         list_for_each_entry(intel_plane,                        \
 460                             &(dev)->mode_config.plane_list,     \
 461                             base.head)
 462
 463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 464         list_for_each_entry(intel_plane,                                \
 465                             &(dev)->mode_config.plane_list,             \
 466                             base.head)                                  \
 467                 for_each_if ((plane_mask) &                             \
 468                              (1 << drm_plane_index(&intel_plane->base)))
 469
 470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 471         list_for_each_entry(intel_plane,                                \
 472                             &(dev)->mode_config.plane_list,             \
 473                             base.head)                                  \
 474                 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
 475
 476 #define for_each_intel_crtc(dev, intel_crtc)                            \
 477         list_for_each_entry(intel_crtc,                                 \
 478                             &(dev)->mode_config.crtc_list,              \
 479                             base.head)
 480
 481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 482         list_for_each_entry(intel_crtc,                                 \
 483                             &(dev)->mode_config.crtc_list,              \
 484                             base.head)                                  \
 485                 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
 486
 487 #define for_each_intel_encoder(dev, intel_encoder)              \
 488         list_for_each_entry(intel_encoder,                      \
 489                             &(dev)->mode_config.encoder_list,   \
 490                             base.head)
 491
 492 #define for_each_intel_connector(dev, intel_connector)          \
 493         list_for_each_entry(intel_connector,                    \
 494                             &(dev)->mode_config.connector_list, \
 495                             base.head)
 496
 497 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 498         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 499                 for_each_if ((intel_encoder)->base.crtc == (__crtc))
 500
 501 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 502         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 503                 for_each_if ((intel_connector)->base.encoder == (__encoder))
 504
 505 #define for_each_power_domain(domain, mask)                             \
 506         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 507                 for_each_if (BIT_ULL(domain) & (mask))
 508
 509 #define for_each_power_well(__dev_priv, __power_well)                           \
 510         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 511              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 512                 (__dev_priv)->power_domains.power_well_count;           \
 513              (__power_well)++)
 514
 515 #define for_each_power_well_rev(__dev_priv, __power_well)                       \
 516         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 517                               (__dev_priv)->power_domains.power_well_count - 1; \
 518              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 519              (__power_well)--)
 520
 521 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 522         for_each_power_well(__dev_priv, __power_well)                           \
 523                 for_each_if ((__power_well)->domains & (__domain_mask))
 524
 525 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
 526         for_each_power_well_rev(__dev_priv, __power_well)                       \
 527                 for_each_if ((__power_well)->domains & (__domain_mask))
 528
 529 struct drm_i915_private;
 530 struct i915_mm_struct;
 531 struct i915_mmu_object;
 532
 533 struct drm_i915_file_private {
 534         struct drm_i915_private *dev_priv;
 535         struct drm_file *file;
 536
 537         struct {
 538                 spinlock_t lock;
 539                 struct list_head request_list;
 540 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
 541  * chosen to prevent the CPU getting more than a frame ahead of the GPU
 542  * (when using lax throttling for the frontbuffer). We also use it to
 543  * offer free GPU waitboosts for severely congested workloads.
 544  */
 545 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
 546         } mm;
 547         struct idr context_idr;
 548
 549         struct intel_rps_client {
 550                 struct list_head link;
 551                 unsigned boosts;
 552         } rps;
 553
 554         unsigned int bsd_engine;
 555
 556 /* Client can have a maximum of 3 contexts banned before
 557  * it is denied of creating new contexts. As one context
 558  * ban needs 4 consecutive hangs, and more if there is
 559  * progress in between, this is a last resort stop gap measure
 560  * to limit the badly behaving clients access to gpu.
 561  */
 562 #define I915_MAX_CLIENT_CONTEXT_BANS 3
 563         int context_bans;
 564 };
 565
 566 /* Used by dp and fdi links */
 567 struct intel_link_m_n {
 568         uint32_t        tu;
 569         uint32_t        gmch_m;
 570         uint32_t        gmch_n;
 571         uint32_t        link_m;
 572         uint32_t        link_n;
 573 };
 574
 575 void intel_link_compute_m_n(int bpp, int nlanes,
 576                             int pixel_clock, int link_clock,
 577                             struct intel_link_m_n *m_n);
 578
 579 /* Interface history:
 580  *
 581  * 1.1: Original.
 582  * 1.2: Add Power Management
 583  * 1.3: Add vblank support
 584  * 1.4: Fix cmdbuffer path, add heap destroy
 585  * 1.5: Add vblank pipe configuration
 586  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 587  *      - Support vertical blank on secondary display pipe
 588  */
 589 #define DRIVER_MAJOR            1
 590 #define DRIVER_MINOR            6
 591 #define DRIVER_PATCHLEVEL       0
 592
 593 struct opregion_header;
 594 struct opregion_acpi;
 595 struct opregion_swsci;
 596 struct opregion_asle;
 597
 598 struct intel_opregion {
 599         struct opregion_header *header;
 600         struct opregion_acpi *acpi;
 601         struct opregion_swsci *swsci;
 602         u32 swsci_gbda_sub_functions;
 603         u32 swsci_sbcb_sub_functions;
 604         struct opregion_asle *asle;
 605         void *rvda;
 606         const void *vbt;
 607         u32 vbt_size;
 608         u32 *lid_state;
 609         struct work_struct asle_work;
 610 };
 611 #define OPREGION_SIZE            (8*1024)
 612
 613 struct intel_overlay;
 614 struct intel_overlay_error_state;
 615
 616 struct sdvo_device_mapping {
 617         u8 initialized;
 618         u8 dvo_port;
 619         u8 slave_addr;
 620         u8 dvo_wiring;
 621         u8 i2c_pin;
 622         u8 ddc_pin;
 623 };
 624
 625 struct intel_connector;
 626 struct intel_encoder;
 627 struct intel_atomic_state;
 628 struct intel_crtc_state;
 629 struct intel_initial_plane_config;
 630 struct intel_crtc;
 631 struct intel_limit;
 632 struct dpll;
 633 struct intel_cdclk_state;
 634
 635 struct drm_i915_display_funcs {
 636         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 637                           struct intel_cdclk_state *cdclk_state);
 638         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 639                           const struct intel_cdclk_state *cdclk_state);
 640         int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
 641         int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
 642         int (*compute_intermediate_wm)(struct drm_device *dev,
 643                                        struct intel_crtc *intel_crtc,
 644                                        struct intel_crtc_state *newstate);
 645         void (*initial_watermarks)(struct intel_atomic_state *state,
 646                                    struct intel_crtc_state *cstate);
 647         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 648                                          struct intel_crtc_state *cstate);
 649         void (*optimize_watermarks)(struct intel_atomic_state *state,
 650                                     struct intel_crtc_state *cstate);
 651         int (*compute_global_watermarks)(struct drm_atomic_state *state);
 652         void (*update_wm)(struct intel_crtc *crtc);
 653         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 654         /* Returns the active state of the crtc, and if the crtc is active,
 655          * fills out the pipe-config with the hw state. */
 656         bool (*get_pipe_config)(struct intel_crtc *,
 657                                 struct intel_crtc_state *);
 658         void (*get_initial_plane_config)(struct intel_crtc *,
 659                                          struct intel_initial_plane_config *);
 660         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 661                                   struct intel_crtc_state *crtc_state);
 662         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 663                             struct drm_atomic_state *old_state);
 664         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 665                              struct drm_atomic_state *old_state);
 666         void (*update_crtcs)(struct drm_atomic_state *state,
 667                              unsigned int *crtc_vblank_mask);
 668         void (*audio_codec_enable)(struct drm_connector *connector,
 669                                    struct intel_encoder *encoder,
 670                                    const struct drm_display_mode *adjusted_mode);
 671         void (*audio_codec_disable)(struct intel_encoder *encoder);
 672         void (*fdi_link_train)(struct intel_crtc *crtc,
 673                                const struct intel_crtc_state *crtc_state);
 674         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 675         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 676                           struct drm_framebuffer *fb,
 677                           struct drm_i915_gem_object *obj,
 678                           struct drm_i915_gem_request *req,
 679                           uint32_t flags);
 680         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 681         /* clock updates for mode set */
 682         /* cursor updates */
 683         /* render clock increase/decrease */
 684         /* display clock increase/decrease */
 685         /* pll clock increase/decrease */
 686
 687         void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
 688         void (*load_luts)(struct drm_crtc_state *crtc_state);
 689 };
 690
 691 enum forcewake_domain_id {
 692         FW_DOMAIN_ID_RENDER = 0,
 693         FW_DOMAIN_ID_BLITTER,
 694         FW_DOMAIN_ID_MEDIA,
 695
 696         FW_DOMAIN_ID_COUNT
 697 };
 698
 699 enum forcewake_domains {
 700         FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
 701         FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
 702         FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
 703         FORCEWAKE_ALL = (FORCEWAKE_RENDER |
 704                          FORCEWAKE_BLITTER |
 705                          FORCEWAKE_MEDIA)
 706 };
 707
 708 #define FW_REG_READ  (1)
 709 #define FW_REG_WRITE (2)
 710
 711 enum decoupled_power_domain {
 712         GEN9_DECOUPLED_PD_BLITTER = 0,
 713         GEN9_DECOUPLED_PD_RENDER,
 714         GEN9_DECOUPLED_PD_MEDIA,
 715         GEN9_DECOUPLED_PD_ALL
 716 };
 717
 718 enum decoupled_ops {
 719         GEN9_DECOUPLED_OP_WRITE = 0,
 720         GEN9_DECOUPLED_OP_READ
 721 };
 722
 723 enum forcewake_domains
 724 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 725                                i915_reg_t reg, unsigned int op);
 726
 727 struct intel_uncore_funcs {
 728         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 729                                                         enum forcewake_domains domains);
 730         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 731                                                         enum forcewake_domains domains);
 732
 733         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 734         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 735         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 736         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 737
 738         void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
 739                                 uint8_t val, bool trace);
 740         void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
 741                                 uint16_t val, bool trace);
 742         void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
 743                                 uint32_t val, bool trace);
 744 };
 745
 746 struct intel_forcewake_range {
 747         u32 start;
 748         u32 end;
 749
 750         enum forcewake_domains domains;
 751 };
 752
 753 struct intel_uncore {
 754         spinlock_t lock; /** lock is also taken in irq contexts. */
 755
 756         const struct intel_forcewake_range *fw_domains_table;
 757         unsigned int fw_domains_table_entries;
 758
 759         struct intel_uncore_funcs funcs;
 760
 761         unsigned fifo_count;
 762
 763         enum forcewake_domains fw_domains;
 764         enum forcewake_domains fw_domains_active;
 765
 766         struct intel_uncore_forcewake_domain {
 767                 struct drm_i915_private *i915;
 768                 enum forcewake_domain_id id;
 769                 enum forcewake_domains mask;
 770                 unsigned wake_count;
 771                 struct hrtimer timer;
 772                 i915_reg_t reg_set;
 773                 u32 val_set;
 774                 u32 val_clear;
 775                 i915_reg_t reg_ack;
 776                 i915_reg_t reg_post;
 777                 u32 val_reset;
 778         } fw_domain[FW_DOMAIN_ID_COUNT];
 779
 780         int unclaimed_mmio_check;
 781 };
 782
 783 /* Iterate over initialised fw domains */
 784 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
 785         for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
 786              (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
 787              (domain__)++) \
 788                 for_each_if ((mask__) & (domain__)->mask)
 789
 790 #define for_each_fw_domain(domain__, dev_priv__) \
 791         for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
 792
 793 #define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
 794 #define CSR_VERSION_MAJOR(version)      ((version) >> 16)
 795 #define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
 796
 797 struct intel_csr {
 798         struct work_struct work;
 799         const char *fw_path;
 800         uint32_t *dmc_payload;
 801         uint32_t dmc_fw_size;
 802         uint32_t version;
 803         uint32_t mmio_count;
 804         i915_reg_t mmioaddr[8];
 805         uint32_t mmiodata[8];
 806         uint32_t dc_state;
 807         uint32_t allowed_dc_mask;
 808 };
 809
 810 #define DEV_INFO_FOR_EACH_FLAG(func) \
 811         func(is_mobile); \
 812         func(is_lp); \
 813         func(is_alpha_support); \
 814         /* Keep has_* in alphabetical order */ \
 815         func(has_64bit_reloc); \
 816         func(has_aliasing_ppgtt); \
 817         func(has_csr); \
 818         func(has_ddi); \
 819         func(has_decoupled_mmio); \
 820         func(has_dp_mst); \
 821         func(has_fbc); \
 822         func(has_fpga_dbg); \
 823         func(has_full_ppgtt); \
 824         func(has_full_48bit_ppgtt); \
 825         func(has_gmbus_irq); \
 826         func(has_gmch_display); \
 827         func(has_guc); \
 828         func(has_hotplug); \
 829         func(has_hw_contexts); \
 830         func(has_l3_dpf); \
 831         func(has_llc); \
 832         func(has_logical_ring_contexts); \
 833         func(has_overlay); \
 834         func(has_pipe_cxsr); \
 835         func(has_pooled_eu); \
 836         func(has_psr); \
 837         func(has_rc6); \
 838         func(has_rc6p); \
 839         func(has_resource_streamer); \
 840         func(has_runtime_pm); \
 841         func(has_snoop); \
 842         func(cursor_needs_physical); \
 843         func(hws_needs_physical); \
 844         func(overlay_needs_physical); \
 845         func(supports_tv);
 846
 847 struct sseu_dev_info {
 848         u8 slice_mask;
 849         u8 subslice_mask;
 850         u8 eu_total;
 851         u8 eu_per_subslice;
 852         u8 min_eu_in_pool;
 853         /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 854         u8 subslice_7eu[3];
 855         u8 has_slice_pg:1;
 856         u8 has_subslice_pg:1;
 857         u8 has_eu_pg:1;
 858 };
 859
 860 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 861 {
 862         return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
 863 }
 864
 865 /* Keep in gen based order, and chronological order within a gen */
 866 enum intel_platform {
 867         INTEL_PLATFORM_UNINITIALIZED = 0,
 868         INTEL_I830,
 869         INTEL_I845G,
 870         INTEL_I85X,
 871         INTEL_I865G,
 872         INTEL_I915G,
 873         INTEL_I915GM,
 874         INTEL_I945G,
 875         INTEL_I945GM,
 876         INTEL_G33,
 877         INTEL_PINEVIEW,
 878         INTEL_I965G,
 879         INTEL_I965GM,
 880         INTEL_G45,
 881         INTEL_GM45,
 882         INTEL_IRONLAKE,
 883         INTEL_SANDYBRIDGE,
 884         INTEL_IVYBRIDGE,
 885         INTEL_VALLEYVIEW,
 886         INTEL_HASWELL,
 887         INTEL_BROADWELL,
 888         INTEL_CHERRYVIEW,
 889         INTEL_SKYLAKE,
 890         INTEL_BROXTON,
 891         INTEL_KABYLAKE,
 892         INTEL_GEMINILAKE,
 893         INTEL_MAX_PLATFORMS
 894 };
 895
 896 struct intel_device_info {
 897         u32 display_mmio_offset;
 898         u16 device_id;
 899         u8 num_pipes;
 900         u8 num_sprites[I915_MAX_PIPES];
 901         u8 num_scalers[I915_MAX_PIPES];
 902         u8 gen;
 903         u16 gen_mask;
 904         enum intel_platform platform;
 905         u8 ring_mask; /* Rings supported by the HW */
 906         u8 num_rings;
 907 #define DEFINE_FLAG(name) u8 name:1
 908         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 909 #undef DEFINE_FLAG
 910         u16 ddb_size; /* in blocks */
 911         /* Register offsets for the various display pipes and transcoders */
 912         int pipe_offsets[I915_MAX_TRANSCODERS];
 913         int trans_offsets[I915_MAX_TRANSCODERS];
 914         int palette_offsets[I915_MAX_PIPES];
 915         int cursor_offsets[I915_MAX_PIPES];
 916
 917         /* Slice/subslice/EU info */
 918         struct sseu_dev_info sseu;
 919
 920         struct color_luts {
 921                 u16 degamma_lut_size;
 922                 u16 gamma_lut_size;
 923         } color;
 924 };
 925
 926 struct intel_display_error_state;
 927
 928 struct i915_gpu_state {
 929         struct kref ref;
 930         struct timeval time;
 931         struct timeval boottime;
 932         struct timeval uptime;
 933
 934         struct drm_i915_private *i915;
 935
 936         char error_msg[128];
 937         bool simulated;
 938         bool awake;
 939         bool wakelock;
 940         bool suspended;
 941         int iommu;
 942         u32 reset_count;
 943         u32 suspend_count;
 944         struct intel_device_info device_info;
 945         struct i915_params params;
 946
 947         /* Generic register state */
 948         u32 eir;
 949         u32 pgtbl_er;
 950         u32 ier;
 951         u32 gtier[4], ngtier;
 952         u32 ccid;
 953         u32 derrmr;
 954         u32 forcewake;
 955         u32 error; /* gen6+ */
 956         u32 err_int; /* gen7 */
 957         u32 fault_data0; /* gen8, gen9 */
 958         u32 fault_data1; /* gen8, gen9 */
 959         u32 done_reg;
 960         u32 gac_eco;
 961         u32 gam_ecochk;
 962         u32 gab_ctl;
 963         u32 gfx_mode;
 964
 965         u32 nfence;
 966         u64 fence[I915_MAX_NUM_FENCES];
 967         struct intel_overlay_error_state *overlay;
 968         struct intel_display_error_state *display;
 969         struct drm_i915_error_object *semaphore;
 970         struct drm_i915_error_object *guc_log;
 971
 972         struct drm_i915_error_engine {
 973                 int engine_id;
 974                 /* Software tracked state */
 975                 bool waiting;
 976                 int num_waiters;
 977                 unsigned long hangcheck_timestamp;
 978                 bool hangcheck_stalled;
 979                 enum intel_engine_hangcheck_action hangcheck_action;
 980                 struct i915_address_space *vm;
 981                 int num_requests;
 982
 983                 /* position of active request inside the ring */
 984                 u32 rq_head, rq_post, rq_tail;
 985
 986                 /* our own tracking of ring head and tail */
 987                 u32 cpu_ring_head;
 988                 u32 cpu_ring_tail;
 989
 990                 u32 last_seqno;
 991
 992                 /* Register state */
 993                 u32 start;
 994                 u32 tail;
 995                 u32 head;
 996                 u32 ctl;
 997                 u32 mode;
 998                 u32 hws;
 999                 u32 ipeir;
1000                 u32 ipehr;
1001                 u32 bbstate;
1002                 u32 instpm;
1003                 u32 instps;
1004                 u32 seqno;
1005                 u64 bbaddr;
1006                 u64 acthd;
1007                 u32 fault_reg;
1008                 u64 faddr;
1009                 u32 rc_psmi; /* sleep state */
1010                 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1011                 struct intel_instdone instdone;
1012
1013                 struct drm_i915_error_context {
1014                         char comm[TASK_COMM_LEN];
1015                         pid_t pid;
1016                         u32 handle;
1017                         u32 hw_id;
1018                         int ban_score;
1019                         int active;
1020                         int guilty;
1021                 } context;
1022
1023                 struct drm_i915_error_object {
1024                         u64 gtt_offset;
1025                         u64 gtt_size;
1026                         int page_count;
1027                         int unused;
1028                         u32 *pages[0];
1029                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1030
1031                 struct drm_i915_error_object *wa_ctx;
1032
1033                 struct drm_i915_error_request {
1034                         long jiffies;
1035                         pid_t pid;
1036                         u32 context;
1037                         int ban_score;
1038                         u32 seqno;
1039                         u32 head;
1040                         u32 tail;
1041                 } *requests, execlist[2];
1042
1043                 struct drm_i915_error_waiter {
1044                         char comm[TASK_COMM_LEN];
1045                         pid_t pid;
1046                         u32 seqno;
1047                 } *waiters;
1048
1049                 struct {
1050                         u32 gfx_mode;
1051                         union {
1052                                 u64 pdp[4];
1053                                 u32 pp_dir_base;
1054                         };
1055                 } vm_info;
1056         } engine[I915_NUM_ENGINES];
1057
1058         struct drm_i915_error_buffer {
1059                 u32 size;
1060                 u32 name;
1061                 u32 rseqno[I915_NUM_ENGINES], wseqno;
1062                 u64 gtt_offset;
1063                 u32 read_domains;
1064                 u32 write_domain;
1065                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1066                 u32 tiling:2;
1067                 u32 dirty:1;
1068                 u32 purgeable:1;
1069                 u32 userptr:1;
1070                 s32 engine:4;
1071                 u32 cache_level:3;
1072         } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1073         u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1074         struct i915_address_space *active_vm[I915_NUM_ENGINES];
1075 };
1076
1077 enum i915_cache_level {
1078         I915_CACHE_NONE = 0,
1079         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1080         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1081                               caches, eg sampler/render caches, and the
1082                               large Last-Level-Cache. LLC is coherent with
1083                               the CPU, but L3 is only visible to the GPU. */
1084         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1085 };
1086
1087 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1088
1089 enum fb_op_origin {
1090         ORIGIN_GTT,
1091         ORIGIN_CPU,
1092         ORIGIN_CS,
1093         ORIGIN_FLIP,
1094         ORIGIN_DIRTYFB,
1095 };
1096
1097 struct intel_fbc {
1098         /* This is always the inner lock when overlapping with struct_mutex and
1099          * it's the outer lock when overlapping with stolen_lock. */
1100         struct mutex lock;
1101         unsigned threshold;
1102         unsigned int possible_framebuffer_bits;
1103         unsigned int busy_bits;
1104         unsigned int visible_pipes_mask;
1105         struct intel_crtc *crtc;
1106
1107         struct drm_mm_node compressed_fb;
1108         struct drm_mm_node *compressed_llb;
1109
1110         bool false_color;
1111
1112         bool enabled;
1113         bool active;
1114
1115         bool underrun_detected;
1116         struct work_struct underrun_work;
1117
1118         struct intel_fbc_state_cache {
1119                 struct i915_vma *vma;
1120
1121                 struct {
1122                         unsigned int mode_flags;
1123                         uint32_t hsw_bdw_pixel_rate;
1124                 } crtc;
1125
1126                 struct {
1127                         unsigned int rotation;
1128                         int src_w;
1129                         int src_h;
1130                         bool visible;
1131                 } plane;
1132
1133                 struct {
1134                         const struct drm_format_info *format;
1135                         unsigned int stride;
1136                 } fb;
1137         } state_cache;
1138
1139         struct intel_fbc_reg_params {
1140                 struct i915_vma *vma;
1141
1142                 struct {
1143                         enum pipe pipe;
1144                         enum plane plane;
1145                         unsigned int fence_y_offset;
1146                 } crtc;
1147
1148                 struct {
1149                         const struct drm_format_info *format;
1150                         unsigned int stride;
1151                 } fb;
1152
1153                 int cfb_size;
1154         } params;
1155
1156         struct intel_fbc_work {
1157                 bool scheduled;
1158                 u32 scheduled_vblank;
1159                 struct work_struct work;
1160         } work;
1161
1162         const char *no_fbc_reason;
1163 };
1164
1165 /*
1166  * HIGH_RR is the highest eDP panel refresh rate read from EDID
1167  * LOW_RR is the lowest eDP panel refresh rate found from EDID
1168  * parsing for same resolution.
1169  */
1170 enum drrs_refresh_rate_type {
1171         DRRS_HIGH_RR,
1172         DRRS_LOW_RR,
1173         DRRS_MAX_RR, /* RR count */
1174 };
1175
1176 enum drrs_support_type {
1177         DRRS_NOT_SUPPORTED = 0,
1178         STATIC_DRRS_SUPPORT = 1,
1179         SEAMLESS_DRRS_SUPPORT = 2
1180 };
1181
1182 struct intel_dp;
1183 struct i915_drrs {
1184         struct mutex mutex;
1185         struct delayed_work work;
1186         struct intel_dp *dp;
1187         unsigned busy_frontbuffer_bits;
1188         enum drrs_refresh_rate_type refresh_rate_type;
1189         enum drrs_support_type type;
1190 };
1191
1192 struct i915_psr {
1193         struct mutex lock;
1194         bool sink_support;
1195         bool source_ok;
1196         struct intel_dp *enabled;
1197         bool active;
1198         struct delayed_work work;
1199         unsigned busy_frontbuffer_bits;
1200         bool psr2_support;
1201         bool aux_frame_sync;
1202         bool link_standby;
1203         bool y_cord_support;
1204         bool colorimetry_support;
1205         bool alpm;
1206 };
1207
1208 enum intel_pch {
1209         PCH_NONE = 0,   /* No PCH present */
1210         PCH_IBX,        /* Ibexpeak PCH */
1211         PCH_CPT,        /* Cougarpoint PCH */
1212         PCH_LPT,        /* Lynxpoint PCH */
1213         PCH_SPT,        /* Sunrisepoint PCH */
1214         PCH_KBP,        /* Kabypoint PCH */
1215         PCH_NOP,
1216 };
1217
1218 enum intel_sbi_destination {
1219         SBI_ICLK,
1220         SBI_MPHY,
1221 };
1222
1223 #define QUIRK_PIPEA_FORCE (1<<0)
1224 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1225 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1226 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1227 #define QUIRK_PIPEB_FORCE (1<<4)
1228 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1229
1230 struct intel_fbdev;
1231 struct intel_fbc_work;
1232
1233 struct intel_gmbus {
1234         struct i2c_adapter adapter;
1235 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1236         u32 force_bit;
1237         u32 reg0;
1238         i915_reg_t gpio_reg;
1239         struct i2c_algo_bit_data bit_algo;
1240         struct drm_i915_private *dev_priv;
1241 };
1242
1243 struct i915_suspend_saved_registers {
1244         u32 saveDSPARB;
1245         u32 saveFBC_CONTROL;
1246         u32 saveCACHE_MODE_0;
1247         u32 saveMI_ARB_STATE;
1248         u32 saveSWF0[16];
1249         u32 saveSWF1[16];
1250         u32 saveSWF3[3];
1251         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1252         u32 savePCH_PORT_HOTPLUG;
1253         u16 saveGCDGMBUS;
1254 };
1255
1256 struct vlv_s0ix_state {
1257         /* GAM */
1258         u32 wr_watermark;
1259         u32 gfx_prio_ctrl;
1260         u32 arb_mode;
1261         u32 gfx_pend_tlb0;
1262         u32 gfx_pend_tlb1;
1263         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1264         u32 media_max_req_count;
1265         u32 gfx_max_req_count;
1266         u32 render_hwsp;
1267         u32 ecochk;
1268         u32 bsd_hwsp;
1269         u32 blt_hwsp;
1270         u32 tlb_rd_addr;
1271
1272         /* MBC */
1273         u32 g3dctl;
1274         u32 gsckgctl;
1275         u32 mbctl;
1276
1277         /* GCP */
1278         u32 ucgctl1;
1279         u32 ucgctl3;
1280         u32 rcgctl1;
1281         u32 rcgctl2;
1282         u32 rstctl;
1283         u32 misccpctl;
1284
1285         /* GPM */
1286         u32 gfxpause;
1287         u32 rpdeuhwtc;
1288         u32 rpdeuc;
1289         u32 ecobus;
1290         u32 pwrdwnupctl;
1291         u32 rp_down_timeout;
1292         u32 rp_deucsw;
1293         u32 rcubmabdtmr;
1294         u32 rcedata;
1295         u32 spare2gh;
1296
1297         /* Display 1 CZ domain */
1298         u32 gt_imr;
1299         u32 gt_ier;
1300         u32 pm_imr;
1301         u32 pm_ier;
1302         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1303
1304         /* GT SA CZ domain */
1305         u32 tilectl;
1306         u32 gt_fifoctl;
1307         u32 gtlc_wake_ctrl;
1308         u32 gtlc_survive;
1309         u32 pmwgicz;
1310
1311         /* Display 2 CZ domain */
1312         u32 gu_ctl0;
1313         u32 gu_ctl1;
1314         u32 pcbr;
1315         u32 clock_gate_dis2;
1316 };
1317
1318 struct intel_rps_ei {
1319         u32 cz_clock;
1320         u32 render_c0;
1321         u32 media_c0;
1322 };
1323
1324 struct intel_gen6_power_mgmt {
1325         /*
1326          * work, interrupts_enabled and pm_iir are protected by
1327          * dev_priv->irq_lock
1328          */
1329         struct work_struct work;
1330         bool interrupts_enabled;
1331         u32 pm_iir;
1332
1333         /* PM interrupt bits that should never be masked */
1334         u32 pm_intr_keep;
1335
1336         /* Frequencies are stored in potentially platform dependent multiples.
1337          * In other words, *_freq needs to be multiplied by X to be interesting.
1338          * Soft limits are those which are used for the dynamic reclocking done
1339          * by the driver (raise frequencies under heavy loads, and lower for
1340          * lighter loads). Hard limits are those imposed by the hardware.
1341          *
1342          * A distinction is made for overclocking, which is never enabled by
1343          * default, and is considered to be above the hard limit if it's
1344          * possible at all.
1345          */
1346         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1347         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1348         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1349         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1350         u8 min_freq;            /* AKA RPn. Minimum frequency */
1351         u8 boost_freq;          /* Frequency to request when wait boosting */
1352         u8 idle_freq;           /* Frequency to request when we are idle */
1353         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1354         u8 rp1_freq;            /* "less than" RP0 power/freqency */
1355         u8 rp0_freq;            /* Non-overclocked max frequency. */
1356         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
1357
1358         u8 up_threshold; /* Current %busy required to uplock */
1359         u8 down_threshold; /* Current %busy required to downclock */
1360
1361         int last_adj;
1362         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1363
1364         spinlock_t client_lock;
1365         struct list_head clients;
1366         bool client_boost;
1367
1368         bool enabled;
1369         struct delayed_work autoenable_work;
1370         unsigned boosts;
1371
1372         /* manual wa residency calculations */
1373         struct intel_rps_ei up_ei, down_ei;
1374
1375         /*
1376          * Protects RPS/RC6 register access and PCU communication.
1377          * Must be taken after struct_mutex if nested. Note that
1378          * this lock may be held for long periods of time when
1379          * talking to hw - so only take it when talking to hw!
1380          */
1381         struct mutex hw_lock;
1382 };
1383
1384 /* defined intel_pm.c */
1385 extern spinlock_t mchdev_lock;
1386
1387 struct intel_ilk_power_mgmt {
1388         u8 cur_delay;
1389         u8 min_delay;
1390         u8 max_delay;
1391         u8 fmax;
1392         u8 fstart;
1393
1394         u64 last_count1;
1395         unsigned long last_time1;
1396         unsigned long chipset_power;
1397         u64 last_count2;
1398         u64 last_time2;
1399         unsigned long gfx_power;
1400         u8 corr;
1401
1402         int c_m;
1403         int r_t;
1404 };
1405
1406 struct drm_i915_private;
1407 struct i915_power_well;
1408
1409 struct i915_power_well_ops {
1410         /*
1411          * Synchronize the well's hw state to match the current sw state, for
1412          * example enable/disable it based on the current refcount. Called
1413          * during driver init and resume time, possibly after first calling
1414          * the enable/disable handlers.
1415          */
1416         void (*sync_hw)(struct drm_i915_private *dev_priv,
1417                         struct i915_power_well *power_well);
1418         /*
1419          * Enable the well and resources that depend on it (for example
1420          * interrupts located on the well). Called after the 0->1 refcount
1421          * transition.
1422          */
1423         void (*enable)(struct drm_i915_private *dev_priv,
1424                        struct i915_power_well *power_well);
1425         /*
1426          * Disable the well and resources that depend on it. Called after
1427          * the 1->0 refcount transition.
1428          */
1429         void (*disable)(struct drm_i915_private *dev_priv,
1430                         struct i915_power_well *power_well);
1431         /* Returns the hw enabled state. */
1432         bool (*is_enabled)(struct drm_i915_private *dev_priv,
1433                            struct i915_power_well *power_well);
1434 };
1435
1436 /* Power well structure for haswell */
1437 struct i915_power_well {
1438         const char *name;
1439         bool always_on;
1440         /* power well enable/disable usage count */
1441         int count;
1442         /* cached hw enabled state */
1443         bool hw_enabled;
1444         u64 domains;
1445         /* unique identifier for this power well */
1446         unsigned long id;
1447         /*
1448          * Arbitraty data associated with this power well. Platform and power
1449          * well specific.
1450          */
1451         unsigned long data;
1452         const struct i915_power_well_ops *ops;
1453 };
1454
1455 struct i915_power_domains {
1456         /*
1457          * Power wells needed for initialization at driver init and suspend
1458          * time are on. They are kept on until after the first modeset.
1459          */
1460         bool init_power_on;
1461         bool initializing;
1462         int power_well_count;
1463
1464         struct mutex lock;
1465         int domain_use_count[POWER_DOMAIN_NUM];
1466         struct i915_power_well *power_wells;
1467 };
1468
1469 #define MAX_L3_SLICES 2
1470 struct intel_l3_parity {
1471         u32 *remap_info[MAX_L3_SLICES];
1472         struct work_struct error_work;
1473         int which_slice;
1474 };
1475
1476 struct i915_gem_mm {
1477         /** Memory allocator for GTT stolen memory */
1478         struct drm_mm stolen;
1479         /** Protects the usage of the GTT stolen memory allocator. This is
1480          * always the inner lock when overlapping with struct_mutex. */
1481         struct mutex stolen_lock;
1482
1483         /** List of all objects in gtt_space. Used to restore gtt
1484          * mappings on resume */
1485         struct list_head bound_list;
1486         /**
1487          * List of objects which are not bound to the GTT (thus
1488          * are idle and not used by the GPU). These objects may or may
1489          * not actually have any pages attached.
1490          */
1491         struct list_head unbound_list;
1492
1493         /** List of all objects in gtt_space, currently mmaped by userspace.
1494          * All objects within this list must also be on bound_list.
1495          */
1496         struct list_head userfault_list;
1497
1498         /**
1499          * List of objects which are pending destruction.
1500          */
1501         struct llist_head free_list;
1502         struct work_struct free_work;
1503
1504         /** Usable portion of the GTT for GEM */
1505         dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1506
1507         /** PPGTT used for aliasing the PPGTT with the GTT */
1508         struct i915_hw_ppgtt *aliasing_ppgtt;
1509
1510         struct notifier_block oom_notifier;
1511         struct notifier_block vmap_notifier;
1512         struct shrinker shrinker;
1513
1514         /** LRU list of objects with fence regs on them. */
1515         struct list_head fence_list;
1516
1517         /**
1518          * Are we in a non-interruptible section of code like
1519          * modesetting?
1520          */
1521         bool interruptible;
1522
1523         /* the indicator for dispatch video commands on two BSD rings */
1524         atomic_t bsd_engine_dispatch_index;
1525
1526         /** Bit 6 swizzling required for X tiling */
1527         uint32_t bit_6_swizzle_x;
1528         /** Bit 6 swizzling required for Y tiling */
1529         uint32_t bit_6_swizzle_y;
1530
1531         /* accounting, useful for userland debugging */
1532         spinlock_t object_stat_lock;
1533         u64 object_memory;
1534         u32 object_count;
1535 };
1536
1537 struct drm_i915_error_state_buf {
1538         struct drm_i915_private *i915;
1539         unsigned bytes;
1540         unsigned size;
1541         int err;
1542         u8 *buf;
1543         loff_t start;
1544         loff_t pos;
1545 };
1546
1547 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1548 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1549
1550 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
1551 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
1552
1553 struct i915_gpu_error {
1554         /* For hangcheck timer */
1555 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1556 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1557
1558         struct delayed_work hangcheck_work;
1559
1560         /* For reset and error_state handling. */
1561         spinlock_t lock;
1562         /* Protected by the above dev->gpu_error.lock. */
1563         struct i915_gpu_state *first_error;
1564
1565         unsigned long missed_irq_rings;
1566
1567         /**
1568          * State variable controlling the reset flow and count
1569          *
1570          * This is a counter which gets incremented when reset is triggered,
1571          *
1572          * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1573          * meaning that any waiters holding onto the struct_mutex should
1574          * relinquish the lock immediately in order for the reset to start.
1575          *
1576          * If reset is not completed succesfully, the I915_WEDGE bit is
1577          * set meaning that hardware is terminally sour and there is no
1578          * recovery. All waiters on the reset_queue will be woken when
1579          * that happens.
1580          *
1581          * This counter is used by the wait_seqno code to notice that reset
1582          * event happened and it needs to restart the entire ioctl (since most
1583          * likely the seqno it waited for won't ever signal anytime soon).
1584          *
1585          * This is important for lock-free wait paths, where no contended lock
1586          * naturally enforces the correct ordering between the bail-out of the
1587          * waiter and the gpu reset work code.
1588          */
1589         unsigned long reset_count;
1590
1591         unsigned long flags;
1592 #define I915_RESET_IN_PROGRESS  0
1593 #define I915_WEDGED             (BITS_PER_LONG - 1)
1594
1595         /**
1596          * Waitqueue to signal when a hang is detected. Used to for waiters
1597          * to release the struct_mutex for the reset to procede.
1598          */
1599         wait_queue_head_t wait_queue;
1600
1601         /**
1602          * Waitqueue to signal when the reset has completed. Used by clients
1603          * that wait for dev_priv->mm.wedged to settle.
1604          */
1605         wait_queue_head_t reset_queue;
1606
1607         /* For missed irq/seqno simulation. */
1608         unsigned long test_irq_rings;
1609 };
1610
1611 enum modeset_restore {
1612         MODESET_ON_LID_OPEN,
1613         MODESET_DONE,
1614         MODESET_SUSPENDED,
1615 };
1616
1617 #define DP_AUX_A 0x40
1618 #define DP_AUX_B 0x10
1619 #define DP_AUX_C 0x20
1620 #define DP_AUX_D 0x30
1621
1622 #define DDC_PIN_B  0x05
1623 #define DDC_PIN_C  0x04
1624 #define DDC_PIN_D  0x06
1625
1626 struct ddi_vbt_port_info {
1627         /*
1628          * This is an index in the HDMI/DVI DDI buffer translation table.
1629          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1630          * populate this field.
1631          */
1632 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1633         uint8_t hdmi_level_shift;
1634
1635         uint8_t supports_dvi:1;
1636         uint8_t supports_hdmi:1;
1637         uint8_t supports_dp:1;
1638         uint8_t supports_edp:1;
1639
1640         uint8_t alternate_aux_channel;
1641         uint8_t alternate_ddc_pin;
1642
1643         uint8_t dp_boost_level;
1644         uint8_t hdmi_boost_level;
1645 };
1646
1647 enum psr_lines_to_wait {
1648         PSR_0_LINES_TO_WAIT = 0,
1649         PSR_1_LINE_TO_WAIT,
1650         PSR_4_LINES_TO_WAIT,
1651         PSR_8_LINES_TO_WAIT
1652 };
1653
1654 struct intel_vbt_data {
1655         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1656         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1657
1658         /* Feature bits */
1659         unsigned int int_tv_support:1;
1660         unsigned int lvds_dither:1;
1661         unsigned int lvds_vbt:1;
1662         unsigned int int_crt_support:1;
1663         unsigned int lvds_use_ssc:1;
1664         unsigned int display_clock_mode:1;
1665         unsigned int fdi_rx_polarity_inverted:1;
1666         unsigned int panel_type:4;
1667         int lvds_ssc_freq;
1668         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1669
1670         enum drrs_support_type drrs_type;
1671
1672         struct {
1673                 int rate;
1674                 int lanes;
1675                 int preemphasis;
1676                 int vswing;
1677                 bool low_vswing;
1678                 bool initialized;
1679                 bool support;
1680                 int bpp;
1681                 struct edp_power_seq pps;
1682         } edp;
1683
1684         struct {
1685                 bool full_link;
1686                 bool require_aux_wakeup;
1687                 int idle_frames;
1688                 enum psr_lines_to_wait lines_to_wait;
1689                 int tp1_wakeup_time;
1690                 int tp2_tp3_wakeup_time;
1691         } psr;
1692
1693         struct {
1694                 u16 pwm_freq_hz;
1695                 bool present;
1696                 bool active_low_pwm;
1697                 u8 min_brightness;      /* min_brightness/255 of max */
1698                 u8 controller;          /* brightness controller number */
1699                 enum intel_backlight_type type;
1700         } backlight;
1701
1702         /* MIPI DSI */
1703         struct {
1704                 u16 panel_id;
1705                 struct mipi_config *config;
1706                 struct mipi_pps_data *pps;
1707                 u8 seq_version;
1708                 u32 size;
1709                 u8 *data;
1710                 const u8 *sequence[MIPI_SEQ_MAX];
1711         } dsi;
1712
1713         int crt_ddc_pin;
1714
1715         int child_dev_num;
1716         union child_device_config *child_dev;
1717
1718         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1719         struct sdvo_device_mapping sdvo_mappings[2];
1720 };
1721
1722 enum intel_ddb_partitioning {
1723         INTEL_DDB_PART_1_2,
1724         INTEL_DDB_PART_5_6, /* IVB+ */
1725 };
1726
1727 struct intel_wm_level {
1728         bool enable;
1729         uint32_t pri_val;
1730         uint32_t spr_val;
1731         uint32_t cur_val;
1732         uint32_t fbc_val;
1733 };
1734
1735 struct ilk_wm_values {
1736         uint32_t wm_pipe[3];
1737         uint32_t wm_lp[3];
1738         uint32_t wm_lp_spr[3];
1739         uint32_t wm_linetime[3];
1740         bool enable_fbc_wm;
1741         enum intel_ddb_partitioning partitioning;
1742 };
1743
1744 struct vlv_pipe_wm {
1745         uint16_t plane[I915_MAX_PLANES];
1746 };
1747
1748 struct vlv_sr_wm {
1749         uint16_t plane;
1750         uint16_t cursor;
1751 };
1752
1753 struct vlv_wm_ddl_values {
1754         uint8_t plane[I915_MAX_PLANES];
1755 };
1756
1757 struct vlv_wm_values {
1758         struct vlv_pipe_wm pipe[3];
1759         struct vlv_sr_wm sr;
1760         struct vlv_wm_ddl_values ddl[3];
1761         uint8_t level;
1762         bool cxsr;
1763 };
1764
1765 struct skl_ddb_entry {
1766         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1767 };
1768
1769 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1770 {
1771         return entry->end - entry->start;
1772 }
1773
1774 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1775                                        const struct skl_ddb_entry *e2)
1776 {
1777         if (e1->start == e2->start && e1->end == e2->end)
1778                 return true;
1779
1780         return false;
1781 }
1782
1783 struct skl_ddb_allocation {
1784         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1785         struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1786 };
1787
1788 struct skl_wm_values {
1789         unsigned dirty_pipes;
1790         struct skl_ddb_allocation ddb;
1791 };
1792
1793 struct skl_wm_level {
1794         bool plane_en;
1795         uint16_t plane_res_b;
1796         uint8_t plane_res_l;
1797 };
1798
1799 /*
1800  * This struct helps tracking the state needed for runtime PM, which puts the
1801  * device in PCI D3 state. Notice that when this happens, nothing on the
1802  * graphics device works, even register access, so we don't get interrupts nor
1803  * anything else.
1804  *
1805  * Every piece of our code that needs to actually touch the hardware needs to
1806  * either call intel_runtime_pm_get or call intel_display_power_get with the
1807  * appropriate power domain.
1808  *
1809  * Our driver uses the autosuspend delay feature, which means we'll only really
1810  * suspend if we stay with zero refcount for a certain amount of time. The
1811  * default value is currently very conservative (see intel_runtime_pm_enable), but
1812  * it can be changed with the standard runtime PM files from sysfs.
1813  *
1814  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1815  * goes back to false exactly before we reenable the IRQs. We use this variable
1816  * to check if someone is trying to enable/disable IRQs while they're supposed
1817  * to be disabled. This shouldn't happen and we'll print some error messages in
1818  * case it happens.
1819  *
1820  * For more, read the Documentation/power/runtime_pm.txt.
1821  */
1822 struct i915_runtime_pm {
1823         atomic_t wakeref_count;
1824         bool suspended;
1825         bool irqs_enabled;
1826 };
1827
1828 enum intel_pipe_crc_source {
1829         INTEL_PIPE_CRC_SOURCE_NONE,
1830         INTEL_PIPE_CRC_SOURCE_PLANE1,
1831         INTEL_PIPE_CRC_SOURCE_PLANE2,
1832         INTEL_PIPE_CRC_SOURCE_PF,
1833         INTEL_PIPE_CRC_SOURCE_PIPE,
1834         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1835         INTEL_PIPE_CRC_SOURCE_TV,
1836         INTEL_PIPE_CRC_SOURCE_DP_B,
1837         INTEL_PIPE_CRC_SOURCE_DP_C,
1838         INTEL_PIPE_CRC_SOURCE_DP_D,
1839         INTEL_PIPE_CRC_SOURCE_AUTO,
1840         INTEL_PIPE_CRC_SOURCE_MAX,
1841 };
1842
1843 struct intel_pipe_crc_entry {
1844         uint32_t frame;
1845         uint32_t crc[5];
1846 };
1847
1848 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1849 struct intel_pipe_crc {
1850         spinlock_t lock;
1851         bool opened;            /* exclusive access to the result file */
1852         struct intel_pipe_crc_entry *entries;
1853         enum intel_pipe_crc_source source;
1854         int head, tail;
1855         wait_queue_head_t wq;
1856         int skipped;
1857 };
1858
1859 struct i915_frontbuffer_tracking {
1860         spinlock_t lock;
1861
1862         /*
1863          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1864          * scheduled flips.
1865          */
1866         unsigned busy_bits;
1867         unsigned flip_bits;
1868 };
1869
1870 struct i915_wa_reg {
1871         i915_reg_t addr;
1872         u32 value;
1873         /* bitmask representing WA bits */
1874         u32 mask;
1875 };
1876
1877 /*
1878  * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1879  * allowing it for RCS as we don't foresee any requirement of having
1880  * a whitelist for other engines. When it is really required for
1881  * other engines then the limit need to be increased.
1882  */
1883 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1884
1885 struct i915_workarounds {
1886         struct i915_wa_reg reg[I915_MAX_WA_REGS];
1887         u32 count;
1888         u32 hw_whitelist_count[I915_NUM_ENGINES];
1889 };
1890
1891 struct i915_virtual_gpu {
1892         bool active;
1893 };
1894
1895 /* used in computing the new watermarks state */
1896 struct intel_wm_config {
1897         unsigned int num_pipes_active;
1898         bool sprites_enabled;
1899         bool sprites_scaled;
1900 };
1901
1902 struct i915_oa_format {
1903         u32 format;
1904         int size;
1905 };
1906
1907 struct i915_oa_reg {
1908         i915_reg_t addr;
1909         u32 value;
1910 };
1911
1912 struct i915_perf_stream;
1913
1914 /**
1915  * struct i915_perf_stream_ops - the OPs to support a specific stream type
1916  */
1917 struct i915_perf_stream_ops {
1918         /**
1919          * @enable: Enables the collection of HW samples, either in response to
1920          * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1921          * without `I915_PERF_FLAG_DISABLED`.
1922          */
1923         void (*enable)(struct i915_perf_stream *stream);
1924
1925         /**
1926          * @disable: Disables the collection of HW samples, either in response
1927          * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1928          * the stream.
1929          */
1930         void (*disable)(struct i915_perf_stream *stream);
1931
1932         /**
1933          * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1934          * once there is something ready to read() for the stream
1935          */
1936         void (*poll_wait)(struct i915_perf_stream *stream,
1937                           struct file *file,
1938                           poll_table *wait);
1939
1940         /**
1941          * @wait_unlocked: For handling a blocking read, wait until there is
1942          * something to ready to read() for the stream. E.g. wait on the same
1943          * wait queue that would be passed to poll_wait().
1944          */
1945         int (*wait_unlocked)(struct i915_perf_stream *stream);
1946
1947         /**
1948          * @read: Copy buffered metrics as records to userspace
1949          * **buf**: the userspace, destination buffer
1950          * **count**: the number of bytes to copy, requested by userspace
1951          * **offset**: zero at the start of the read, updated as the read
1952          * proceeds, it represents how many bytes have been copied so far and
1953          * the buffer offset for copying the next record.
1954          *
1955          * Copy as many buffered i915 perf samples and records for this stream
1956          * to userspace as will fit in the given buffer.
1957          *
1958          * Only write complete records; returning -%ENOSPC if there isn't room
1959          * for a complete record.
1960          *
1961          * Return any error condition that results in a short read such as
1962          * -%ENOSPC or -%EFAULT, even though these may be squashed before
1963          * returning to userspace.
1964          */
1965         int (*read)(struct i915_perf_stream *stream,
1966                     char __user *buf,
1967                     size_t count,
1968                     size_t *offset);
1969
1970         /**
1971          * @destroy: Cleanup any stream specific resources.
1972          *
1973          * The stream will always be disabled before this is called.
1974          */
1975         void (*destroy)(struct i915_perf_stream *stream);
1976 };
1977
1978 /**
1979  * struct i915_perf_stream - state for a single open stream FD
1980  */
1981 struct i915_perf_stream {
1982         /**
1983          * @dev_priv: i915 drm device
1984          */
1985         struct drm_i915_private *dev_priv;
1986
1987         /**
1988          * @link: Links the stream into ``&drm_i915_private->streams``
1989          */
1990         struct list_head link;
1991
1992         /**
1993          * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1994          * properties given when opening a stream, representing the contents
1995          * of a single sample as read() by userspace.
1996          */
1997         u32 sample_flags;
1998
1999         /**
2000          * @sample_size: Considering the configured contents of a sample
2001          * combined with the required header size, this is the total size
2002          * of a single sample record.
2003          */
2004         int sample_size;
2005
2006         /**
2007          * @ctx: %NULL if measuring system-wide across all contexts or a
2008          * specific context that is being monitored.
2009          */
2010         struct i915_gem_context *ctx;
2011
2012         /**
2013          * @enabled: Whether the stream is currently enabled, considering
2014          * whether the stream was opened in a disabled state and based
2015          * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2016          */
2017         bool enabled;
2018
2019         /**
2020          * @ops: The callbacks providing the implementation of this specific
2021          * type of configured stream.
2022          */
2023         const struct i915_perf_stream_ops *ops;
2024 };
2025
2026 /**
2027  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2028  */
2029 struct i915_oa_ops {
2030         /**
2031          * @init_oa_buffer: Resets the head and tail pointers of the
2032          * circular buffer for periodic OA reports.
2033          *
2034          * Called when first opening a stream for OA metrics, but also may be
2035          * called in response to an OA buffer overflow or other error
2036          * condition.
2037          *
2038          * Note it may be necessary to clear the full OA buffer here as part of
2039          * maintaining the invariable that new reports must be written to
2040          * zeroed memory for us to be able to reliable detect if an expected
2041          * report has not yet landed in memory.  (At least on Haswell the OA
2042          * buffer tail pointer is not synchronized with reports being visible
2043          * to the CPU)
2044          */
2045         void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2046
2047         /**
2048          * @enable_metric_set: Applies any MUX configuration to set up the
2049          * Boolean and Custom (B/C) counters that are part of the counter
2050          * reports being sampled. May apply system constraints such as
2051          * disabling EU clock gating as required.
2052          */
2053         int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2054
2055         /**
2056          * @disable_metric_set: Remove system constraints associated with using
2057          * the OA unit.
2058          */
2059         void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2060
2061         /**
2062          * @oa_enable: Enable periodic sampling
2063          */
2064         void (*oa_enable)(struct drm_i915_private *dev_priv);
2065
2066         /**
2067          * @oa_disable: Disable periodic sampling
2068          */
2069         void (*oa_disable)(struct drm_i915_private *dev_priv);
2070
2071         /**
2072          * @read: Copy data from the circular OA buffer into a given userspace
2073          * buffer.
2074          */
2075         int (*read)(struct i915_perf_stream *stream,
2076                     char __user *buf,
2077                     size_t count,
2078                     size_t *offset);
2079
2080         /**
2081          * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2082          *
2083          * This is either called via fops or the poll check hrtimer (atomic
2084          * ctx) without any locks taken.
2085          *
2086          * It's safe to read OA config state here unlocked, assuming that this
2087          * is only called while the stream is enabled, while the global OA
2088          * configuration can't be modified.
2089          *
2090          * Efficiency is more important than avoiding some false positives
2091          * here, which will be handled gracefully - likely resulting in an
2092          * %EAGAIN error for userspace.
2093          */
2094         bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2095 };
2096
2097 struct intel_cdclk_state {
2098         unsigned int cdclk, vco, ref;
2099 };
2100
2101 struct drm_i915_private {
2102         struct drm_device drm;
2103
2104         struct kmem_cache *objects;
2105         struct kmem_cache *vmas;
2106         struct kmem_cache *requests;
2107         struct kmem_cache *dependencies;
2108
2109         const struct intel_device_info info;
2110
2111         void __iomem *regs;
2112
2113         struct intel_uncore uncore;
2114
2115         struct i915_virtual_gpu vgpu;
2116
2117         struct intel_gvt *gvt;
2118
2119         struct intel_huc huc;
2120         struct intel_guc guc;
2121
2122         struct intel_csr csr;
2123
2124         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2125
2126         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2127          * controller on different i2c buses. */
2128         struct mutex gmbus_mutex;
2129
2130         /**
2131          * Base address of the gmbus and gpio block.
2132          */
2133         uint32_t gpio_mmio_base;
2134
2135         /* MMIO base address for MIPI regs */
2136         uint32_t mipi_mmio_base;
2137
2138         uint32_t psr_mmio_base;
2139
2140         uint32_t pps_mmio_base;
2141
2142         wait_queue_head_t gmbus_wait_queue;
2143
2144         struct pci_dev *bridge_dev;
2145         struct i915_gem_context *kernel_context;
2146         struct intel_engine_cs *engine[I915_NUM_ENGINES];
2147         struct i915_vma *semaphore;
2148
2149         struct drm_dma_handle *status_page_dmah;
2150         struct resource mch_res;
2151
2152         /* protects the irq masks */
2153         spinlock_t irq_lock;
2154
2155         /* protects the mmio flip data */
2156         spinlock_t mmio_flip_lock;
2157
2158         bool display_irqs_enabled;
2159
2160         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2161         struct pm_qos_request pm_qos;
2162
2163         /* Sideband mailbox protection */
2164         struct mutex sb_lock;
2165
2166         /** Cached value of IMR to avoid reads in updating the bitfield */
2167         union {
2168                 u32 irq_mask;
2169                 u32 de_irq_mask[I915_MAX_PIPES];
2170         };
2171         u32 gt_irq_mask;
2172         u32 pm_imr;
2173         u32 pm_ier;
2174         u32 pm_rps_events;
2175         u32 pm_guc_events;
2176         u32 pipestat_irq_mask[I915_MAX_PIPES];
2177
2178         struct i915_hotplug hotplug;
2179         struct intel_fbc fbc;
2180         struct i915_drrs drrs;
2181         struct intel_opregion opregion;
2182         struct intel_vbt_data vbt;
2183
2184         bool preserve_bios_swizzle;
2185
2186         /* overlay */
2187         struct intel_overlay *overlay;
2188
2189         /* backlight registers and fields in struct intel_panel */
2190         struct mutex backlight_lock;
2191
2192         /* LVDS info */
2193         bool no_aux_handshake;
2194
2195         /* protects panel power sequencer state */
2196         struct mutex pps_mutex;
2197
2198         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2199         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2200
2201         unsigned int fsb_freq, mem_freq, is_ddr3;
2202         unsigned int skl_preferred_vco_freq;
2203         unsigned int max_cdclk_freq;
2204
2205         unsigned int max_dotclk_freq;
2206         unsigned int rawclk_freq;
2207         unsigned int hpll_freq;
2208         unsigned int czclk_freq;
2209
2210         struct {
2211                 /*
2212                  * The current logical cdclk state.
2213                  * See intel_atomic_state.cdclk.logical
2214                  *
2215                  * For reading holding any crtc lock is sufficient,
2216                  * for writing must hold all of them.
2217                  */
2218                 struct intel_cdclk_state logical;
2219                 /*
2220                  * The current actual cdclk state.
2221                  * See intel_atomic_state.cdclk.actual
2222                  */
2223                 struct intel_cdclk_state actual;
2224                 /* The current hardware cdclk state */
2225                 struct intel_cdclk_state hw;
2226         } cdclk;
2227
2228         /**
2229          * wq - Driver workqueue for GEM.
2230          *
2231          * NOTE: Work items scheduled here are not allowed to grab any modeset
2232          * locks, for otherwise the flushing done in the pageflip code will
2233          * result in deadlocks.
2234          */
2235         struct workqueue_struct *wq;
2236
2237         /* Display functions */
2238         struct drm_i915_display_funcs display;
2239
2240         /* PCH chipset type */
2241         enum intel_pch pch_type;
2242         unsigned short pch_id;
2243
2244         unsigned long quirks;
2245
2246         enum modeset_restore modeset_restore;
2247         struct mutex modeset_restore_lock;
2248         struct drm_atomic_state *modeset_restore_state;
2249         struct drm_modeset_acquire_ctx reset_ctx;
2250
2251         struct list_head vm_list; /* Global list of all address spaces */
2252         struct i915_ggtt ggtt; /* VM representing the global address space */
2253
2254         struct i915_gem_mm mm;
2255         DECLARE_HASHTABLE(mm_structs, 7);
2256         struct mutex mm_lock;
2257
2258         /* The hw wants to have a stable context identifier for the lifetime
2259          * of the context (for OA, PASID, faults, etc). This is limited
2260          * in execlists to 21 bits.
2261          */
2262         struct ida context_hw_ida;
2263 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2264
2265         /* Kernel Modesetting */
2266
2267         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2268         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2269         wait_queue_head_t pending_flip_queue;
2270
2271 #ifdef CONFIG_DEBUG_FS
2272         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2273 #endif
2274
2275         /* dpll and cdclk state is protected by connection_mutex */
2276         int num_shared_dpll;
2277         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2278         const struct intel_dpll_mgr *dpll_mgr;
2279
2280         /*
2281          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2282          * Must be global rather than per dpll, because on some platforms
2283          * plls share registers.
2284          */
2285         struct mutex dpll_lock;
2286
2287         unsigned int active_crtcs;
2288         unsigned int min_pixclk[I915_MAX_PIPES];
2289
2290         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2291
2292         struct i915_workarounds workarounds;
2293
2294         struct i915_frontbuffer_tracking fb_tracking;
2295
2296         struct intel_atomic_helper {
2297                 struct llist_head free_list;
2298                 struct work_struct free_work;
2299         } atomic_helper;
2300
2301         u16 orig_clock;
2302
2303         bool mchbar_need_disable;
2304
2305         struct intel_l3_parity l3_parity;
2306
2307         /* Cannot be determined by PCIID. You must always read a register. */
2308         u32 edram_cap;
2309
2310         /* gen6+ rps state */
2311         struct intel_gen6_power_mgmt rps;
2312
2313         /* ilk-only ips/rps state. Everything in here is protected by the global
2314          * mchdev_lock in intel_pm.c */
2315         struct intel_ilk_power_mgmt ips;
2316
2317         struct i915_power_domains power_domains;
2318
2319         struct i915_psr psr;
2320
2321         struct i915_gpu_error gpu_error;
2322
2323         struct drm_i915_gem_object *vlv_pctx;
2324
2325 #ifdef CONFIG_DRM_FBDEV_EMULATION
2326         /* list of fbdev register on this device */
2327         struct intel_fbdev *fbdev;
2328         struct work_struct fbdev_suspend_work;
2329 #endif
2330
2331         struct drm_property *broadcast_rgb_property;
2332         struct drm_property *force_audio_property;
2333
2334         /* hda/i915 audio component */
2335         struct i915_audio_component *audio_component;
2336         bool audio_component_registered;
2337         /**
2338          * av_mutex - mutex for audio/video sync
2339          *
2340          */
2341         struct mutex av_mutex;
2342
2343         uint32_t hw_context_size;
2344         struct list_head context_list;
2345
2346         u32 fdi_rx_config;
2347
2348         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2349         u32 chv_phy_control;
2350         /*
2351          * Shadows for CHV DPLL_MD regs to keep the state
2352          * checker somewhat working in the presence hardware
2353          * crappiness (can't read out DPLL_MD for pipes B & C).
2354          */
2355         u32 chv_dpll_md[I915_MAX_PIPES];
2356         u32 bxt_phy_grc;
2357
2358         u32 suspend_count;
2359         bool suspended_to_idle;
2360         struct i915_suspend_saved_registers regfile;
2361         struct vlv_s0ix_state vlv_s0ix_state;
2362
2363         enum {
2364                 I915_SAGV_UNKNOWN = 0,
2365                 I915_SAGV_DISABLED,
2366                 I915_SAGV_ENABLED,
2367                 I915_SAGV_NOT_CONTROLLED
2368         } sagv_status;
2369
2370         struct {
2371                 /* protects DSPARB registers on pre-g4x/vlv/chv */
2372                 spinlock_t dsparb_lock;
2373
2374                 /*
2375                  * Raw watermark latency values:
2376                  * in 0.1us units for WM0,
2377                  * in 0.5us units for WM1+.
2378                  */
2379                 /* primary */
2380                 uint16_t pri_latency[5];
2381                 /* sprite */
2382                 uint16_t spr_latency[5];
2383                 /* cursor */
2384                 uint16_t cur_latency[5];
2385                 /*
2386                  * Raw watermark memory latency values
2387                  * for SKL for all 8 levels
2388                  * in 1us units.
2389                  */
2390                 uint16_t skl_latency[8];
2391
2392                 /* current hardware state */
2393                 union {
2394                         struct ilk_wm_values hw;
2395                         struct skl_wm_values skl_hw;
2396                         struct vlv_wm_values vlv;
2397                 };
2398
2399                 uint8_t max_level;
2400
2401                 /*
2402                  * Should be held around atomic WM register writing; also
2403                  * protects * intel_crtc->wm.active and
2404                  * cstate->wm.need_postvbl_update.
2405                  */
2406                 struct mutex wm_mutex;
2407
2408                 /*
2409                  * Set during HW readout of watermarks/DDB.  Some platforms
2410                  * need to know when we're still using BIOS-provided values
2411                  * (which we don't fully trust).
2412                  */
2413                 bool distrust_bios_wm;
2414         } wm;
2415
2416         struct i915_runtime_pm pm;
2417
2418         struct {
2419                 bool initialized;
2420
2421                 struct kobject *metrics_kobj;
2422                 struct ctl_table_header *sysctl_header;
2423
2424                 struct mutex lock;
2425                 struct list_head streams;
2426
2427                 spinlock_t hook_lock;
2428
2429                 struct {
2430                         struct i915_perf_stream *exclusive_stream;
2431
2432                         u32 specific_ctx_id;
2433
2434                         struct hrtimer poll_check_timer;
2435                         wait_queue_head_t poll_wq;
2436                         bool pollin;
2437
2438                         bool periodic;
2439                         int period_exponent;
2440                         int timestamp_frequency;
2441
2442                         int tail_margin;
2443
2444                         int metrics_set;
2445
2446                         const struct i915_oa_reg *mux_regs;
2447                         int mux_regs_len;
2448                         const struct i915_oa_reg *b_counter_regs;
2449                         int b_counter_regs_len;
2450
2451                         struct {
2452                                 struct i915_vma *vma;
2453                                 u8 *vaddr;
2454                                 int format;
2455                                 int format_size;
2456                         } oa_buffer;
2457
2458                         u32 gen7_latched_oastatus1;
2459
2460                         struct i915_oa_ops ops;
2461                         const struct i915_oa_format *oa_formats;
2462                         int n_builtin_sets;
2463                 } oa;
2464         } perf;
2465
2466         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2467         struct {
2468                 void (*resume)(struct drm_i915_private *);
2469                 void (*cleanup_engine)(struct intel_engine_cs *engine);
2470
2471                 struct list_head timelines;
2472                 struct i915_gem_timeline global_timeline;
2473                 u32 active_requests;
2474
2475                 /**
2476                  * Is the GPU currently considered idle, or busy executing
2477                  * userspace requests? Whilst idle, we allow runtime power
2478                  * management to power down the hardware and display clocks.
2479                  * In order to reduce the effect on performance, there
2480                  * is a slight delay before we do so.
2481                  */
2482                 bool awake;
2483
2484                 /**
2485                  * We leave the user IRQ off as much as possible,
2486                  * but this means that requests will finish and never
2487                  * be retired once the system goes idle. Set a timer to
2488                  * fire periodically while the ring is running. When it
2489                  * fires, go retire requests.
2490                  */
2491                 struct delayed_work retire_work;
2492
2493                 /**
2494                  * When we detect an idle GPU, we want to turn on
2495                  * powersaving features. So once we see that there
2496                  * are no more requests outstanding and no more
2497                  * arrive within a small period of time, we fire
2498                  * off the idle_work.
2499                  */
2500                 struct delayed_work idle_work;
2501
2502                 ktime_t last_init_time;
2503         } gt;
2504
2505         /* perform PHY state sanity checks? */
2506         bool chv_phy_assert[2];
2507
2508         bool ipc_enabled;
2509
2510         /* Used to save the pipe-to-encoder mapping for audio */
2511         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2512
2513         /*
2514          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2515          * will be rejected. Instead look for a better place.
2516          */
2517 };
2518
2519 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2520 {
2521         return container_of(dev, struct drm_i915_private, drm);
2522 }
2523
2524 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2525 {
2526         return to_i915(dev_get_drvdata(kdev));
2527 }
2528
2529 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2530 {
2531         return container_of(guc, struct drm_i915_private, guc);
2532 }
2533
2534 /* Simple iterator over all initialised engines */
2535 #define for_each_engine(engine__, dev_priv__, id__) \
2536         for ((id__) = 0; \
2537              (id__) < I915_NUM_ENGINES; \
2538              (id__)++) \
2539                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2540
2541 #define __mask_next_bit(mask) ({                                        \
2542         int __idx = ffs(mask) - 1;                                      \
2543         mask &= ~BIT(__idx);                                            \
2544         __idx;                                                          \
2545 })
2546
2547 /* Iterator over subset of engines selected by mask */
2548 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2549         for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;        \
2550              tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2551
2552 enum hdmi_force_audio {
2553         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2554         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2555         HDMI_AUDIO_AUTO,                /* trust EDID */
2556         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2557 };
2558
2559 #define I915_GTT_OFFSET_NONE ((u32)-1)
2560
2561 /*
2562  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2563  * considered to be the frontbuffer for the given plane interface-wise. This
2564  * doesn't mean that the hw necessarily already scans it out, but that any
2565  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2566  *
2567  * We have one bit per pipe and per scanout plane type.
2568  */
2569 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2570 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2571 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2572         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2573 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2574         (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2575 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2576         (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2577 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2578         (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2579 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2580         (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2581
2582 /*
2583  * Optimised SGL iterator for GEM objects
2584  */
2585 static __always_inline struct sgt_iter {
2586         struct scatterlist *sgp;
2587         union {
2588                 unsigned long pfn;
2589                 dma_addr_t dma;
2590         };
2591         unsigned int curr;
2592         unsigned int max;
2593 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2594         struct sgt_iter s = { .sgp = sgl };
2595
2596         if (s.sgp) {
2597                 s.max = s.curr = s.sgp->offset;
2598                 s.max += s.sgp->length;
2599                 if (dma)
2600                         s.dma = sg_dma_address(s.sgp);
2601                 else
2602                         s.pfn = page_to_pfn(sg_page(s.sgp));
2603         }
2604
2605         return s;
2606 }
2607
2608 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2609 {
2610         ++sg;
2611         if (unlikely(sg_is_chain(sg)))
2612                 sg = sg_chain_ptr(sg);
2613         return sg;
2614 }
2615
2616 /**
2617  * __sg_next - return the next scatterlist entry in a list
2618  * @sg:         The current sg entry
2619  *
2620  * Description:
2621  *   If the entry is the last, return NULL; otherwise, step to the next
2622  *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2623  *   otherwise just return the pointer to the current element.
2624  **/
2625 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2626 {
2627 #ifdef CONFIG_DEBUG_SG
2628         BUG_ON(sg->sg_magic != SG_MAGIC);
2629 #endif
2630         return sg_is_last(sg) ? NULL : ____sg_next(sg);
2631 }
2632
2633 /**
2634  * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2635  * @__dmap:     DMA address (output)
2636  * @__iter:     'struct sgt_iter' (iterator state, internal)
2637  * @__sgt:      sg_table to iterate over (input)
2638  */
2639 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2640         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2641              ((__dmap) = (__iter).dma + (__iter).curr);                 \
2642              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2643              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2644
2645 /**
2646  * for_each_sgt_page - iterate over the pages of the given sg_table
2647  * @__pp:       page pointer (output)
2648  * @__iter:     'struct sgt_iter' (iterator state, internal)
2649  * @__sgt:      sg_table to iterate over (input)
2650  */
2651 #define for_each_sgt_page(__pp, __iter, __sgt)                          \
2652         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2653              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2654               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2655              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2656              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2657
2658 static inline const struct intel_device_info *
2659 intel_info(const struct drm_i915_private *dev_priv)
2660 {
2661         return &dev_priv->info;
2662 }
2663
2664 #define INTEL_INFO(dev_priv)    intel_info((dev_priv))
2665
2666 #define INTEL_GEN(dev_priv)     ((dev_priv)->info.gen)
2667 #define INTEL_DEVID(dev_priv)   ((dev_priv)->info.device_id)
2668
2669 #define REVID_FOREVER           0xff
2670 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
2671
2672 #define GEN_FOREVER (0)
2673 /*
2674  * Returns true if Gen is in inclusive range [Start, End].
2675  *
2676  * Use GEN_FOREVER for unbound start and or end.
2677  */
2678 #define IS_GEN(dev_priv, s, e) ({ \
2679         unsigned int __s = (s), __e = (e); \
2680         BUILD_BUG_ON(!__builtin_constant_p(s)); \
2681         BUILD_BUG_ON(!__builtin_constant_p(e)); \
2682         if ((__s) != GEN_FOREVER) \
2683                 __s = (s) - 1; \
2684         if ((__e) == GEN_FOREVER) \
2685                 __e = BITS_PER_LONG - 1; \
2686         else \
2687                 __e = (e) - 1; \
2688         !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2689 })
2690
2691 /*
2692  * Return true if revision is in range [since,until] inclusive.
2693  *
2694  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2695  */
2696 #define IS_REVID(p, since, until) \
2697         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2698
2699 #define IS_I830(dev_priv)       ((dev_priv)->info.platform == INTEL_I830)
2700 #define IS_I845G(dev_priv)      ((dev_priv)->info.platform == INTEL_I845G)
2701 #define IS_I85X(dev_priv)       ((dev_priv)->info.platform == INTEL_I85X)
2702 #define IS_I865G(dev_priv)      ((dev_priv)->info.platform == INTEL_I865G)
2703 #define IS_I915G(dev_priv)      ((dev_priv)->info.platform == INTEL_I915G)
2704 #define IS_I915GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I915GM)
2705 #define IS_I945G(dev_priv)      ((dev_priv)->info.platform == INTEL_I945G)
2706 #define IS_I945GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I945GM)
2707 #define IS_I965G(dev_priv)      ((dev_priv)->info.platform == INTEL_I965G)
2708 #define IS_I965GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I965GM)
2709 #define IS_G45(dev_priv)        ((dev_priv)->info.platform == INTEL_G45)
2710 #define IS_GM45(dev_priv)       ((dev_priv)->info.platform == INTEL_GM45)
2711 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
2712 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2713 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2714 #define IS_PINEVIEW(dev_priv)   ((dev_priv)->info.platform == INTEL_PINEVIEW)
2715 #define IS_G33(dev_priv)        ((dev_priv)->info.platform == INTEL_G33)
2716 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2717 #define IS_IVYBRIDGE(dev_priv)  ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2718 #define IS_IVB_GT1(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0156 || \
2719                                  INTEL_DEVID(dev_priv) == 0x0152 || \
2720                                  INTEL_DEVID(dev_priv) == 0x015a)
2721 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2722 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2723 #define IS_HASWELL(dev_priv)    ((dev_priv)->info.platform == INTEL_HASWELL)
2724 #define IS_BROADWELL(dev_priv)  ((dev_priv)->info.platform == INTEL_BROADWELL)
2725 #define IS_SKYLAKE(dev_priv)    ((dev_priv)->info.platform == INTEL_SKYLAKE)
2726 #define IS_BROXTON(dev_priv)    ((dev_priv)->info.platform == INTEL_BROXTON)
2727 #define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.platform == INTEL_KABYLAKE)
2728 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2729 #define IS_MOBILE(dev_priv)     ((dev_priv)->info.is_mobile)
2730 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2731                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2732 #define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
2733                                  ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||       \
2734                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||        \
2735                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2736 /* ULX machines are also considered ULT. */
2737 #define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
2738                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2739 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
2740                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2741 #define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
2742                                  (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2743 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
2744                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2745 /* ULX machines are also considered ULT. */
2746 #define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
2747                                  INTEL_DEVID(dev_priv) == 0x0A1E)
2748 #define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
2749                                  INTEL_DEVID(dev_priv) == 0x1913 || \
2750                                  INTEL_DEVID(dev_priv) == 0x1916 || \
2751                                  INTEL_DEVID(dev_priv) == 0x1921 || \
2752                                  INTEL_DEVID(dev_priv) == 0x1926)
2753 #define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
2754                                  INTEL_DEVID(dev_priv) == 0x1915 || \
2755                                  INTEL_DEVID(dev_priv) == 0x191E)
2756 #define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
2757                                  INTEL_DEVID(dev_priv) == 0x5913 || \
2758                                  INTEL_DEVID(dev_priv) == 0x5916 || \
2759                                  INTEL_DEVID(dev_priv) == 0x5921 || \
2760                                  INTEL_DEVID(dev_priv) == 0x5926)
2761 #define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
2762                                  INTEL_DEVID(dev_priv) == 0x5915 || \
2763                                  INTEL_DEVID(dev_priv) == 0x591E)
2764 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2765                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2766 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2767                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2768
2769 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2770
2771 #define SKL_REVID_A0            0x0
2772 #define SKL_REVID_B0            0x1
2773 #define SKL_REVID_C0            0x2
2774 #define SKL_REVID_D0            0x3
2775 #define SKL_REVID_E0            0x4
2776 #define SKL_REVID_F0            0x5
2777 #define SKL_REVID_G0            0x6
2778 #define SKL_REVID_H0            0x7
2779
2780 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2781
2782 #define BXT_REVID_A0            0x0
2783 #define BXT_REVID_A1            0x1
2784 #define BXT_REVID_B0            0x3
2785 #define BXT_REVID_B_LAST        0x8
2786 #define BXT_REVID_C0            0x9
2787
2788 #define IS_BXT_REVID(dev_priv, since, until) \
2789         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2790
2791 #define KBL_REVID_A0            0x0
2792 #define KBL_REVID_B0            0x1
2793 #define KBL_REVID_C0            0x2
2794 #define KBL_REVID_D0            0x3
2795 #define KBL_REVID_E0            0x4
2796
2797 #define IS_KBL_REVID(dev_priv, since, until) \
2798         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2799
2800 #define GLK_REVID_A0            0x0
2801 #define GLK_REVID_A1            0x1
2802
2803 #define IS_GLK_REVID(dev_priv, since, until) \
2804         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2805
2806 /*
2807  * The genX designation typically refers to the render engine, so render
2808  * capability related checks should use IS_GEN, while display and other checks
2809  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2810  * chips, etc.).
2811  */
2812 #define IS_GEN2(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(1)))
2813 #define IS_GEN3(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(2)))
2814 #define IS_GEN4(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(3)))
2815 #define IS_GEN5(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(4)))
2816 #define IS_GEN6(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(5)))
2817 #define IS_GEN7(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(6)))
2818 #define IS_GEN8(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(7)))
2819 #define IS_GEN9(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(8)))
2820
2821 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2822 #define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2823 #define IS_GEN9_BC(dev_priv)    (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2824
2825 #define ENGINE_MASK(id) BIT(id)
2826 #define RENDER_RING     ENGINE_MASK(RCS)
2827 #define BSD_RING        ENGINE_MASK(VCS)
2828 #define BLT_RING        ENGINE_MASK(BCS)
2829 #define VEBOX_RING      ENGINE_MASK(VECS)
2830 #define BSD2_RING       ENGINE_MASK(VCS2)
2831 #define ALL_ENGINES     (~0)
2832
2833 #define HAS_ENGINE(dev_priv, id) \
2834         (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2835
2836 #define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2837 #define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2838 #define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2839 #define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2840
2841 #define HAS_LLC(dev_priv)       ((dev_priv)->info.has_llc)
2842 #define HAS_SNOOP(dev_priv)     ((dev_priv)->info.has_snoop)
2843 #define HAS_EDRAM(dev_priv)     (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2844 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
2845                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2846
2847 #define HWS_NEEDS_PHYSICAL(dev_priv)    ((dev_priv)->info.hws_needs_physical)
2848
2849 #define HAS_HW_CONTEXTS(dev_priv)           ((dev_priv)->info.has_hw_contexts)
2850 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2851                 ((dev_priv)->info.has_logical_ring_contexts)
2852 #define USES_PPGTT(dev_priv)            (i915.enable_ppgtt)
2853 #define USES_FULL_PPGTT(dev_priv)       (i915.enable_ppgtt >= 2)
2854 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2855
2856 #define HAS_OVERLAY(dev_priv)            ((dev_priv)->info.has_overlay)
2857 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2858                 ((dev_priv)->info.overlay_needs_physical)
2859
2860 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2861 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
2862
2863 /* WaRsDisableCoarsePowerGating:skl,bxt */
2864 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2865         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2866
2867 /*
2868  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2869  * even when in MSI mode. This results in spurious interrupt warnings if the
2870  * legacy irq no. is shared with another device. The kernel then disables that
2871  * interrupt source and so prevents the other device from working properly.
2872  */
2873 #define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
2874 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2875
2876 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2877  * rows, which changed the alignment requirements and fence programming.
2878  */
2879 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2880                                          !(IS_I915G(dev_priv) || \
2881                                          IS_I915GM(dev_priv)))
2882 #define SUPPORTS_TV(dev_priv)           ((dev_priv)->info.supports_tv)
2883 #define I915_HAS_HOTPLUG(dev_priv)      ((dev_priv)->info.has_hotplug)
2884
2885 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
2886 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2887 #define HAS_FBC(dev_priv)       ((dev_priv)->info.has_fbc)
2888
2889 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2890
2891 #define HAS_DP_MST(dev_priv)    ((dev_priv)->info.has_dp_mst)
2892
2893 #define HAS_DDI(dev_priv)                ((dev_priv)->info.has_ddi)
2894 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2895 #define HAS_PSR(dev_priv)                ((dev_priv)->info.has_psr)
2896 #define HAS_RC6(dev_priv)                ((dev_priv)->info.has_rc6)
2897 #define HAS_RC6p(dev_priv)               ((dev_priv)->info.has_rc6p)
2898
2899 #define HAS_CSR(dev_priv)       ((dev_priv)->info.has_csr)
2900
2901 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2902 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2903
2904 /*
2905  * For now, anything with a GuC requires uCode loading, and then supports
2906  * command submission once loaded. But these are logically independent
2907  * properties, so we have separate macros to test them.
2908  */
2909 #define HAS_GUC(dev_priv)       ((dev_priv)->info.has_guc)
2910 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2911 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2912 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2913
2914 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2915
2916 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2917
2918 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2919 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2920 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2921 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2922 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2923 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2924 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2925 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2926 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA200
2927 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2928 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2929 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2930
2931 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2932 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2933 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2934 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2935 #define HAS_PCH_LPT_LP(dev_priv) \
2936         ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2937 #define HAS_PCH_LPT_H(dev_priv) \
2938         ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2939 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2940 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2941 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2942 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2943
2944 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2945
2946 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2947
2948 /* DPF == dynamic parity feature */
2949 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2950 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2951                                  2 : HAS_L3_DPF(dev_priv))
2952
2953 #define GT_FREQUENCY_MULTIPLIER 50
2954 #define GEN9_FREQ_SCALER 3
2955
2956 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2957
2958 #include "i915_trace.h"
2959
2960 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2961 {
2962 #ifdef CONFIG_INTEL_IOMMU
2963         if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2964                 return true;
2965 #endif
2966         return false;
2967 }
2968
2969 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2970                                 int enable_ppgtt);
2971
2972 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2973
2974 /* i915_drv.c */
2975 void __printf(3, 4)
2976 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2977               const char *fmt, ...);
2978
2979 #define i915_report_error(dev_priv, fmt, ...)                              \
2980         __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2981
2982 #ifdef CONFIG_COMPAT
2983 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2984                               unsigned long arg);
2985 #else
2986 #define i915_compat_ioctl NULL
2987 #endif
2988 extern const struct dev_pm_ops i915_pm_ops;
2989
2990 extern int i915_driver_load(struct pci_dev *pdev,
2991                             const struct pci_device_id *ent);
2992 extern void i915_driver_unload(struct drm_device *dev);
2993 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2994 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2995 extern void i915_reset(struct drm_i915_private *dev_priv);
2996 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2997 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2998 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2999 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3000 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3001 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3002 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3003 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3004
3005 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3006 int intel_engines_init(struct drm_i915_private *dev_priv);
3007
3008 /* intel_hotplug.c */
3009 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3010                            u32 pin_mask, u32 long_mask);
3011 void intel_hpd_init(struct drm_i915_private *dev_priv);
3012 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3013 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3014 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3015 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3016 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3017
3018 /* i915_irq.c */
3019 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3020 {
3021         unsigned long delay;
3022
3023         if (unlikely(!i915.enable_hangcheck))
3024                 return;
3025
3026         /* Don't continually defer the hangcheck so that it is always run at
3027          * least once after work has been scheduled on any ring. Otherwise,
3028          * we will ignore a hung ring if a second ring is kept busy.
3029          */
3030
3031         delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3032         queue_delayed_work(system_long_wq,
3033                            &dev_priv->gpu_error.hangcheck_work, delay);
3034 }
3035
3036 __printf(3, 4)
3037 void i915_handle_error(struct drm_i915_private *dev_priv,
3038                        u32 engine_mask,
3039                        const char *fmt, ...);
3040
3041 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3042 int intel_irq_install(struct drm_i915_private *dev_priv);
3043 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3044
3045 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3046 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3047                                         bool restore_forcewake);
3048 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3049 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3050 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3051 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3052 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3053                                          bool restore);
3054 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3055 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3056                                 enum forcewake_domains domains);
3057 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3058                                 enum forcewake_domains domains);
3059 /* Like above but the caller must manage the uncore.lock itself.
3060  * Must be used with I915_READ_FW and friends.
3061  */
3062 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3063                                         enum forcewake_domains domains);
3064 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3065                                         enum forcewake_domains domains);
3066 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3067
3068 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3069
3070 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3071                             i915_reg_t reg,
3072                             const u32 mask,
3073                             const u32 value,
3074                             const unsigned long timeout_ms);
3075 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3076                                i915_reg_t reg,
3077                                const u32 mask,
3078                                const u32 value,
3079                                const unsigned long timeout_ms);
3080
3081 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3082 {
3083         return dev_priv->gvt;
3084 }
3085
3086 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3087 {
3088         return dev_priv->vgpu.active;
3089 }
3090
3091 void
3092 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3093                      u32 status_mask);
3094
3095 void
3096 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3097                       u32 status_mask);
3098
3099 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3100 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3101 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3102                                    uint32_t mask,
3103                                    uint32_t bits);
3104 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3105                             uint32_t interrupt_mask,
3106                             uint32_t enabled_irq_mask);
3107 static inline void
3108 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3109 {
3110         ilk_update_display_irq(dev_priv, bits, bits);
3111 }
3112 static inline void
3113 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3114 {
3115         ilk_update_display_irq(dev_priv, bits, 0);
3116 }
3117 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3118                          enum pipe pipe,
3119                          uint32_t interrupt_mask,
3120                          uint32_t enabled_irq_mask);
3121 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3122                                        enum pipe pipe, uint32_t bits)
3123 {
3124         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3125 }
3126 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3127                                         enum pipe pipe, uint32_t bits)
3128 {
3129         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3130 }
3131 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3132                                   uint32_t interrupt_mask,
3133                                   uint32_t enabled_irq_mask);
3134 static inline void
3135 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3136 {
3137         ibx_display_interrupt_update(dev_priv, bits, bits);
3138 }
3139 static inline void
3140 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3141 {
3142         ibx_display_interrupt_update(dev_priv, bits, 0);
3143 }
3144
3145 /* i915_gem.c */
3146 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3147                           struct drm_file *file_priv);
3148 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3149                          struct drm_file *file_priv);
3150 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3151                           struct drm_file *file_priv);
3152 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3153                         struct drm_file *file_priv);
3154 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3155                         struct drm_file *file_priv);
3156 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3157                               struct drm_file *file_priv);
3158 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3159                              struct drm_file *file_priv);
3160 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3161                         struct drm_file *file_priv);
3162 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3163                          struct drm_file *file_priv);
3164 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3165                         struct drm_file *file_priv);
3166 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3167                                struct drm_file *file);
3168 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3169                                struct drm_file *file);
3170 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3171                             struct drm_file *file_priv);
3172 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3173                            struct drm_file *file_priv);
3174 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3175                               struct drm_file *file_priv);
3176 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3177                               struct drm_file *file_priv);
3178 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3179 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3180                            struct drm_file *file);
3181 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3182                                 struct drm_file *file_priv);
3183 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3184                         struct drm_file *file_priv);
3185 void i915_gem_sanitize(struct drm_i915_private *i915);
3186 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3187 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3188 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3189 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3190 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3191
3192 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3193 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3194 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3195                          const struct drm_i915_gem_object_ops *ops);
3196 struct drm_i915_gem_object *
3197 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3198 struct drm_i915_gem_object *
3199 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3200                                  const void *data, size_t size);
3201 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3202 void i915_gem_free_object(struct drm_gem_object *obj);
3203
3204 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3205 {
3206         /* A single pass should suffice to release all the freed objects (along
3207          * most call paths) , but be a little more paranoid in that freeing
3208          * the objects does take a little amount of time, during which the rcu
3209          * callbacks could have added new objects into the freed list, and
3210          * armed the work again.
3211          */
3212         do {
3213                 rcu_barrier();
3214         } while (flush_work(&i915->mm.free_work));
3215 }
3216
3217 struct i915_vma * __must_check
3218 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3219                          const struct i915_ggtt_view *view,
3220                          u64 size,
3221                          u64 alignment,
3222                          u64 flags);
3223
3224 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3225 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3226
3227 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3228
3229 static inline int __sg_page_count(const struct scatterlist *sg)
3230 {
3231         return sg->length >> PAGE_SHIFT;
3232 }
3233
3234 struct scatterlist *
3235 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3236                        unsigned int n, unsigned int *offset);
3237
3238 struct page *
3239 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3240                          unsigned int n);
3241
3242 struct page *
3243 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3244                                unsigned int n);
3245
3246 dma_addr_t
3247 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3248                                 unsigned long n);
3249
3250 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3251                                  struct sg_table *pages);
3252 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3253
3254 static inline int __must_check
3255 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3256 {
3257         might_lock(&obj->mm.lock);
3258
3259         if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3260                 return 0;
3261
3262         return __i915_gem_object_get_pages(obj);
3263 }
3264
3265 static inline void
3266 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3267 {
3268         GEM_BUG_ON(!obj->mm.pages);
3269
3270         atomic_inc(&obj->mm.pages_pin_count);
3271 }
3272
3273 static inline bool
3274 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3275 {
3276         return atomic_read(&obj->mm.pages_pin_count);
3277 }
3278
3279 static inline void
3280 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3281 {
3282         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3283         GEM_BUG_ON(!obj->mm.pages);
3284
3285         atomic_dec(&obj->mm.pages_pin_count);
3286 }
3287
3288 static inline void
3289 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3290 {
3291         __i915_gem_object_unpin_pages(obj);
3292 }
3293
3294 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3295         I915_MM_NORMAL = 0,
3296         I915_MM_SHRINKER
3297 };
3298
3299 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3300                                  enum i915_mm_subclass subclass);
3301 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3302
3303 enum i915_map_type {
3304         I915_MAP_WB = 0,
3305         I915_MAP_WC,
3306 };
3307
3308 /**
3309  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3310  * @obj: the object to map into kernel address space
3311  * @type: the type of mapping, used to select pgprot_t
3312  *
3313  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3314  * pages and then returns a contiguous mapping of the backing storage into
3315  * the kernel address space. Based on the @type of mapping, the PTE will be
3316  * set to either WriteBack or WriteCombine (via pgprot_t).
3317  *
3318  * The caller is responsible for calling i915_gem_object_unpin_map() when the
3319  * mapping is no longer required.
3320  *
3321  * Returns the pointer through which to access the mapped object, or an
3322  * ERR_PTR() on error.
3323  */
3324 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3325                                            enum i915_map_type type);
3326
3327 /**
3328  * i915_gem_object_unpin_map - releases an earlier mapping
3329  * @obj: the object to unmap
3330  *
3331  * After pinning the object and mapping its pages, once you are finished
3332  * with your access, call i915_gem_object_unpin_map() to release the pin
3333  * upon the mapping. Once the pin count reaches zero, that mapping may be
3334  * removed.
3335  */
3336 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3337 {
3338         i915_gem_object_unpin_pages(obj);
3339 }
3340
3341 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3342                                     unsigned int *needs_clflush);
3343 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3344                                      unsigned int *needs_clflush);
3345 #define CLFLUSH_BEFORE 0x1
3346 #define CLFLUSH_AFTER 0x2
3347 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3348
3349 static inline void
3350 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3351 {
3352         i915_gem_object_unpin_pages(obj);
3353 }
3354
3355 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3356 void i915_vma_move_to_active(struct i915_vma *vma,
3357                              struct drm_i915_gem_request *req,
3358                              unsigned int flags);
3359 int i915_gem_dumb_create(struct drm_file *file_priv,
3360                          struct drm_device *dev,
3361                          struct drm_mode_create_dumb *args);
3362 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3363                       uint32_t handle, uint64_t *offset);
3364 int i915_gem_mmap_gtt_version(void);
3365
3366 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3367                        struct drm_i915_gem_object *new,
3368                        unsigned frontbuffer_bits);
3369
3370 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3371
3372 struct drm_i915_gem_request *
3373 i915_gem_find_active_request(struct intel_engine_cs *engine);
3374
3375 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3376
3377 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3378 {
3379         return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3380 }
3381
3382 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3383 {
3384         return unlikely(test_bit(I915_WEDGED, &error->flags));
3385 }
3386
3387 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3388 {
3389         return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3390 }
3391
3392 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3393 {
3394         return READ_ONCE(error->reset_count);
3395 }
3396
3397 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3398 void i915_gem_reset(struct drm_i915_private *dev_priv);
3399 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3400 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3401
3402 void i915_gem_init_mmio(struct drm_i915_private *i915);
3403 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3404 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3405 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3406 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3407 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3408                            unsigned int flags);
3409 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3410 void i915_gem_resume(struct drm_i915_private *dev_priv);
3411 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3412 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3413                          unsigned int flags,
3414                          long timeout,
3415                          struct intel_rps_client *rps);
3416 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3417                                   unsigned int flags,
3418                                   int priority);
3419 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3420
3421 int __must_check
3422 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3423                                   bool write);
3424 int __must_check
3425 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3426 struct i915_vma * __must_check
3427 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3428                                      u32 alignment,
3429                                      const struct i915_ggtt_view *view);
3430 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3431 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3432                                 int align);
3433 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3434 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3435
3436 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3437                                     enum i915_cache_level cache_level);
3438
3439 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3440                                 struct dma_buf *dma_buf);
3441
3442 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3443                                 struct drm_gem_object *gem_obj, int flags);
3444
3445 static inline struct i915_hw_ppgtt *
3446 i915_vm_to_ppgtt(struct i915_address_space *vm)
3447 {
3448         return container_of(vm, struct i915_hw_ppgtt, base);
3449 }
3450
3451 /* i915_gem_fence_reg.c */
3452 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3453 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3454
3455 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3456 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3457
3458 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3459 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3460                                        struct sg_table *pages);
3461 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3462                                          struct sg_table *pages);
3463
3464 static inline struct i915_gem_context *
3465 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3466 {
3467         struct i915_gem_context *ctx;
3468
3469         lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3470
3471         ctx = idr_find(&file_priv->context_idr, id);
3472         if (!ctx)
3473                 return ERR_PTR(-ENOENT);
3474
3475         return ctx;
3476 }
3477
3478 static inline struct i915_gem_context *
3479 i915_gem_context_get(struct i915_gem_context *ctx)
3480 {
3481         kref_get(&ctx->ref);
3482         return ctx;
3483 }
3484
3485 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3486 {
3487         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3488         kref_put(&ctx->ref, i915_gem_context_free);
3489 }
3490
3491 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3492 {
3493         struct mutex *lock = &ctx->i915->drm.struct_mutex;
3494
3495         if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3496                 mutex_unlock(lock);
3497 }
3498
3499 static inline struct intel_timeline *
3500 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3501                                  struct intel_engine_cs *engine)
3502 {
3503         struct i915_address_space *vm;
3504
3505         vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3506         return &vm->timeline.engine[engine->id];
3507 }
3508
3509 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3510                          struct drm_file *file);
3511
3512 /* i915_gem_evict.c */
3513 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3514                                           u64 min_size, u64 alignment,
3515                                           unsigned cache_level,
3516                                           u64 start, u64 end,
3517                                           unsigned flags);
3518 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3519                                          struct drm_mm_node *node,
3520                                          unsigned int flags);
3521 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3522
3523 /* belongs in i915_gem_gtt.h */
3524 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3525 {
3526         wmb();
3527         if (INTEL_GEN(dev_priv) < 6)
3528                 intel_gtt_chipset_flush();
3529 }
3530
3531 /* i915_gem_stolen.c */
3532 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3533                                 struct drm_mm_node *node, u64 size,
3534                                 unsigned alignment);
3535 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3536                                          struct drm_mm_node *node, u64 size,
3537                                          unsigned alignment, u64 start,
3538                                          u64 end);
3539 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3540                                  struct drm_mm_node *node);
3541 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3542 void i915_gem_cleanup_stolen(struct drm_device *dev);
3543 struct drm_i915_gem_object *
3544 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3545 struct drm_i915_gem_object *
3546 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3547                                                u32 stolen_offset,
3548                                                u32 gtt_offset,
3549                                                u32 size);
3550
3551 /* i915_gem_internal.c */
3552 struct drm_i915_gem_object *
3553 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3554                                 phys_addr_t size);
3555
3556 /* i915_gem_shrinker.c */
3557 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3558                               unsigned long target,
3559                               unsigned flags);
3560 #define I915_SHRINK_PURGEABLE 0x1
3561 #define I915_SHRINK_UNBOUND 0x2
3562 #define I915_SHRINK_BOUND 0x4
3563 #define I915_SHRINK_ACTIVE 0x8
3564 #define I915_SHRINK_VMAPS 0x10
3565 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3566 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3567 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3568
3569
3570 /* i915_gem_tiling.c */
3571 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3572 {
3573         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3574
3575         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3576                 i915_gem_object_is_tiled(obj);
3577 }
3578
3579 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3580                         unsigned int tiling, unsigned int stride);
3581 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3582                              unsigned int tiling, unsigned int stride);
3583
3584 /* i915_debugfs.c */
3585 #ifdef CONFIG_DEBUG_FS
3586 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3587 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3588 int i915_debugfs_connector_add(struct drm_connector *connector);
3589 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3590 #else
3591 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3592 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3593 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3594 { return 0; }
3595 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3596 #endif
3597
3598 /* i915_gpu_error.c */
3599 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3600
3601 __printf(2, 3)
3602 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3603 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3604                             const struct i915_gpu_state *gpu);
3605 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3606                               struct drm_i915_private *i915,
3607                               size_t count, loff_t pos);
3608 static inline void i915_error_state_buf_release(
3609         struct drm_i915_error_state_buf *eb)
3610 {
3611         kfree(eb->buf);
3612 }
3613
3614 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3615 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3616                               u32 engine_mask,
3617                               const char *error_msg);
3618
3619 static inline struct i915_gpu_state *
3620 i915_gpu_state_get(struct i915_gpu_state *gpu)
3621 {
3622         kref_get(&gpu->ref);
3623         return gpu;
3624 }
3625
3626 void __i915_gpu_state_free(struct kref *kref);
3627 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3628 {
3629         if (gpu)
3630                 kref_put(&gpu->ref, __i915_gpu_state_free);
3631 }
3632
3633 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3634 void i915_reset_error_state(struct drm_i915_private *i915);
3635
3636 #else
3637
3638 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3639                                             u32 engine_mask,
3640                                             const char *error_msg)
3641 {
3642 }
3643
3644 static inline struct i915_gpu_state *
3645 i915_first_error_state(struct drm_i915_private *i915)
3646 {
3647         return NULL;
3648 }
3649
3650 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3651 {
3652 }
3653
3654 #endif
3655
3656 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3657
3658 /* i915_cmd_parser.c */
3659 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3660 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3661 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3662 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3663                             struct drm_i915_gem_object *batch_obj,
3664                             struct drm_i915_gem_object *shadow_batch_obj,
3665                             u32 batch_start_offset,
3666                             u32 batch_len,
3667                             bool is_master);
3668
3669 /* i915_perf.c */
3670 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3671 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3672 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3673 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3674
3675 /* i915_suspend.c */
3676 extern int i915_save_state(struct drm_i915_private *dev_priv);
3677 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3678
3679 /* i915_sysfs.c */
3680 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3681 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3682
3683 /* intel_i2c.c */
3684 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3685 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3686 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3687                                      unsigned int pin);
3688
3689 extern struct i2c_adapter *
3690 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3691 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3692 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3693 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3694 {
3695         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3696 }
3697 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3698
3699 /* intel_bios.c */
3700 int intel_bios_init(struct drm_i915_private *dev_priv);
3701 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3702 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3703 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3704 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3705 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3706 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3707 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3708 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3709                                      enum port port);
3710 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3711                                 enum port port);
3712
3713
3714 /* intel_opregion.c */
3715 #ifdef CONFIG_ACPI
3716 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3717 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3718 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3719 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3720 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3721                                          bool enable);
3722 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3723                                          pci_power_t state);
3724 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3725 #else
3726 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3727 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3728 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3729 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3730 {
3731 }
3732 static inline int
3733 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3734 {
3735         return 0;
3736 }
3737 static inline int
3738 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3739 {
3740         return 0;
3741 }
3742 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3743 {
3744         return -ENODEV;
3745 }
3746 #endif
3747
3748 /* intel_acpi.c */
3749 #ifdef CONFIG_ACPI
3750 extern void intel_register_dsm_handler(void);
3751 extern void intel_unregister_dsm_handler(void);
3752 #else
3753 static inline void intel_register_dsm_handler(void) { return; }
3754 static inline void intel_unregister_dsm_handler(void) { return; }
3755 #endif /* CONFIG_ACPI */
3756
3757 /* intel_device_info.c */
3758 static inline struct intel_device_info *
3759 mkwrite_device_info(struct drm_i915_private *dev_priv)
3760 {
3761         return (struct intel_device_info *)&dev_priv->info;
3762 }
3763
3764 const char *intel_platform_name(enum intel_platform platform);
3765 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3766 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3767
3768 /* modesetting */
3769 extern void intel_modeset_init_hw(struct drm_device *dev);
3770 extern int intel_modeset_init(struct drm_device *dev);
3771 extern void intel_modeset_gem_init(struct drm_device *dev);
3772 extern void intel_modeset_cleanup(struct drm_device *dev);
3773 extern int intel_connector_register(struct drm_connector *);
3774 extern void intel_connector_unregister(struct drm_connector *);
3775 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3776                                        bool state);
3777 extern void intel_display_resume(struct drm_device *dev);
3778 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3779 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3780 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3781 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3782 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3783 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3784                                   bool enable);
3785
3786 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3787                         struct drm_file *file);
3788
3789 /* overlay */
3790 extern struct intel_overlay_error_state *
3791 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3792 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3793                                             struct intel_overlay_error_state *error);
3794
3795 extern struct intel_display_error_state *
3796 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3797 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3798                                             struct intel_display_error_state *error);
3799
3800 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3801 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3802 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3803                       u32 reply_mask, u32 reply, int timeout_base_ms);
3804
3805 /* intel_sideband.c */
3806 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3807 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3808 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3809 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3810 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3811 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3812 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3813 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3814 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3815 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3816 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3817 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3818 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3819 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3820                    enum intel_sbi_destination destination);
3821 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3822                      enum intel_sbi_destination destination);
3823 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3824 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3825
3826 /* intel_dpio_phy.c */
3827 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3828                              enum dpio_phy *phy, enum dpio_channel *ch);
3829 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3830                                   enum port port, u32 margin, u32 scale,
3831                                   u32 enable, u32 deemphasis);
3832 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3833 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3834 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3835                             enum dpio_phy phy);
3836 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3837                               enum dpio_phy phy);
3838 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3839                                              uint8_t lane_count);
3840 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3841                                      uint8_t lane_lat_optim_mask);
3842 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3843
3844 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3845                               u32 deemph_reg_value, u32 margin_reg_value,
3846                               bool uniq_trans_scale);
3847 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3848                               bool reset);
3849 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3850 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3851 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3852 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3853
3854 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3855                               u32 demph_reg_value, u32 preemph_reg_value,
3856                               u32 uniqtranscale_reg_value, u32 tx3_demph);
3857 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3858 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3859 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3860
3861 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3862 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3863
3864 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3865 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3866
3867 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3868 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3869 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3870 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3871
3872 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3873 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3874 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3875 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3876
3877 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3878  * will be implemented using 2 32-bit writes in an arbitrary order with
3879  * an arbitrary delay between them. This can cause the hardware to
3880  * act upon the intermediate value, possibly leading to corruption and
3881  * machine death. For this reason we do not support I915_WRITE64, or
3882  * dev_priv->uncore.funcs.mmio_writeq.
3883  *
3884  * When reading a 64-bit value as two 32-bit values, the delay may cause
3885  * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3886  * occasionally a 64-bit register does not actualy support a full readq
3887  * and must be read using two 32-bit reads.
3888  *
3889  * You have been warned.
3890  */
3891 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3892
3893 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3894         u32 upper, lower, old_upper, loop = 0;                          \
3895         upper = I915_READ(upper_reg);                                   \
3896         do {                                                            \
3897                 old_upper = upper;                                      \
3898                 lower = I915_READ(lower_reg);                           \
3899                 upper = I915_READ(upper_reg);                           \
3900         } while (upper != old_upper && loop++ < 2);                     \
3901         (u64)upper << 32 | lower; })
3902
3903 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3904 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3905
3906 #define __raw_read(x, s) \
3907 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3908                                              i915_reg_t reg) \
3909 { \
3910         return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3911 }
3912
3913 #define __raw_write(x, s) \
3914 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3915                                        i915_reg_t reg, uint##x##_t val) \
3916 { \
3917         write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3918 }
3919 __raw_read(8, b)
3920 __raw_read(16, w)
3921 __raw_read(32, l)
3922 __raw_read(64, q)
3923
3924 __raw_write(8, b)
3925 __raw_write(16, w)
3926 __raw_write(32, l)
3927 __raw_write(64, q)
3928
3929 #undef __raw_read
3930 #undef __raw_write
3931
3932 /* These are untraced mmio-accessors that are only valid to be used inside
3933  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3934  * controlled.
3935  *
3936  * Think twice, and think again, before using these.
3937  *
3938  * As an example, these accessors can possibly be used between:
3939  *
3940  * spin_lock_irq(&dev_priv->uncore.lock);
3941  * intel_uncore_forcewake_get__locked();
3942  *
3943  * and
3944  *
3945  * intel_uncore_forcewake_put__locked();
3946  * spin_unlock_irq(&dev_priv->uncore.lock);
3947  *
3948  *
3949  * Note: some registers may not need forcewake held, so
3950  * intel_uncore_forcewake_{get,put} can be omitted, see
3951  * intel_uncore_forcewake_for_reg().
3952  *
3953  * Certain architectures will die if the same cacheline is concurrently accessed
3954  * by different clients (e.g. on Ivybridge). Access to registers should
3955  * therefore generally be serialised, by either the dev_priv->uncore.lock or
3956  * a more localised lock guarding all access to that bank of registers.
3957  */
3958 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3959 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3960 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3961 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3962
3963 /* "Broadcast RGB" property */
3964 #define INTEL_BROADCAST_RGB_AUTO 0
3965 #define INTEL_BROADCAST_RGB_FULL 1
3966 #define INTEL_BROADCAST_RGB_LIMITED 2
3967
3968 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3969 {
3970         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3971                 return VLV_VGACNTRL;
3972         else if (INTEL_GEN(dev_priv) >= 5)
3973                 return CPU_VGACNTRL;
3974         else
3975                 return VGACNTRL;
3976 }
3977
3978 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3979 {
3980         unsigned long j = msecs_to_jiffies(m);
3981
3982         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3983 }
3984
3985 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3986 {
3987         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3988 }
3989
3990 static inline unsigned long
3991 timespec_to_jiffies_timeout(const struct timespec *value)
3992 {
3993         unsigned long j = timespec_to_jiffies(value);
3994
3995         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3996 }
3997
3998 /*
3999  * If you need to wait X milliseconds between events A and B, but event B
4000  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4001  * when event A happened, then just before event B you call this function and
4002  * pass the timestamp as the first argument, and X as the second argument.
4003  */
4004 static inline void
4005 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4006 {
4007         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4008
4009         /*
4010          * Don't re-read the value of "jiffies" every time since it may change
4011          * behind our back and break the math.
4012          */
4013         tmp_jiffies = jiffies;
4014         target_jiffies = timestamp_jiffies +
4015                          msecs_to_jiffies_timeout(to_wait_ms);
4016
4017         if (time_after(target_jiffies, tmp_jiffies)) {
4018                 remaining_jiffies = target_jiffies - tmp_jiffies;
4019                 while (remaining_jiffies)
4020                         remaining_jiffies =
4021                             schedule_timeout_uninterruptible(remaining_jiffies);
4022         }
4023 }
4024
4025 static inline bool
4026 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4027 {
4028         struct intel_engine_cs *engine = req->engine;
4029         u32 seqno;
4030
4031         /* Note that the engine may have wrapped around the seqno, and
4032          * so our request->global_seqno will be ahead of the hardware,
4033          * even though it completed the request before wrapping. We catch
4034          * this by kicking all the waiters before resetting the seqno
4035          * in hardware, and also signal the fence.
4036          */
4037         if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4038                 return true;
4039
4040         /* The request was dequeued before we were awoken. We check after
4041          * inspecting the hw to confirm that this was the same request
4042          * that generated the HWS update. The memory barriers within
4043          * the request execution are sufficient to ensure that a check
4044          * after reading the value from hw matches this request.
4045          */
4046         seqno = i915_gem_request_global_seqno(req);
4047         if (!seqno)
4048                 return false;
4049
4050         /* Before we do the heavier coherent read of the seqno,
4051          * check the value (hopefully) in the CPU cacheline.
4052          */
4053         if (__i915_gem_request_completed(req, seqno))
4054                 return true;
4055
4056         /* Ensure our read of the seqno is coherent so that we
4057          * do not "miss an interrupt" (i.e. if this is the last
4058          * request and the seqno write from the GPU is not visible
4059          * by the time the interrupt fires, we will see that the
4060          * request is incomplete and go back to sleep awaiting
4061          * another interrupt that will never come.)
4062          *
4063          * Strictly, we only need to do this once after an interrupt,
4064          * but it is easier and safer to do it every time the waiter
4065          * is woken.
4066          */
4067         if (engine->irq_seqno_barrier &&
4068             test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4069                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4070                 unsigned long flags;
4071
4072                 /* The ordering of irq_posted versus applying the barrier
4073                  * is crucial. The clearing of the current irq_posted must
4074                  * be visible before we perform the barrier operation,
4075                  * such that if a subsequent interrupt arrives, irq_posted
4076                  * is reasserted and our task rewoken (which causes us to
4077                  * do another __i915_request_irq_complete() immediately
4078                  * and reapply the barrier). Conversely, if the clear
4079                  * occurs after the barrier, then an interrupt that arrived
4080                  * whilst we waited on the barrier would not trigger a
4081                  * barrier on the next pass, and the read may not see the
4082                  * seqno update.
4083                  */
4084                 engine->irq_seqno_barrier(engine);
4085
4086                 /* If we consume the irq, but we are no longer the bottom-half,
4087                  * the real bottom-half may not have serialised their own
4088                  * seqno check with the irq-barrier (i.e. may have inspected
4089                  * the seqno before we believe it coherent since they see
4090                  * irq_posted == false but we are still running).
4091                  */
4092                 spin_lock_irqsave(&b->lock, flags);
4093                 if (b->first_wait && b->first_wait->tsk != current)
4094                         /* Note that if the bottom-half is changed as we
4095                          * are sending the wake-up, the new bottom-half will
4096                          * be woken by whomever made the change. We only have
4097                          * to worry about when we steal the irq-posted for
4098                          * ourself.
4099                          */
4100                         wake_up_process(b->first_wait->tsk);
4101                 spin_unlock_irqrestore(&b->lock, flags);
4102
4103                 if (__i915_gem_request_completed(req, seqno))
4104                         return true;
4105         }
4106
4107         return false;
4108 }
4109
4110 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4111 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4112
4113 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4114  * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4115  * perform the operation. To check beforehand, pass in the parameters to
4116  * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4117  * you only need to pass in the minor offsets, page-aligned pointers are
4118  * always valid.
4119  *
4120  * For just checking for SSE4.1, in the foreknowledge that the future use
4121  * will be correctly aligned, just use i915_has_memcpy_from_wc().
4122  */
4123 #define i915_can_memcpy_from_wc(dst, src, len) \
4124         i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4125
4126 #define i915_has_memcpy_from_wc() \
4127         i915_memcpy_from_wc(NULL, NULL, 0)
4128
4129 /* i915_mm.c */
4130 int remap_io_mapping(struct vm_area_struct *vma,
4131                      unsigned long addr, unsigned long pfn, unsigned long size,
4132                      struct io_mapping *iomap);
4133
4134 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4135 {
4136         return (obj->cache_level != I915_CACHE_NONE ||
4137                 HAS_LLC(to_i915(obj->base.dev)));
4138 }
4139
4140 #endif