drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <asm/hypervisor.h>
  37
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <linux/backlight.h>
  42 #include <linux/hash.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/mm_types.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/pm_qos.h>
  48 #include <linux/dma-resv.h>
  49 #include <linux/shmem_fs.h>
  50 #include <linux/stackdepot.h>
  51 #include <linux/xarray.h>
  52
  53 #include <drm/intel-gtt.h>
  54 #include <drm/drm_gem.h>
  55 #include <drm/drm_auth.h>
  56 #include <drm/drm_cache.h>
  57 #include <drm/drm_util.h>
  58 #include <drm/drm_dsc.h>
  59 #include <drm/drm_atomic.h>
  60 #include <drm/drm_connector.h>
  61 #include <drm/i915_mei_hdcp_interface.h>
  62 #include <drm/ttm/ttm_device.h>
  63
  64 #include "i915_params.h"
  65 #include "i915_reg.h"
  66 #include "i915_utils.h"
  67
  68 #include "display/intel_bios.h"
  69 #include "display/intel_display.h"
  70 #include "display/intel_display_power.h"
  71 #include "display/intel_dmc.h"
  72 #include "display/intel_dpll_mgr.h"
  73 #include "display/intel_dsb.h"
  74 #include "display/intel_frontbuffer.h"
  75 #include "display/intel_global_state.h"
  76 #include "display/intel_gmbus.h"
  77 #include "display/intel_opregion.h"
  78
  79 #include "gem/i915_gem_context_types.h"
  80 #include "gem/i915_gem_shrinker.h"
  81 #include "gem/i915_gem_stolen.h"
  82 #include "gem/i915_gem_lmem.h"
  83
  84 #include "gt/intel_engine.h"
  85 #include "gt/intel_gt_types.h"
  86 #include "gt/intel_region_lmem.h"
  87 #include "gt/intel_workarounds.h"
  88 #include "gt/uc/intel_uc.h"
  89
  90 #include "intel_device_info.h"
  91 #include "intel_memory_region.h"
  92 #include "intel_pch.h"
  93 #include "intel_runtime_pm.h"
  94 #include "intel_step.h"
  95 #include "intel_uncore.h"
  96 #include "intel_wakeref.h"
  97 #include "intel_wopcm.h"
  98
  99 #include "i915_gem.h"
 100 #include "i915_gem_gtt.h"
 101 #include "i915_gpu_error.h"
 102 #include "i915_perf_types.h"
 103 #include "i915_request.h"
 104 #include "i915_scheduler.h"
 105 #include "gt/intel_timeline.h"
 106 #include "i915_vma.h"
 107 #include "i915_irq.h"
 108
 109
 110 /* General customization:
 111  */
 112
 113 #define DRIVER_NAME             "i915"
 114 #define DRIVER_DESC             "Intel Graphics"
 115 #define DRIVER_DATE             "20201103"
 116 #define DRIVER_TIMESTAMP        1604406085
 117
 118 struct drm_i915_gem_object;
 119
 120 enum hpd_pin {
 121         HPD_NONE = 0,
 122         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 123         HPD_CRT,
 124         HPD_SDVO_B,
 125         HPD_SDVO_C,
 126         HPD_PORT_A,
 127         HPD_PORT_B,
 128         HPD_PORT_C,
 129         HPD_PORT_D,
 130         HPD_PORT_E,
 131         HPD_PORT_TC1,
 132         HPD_PORT_TC2,
 133         HPD_PORT_TC3,
 134         HPD_PORT_TC4,
 135         HPD_PORT_TC5,
 136         HPD_PORT_TC6,
 137
 138         HPD_NUM_PINS
 139 };
 140
 141 #define for_each_hpd_pin(__pin) \
 142         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 143
 144 /* Threshold == 5 for long IRQs, 50 for short */
 145 #define HPD_STORM_DEFAULT_THRESHOLD 50
 146
 147 struct i915_hotplug {
 148         struct delayed_work hotplug_work;
 149
 150         const u32 *hpd, *pch_hpd;
 151
 152         struct {
 153                 unsigned long last_jiffies;
 154                 int count;
 155                 enum {
 156                         HPD_ENABLED = 0,
 157                         HPD_DISABLED = 1,
 158                         HPD_MARK_DISABLED = 2
 159                 } state;
 160         } stats[HPD_NUM_PINS];
 161         u32 event_bits;
 162         u32 retry_bits;
 163         struct delayed_work reenable_work;
 164
 165         u32 long_port_mask;
 166         u32 short_port_mask;
 167         struct work_struct dig_port_work;
 168
 169         struct work_struct poll_init_work;
 170         bool poll_enabled;
 171
 172         unsigned int hpd_storm_threshold;
 173         /* Whether or not to count short HPD IRQs in HPD storms */
 174         u8 hpd_short_storm_enabled;
 175
 176         /*
 177          * if we get a HPD irq from DP and a HPD irq from non-DP
 178          * the non-DP HPD could block the workqueue on a mode config
 179          * mutex getting, that userspace may have taken. However
 180          * userspace is waiting on the DP workqueue to run which is
 181          * blocked behind the non-DP one.
 182          */
 183         struct workqueue_struct *dp_wq;
 184 };
 185
 186 #define I915_GEM_GPU_DOMAINS \
 187         (I915_GEM_DOMAIN_RENDER | \
 188          I915_GEM_DOMAIN_SAMPLER | \
 189          I915_GEM_DOMAIN_COMMAND | \
 190          I915_GEM_DOMAIN_INSTRUCTION | \
 191          I915_GEM_DOMAIN_VERTEX)
 192
 193 struct drm_i915_private;
 194 struct i915_mm_struct;
 195 struct i915_mmu_object;
 196
 197 struct drm_i915_file_private {
 198         struct drm_i915_private *dev_priv;
 199
 200         union {
 201                 struct drm_file *file;
 202                 struct rcu_head rcu;
 203         };
 204
 205         /** @proto_context_lock: Guards all struct i915_gem_proto_context
 206          * operations
 207          *
 208          * This not only guards @proto_context_xa, but is always held
 209          * whenever we manipulate any struct i915_gem_proto_context,
 210          * including finalizing it on first actual use of the GEM context.
 211          *
 212          * See i915_gem_proto_context.
 213          */
 214         struct mutex proto_context_lock;
 215
 216         /** @proto_context_xa: xarray of struct i915_gem_proto_context
 217          *
 218          * Historically, the context uAPI allowed for two methods of
 219          * setting context parameters: SET_CONTEXT_PARAM and
 220          * CONTEXT_CREATE_EXT_SETPARAM.  The former is allowed to be called
 221          * at any time while the later happens as part of
 222          * GEM_CONTEXT_CREATE.  Everything settable via one was settable
 223          * via the other.  While some params are fairly simple and setting
 224          * them on a live context is harmless such as the context priority,
 225          * others are far trickier such as the VM or the set of engines.
 226          * In order to swap out the VM, for instance, we have to delay
 227          * until all current in-flight work is complete, swap in the new
 228          * VM, and then continue.  This leads to a plethora of potential
 229          * race conditions we'd really rather avoid.
 230          *
 231          * We have since disallowed setting these more complex parameters
 232          * on active contexts.  This works by delaying the creation of the
 233          * actual context until after the client is done configuring it
 234          * with SET_CONTEXT_PARAM.  From the perspective of the client, it
 235          * has the same u32 context ID the whole time.  From the
 236          * perspective of i915, however, it's a struct i915_gem_proto_context
 237          * right up until the point where we attempt to do something which
 238          * the proto-context can't handle.  Then the struct i915_gem_context
 239          * gets created.
 240          *
 241          * This is accomplished via a little xarray dance.  When
 242          * GEM_CONTEXT_CREATE is called, we create a struct
 243          * i915_gem_proto_context, reserve a slot in @context_xa but leave
 244          * it NULL, and place the proto-context in the corresponding slot
 245          * in @proto_context_xa.  Then, in i915_gem_context_lookup(), we
 246          * first check @context_xa.  If it's there, we return the struct
 247          * i915_gem_context and we're done.  If it's not, we look in
 248          * @proto_context_xa and, if we find it there, we create the actual
 249          * context and kill the proto-context.
 250          *
 251          * In order for this dance to work properly, everything which ever
 252          * touches a struct i915_gem_proto_context is guarded by
 253          * @proto_context_lock, including context creation.  Yes, this
 254          * means context creation now takes a giant global lock but it
 255          * can't really be helped and that should never be on any driver's
 256          * fast-path anyway.
 257          */
 258         struct xarray proto_context_xa;
 259
 260         /** @context_xa: xarray of fully created i915_gem_context
 261          *
 262          * Write access to this xarray is guarded by @proto_context_lock.
 263          * Otherwise, writers may race with finalize_create_context_locked().
 264          *
 265          * See @proto_context_xa.
 266          */
 267         struct xarray context_xa;
 268         struct xarray vm_xa;
 269
 270         unsigned int bsd_engine;
 271
 272 /*
 273  * Every context ban increments per client ban score. Also
 274  * hangs in short succession increments ban score. If ban threshold
 275  * is reached, client is considered banned and submitting more work
 276  * will fail. This is a stop gap measure to limit the badly behaving
 277  * clients access to gpu. Note that unbannable contexts never increment
 278  * the client ban score.
 279  */
 280 #define I915_CLIENT_SCORE_HANG_FAST     1
 281 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 282 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 283 #define I915_CLIENT_SCORE_BANNED        9
 284         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 285         atomic_t ban_score;
 286         unsigned long hang_timestamp;
 287 };
 288
 289 /* Interface history:
 290  *
 291  * 1.1: Original.
 292  * 1.2: Add Power Management
 293  * 1.3: Add vblank support
 294  * 1.4: Fix cmdbuffer path, add heap destroy
 295  * 1.5: Add vblank pipe configuration
 296  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 297  *      - Support vertical blank on secondary display pipe
 298  */
 299 #define DRIVER_MAJOR            1
 300 #define DRIVER_MINOR            6
 301 #define DRIVER_PATCHLEVEL       0
 302
 303 struct intel_overlay;
 304 struct intel_overlay_error_state;
 305
 306 struct sdvo_device_mapping {
 307         u8 initialized;
 308         u8 dvo_port;
 309         u8 slave_addr;
 310         u8 dvo_wiring;
 311         u8 i2c_pin;
 312         u8 ddc_pin;
 313 };
 314
 315 struct intel_connector;
 316 struct intel_encoder;
 317 struct intel_atomic_state;
 318 struct intel_cdclk_config;
 319 struct intel_cdclk_state;
 320 struct intel_cdclk_vals;
 321 struct intel_initial_plane_config;
 322 struct intel_crtc;
 323 struct intel_limit;
 324 struct dpll;
 325
 326 struct drm_i915_display_funcs {
 327         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 328                           struct intel_cdclk_config *cdclk_config);
 329         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 330                           const struct intel_cdclk_config *cdclk_config,
 331                           enum pipe pipe);
 332         int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 333         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 334                              enum i9xx_plane_id i9xx_plane);
 335         int (*compute_pipe_wm)(struct intel_atomic_state *state,
 336                                struct intel_crtc *crtc);
 337         int (*compute_intermediate_wm)(struct intel_atomic_state *state,
 338                                        struct intel_crtc *crtc);
 339         void (*initial_watermarks)(struct intel_atomic_state *state,
 340                                    struct intel_crtc *crtc);
 341         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 342                                          struct intel_crtc *crtc);
 343         void (*optimize_watermarks)(struct intel_atomic_state *state,
 344                                     struct intel_crtc *crtc);
 345         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 346         void (*update_wm)(struct intel_crtc *crtc);
 347         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 348         u8 (*calc_voltage_level)(int cdclk);
 349         /* Returns the active state of the crtc, and if the crtc is active,
 350          * fills out the pipe-config with the hw state. */
 351         bool (*get_pipe_config)(struct intel_crtc *,
 352                                 struct intel_crtc_state *);
 353         void (*get_initial_plane_config)(struct intel_crtc *,
 354                                          struct intel_initial_plane_config *);
 355         int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
 356         void (*crtc_enable)(struct intel_atomic_state *state,
 357                             struct intel_crtc *crtc);
 358         void (*crtc_disable)(struct intel_atomic_state *state,
 359                              struct intel_crtc *crtc);
 360         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 361         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 362         void (*audio_codec_enable)(struct intel_encoder *encoder,
 363                                    const struct intel_crtc_state *crtc_state,
 364                                    const struct drm_connector_state *conn_state);
 365         void (*audio_codec_disable)(struct intel_encoder *encoder,
 366                                     const struct intel_crtc_state *old_crtc_state,
 367                                     const struct drm_connector_state *old_conn_state);
 368         void (*fdi_link_train)(struct intel_crtc *crtc,
 369                                const struct intel_crtc_state *crtc_state);
 370         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 371         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 372         /* clock updates for mode set */
 373         /* cursor updates */
 374         /* render clock increase/decrease */
 375         /* display clock increase/decrease */
 376         /* pll clock increase/decrease */
 377
 378         int (*color_check)(struct intel_crtc_state *crtc_state);
 379         /*
 380          * Program double buffered color management registers during
 381          * vblank evasion. The registers should then latch during the
 382          * next vblank start, alongside any other double buffered registers
 383          * involved with the same commit.
 384          */
 385         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 386         /*
 387          * Load LUTs (and other single buffered color management
 388          * registers). Will (hopefully) be called during the vblank
 389          * following the latching of any double buffered registers
 390          * involved with the same commit.
 391          */
 392         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 393         void (*read_luts)(struct intel_crtc_state *crtc_state);
 394 };
 395
 396
 397 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 398
 399 struct intel_fbc {
 400         /* This is always the inner lock when overlapping with struct_mutex and
 401          * it's the outer lock when overlapping with stolen_lock. */
 402         struct mutex lock;
 403         unsigned int possible_framebuffer_bits;
 404         unsigned int busy_bits;
 405         struct intel_crtc *crtc;
 406
 407         struct drm_mm_node compressed_fb;
 408         struct drm_mm_node compressed_llb;
 409
 410         u8 limit;
 411
 412         bool false_color;
 413
 414         bool active;
 415         bool activated;
 416         bool flip_pending;
 417
 418         bool underrun_detected;
 419         struct work_struct underrun_work;
 420
 421         /*
 422          * Due to the atomic rules we can't access some structures without the
 423          * appropriate locking, so we cache information here in order to avoid
 424          * these problems.
 425          */
 426         struct intel_fbc_state_cache {
 427                 struct {
 428                         unsigned int mode_flags;
 429                         u32 hsw_bdw_pixel_rate;
 430                 } crtc;
 431
 432                 struct {
 433                         unsigned int rotation;
 434                         int src_w;
 435                         int src_h;
 436                         bool visible;
 437                         /*
 438                          * Display surface base address adjustement for
 439                          * pageflips. Note that on gen4+ this only adjusts up
 440                          * to a tile, offsets within a tile are handled in
 441                          * the hw itself (with the TILEOFF register).
 442                          */
 443                         int adjusted_x;
 444                         int adjusted_y;
 445
 446                         u16 pixel_blend_mode;
 447                 } plane;
 448
 449                 struct {
 450                         const struct drm_format_info *format;
 451                         unsigned int stride;
 452                         u64 modifier;
 453                 } fb;
 454
 455                 unsigned int fence_y_offset;
 456                 u16 override_cfb_stride;
 457                 u16 interval;
 458                 s8 fence_id;
 459                 bool psr2_active;
 460         } state_cache;
 461
 462         /*
 463          * This structure contains everything that's relevant to program the
 464          * hardware registers. When we want to figure out if we need to disable
 465          * and re-enable FBC for a new configuration we just check if there's
 466          * something different in the struct. The genx_fbc_activate functions
 467          * are supposed to read from it in order to program the registers.
 468          */
 469         struct intel_fbc_reg_params {
 470                 struct {
 471                         enum pipe pipe;
 472                         enum i9xx_plane_id i9xx_plane;
 473                 } crtc;
 474
 475                 struct {
 476                         const struct drm_format_info *format;
 477                         unsigned int stride;
 478                         u64 modifier;
 479                 } fb;
 480
 481                 int cfb_size;
 482                 unsigned int fence_y_offset;
 483                 u16 override_cfb_stride;
 484                 u16 interval;
 485                 s8 fence_id;
 486                 bool plane_visible;
 487         } params;
 488
 489         const char *no_fbc_reason;
 490 };
 491
 492 /*
 493  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 494  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 495  * parsing for same resolution.
 496  */
 497 enum drrs_refresh_rate_type {
 498         DRRS_HIGH_RR,
 499         DRRS_LOW_RR,
 500         DRRS_MAX_RR, /* RR count */
 501 };
 502
 503 enum drrs_support_type {
 504         DRRS_NOT_SUPPORTED = 0,
 505         STATIC_DRRS_SUPPORT = 1,
 506         SEAMLESS_DRRS_SUPPORT = 2
 507 };
 508
 509 struct intel_dp;
 510 struct i915_drrs {
 511         struct mutex mutex;
 512         struct delayed_work work;
 513         struct intel_dp *dp;
 514         unsigned busy_frontbuffer_bits;
 515         enum drrs_refresh_rate_type refresh_rate_type;
 516         enum drrs_support_type type;
 517 };
 518
 519 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 520 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 521 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 522 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 523 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 524 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 525 #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
 526
 527 struct intel_fbdev;
 528 struct intel_fbc_work;
 529
 530 struct intel_gmbus {
 531         struct i2c_adapter adapter;
 532 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 533         u32 force_bit;
 534         u32 reg0;
 535         i915_reg_t gpio_reg;
 536         struct i2c_algo_bit_data bit_algo;
 537         struct drm_i915_private *dev_priv;
 538 };
 539
 540 struct i915_suspend_saved_registers {
 541         u32 saveDSPARB;
 542         u32 saveSWF0[16];
 543         u32 saveSWF1[16];
 544         u32 saveSWF3[3];
 545         u16 saveGCDGMBUS;
 546 };
 547
 548 struct vlv_s0ix_state;
 549
 550 #define MAX_L3_SLICES 2
 551 struct intel_l3_parity {
 552         u32 *remap_info[MAX_L3_SLICES];
 553         struct work_struct error_work;
 554         int which_slice;
 555 };
 556
 557 struct i915_gem_mm {
 558         /*
 559          * Shortcut for the stolen region. This points to either
 560          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 561          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 562          * support stolen.
 563          */
 564         struct intel_memory_region *stolen_region;
 565         /** Memory allocator for GTT stolen memory */
 566         struct drm_mm stolen;
 567         /** Protects the usage of the GTT stolen memory allocator. This is
 568          * always the inner lock when overlapping with struct_mutex. */
 569         struct mutex stolen_lock;
 570
 571         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 572         spinlock_t obj_lock;
 573
 574         /**
 575          * List of objects which are purgeable.
 576          */
 577         struct list_head purge_list;
 578
 579         /**
 580          * List of objects which have allocated pages and are shrinkable.
 581          */
 582         struct list_head shrink_list;
 583
 584         /**
 585          * List of objects which are pending destruction.
 586          */
 587         struct llist_head free_list;
 588         struct work_struct free_work;
 589         /**
 590          * Count of objects pending destructions. Used to skip needlessly
 591          * waiting on an RCU barrier if no objects are waiting to be freed.
 592          */
 593         atomic_t free_count;
 594
 595         /**
 596          * tmpfs instance used for shmem backed objects
 597          */
 598         struct vfsmount *gemfs;
 599
 600         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 601
 602         struct notifier_block oom_notifier;
 603         struct notifier_block vmap_notifier;
 604         struct shrinker shrinker;
 605
 606 #ifdef CONFIG_MMU_NOTIFIER
 607         /**
 608          * notifier_lock for mmu notifiers, memory may not be allocated
 609          * while holding this lock.
 610          */
 611         rwlock_t notifier_lock;
 612 #endif
 613
 614         /* shrinker accounting, also useful for userland debugging */
 615         u64 shrink_memory;
 616         u32 shrink_count;
 617 };
 618
 619 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 620
 621 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 622                                          u64 context);
 623
 624 static inline unsigned long
 625 i915_fence_timeout(const struct drm_i915_private *i915)
 626 {
 627         return i915_fence_context_timeout(i915, U64_MAX);
 628 }
 629
 630 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 631 #define I915_NUM_QGV_POINTS 8
 632
 633 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 634
 635 /* Amount of PSF GV points, BSpec precisely defines this */
 636 #define I915_NUM_PSF_GV_POINTS 3
 637
 638 enum psr_lines_to_wait {
 639         PSR_0_LINES_TO_WAIT = 0,
 640         PSR_1_LINE_TO_WAIT,
 641         PSR_4_LINES_TO_WAIT,
 642         PSR_8_LINES_TO_WAIT
 643 };
 644
 645 struct intel_vbt_data {
 646         /* bdb version */
 647         u16 version;
 648
 649         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 650         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 651
 652         /* Feature bits */
 653         unsigned int int_tv_support:1;
 654         unsigned int lvds_dither:1;
 655         unsigned int int_crt_support:1;
 656         unsigned int lvds_use_ssc:1;
 657         unsigned int int_lvds_support:1;
 658         unsigned int display_clock_mode:1;
 659         unsigned int fdi_rx_polarity_inverted:1;
 660         unsigned int panel_type:4;
 661         int lvds_ssc_freq;
 662         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 663         enum drm_panel_orientation orientation;
 664
 665         enum drrs_support_type drrs_type;
 666
 667         struct {
 668                 int rate;
 669                 int lanes;
 670                 int preemphasis;
 671                 int vswing;
 672                 bool low_vswing;
 673                 bool initialized;
 674                 int bpp;
 675                 struct edp_power_seq pps;
 676                 bool hobl;
 677         } edp;
 678
 679         struct {
 680                 bool enable;
 681                 bool full_link;
 682                 bool require_aux_wakeup;
 683                 int idle_frames;
 684                 enum psr_lines_to_wait lines_to_wait;
 685                 int tp1_wakeup_time_us;
 686                 int tp2_tp3_wakeup_time_us;
 687                 int psr2_tp2_tp3_wakeup_time_us;
 688         } psr;
 689
 690         struct {
 691                 u16 pwm_freq_hz;
 692                 u16 brightness_precision_bits;
 693                 bool present;
 694                 bool active_low_pwm;
 695                 u8 min_brightness;      /* min_brightness/255 of max */
 696                 u8 controller;          /* brightness controller number */
 697                 enum intel_backlight_type type;
 698         } backlight;
 699
 700         /* MIPI DSI */
 701         struct {
 702                 u16 panel_id;
 703                 struct mipi_config *config;
 704                 struct mipi_pps_data *pps;
 705                 u16 bl_ports;
 706                 u16 cabc_ports;
 707                 u8 seq_version;
 708                 u32 size;
 709                 u8 *data;
 710                 const u8 *sequence[MIPI_SEQ_MAX];
 711                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 712                 enum drm_panel_orientation orientation;
 713         } dsi;
 714
 715         int crt_ddc_pin;
 716
 717         struct list_head display_devices;
 718
 719         struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
 720         struct sdvo_device_mapping sdvo_mappings[2];
 721 };
 722
 723 enum intel_ddb_partitioning {
 724         INTEL_DDB_PART_1_2,
 725         INTEL_DDB_PART_5_6, /* IVB+ */
 726 };
 727
 728 struct ilk_wm_values {
 729         u32 wm_pipe[3];
 730         u32 wm_lp[3];
 731         u32 wm_lp_spr[3];
 732         bool enable_fbc_wm;
 733         enum intel_ddb_partitioning partitioning;
 734 };
 735
 736 struct g4x_pipe_wm {
 737         u16 plane[I915_MAX_PLANES];
 738         u16 fbc;
 739 };
 740
 741 struct g4x_sr_wm {
 742         u16 plane;
 743         u16 cursor;
 744         u16 fbc;
 745 };
 746
 747 struct vlv_wm_ddl_values {
 748         u8 plane[I915_MAX_PLANES];
 749 };
 750
 751 struct vlv_wm_values {
 752         struct g4x_pipe_wm pipe[3];
 753         struct g4x_sr_wm sr;
 754         struct vlv_wm_ddl_values ddl[3];
 755         u8 level;
 756         bool cxsr;
 757 };
 758
 759 struct g4x_wm_values {
 760         struct g4x_pipe_wm pipe[2];
 761         struct g4x_sr_wm sr;
 762         struct g4x_sr_wm hpll;
 763         bool cxsr;
 764         bool hpll_en;
 765         bool fbc_en;
 766 };
 767
 768 struct skl_ddb_entry {
 769         u16 start, end; /* in number of blocks, 'end' is exclusive */
 770 };
 771
 772 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 773 {
 774         return entry->end - entry->start;
 775 }
 776
 777 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 778                                        const struct skl_ddb_entry *e2)
 779 {
 780         if (e1->start == e2->start && e1->end == e2->end)
 781                 return true;
 782
 783         return false;
 784 }
 785
 786 struct i915_frontbuffer_tracking {
 787         spinlock_t lock;
 788
 789         /*
 790          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 791          * scheduled flips.
 792          */
 793         unsigned busy_bits;
 794         unsigned flip_bits;
 795 };
 796
 797 struct i915_virtual_gpu {
 798         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 799         bool active;
 800         u32 caps;
 801 };
 802
 803 struct intel_cdclk_config {
 804         unsigned int cdclk, vco, ref, bypass;
 805         u8 voltage_level;
 806 };
 807
 808 struct i915_selftest_stash {
 809         atomic_t counter;
 810         struct ida mock_region_instances;
 811 };
 812
 813 struct drm_i915_private {
 814         struct drm_device drm;
 815
 816         /* FIXME: Device release actions should all be moved to drmm_ */
 817         bool do_release;
 818
 819         /* i915 device parameters */
 820         struct i915_params params;
 821
 822         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 823         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 824         struct intel_driver_caps caps;
 825
 826         /**
 827          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 828          * end of stolen which we can optionally use to create GEM objects
 829          * backed by stolen memory. Note that stolen_usable_size tells us
 830          * exactly how much of this we are actually allowed to use, given that
 831          * some portion of it is in fact reserved for use by hardware functions.
 832          */
 833         struct resource dsm;
 834         /**
 835          * Reseved portion of Data Stolen Memory
 836          */
 837         struct resource dsm_reserved;
 838
 839         /*
 840          * Stolen memory is segmented in hardware with different portions
 841          * offlimits to certain functions.
 842          *
 843          * The drm_mm is initialised to the total accessible range, as found
 844          * from the PCI config. On Broadwell+, this is further restricted to
 845          * avoid the first page! The upper end of stolen memory is reserved for
 846          * hardware functions and similarly removed from the accessible range.
 847          */
 848         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 849
 850         struct intel_uncore uncore;
 851         struct intel_uncore_mmio_debug mmio_debug;
 852
 853         struct i915_virtual_gpu vgpu;
 854
 855         struct intel_gvt *gvt;
 856
 857         struct intel_wopcm wopcm;
 858
 859         struct intel_dmc dmc;
 860
 861         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 862
 863         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 864          * controller on different i2c buses. */
 865         struct mutex gmbus_mutex;
 866
 867         /**
 868          * Base address of where the gmbus and gpio blocks are located (either
 869          * on PCH or on SoC for platforms without PCH).
 870          */
 871         u32 gpio_mmio_base;
 872
 873         /* MMIO base address for MIPI regs */
 874         u32 mipi_mmio_base;
 875
 876         u32 pps_mmio_base;
 877
 878         wait_queue_head_t gmbus_wait_queue;
 879
 880         struct pci_dev *bridge_dev;
 881
 882         struct rb_root uabi_engines;
 883
 884         struct resource mch_res;
 885
 886         /* protects the irq masks */
 887         spinlock_t irq_lock;
 888
 889         bool display_irqs_enabled;
 890
 891         /* Sideband mailbox protection */
 892         struct mutex sb_lock;
 893         struct pm_qos_request sb_qos;
 894
 895         /** Cached value of IMR to avoid reads in updating the bitfield */
 896         union {
 897                 u32 irq_mask;
 898                 u32 de_irq_mask[I915_MAX_PIPES];
 899         };
 900         u32 pipestat_irq_mask[I915_MAX_PIPES];
 901
 902         struct i915_hotplug hotplug;
 903         struct intel_fbc fbc;
 904         struct i915_drrs drrs;
 905         struct intel_opregion opregion;
 906         struct intel_vbt_data vbt;
 907
 908         bool preserve_bios_swizzle;
 909
 910         /* overlay */
 911         struct intel_overlay *overlay;
 912
 913         /* backlight registers and fields in struct intel_panel */
 914         struct mutex backlight_lock;
 915
 916         /* protects panel power sequencer state */
 917         struct mutex pps_mutex;
 918
 919         unsigned int fsb_freq, mem_freq, is_ddr3;
 920         unsigned int skl_preferred_vco_freq;
 921         unsigned int max_cdclk_freq;
 922
 923         unsigned int max_dotclk_freq;
 924         unsigned int hpll_freq;
 925         unsigned int fdi_pll_freq;
 926         unsigned int czclk_freq;
 927
 928         struct {
 929                 /* The current hardware cdclk configuration */
 930                 struct intel_cdclk_config hw;
 931
 932                 /* cdclk, divider, and ratio table from bspec */
 933                 const struct intel_cdclk_vals *table;
 934
 935                 struct intel_global_obj obj;
 936         } cdclk;
 937
 938         struct {
 939                 /* The current hardware dbuf configuration */
 940                 u8 enabled_slices;
 941
 942                 struct intel_global_obj obj;
 943         } dbuf;
 944
 945         /**
 946          * wq - Driver workqueue for GEM.
 947          *
 948          * NOTE: Work items scheduled here are not allowed to grab any modeset
 949          * locks, for otherwise the flushing done in the pageflip code will
 950          * result in deadlocks.
 951          */
 952         struct workqueue_struct *wq;
 953
 954         /* ordered wq for modesets */
 955         struct workqueue_struct *modeset_wq;
 956         /* unbound hipri wq for page flips/plane updates */
 957         struct workqueue_struct *flip_wq;
 958
 959         /* Display functions */
 960         struct drm_i915_display_funcs display;
 961
 962         /* PCH chipset type */
 963         enum intel_pch pch_type;
 964         unsigned short pch_id;
 965
 966         unsigned long quirks;
 967
 968         struct drm_atomic_state *modeset_restore_state;
 969         struct drm_modeset_acquire_ctx reset_ctx;
 970
 971         struct i915_ggtt ggtt; /* VM representing the global address space */
 972
 973         struct i915_gem_mm mm;
 974
 975         /* Kernel Modesetting */
 976
 977         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
 978         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 979
 980         /**
 981          * dpll and cdclk state is protected by connection_mutex
 982          * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 983          * Must be global rather than per dpll, because on some platforms plls
 984          * share registers.
 985          */
 986         struct {
 987                 struct mutex lock;
 988
 989                 int num_shared_dpll;
 990                 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 991                 const struct intel_dpll_mgr *mgr;
 992
 993                 struct {
 994                         int nssc;
 995                         int ssc;
 996                 } ref_clks;
 997         } dpll;
 998
 999         struct list_head global_obj_list;
1000
1001         struct i915_wa_list gt_wa_list;
1002
1003         struct i915_frontbuffer_tracking fb_tracking;
1004
1005         struct intel_atomic_helper {
1006                 struct llist_head free_list;
1007                 struct work_struct free_work;
1008         } atomic_helper;
1009
1010         bool mchbar_need_disable;
1011
1012         struct intel_l3_parity l3_parity;
1013
1014         /*
1015          * HTI (aka HDPORT) state read during initial hw readout.  Most
1016          * platforms don't have HTI, so this will just stay 0.  Those that do
1017          * will use this later to figure out which PLLs and PHYs are unavailable
1018          * for driver usage.
1019          */
1020         u32 hti_state;
1021
1022         /*
1023          * edram size in MB.
1024          * Cannot be determined by PCIID. You must always read a register.
1025          */
1026         u32 edram_size_mb;
1027
1028         struct i915_power_domains power_domains;
1029
1030         struct i915_gpu_error gpu_error;
1031
1032         struct drm_i915_gem_object *vlv_pctx;
1033
1034         /* list of fbdev register on this device */
1035         struct intel_fbdev *fbdev;
1036         struct work_struct fbdev_suspend_work;
1037
1038         struct drm_property *broadcast_rgb_property;
1039         struct drm_property *force_audio_property;
1040
1041         /* hda/i915 audio component */
1042         struct i915_audio_component *audio_component;
1043         bool audio_component_registered;
1044         /**
1045          * av_mutex - mutex for audio/video sync
1046          *
1047          */
1048         struct mutex av_mutex;
1049         int audio_power_refcount;
1050         u32 audio_freq_cntrl;
1051
1052         u32 fdi_rx_config;
1053
1054         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1055         u32 chv_phy_control;
1056         /*
1057          * Shadows for CHV DPLL_MD regs to keep the state
1058          * checker somewhat working in the presence hardware
1059          * crappiness (can't read out DPLL_MD for pipes B & C).
1060          */
1061         u32 chv_dpll_md[I915_MAX_PIPES];
1062         u32 bxt_phy_grc;
1063
1064         u32 suspend_count;
1065         bool power_domains_suspended;
1066         struct i915_suspend_saved_registers regfile;
1067         struct vlv_s0ix_state *vlv_s0ix_state;
1068
1069         enum {
1070                 I915_SAGV_UNKNOWN = 0,
1071                 I915_SAGV_DISABLED,
1072                 I915_SAGV_ENABLED,
1073                 I915_SAGV_NOT_CONTROLLED
1074         } sagv_status;
1075
1076         u32 sagv_block_time_us;
1077
1078         struct {
1079                 /*
1080                  * Raw watermark latency values:
1081                  * in 0.1us units for WM0,
1082                  * in 0.5us units for WM1+.
1083                  */
1084                 /* primary */
1085                 u16 pri_latency[5];
1086                 /* sprite */
1087                 u16 spr_latency[5];
1088                 /* cursor */
1089                 u16 cur_latency[5];
1090                 /*
1091                  * Raw watermark memory latency values
1092                  * for SKL for all 8 levels
1093                  * in 1us units.
1094                  */
1095                 u16 skl_latency[8];
1096
1097                 /* current hardware state */
1098                 union {
1099                         struct ilk_wm_values hw;
1100                         struct vlv_wm_values vlv;
1101                         struct g4x_wm_values g4x;
1102                 };
1103
1104                 u8 max_level;
1105
1106                 /*
1107                  * Should be held around atomic WM register writing; also
1108                  * protects * intel_crtc->wm.active and
1109                  * crtc_state->wm.need_postvbl_update.
1110                  */
1111                 struct mutex wm_mutex;
1112         } wm;
1113
1114         struct dram_info {
1115                 bool wm_lv_0_adjust_needed;
1116                 u8 num_channels;
1117                 bool symmetric_memory;
1118                 enum intel_dram_type {
1119                         INTEL_DRAM_UNKNOWN,
1120                         INTEL_DRAM_DDR3,
1121                         INTEL_DRAM_DDR4,
1122                         INTEL_DRAM_LPDDR3,
1123                         INTEL_DRAM_LPDDR4,
1124                         INTEL_DRAM_DDR5,
1125                         INTEL_DRAM_LPDDR5,
1126                 } type;
1127                 u8 num_qgv_points;
1128                 u8 num_psf_gv_points;
1129         } dram_info;
1130
1131         struct intel_bw_info {
1132                 /* for each QGV point */
1133                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1134                 /* for each PSF GV point */
1135                 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
1136                 u8 num_qgv_points;
1137                 u8 num_psf_gv_points;
1138                 u8 num_planes;
1139         } max_bw[6];
1140
1141         struct intel_global_obj bw_obj;
1142
1143         struct intel_runtime_pm runtime_pm;
1144
1145         struct i915_perf perf;
1146
1147         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1148         struct intel_gt gt;
1149
1150         struct {
1151                 struct i915_gem_contexts {
1152                         spinlock_t lock; /* locks list */
1153                         struct list_head list;
1154                 } contexts;
1155
1156                 /*
1157                  * We replace the local file with a global mappings as the
1158                  * backing storage for the mmap is on the device and not
1159                  * on the struct file, and we do not want to prolong the
1160                  * lifetime of the local fd. To minimise the number of
1161                  * anonymous inodes we create, we use a global singleton to
1162                  * share the global mapping.
1163                  */
1164                 struct file *mmap_singleton;
1165         } gem;
1166
1167         u8 framestart_delay;
1168
1169         /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
1170         u8 window2_delay;
1171
1172         u8 pch_ssc_use;
1173
1174         /* For i915gm/i945gm vblank irq workaround */
1175         u8 vblank_enabled;
1176
1177         bool irq_enabled;
1178
1179         /* perform PHY state sanity checks? */
1180         bool chv_phy_assert[2];
1181
1182         bool ipc_enabled;
1183
1184         /* Used to save the pipe-to-encoder mapping for audio */
1185         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1186
1187         /* necessary resource sharing with HDMI LPE audio driver. */
1188         struct {
1189                 struct platform_device *platdev;
1190                 int     irq;
1191         } lpe_audio;
1192
1193         struct i915_pmu pmu;
1194
1195         struct i915_hdcp_comp_master *hdcp_master;
1196         bool hdcp_comp_added;
1197
1198         /* Mutex to protect the above hdcp component related values. */
1199         struct mutex hdcp_comp_mutex;
1200
1201         /* The TTM device structure. */
1202         struct ttm_device bdev;
1203
1204         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1205
1206         /*
1207          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1208          * will be rejected. Instead look for a better place.
1209          */
1210 };
1211
1212 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1213 {
1214         return container_of(dev, struct drm_i915_private, drm);
1215 }
1216
1217 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1218 {
1219         return dev_get_drvdata(kdev);
1220 }
1221
1222 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1223 {
1224         return pci_get_drvdata(pdev);
1225 }
1226
1227 /* Simple iterator over all initialised engines */
1228 #define for_each_engine(engine__, dev_priv__, id__) \
1229         for ((id__) = 0; \
1230              (id__) < I915_NUM_ENGINES; \
1231              (id__)++) \
1232                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1233
1234 /* Iterator over subset of engines selected by mask */
1235 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1236         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1237              (tmp__) ? \
1238              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1239              0;)
1240
1241 #define rb_to_uabi_engine(rb) \
1242         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1243
1244 #define for_each_uabi_engine(engine__, i915__) \
1245         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1246              (engine__); \
1247              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1248
1249 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1250         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1251              (engine__) && (engine__)->uabi_class == (class__); \
1252              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1253
1254 #define I915_GTT_OFFSET_NONE ((u32)-1)
1255
1256 /*
1257  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1258  * considered to be the frontbuffer for the given plane interface-wise. This
1259  * doesn't mean that the hw necessarily already scans it out, but that any
1260  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1261  *
1262  * We have one bit per pipe and per scanout plane type.
1263  */
1264 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1265 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1266         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1267         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1268         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1269 })
1270 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1271         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1272 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1273         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1274                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1275
1276 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1277 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1278 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1279
1280 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1281
1282 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
1283
1284 #define GRAPHICS_VER(i915)              (INTEL_INFO(i915)->graphics_ver)
1285 #define GRAPHICS_VER_FULL(i915)         IP_VER(INTEL_INFO(i915)->graphics_ver, \
1286                                                INTEL_INFO(i915)->graphics_rel)
1287 #define IS_GRAPHICS_VER(i915, from, until) \
1288         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1289
1290 #define MEDIA_VER(i915)                 (INTEL_INFO(i915)->media_ver)
1291 #define MEDIA_VER_FULL(i915)            IP_VER(INTEL_INFO(i915)->media_ver, \
1292                                                INTEL_INFO(i915)->media_rel)
1293 #define IS_MEDIA_VER(i915, from, until) \
1294         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1295
1296 #define DISPLAY_VER(i915)       (INTEL_INFO(i915)->display.ver)
1297 #define IS_DISPLAY_VER(i915, from, until) \
1298         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1299
1300 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
1301
1302 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1303
1304 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1305 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1306
1307 #define IS_DISPLAY_STEP(__i915, since, until) \
1308         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1309          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
1310
1311 #define IS_GT_STEP(__i915, since, until) \
1312         (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1313          INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
1314
1315 static __always_inline unsigned int
1316 __platform_mask_index(const struct intel_runtime_info *info,
1317                       enum intel_platform p)
1318 {
1319         const unsigned int pbits =
1320                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1321
1322         /* Expand the platform_mask array if this fails. */
1323         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1324                      pbits * ARRAY_SIZE(info->platform_mask));
1325
1326         return p / pbits;
1327 }
1328
1329 static __always_inline unsigned int
1330 __platform_mask_bit(const struct intel_runtime_info *info,
1331                     enum intel_platform p)
1332 {
1333         const unsigned int pbits =
1334                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1335
1336         return p % pbits + INTEL_SUBPLATFORM_BITS;
1337 }
1338
1339 static inline u32
1340 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1341 {
1342         const unsigned int pi = __platform_mask_index(info, p);
1343
1344         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1345 }
1346
1347 static __always_inline bool
1348 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1349 {
1350         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1351         const unsigned int pi = __platform_mask_index(info, p);
1352         const unsigned int pb = __platform_mask_bit(info, p);
1353
1354         BUILD_BUG_ON(!__builtin_constant_p(p));
1355
1356         return info->platform_mask[pi] & BIT(pb);
1357 }
1358
1359 static __always_inline bool
1360 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1361                enum intel_platform p, unsigned int s)
1362 {
1363         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1364         const unsigned int pi = __platform_mask_index(info, p);
1365         const unsigned int pb = __platform_mask_bit(info, p);
1366         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1367         const u32 mask = info->platform_mask[pi];
1368
1369         BUILD_BUG_ON(!__builtin_constant_p(p));
1370         BUILD_BUG_ON(!__builtin_constant_p(s));
1371         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1372
1373         /* Shift and test on the MSB position so sign flag can be used. */
1374         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1375 }
1376
1377 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1378 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1379
1380 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1381 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1382 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1383 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1384 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1385 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1386 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1387 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1388 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1389 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1390 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1391 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1392 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1393 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1394 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1395 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1396 #define IS_IRONLAKE_M(dev_priv) \
1397         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1398 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1399 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1400 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1401                                  INTEL_INFO(dev_priv)->gt == 1)
1402 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1403 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1404 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1405 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1406 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1407 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1408 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1409 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1410 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1411 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1412 #define IS_CANNONLAKE(dev_priv) 0
1413 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1414 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1415                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1416 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1417 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1418 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1419 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1420 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1421 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
1422 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
1423 #define IS_DG2_G10(dev_priv) \
1424         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
1425 #define IS_DG2_G11(dev_priv) \
1426         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
1427 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1428                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1429 #define IS_BDW_ULT(dev_priv) \
1430         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1431 #define IS_BDW_ULX(dev_priv) \
1432         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1433 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1434                                  INTEL_INFO(dev_priv)->gt == 3)
1435 #define IS_HSW_ULT(dev_priv) \
1436         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1437 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1438                                  INTEL_INFO(dev_priv)->gt == 3)
1439 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1440                                  INTEL_INFO(dev_priv)->gt == 1)
1441 /* ULX machines are also considered ULT. */
1442 #define IS_HSW_ULX(dev_priv) \
1443         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1444 #define IS_SKL_ULT(dev_priv) \
1445         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1446 #define IS_SKL_ULX(dev_priv) \
1447         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1448 #define IS_KBL_ULT(dev_priv) \
1449         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1450 #define IS_KBL_ULX(dev_priv) \
1451         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1452 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1453                                  INTEL_INFO(dev_priv)->gt == 2)
1454 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1455                                  INTEL_INFO(dev_priv)->gt == 3)
1456 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1457                                  INTEL_INFO(dev_priv)->gt == 4)
1458 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1459                                  INTEL_INFO(dev_priv)->gt == 2)
1460 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1461                                  INTEL_INFO(dev_priv)->gt == 3)
1462 #define IS_CFL_ULT(dev_priv) \
1463         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1464 #define IS_CFL_ULX(dev_priv) \
1465         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1466 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1467                                  INTEL_INFO(dev_priv)->gt == 2)
1468 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1469                                  INTEL_INFO(dev_priv)->gt == 3)
1470
1471 #define IS_CML_ULT(dev_priv) \
1472         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1473 #define IS_CML_ULX(dev_priv) \
1474         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1475 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
1476                                  INTEL_INFO(dev_priv)->gt == 2)
1477
1478 #define IS_ICL_WITH_PORT_F(dev_priv) \
1479         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1480
1481 #define IS_TGL_U(dev_priv) \
1482         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1483
1484 #define IS_TGL_Y(dev_priv) \
1485         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1486
1487 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
1488
1489 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1490         (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1491 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1492         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1493
1494 #define IS_JSL_EHL_GT_STEP(p, since, until) \
1495         (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
1496 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
1497         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
1498
1499 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1500         (IS_TIGERLAKE(__i915) && \
1501          IS_DISPLAY_STEP(__i915, since, until))
1502
1503 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1504         ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1505          IS_GT_STEP(__i915, since, until))
1506
1507 #define IS_TGL_GT_STEP(__i915, since, until) \
1508         (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1509          IS_GT_STEP(__i915, since, until))
1510
1511 #define IS_RKL_DISPLAY_STEP(p, since, until) \
1512         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
1513
1514 #define IS_DG1_GT_STEP(p, since, until) \
1515         (IS_DG1(p) && IS_GT_STEP(p, since, until))
1516 #define IS_DG1_DISPLAY_STEP(p, since, until) \
1517         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
1518
1519 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1520         (IS_ALDERLAKE_S(__i915) && \
1521          IS_DISPLAY_STEP(__i915, since, until))
1522
1523 #define IS_ADLS_GT_STEP(__i915, since, until) \
1524         (IS_ALDERLAKE_S(__i915) && \
1525          IS_GT_STEP(__i915, since, until))
1526
1527 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1528         (IS_ALDERLAKE_P(__i915) && \
1529          IS_DISPLAY_STEP(__i915, since, until))
1530
1531 #define IS_ADLP_GT_STEP(__i915, since, until) \
1532         (IS_ALDERLAKE_P(__i915) && \
1533          IS_GT_STEP(__i915, since, until))
1534
1535 #define IS_XEHPSDV_GT_STEP(__i915, since, until) \
1536         (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until))
1537
1538 /*
1539  * DG2 hardware steppings are a bit unusual.  The hardware design was forked
1540  * to create two variants (G10 and G11) which have distinct workaround sets.
1541  * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
1542  * first iteration, even though it's more similar to a G10 B0 stepping in terms
1543  * of functionality and workarounds.  However the display stepping does not
1544  * reset in the same manner --- a specific stepping like "B0" has a consistent
1545  * meaning regardless of whether it belongs to a G10 or G11 DG2.
1546  *
1547  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
1548  * relation to a specific subplatform (G10 or G11), whereas display workarounds
1549  * and stepping-specific logic will be applied with a general DG2-wide stepping
1550  * number.
1551  */
1552 #define IS_DG2_GT_STEP(__i915, variant, since, until) \
1553         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
1554          IS_GT_STEP(__i915, since, until))
1555
1556 #define IS_DG2_DISP_STEP(__i915, since, until) \
1557         (IS_DG2(__i915) && \
1558          IS_DISPLAY_STEP(__i915, since, until))
1559
1560 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
1561 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
1562 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
1563
1564 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1565 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1566
1567 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
1568         unsigned int first__ = (first);                                 \
1569         unsigned int count__ = (count);                                 \
1570         ((gt)->info.engine_mask &                                               \
1571          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1572 })
1573 #define VDBOX_MASK(gt) \
1574         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1575 #define VEBOX_MASK(gt) \
1576         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1577
1578 /*
1579  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1580  * All later gens can run the final buffer from the ppgtt
1581  */
1582 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
1583
1584 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1585 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1586 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1587 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
1588 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
1589
1590 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1591
1592 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1593                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1594 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1595                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1596
1597 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1598
1599 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1600 #define HAS_PPGTT(dev_priv) \
1601         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1602 #define HAS_FULL_PPGTT(dev_priv) \
1603         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1604
1605 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1606         GEM_BUG_ON((sizes) == 0); \
1607         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1608 })
1609
1610 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1611 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1612                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1613
1614 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1615 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1616
1617 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1618         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
1619
1620 /* WaRsDisableCoarsePowerGating:skl,cnl */
1621 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1622         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1623
1624 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1625 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
1626                                         IS_GEMINILAKE(dev_priv) || \
1627                                         IS_KABYLAKE(dev_priv))
1628
1629 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1630  * rows, which changed the alignment requirements and fence programming.
1631  */
1632 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
1633                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
1634 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1635 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1636
1637 #define HAS_FW_BLC(dev_priv)    (GRAPHICS_VER(dev_priv) > 2)
1638 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1639 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
1640
1641 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1642
1643 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1644
1645 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
1646 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1647 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1648 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1649 #define HAS_PSR_HW_TRACKING(dev_priv) \
1650         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1651 #define HAS_PSR2_SEL_FETCH(dev_priv)     (GRAPHICS_VER(dev_priv) >= 12)
1652 #define HAS_TRANSCODER(dev_priv, trans)  ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1653
1654 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1655 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1656 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1657
1658 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1659
1660 #define HAS_DMC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dmc)
1661
1662 #define HAS_MSO(i915)           (GRAPHICS_VER(i915) >= 12)
1663
1664 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1665 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1666
1667 #define HAS_MSLICES(dev_priv) \
1668         (INTEL_INFO(dev_priv)->has_mslices)
1669
1670 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1671
1672 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1673 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1674
1675 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1676
1677 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1678
1679 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1680
1681
1682 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1683
1684 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
1685
1686 /* DPF == dynamic parity feature */
1687 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1688 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1689                                  2 : HAS_L3_DPF(dev_priv))
1690
1691 #define GT_FREQUENCY_MULTIPLIER 50
1692 #define GEN9_FREQ_SCALER 3
1693
1694 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1695
1696 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1697
1698 #define HAS_VRR(i915)   (GRAPHICS_VER(i915) >= 12)
1699
1700 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
1701
1702 /* Only valid when HAS_DISPLAY() is true */
1703 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1704         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1705
1706 static inline bool run_as_guest(void)
1707 {
1708         return !hypervisor_is_type(X86_HYPER_NATIVE);
1709 }
1710
1711 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1712                                               IS_ALDERLAKE_S(dev_priv))
1713
1714 static inline bool intel_vtd_active(void)
1715 {
1716 #ifdef CONFIG_INTEL_IOMMU
1717         if (intel_iommu_gfx_mapped)
1718                 return true;
1719 #endif
1720
1721         /* Running as a guest, we assume the host is enforcing VT'd */
1722         return run_as_guest();
1723 }
1724
1725 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1726 {
1727         return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
1728 }
1729
1730 static inline bool
1731 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
1732 {
1733         return IS_BROXTON(i915) && intel_vtd_active();
1734 }
1735
1736 static inline bool
1737 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915)
1738 {
1739         return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
1740 }
1741
1742 /* i915_drv.c */
1743 extern const struct dev_pm_ops i915_pm_ops;
1744
1745 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1746 void i915_driver_remove(struct drm_i915_private *i915);
1747 void i915_driver_shutdown(struct drm_i915_private *i915);
1748
1749 int i915_resume_switcheroo(struct drm_i915_private *i915);
1750 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1751
1752 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1753                         struct drm_file *file_priv);
1754
1755 /* i915_gem.c */
1756 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1757 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1758 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1759 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1760
1761 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1762 {
1763         /*
1764          * A single pass should suffice to release all the freed objects (along
1765          * most call paths) , but be a little more paranoid in that freeing
1766          * the objects does take a little amount of time, during which the rcu
1767          * callbacks could have added new objects into the freed list, and
1768          * armed the work again.
1769          */
1770         while (atomic_read(&i915->mm.free_count)) {
1771                 flush_work(&i915->mm.free_work);
1772                 rcu_barrier();
1773         }
1774 }
1775
1776 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1777 {
1778         /*
1779          * Similar to objects above (see i915_gem_drain_freed-objects), in
1780          * general we have workers that are armed by RCU and then rearm
1781          * themselves in their callbacks. To be paranoid, we need to
1782          * drain the workqueue a second time after waiting for the RCU
1783          * grace period so that we catch work queued via RCU from the first
1784          * pass. As neither drain_workqueue() nor flush_workqueue() report
1785          * a result, we make an assumption that we only don't require more
1786          * than 3 passes to catch all _recursive_ RCU delayed work.
1787          *
1788          */
1789         int pass = 3;
1790         do {
1791                 flush_workqueue(i915->wq);
1792                 rcu_barrier();
1793                 i915_gem_drain_freed_objects(i915);
1794         } while (--pass);
1795         drain_workqueue(i915->wq);
1796 }
1797
1798 struct i915_vma * __must_check
1799 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1800                             struct i915_gem_ww_ctx *ww,
1801                             const struct i915_ggtt_view *view,
1802                             u64 size, u64 alignment, u64 flags);
1803
1804 static inline struct i915_vma * __must_check
1805 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1806                          const struct i915_ggtt_view *view,
1807                          u64 size, u64 alignment, u64 flags)
1808 {
1809         return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1810 }
1811
1812 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1813                            unsigned long flags);
1814 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1815 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1816 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1817 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3)
1818
1819 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1820
1821 int i915_gem_dumb_create(struct drm_file *file_priv,
1822                          struct drm_device *dev,
1823                          struct drm_mode_create_dumb *args);
1824
1825 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1826
1827 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1828 {
1829         return atomic_read(&error->reset_count);
1830 }
1831
1832 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1833                                           const struct intel_engine_cs *engine)
1834 {
1835         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1836 }
1837
1838 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1839 void i915_gem_driver_register(struct drm_i915_private *i915);
1840 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1841 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1842 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1843 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1844 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1845 void i915_gem_resume(struct drm_i915_private *dev_priv);
1846
1847 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1848
1849 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1850                                     enum i915_cache_level cache_level);
1851
1852 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1853                                 struct dma_buf *dma_buf);
1854
1855 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1856
1857 static inline struct i915_address_space *
1858 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
1859 {
1860         struct i915_address_space *vm;
1861
1862         rcu_read_lock();
1863         vm = xa_load(&file_priv->vm_xa, id);
1864         if (vm && !kref_get_unless_zero(&vm->ref))
1865                 vm = NULL;
1866         rcu_read_unlock();
1867
1868         return vm;
1869 }
1870
1871 /* i915_gem_evict.c */
1872 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1873                                           u64 min_size, u64 alignment,
1874                                           unsigned long color,
1875                                           u64 start, u64 end,
1876                                           unsigned flags);
1877 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1878                                          struct drm_mm_node *node,
1879                                          unsigned int flags);
1880 int i915_gem_evict_vm(struct i915_address_space *vm);
1881
1882 /* i915_gem_internal.c */
1883 struct drm_i915_gem_object *
1884 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1885                                 phys_addr_t size);
1886
1887 /* i915_gem_tiling.c */
1888 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1889 {
1890         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1891
1892         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1893                 i915_gem_object_is_tiled(obj);
1894 }
1895
1896 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1897                         unsigned int tiling, unsigned int stride);
1898 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1899                              unsigned int tiling, unsigned int stride);
1900
1901 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1902
1903 /* i915_cmd_parser.c */
1904 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1905 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1906 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1907 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1908                             struct i915_vma *batch,
1909                             unsigned long batch_offset,
1910                             unsigned long batch_length,
1911                             struct i915_vma *shadow,
1912                             bool trampoline);
1913 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1914
1915 /* intel_device_info.c */
1916 static inline struct intel_device_info *
1917 mkwrite_device_info(struct drm_i915_private *dev_priv)
1918 {
1919         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1920 }
1921
1922 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1923                         struct drm_file *file);
1924
1925 /* i915_mm.c */
1926 int remap_io_mapping(struct vm_area_struct *vma,
1927                      unsigned long addr, unsigned long pfn, unsigned long size,
1928                      struct io_mapping *iomap);
1929 int remap_io_sg(struct vm_area_struct *vma,
1930                 unsigned long addr, unsigned long size,
1931                 struct scatterlist *sgl, resource_size_t iobase);
1932
1933 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1934 {
1935         if (GRAPHICS_VER(i915) >= 11)
1936                 return ICL_HWS_CSB_WRITE_INDEX;
1937         else
1938                 return I915_HWS_CSB_WRITE_INDEX;
1939 }
1940
1941 static inline enum i915_map_type
1942 i915_coherent_map_type(struct drm_i915_private *i915,
1943                        struct drm_i915_gem_object *obj, bool always_coherent)
1944 {
1945         if (i915_gem_object_is_lmem(obj))
1946                 return I915_MAP_WC;
1947         if (HAS_LLC(i915) || always_coherent)
1948                 return I915_MAP_WB;
1949         else
1950                 return I915_MAP_WC;
1951 }
1952
1953 #endif