1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
66 #define plane_name(p) ((p) + 'A')
76 #define port_name(p) ((p) + 'A')
78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
82 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
83 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
84 if ((intel_encoder)->base.crtc == (__crtc))
86 struct intel_pch_pll {
87 int refcount; /* count of number of CRTCs sharing this PLL */
88 int active; /* count of number of active CRTCs (i.e. DPMS on) */
89 bool on; /* is the PLL actually active? Disabled during modeset */
94 #define I915_NUM_PLLS 2
99 * 1.2: Add Power Management
100 * 1.3: Add vblank support
101 * 1.4: Fix cmdbuffer path, add heap destroy
102 * 1.5: Add vblank pipe configuration
103 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
104 * - Support vertical blank on secondary display pipe
106 #define DRIVER_MAJOR 1
107 #define DRIVER_MINOR 6
108 #define DRIVER_PATCHLEVEL 0
110 #define WATCH_COHERENCY 0
111 #define WATCH_LISTS 0
114 #define I915_GEM_PHYS_CURSOR_0 1
115 #define I915_GEM_PHYS_CURSOR_1 2
116 #define I915_GEM_PHYS_OVERLAY_REGS 3
117 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
119 struct drm_i915_gem_phys_object {
121 struct page **page_list;
122 drm_dma_handle_t *handle;
123 struct drm_i915_gem_object *cur_obj;
127 struct mem_block *next;
128 struct mem_block *prev;
131 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
134 struct opregion_header;
135 struct opregion_acpi;
136 struct opregion_swsci;
137 struct opregion_asle;
138 struct drm_i915_private;
140 struct intel_opregion {
141 struct opregion_header __iomem *header;
142 struct opregion_acpi __iomem *acpi;
143 struct opregion_swsci __iomem *swsci;
144 struct opregion_asle __iomem *asle;
146 u32 __iomem *lid_state;
148 #define OPREGION_SIZE (8*1024)
150 struct intel_overlay;
151 struct intel_overlay_error_state;
153 struct drm_i915_master_private {
154 drm_local_map_t *sarea;
155 struct _drm_i915_sarea *sarea_priv;
157 #define I915_FENCE_REG_NONE -1
158 #define I915_MAX_NUM_FENCES 16
159 /* 16 fences + sign bit for FENCE_REG_NONE */
160 #define I915_MAX_NUM_FENCE_BITS 5
162 struct drm_i915_fence_reg {
163 struct list_head lru_list;
164 struct drm_i915_gem_object *obj;
168 struct sdvo_device_mapping {
177 struct intel_display_error_state;
179 struct drm_i915_error_state {
185 bool waiting[I915_NUM_RINGS];
186 u32 pipestat[I915_MAX_PIPES];
187 u32 tail[I915_NUM_RINGS];
188 u32 head[I915_NUM_RINGS];
189 u32 ipeir[I915_NUM_RINGS];
190 u32 ipehr[I915_NUM_RINGS];
191 u32 instdone[I915_NUM_RINGS];
192 u32 acthd[I915_NUM_RINGS];
193 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
194 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
195 /* our own tracking of ring head and tail */
196 u32 cpu_ring_head[I915_NUM_RINGS];
197 u32 cpu_ring_tail[I915_NUM_RINGS];
198 u32 error; /* gen6+ */
199 u32 err_int; /* gen7 */
200 u32 instpm[I915_NUM_RINGS];
201 u32 instps[I915_NUM_RINGS];
202 u32 extra_instdone[I915_NUM_INSTDONE_REG];
203 u32 seqno[I915_NUM_RINGS];
205 u32 fault_reg[I915_NUM_RINGS];
207 u32 faddr[I915_NUM_RINGS];
208 u64 fence[I915_MAX_NUM_FENCES];
210 struct drm_i915_error_ring {
211 struct drm_i915_error_object {
215 } *ringbuffer, *batchbuffer;
216 struct drm_i915_error_request {
222 } ring[I915_NUM_RINGS];
223 struct drm_i915_error_buffer {
230 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
237 } *active_bo, *pinned_bo;
238 u32 active_bo_count, pinned_bo_count;
239 struct intel_overlay_error_state *overlay;
240 struct intel_display_error_state *display;
243 struct drm_i915_display_funcs {
244 bool (*fbc_enabled)(struct drm_device *dev);
245 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
246 void (*disable_fbc)(struct drm_device *dev);
247 int (*get_display_clock_speed)(struct drm_device *dev);
248 int (*get_fifo_size)(struct drm_device *dev, int plane);
249 void (*update_wm)(struct drm_device *dev);
250 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
251 uint32_t sprite_width, int pixel_size);
252 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
253 struct drm_display_mode *mode);
254 int (*crtc_mode_set)(struct drm_crtc *crtc,
255 struct drm_display_mode *mode,
256 struct drm_display_mode *adjusted_mode,
258 struct drm_framebuffer *old_fb);
259 void (*crtc_enable)(struct drm_crtc *crtc);
260 void (*crtc_disable)(struct drm_crtc *crtc);
261 void (*off)(struct drm_crtc *crtc);
262 void (*write_eld)(struct drm_connector *connector,
263 struct drm_crtc *crtc);
264 void (*fdi_link_train)(struct drm_crtc *crtc);
265 void (*init_clock_gating)(struct drm_device *dev);
266 void (*init_pch_clock_gating)(struct drm_device *dev);
267 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
268 struct drm_framebuffer *fb,
269 struct drm_i915_gem_object *obj);
270 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
272 /* clock updates for mode set */
274 /* render clock increase/decrease */
275 /* display clock increase/decrease */
276 /* pll clock increase/decrease */
279 struct drm_i915_gt_funcs {
280 void (*force_wake_get)(struct drm_i915_private *dev_priv);
281 void (*force_wake_put)(struct drm_i915_private *dev_priv);
284 #define DEV_INFO_FLAGS \
285 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
286 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
287 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
288 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
289 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
290 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
291 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
292 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
297 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
298 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
299 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
300 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
301 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
302 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
303 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
304 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
305 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
306 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_llc)
310 struct intel_device_info {
329 u8 cursor_needs_physical:1;
331 u8 overlay_needs_physical:1;
338 #define I915_PPGTT_PD_ENTRIES 512
339 #define I915_PPGTT_PT_ENTRIES 1024
340 struct i915_hw_ppgtt {
341 unsigned num_pd_entries;
342 struct page **pt_pages;
344 dma_addr_t *pt_dma_addr;
345 dma_addr_t scratch_page_dma_addr;
349 /* This must match up with the value previously used for execbuf2.rsvd1. */
350 #define DEFAULT_CONTEXT_ID 0
351 struct i915_hw_context {
354 struct drm_i915_file_private *file_priv;
355 struct intel_ring_buffer *ring;
356 struct drm_i915_gem_object *obj;
360 FBC_NO_OUTPUT, /* no outputs enabled to compress */
361 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
362 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
363 FBC_MODE_TOO_LARGE, /* mode too large for compression */
364 FBC_BAD_PLANE, /* fbc not supported on plane */
365 FBC_NOT_TILED, /* buffer not tiled */
366 FBC_MULTIPLE_PIPES, /* more than one pipe active */
371 PCH_NONE = 0, /* No PCH present */
372 PCH_IBX, /* Ibexpeak PCH */
373 PCH_CPT, /* Cougarpoint PCH */
374 PCH_LPT, /* Lynxpoint PCH */
377 #define QUIRK_PIPEA_FORCE (1<<0)
378 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
379 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
382 struct intel_fbc_work;
385 struct i2c_adapter adapter;
389 struct i2c_algo_bit_data bit_algo;
390 struct drm_i915_private *dev_priv;
393 typedef struct drm_i915_private {
394 struct drm_device *dev;
396 const struct intel_device_info *info;
398 int relative_constants_mode;
402 struct drm_i915_gt_funcs gt;
403 /** gt_fifo_count and the subsequent register write are synchronized
404 * with dev->struct_mutex. */
405 unsigned gt_fifo_count;
406 /** forcewake_count is protected by gt_lock */
407 unsigned forcewake_count;
408 /** gt_lock is also taken in irq contexts. */
409 struct spinlock gt_lock;
411 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
413 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
414 * controller on different i2c buses. */
415 struct mutex gmbus_mutex;
418 * Base address of the gmbus and gpio block.
420 uint32_t gpio_mmio_base;
422 struct pci_dev *bridge_dev;
423 struct intel_ring_buffer ring[I915_NUM_RINGS];
426 drm_dma_handle_t *status_page_dmah;
428 struct drm_i915_gem_object *pwrctx;
429 struct drm_i915_gem_object *renderctx;
431 struct resource mch_res;
433 atomic_t irq_received;
435 /* protects the irq masks */
438 /* DPIO indirect register protection */
439 spinlock_t dpio_lock;
441 /** Cached value of IMR to avoid reads in updating the bitfield */
447 u32 hotplug_supported_mask;
448 struct work_struct hotplug_work;
453 /* For hangcheck timer */
454 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
455 struct timer_list hangcheck_timer;
457 uint32_t last_acthd[I915_NUM_RINGS];
458 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
460 unsigned int stop_rings;
462 unsigned long cfb_size;
464 enum plane cfb_plane;
466 struct intel_fbc_work *fbc_work;
468 struct intel_opregion opregion;
471 struct intel_overlay *overlay;
472 bool sprite_scaling_enabled;
475 int backlight_level; /* restore backlight to this value */
476 bool backlight_enabled;
477 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
478 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
480 /* Feature bits from the VBIOS */
481 unsigned int int_tv_support:1;
482 unsigned int lvds_dither:1;
483 unsigned int lvds_vbt:1;
484 unsigned int int_crt_support:1;
485 unsigned int lvds_use_ssc:1;
486 unsigned int display_clock_mode:1;
488 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
489 unsigned int lvds_val; /* used for checking LVDS channel mode */
499 struct edp_power_seq pps;
501 bool no_aux_handshake;
503 struct notifier_block lid_notifier;
506 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
507 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
508 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
510 unsigned int fsb_freq, mem_freq, is_ddr3;
512 spinlock_t error_lock;
513 /* Protected by dev->error_lock. */
514 struct drm_i915_error_state *first_error;
515 struct work_struct error_work;
516 struct completion error_completion;
517 struct workqueue_struct *wq;
519 /* Display functions */
520 struct drm_i915_display_funcs display;
522 /* PCH chipset type */
523 enum intel_pch pch_type;
525 unsigned long quirks;
550 u32 saveTRANS_HTOTAL_A;
551 u32 saveTRANS_HBLANK_A;
552 u32 saveTRANS_HSYNC_A;
553 u32 saveTRANS_VTOTAL_A;
554 u32 saveTRANS_VBLANK_A;
555 u32 saveTRANS_VSYNC_A;
563 u32 savePFIT_PGM_RATIOS;
564 u32 saveBLC_HIST_CTL;
566 u32 saveBLC_PWM_CTL2;
567 u32 saveBLC_CPU_PWM_CTL;
568 u32 saveBLC_CPU_PWM_CTL2;
581 u32 saveTRANS_HTOTAL_B;
582 u32 saveTRANS_HBLANK_B;
583 u32 saveTRANS_HSYNC_B;
584 u32 saveTRANS_VTOTAL_B;
585 u32 saveTRANS_VBLANK_B;
586 u32 saveTRANS_VSYNC_B;
600 u32 savePP_ON_DELAYS;
601 u32 savePP_OFF_DELAYS;
609 u32 savePFIT_CONTROL;
610 u32 save_palette_a[256];
611 u32 save_palette_b[256];
612 u32 saveDPFC_CB_BASE;
613 u32 saveFBC_CFB_BASE;
616 u32 saveFBC_CONTROL2;
626 u32 saveCACHE_MODE_0;
627 u32 saveMI_ARB_STATE;
638 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
649 u32 savePIPEA_GMCH_DATA_M;
650 u32 savePIPEB_GMCH_DATA_M;
651 u32 savePIPEA_GMCH_DATA_N;
652 u32 savePIPEB_GMCH_DATA_N;
653 u32 savePIPEA_DP_LINK_M;
654 u32 savePIPEB_DP_LINK_M;
655 u32 savePIPEA_DP_LINK_N;
656 u32 savePIPEB_DP_LINK_N;
667 u32 savePCH_DREF_CONTROL;
668 u32 saveDISP_ARB_CTL;
669 u32 savePIPEA_DATA_M1;
670 u32 savePIPEA_DATA_N1;
671 u32 savePIPEA_LINK_M1;
672 u32 savePIPEA_LINK_N1;
673 u32 savePIPEB_DATA_M1;
674 u32 savePIPEB_DATA_N1;
675 u32 savePIPEB_LINK_M1;
676 u32 savePIPEB_LINK_N1;
677 u32 saveMCHBAR_RENDER_STANDBY;
678 u32 savePCH_PORT_HOTPLUG;
681 /** Bridge to intel-gtt-ko */
682 const struct intel_gtt *gtt;
683 /** Memory allocator for GTT stolen memory */
684 struct drm_mm stolen;
685 /** Memory allocator for GTT */
686 struct drm_mm gtt_space;
687 /** List of all objects in gtt_space. Used to restore gtt
688 * mappings on resume */
689 struct list_head bound_list;
691 * List of objects which are not bound to the GTT (thus
692 * are idle and not used by the GPU) but still have
693 * (presumably uncached) pages still attached.
695 struct list_head unbound_list;
697 /** Usable portion of the GTT for GEM */
698 unsigned long gtt_start;
699 unsigned long gtt_mappable_end;
700 unsigned long gtt_end;
702 struct io_mapping *gtt_mapping;
703 phys_addr_t gtt_base_addr;
706 /** PPGTT used for aliasing the PPGTT with the GTT */
707 struct i915_hw_ppgtt *aliasing_ppgtt;
711 struct shrinker inactive_shrinker;
714 * List of objects currently involved in rendering.
716 * Includes buffers having the contents of their GPU caches
717 * flushed, not necessarily primitives. last_rendering_seqno
718 * represents when the rendering involved will be completed.
720 * A reference is held on the buffer while on this list.
722 struct list_head active_list;
725 * LRU list of objects which are not in the ringbuffer and
726 * are ready to unbind, but are still in the GTT.
728 * last_rendering_seqno is 0 while an object is in this list.
730 * A reference is not held on the buffer while on this list,
731 * as merely being GTT-bound shouldn't prevent its being
732 * freed, and we'll pull it off the list in the free path.
734 struct list_head inactive_list;
736 /** LRU list of objects with fence regs on them. */
737 struct list_head fence_list;
740 * We leave the user IRQ off as much as possible,
741 * but this means that requests will finish and never
742 * be retired once the system goes idle. Set a timer to
743 * fire periodically while the ring is running. When it
744 * fires, go retire requests.
746 struct delayed_work retire_work;
749 * Are we in a non-interruptible section of code like
755 * Flag if the X Server, and thus DRM, is not currently in
756 * control of the device.
758 * This is set between LeaveVT and EnterVT. It needs to be
759 * replaced with a semaphore. It also needs to be
760 * transitioned away from for kernel modesetting.
765 * Flag if the hardware appears to be wedged.
767 * This is set when attempts to idle the device timeout.
768 * It prevents command submission from occurring and makes
769 * every pending request fail
773 /** Bit 6 swizzling required for X tiling */
774 uint32_t bit_6_swizzle_x;
775 /** Bit 6 swizzling required for Y tiling */
776 uint32_t bit_6_swizzle_y;
778 /* storage for physical objects */
779 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
781 /* accounting, useful for userland debugging */
783 size_t mappable_gtt_total;
784 size_t object_memory;
788 /* Old dri1 support infrastructure, beware the dragons ya fools entering
791 unsigned allow_batchbuffer : 1;
792 u32 __iomem *gfx_hws_cpu_addr;
801 /* Kernel Modesetting */
803 struct sdvo_device_mapping sdvo_mappings[2];
804 /* indicate whether the LVDS_BORDER should be enabled or not */
805 unsigned int lvds_border_bits;
806 /* Panel fitter placement and size for Ironlake+ */
807 u32 pch_pf_pos, pch_pf_size;
809 struct drm_crtc *plane_to_crtc_mapping[3];
810 struct drm_crtc *pipe_to_crtc_mapping[3];
811 wait_queue_head_t pending_flip_queue;
813 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
815 /* Reclocking support */
816 bool render_reclock_avail;
817 bool lvds_downclock_avail;
818 /* indicates the reduced downclock for LVDS*/
822 struct child_device_config *child_dev;
823 struct drm_connector *int_lvds_connector;
824 struct drm_connector *int_edp_connector;
826 bool mchbar_need_disable;
828 /* gen6+ rps state */
830 struct work_struct work;
832 /* lock - irqsave spinlock that protectects the work_struct and
836 /* The below variables an all the rps hw state are protected by
837 * dev->struct mutext. */
843 /* ilk-only ips/rps state. Everything in here is protected by the global
844 * mchdev_lock in intel_pm.c */
853 unsigned long last_time1;
854 unsigned long chipset_power;
856 struct timespec last_time2;
857 unsigned long gfx_power;
864 enum no_fbc_reason no_fbc_reason;
866 struct drm_mm_node *compressed_fb;
867 struct drm_mm_node *compressed_llb;
869 unsigned long last_gpu_reset;
871 /* list of fbdev register on this device */
872 struct intel_fbdev *fbdev;
874 struct backlight_device *backlight;
876 struct drm_property *broadcast_rgb_property;
877 struct drm_property *force_audio_property;
879 struct work_struct parity_error_work;
880 bool hw_contexts_disabled;
881 uint32_t hw_context_size;
882 } drm_i915_private_t;
884 /* Iterate over initialised rings */
885 #define for_each_ring(ring__, dev_priv__, i__) \
886 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
887 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
889 enum hdmi_force_audio {
890 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
891 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
892 HDMI_AUDIO_AUTO, /* trust EDID */
893 HDMI_AUDIO_ON, /* force turn on HDMI audio */
896 enum i915_cache_level {
899 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
902 struct drm_i915_gem_object_ops {
903 /* Interface between the GEM object and its backing storage.
904 * get_pages() is called once prior to the use of the associated set
905 * of pages before to binding them into the GTT, and put_pages() is
906 * called after we no longer need them. As we expect there to be
907 * associated cost with migrating pages between the backing storage
908 * and making them available for the GPU (e.g. clflush), we may hold
909 * onto the pages after they are no longer referenced by the GPU
910 * in case they may be used again shortly (for example migrating the
911 * pages to a different memory domain within the GTT). put_pages()
912 * will therefore most likely be called when the object itself is
913 * being released or under memory pressure (where we attempt to
914 * reap pages for the shrinker).
916 int (*get_pages)(struct drm_i915_gem_object *);
917 void (*put_pages)(struct drm_i915_gem_object *);
920 struct drm_i915_gem_object {
921 struct drm_gem_object base;
923 const struct drm_i915_gem_object_ops *ops;
925 /** Current space allocated to this object in the GTT, if any. */
926 struct drm_mm_node *gtt_space;
927 struct list_head gtt_list;
929 /** This object's place on the active/inactive lists */
930 struct list_head ring_list;
931 struct list_head mm_list;
932 /** This object's place in the batchbuffer or on the eviction list */
933 struct list_head exec_list;
936 * This is set if the object is on the active lists (has pending
937 * rendering and so a non-zero seqno), and is not set if it i s on
938 * inactive (ready to be unbound) list.
940 unsigned int active:1;
943 * This is set if the object has been written to since last bound
946 unsigned int dirty:1;
949 * Fence register bits (if any) for this object. Will be set
950 * as needed when mapped into the GTT.
951 * Protected by dev->struct_mutex.
953 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
956 * Advice: are the backing pages purgeable?
961 * Current tiling mode for the object.
963 unsigned int tiling_mode:2;
965 * Whether the tiling parameters for the currently associated fence
966 * register have changed. Note that for the purposes of tracking
967 * tiling changes we also treat the unfenced register, the register
968 * slot that the object occupies whilst it executes a fenced
969 * command (such as BLT on gen2/3), as a "fence".
971 unsigned int fence_dirty:1;
973 /** How many users have pinned this object in GTT space. The following
974 * users can each hold at most one reference: pwrite/pread, pin_ioctl
975 * (via user_pin_count), execbuffer (objects are not allowed multiple
976 * times for the same batchbuffer), and the framebuffer code. When
977 * switching/pageflipping, the framebuffer code has at most two buffers
980 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
981 * bits with absolutely no headroom. So use 4 bits. */
982 unsigned int pin_count:4;
983 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
986 * Is the object at the current location in the gtt mappable and
987 * fenceable? Used to avoid costly recalculations.
989 unsigned int map_and_fenceable:1;
992 * Whether the current gtt mapping needs to be mappable (and isn't just
993 * mappable by accident). Track pin and fault separate for a more
994 * accurate mappable working set.
996 unsigned int fault_mappable:1;
997 unsigned int pin_mappable:1;
1000 * Is the GPU currently using a fence to access this buffer,
1002 unsigned int pending_fenced_gpu_access:1;
1003 unsigned int fenced_gpu_access:1;
1005 unsigned int cache_level:2;
1007 unsigned int has_aliasing_ppgtt_mapping:1;
1008 unsigned int has_global_gtt_mapping:1;
1009 unsigned int has_dma_mapping:1;
1011 struct sg_table *pages;
1012 int pages_pin_count;
1014 /* prime dma-buf support */
1015 void *dma_buf_vmapping;
1019 * Used for performing relocations during execbuffer insertion.
1021 struct hlist_node exec_node;
1022 unsigned long exec_handle;
1023 struct drm_i915_gem_exec_object2 *exec_entry;
1026 * Current offset of the object in GTT space.
1028 * This is the same as gtt_space->start
1030 uint32_t gtt_offset;
1032 struct intel_ring_buffer *ring;
1034 /** Breadcrumb of last rendering to the buffer. */
1035 uint32_t last_read_seqno;
1036 uint32_t last_write_seqno;
1037 /** Breadcrumb of last fenced GPU access to the buffer. */
1038 uint32_t last_fenced_seqno;
1040 /** Current tiling stride for the object, if it's tiled. */
1043 /** Record of address bit 17 of each page at last unbind. */
1044 unsigned long *bit_17;
1046 /** User space pin count and filp owning the pin */
1047 uint32_t user_pin_count;
1048 struct drm_file *pin_filp;
1050 /** for phy allocated objects */
1051 struct drm_i915_gem_phys_object *phys_obj;
1054 * Number of crtcs where this object is currently the fb, but
1055 * will be page flipped away on the next vblank. When it
1056 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1058 atomic_t pending_flip;
1061 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1064 * Request queue structure.
1066 * The request queue allows us to note sequence numbers that have been emitted
1067 * and may be associated with active buffers to be retired.
1069 * By keeping this list, we can avoid having to do questionable
1070 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1071 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1073 struct drm_i915_gem_request {
1074 /** On Which ring this request was generated */
1075 struct intel_ring_buffer *ring;
1077 /** GEM sequence number associated with this request. */
1080 /** Postion in the ringbuffer of the end of the request */
1083 /** Time at which this request was emitted, in jiffies. */
1084 unsigned long emitted_jiffies;
1086 /** global list entry for this request */
1087 struct list_head list;
1089 struct drm_i915_file_private *file_priv;
1090 /** file_priv list entry for this request */
1091 struct list_head client_list;
1094 struct drm_i915_file_private {
1096 struct spinlock lock;
1097 struct list_head request_list;
1099 struct idr context_idr;
1102 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1104 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1105 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1106 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1107 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1108 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1109 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1110 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1111 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1112 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1113 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1114 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1115 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1116 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1117 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1118 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1119 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1120 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1121 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1122 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1123 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1124 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1125 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1128 * The genX designation typically refers to the render engine, so render
1129 * capability related checks should use IS_GEN, while display and other checks
1130 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1133 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1134 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1135 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1136 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1137 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1138 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1140 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1141 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1142 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1143 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1145 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1146 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1148 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1149 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1151 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1152 * rows, which changed the alignment requirements and fence programming.
1154 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1156 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1157 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1158 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1159 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1160 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1161 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1162 /* dsparb controlled by hw only */
1163 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1165 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1166 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1167 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1169 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1171 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1172 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1173 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1174 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1175 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1177 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1179 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1181 #define GT_FREQUENCY_MULTIPLIER 50
1183 #include "i915_trace.h"
1186 * RC6 is a special power stage which allows the GPU to enter an very
1187 * low-voltage mode when idle, using down to 0V while at this stage. This
1188 * stage is entered automatically when the GPU is idle when RC6 support is
1189 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1191 * There are different RC6 modes available in Intel GPU, which differentiate
1192 * among each other with the latency required to enter and leave RC6 and
1193 * voltage consumed by the GPU in different states.
1195 * The combination of the following flags define which states GPU is allowed
1196 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1197 * RC6pp is deepest RC6. Their support by hardware varies according to the
1198 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1199 * which brings the most power savings; deeper states save more power, but
1200 * require higher latency to switch to and wake up.
1202 #define INTEL_RC6_ENABLE (1<<0)
1203 #define INTEL_RC6p_ENABLE (1<<1)
1204 #define INTEL_RC6pp_ENABLE (1<<2)
1206 extern struct drm_ioctl_desc i915_ioctls[];
1207 extern int i915_max_ioctl;
1208 extern unsigned int i915_fbpercrtc __always_unused;
1209 extern int i915_panel_ignore_lid __read_mostly;
1210 extern unsigned int i915_powersave __read_mostly;
1211 extern int i915_semaphores __read_mostly;
1212 extern unsigned int i915_lvds_downclock __read_mostly;
1213 extern int i915_lvds_channel_mode __read_mostly;
1214 extern int i915_panel_use_ssc __read_mostly;
1215 extern int i915_vbt_sdvo_panel_type __read_mostly;
1216 extern int i915_enable_rc6 __read_mostly;
1217 extern int i915_enable_fbc __read_mostly;
1218 extern bool i915_enable_hangcheck __read_mostly;
1219 extern int i915_enable_ppgtt __read_mostly;
1220 extern unsigned int i915_preliminary_hw_support __read_mostly;
1222 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1223 extern int i915_resume(struct drm_device *dev);
1224 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1225 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1228 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1229 extern void i915_kernel_lost_context(struct drm_device * dev);
1230 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1231 extern int i915_driver_unload(struct drm_device *);
1232 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1233 extern void i915_driver_lastclose(struct drm_device * dev);
1234 extern void i915_driver_preclose(struct drm_device *dev,
1235 struct drm_file *file_priv);
1236 extern void i915_driver_postclose(struct drm_device *dev,
1237 struct drm_file *file_priv);
1238 extern int i915_driver_device_is_agp(struct drm_device * dev);
1239 #ifdef CONFIG_COMPAT
1240 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1243 extern int i915_emit_box(struct drm_device *dev,
1244 struct drm_clip_rect *box,
1246 extern int intel_gpu_reset(struct drm_device *dev);
1247 extern int i915_reset(struct drm_device *dev);
1248 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1249 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1250 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1251 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1255 void i915_hangcheck_elapsed(unsigned long data);
1256 void i915_handle_error(struct drm_device *dev, bool wedged);
1258 extern void intel_irq_init(struct drm_device *dev);
1259 extern void intel_gt_init(struct drm_device *dev);
1261 void i915_error_state_free(struct kref *error_ref);
1264 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1267 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1269 void intel_enable_asle(struct drm_device *dev);
1271 #ifdef CONFIG_DEBUG_FS
1272 extern void i915_destroy_error_state(struct drm_device *dev);
1274 #define i915_destroy_error_state(x)
1279 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1280 struct drm_file *file_priv);
1281 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1282 struct drm_file *file_priv);
1283 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1284 struct drm_file *file_priv);
1285 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1286 struct drm_file *file_priv);
1287 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1288 struct drm_file *file_priv);
1289 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1290 struct drm_file *file_priv);
1291 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1292 struct drm_file *file_priv);
1293 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1294 struct drm_file *file_priv);
1295 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1296 struct drm_file *file_priv);
1297 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1298 struct drm_file *file_priv);
1299 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1300 struct drm_file *file_priv);
1301 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1302 struct drm_file *file_priv);
1303 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1304 struct drm_file *file_priv);
1305 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1306 struct drm_file *file);
1307 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1308 struct drm_file *file);
1309 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1310 struct drm_file *file_priv);
1311 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1312 struct drm_file *file_priv);
1313 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1314 struct drm_file *file_priv);
1315 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *file_priv);
1317 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1318 struct drm_file *file_priv);
1319 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1320 struct drm_file *file_priv);
1321 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *file_priv);
1323 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *file_priv);
1325 void i915_gem_load(struct drm_device *dev);
1326 int i915_gem_init_object(struct drm_gem_object *obj);
1327 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1328 const struct drm_i915_gem_object_ops *ops);
1329 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1331 void i915_gem_free_object(struct drm_gem_object *obj);
1332 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1334 bool map_and_fenceable,
1336 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1337 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1338 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1339 void i915_gem_lastclose(struct drm_device *dev);
1341 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1342 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1344 struct scatterlist *sg = obj->pages->sgl;
1345 int nents = obj->pages->nents;
1346 while (nents > SG_MAX_SINGLE_ALLOC) {
1347 if (n < SG_MAX_SINGLE_ALLOC - 1)
1350 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1351 n -= SG_MAX_SINGLE_ALLOC - 1;
1352 nents -= SG_MAX_SINGLE_ALLOC - 1;
1354 return sg_page(sg+n);
1356 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1358 BUG_ON(obj->pages == NULL);
1359 obj->pages_pin_count++;
1361 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1363 BUG_ON(obj->pages_pin_count == 0);
1364 obj->pages_pin_count--;
1367 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1368 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1369 struct intel_ring_buffer *to);
1370 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1371 struct intel_ring_buffer *ring,
1374 int i915_gem_dumb_create(struct drm_file *file_priv,
1375 struct drm_device *dev,
1376 struct drm_mode_create_dumb *args);
1377 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1378 uint32_t handle, uint64_t *offset);
1379 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1382 * Returns true if seq1 is later than seq2.
1385 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1387 return (int32_t)(seq1 - seq2) >= 0;
1390 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1392 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1393 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1396 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1398 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1399 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1400 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1407 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1409 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1410 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1411 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1415 void i915_gem_retire_requests(struct drm_device *dev);
1416 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1417 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1418 bool interruptible);
1420 void i915_gem_reset(struct drm_device *dev);
1421 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1422 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1423 uint32_t read_domains,
1424 uint32_t write_domain);
1425 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1426 int __must_check i915_gem_init(struct drm_device *dev);
1427 int __must_check i915_gem_init_hw(struct drm_device *dev);
1428 void i915_gem_l3_remap(struct drm_device *dev);
1429 void i915_gem_init_swizzling(struct drm_device *dev);
1430 void i915_gem_init_ppgtt(struct drm_device *dev);
1431 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1432 int __must_check i915_gpu_idle(struct drm_device *dev);
1433 int __must_check i915_gem_idle(struct drm_device *dev);
1434 int i915_add_request(struct intel_ring_buffer *ring,
1435 struct drm_file *file,
1437 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1439 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1441 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1444 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1446 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1448 struct intel_ring_buffer *pipelined);
1449 int i915_gem_attach_phys_object(struct drm_device *dev,
1450 struct drm_i915_gem_object *obj,
1453 void i915_gem_detach_phys_object(struct drm_device *dev,
1454 struct drm_i915_gem_object *obj);
1455 void i915_gem_free_all_phys_object(struct drm_device *dev);
1456 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1459 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1463 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1464 enum i915_cache_level cache_level);
1466 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1467 struct dma_buf *dma_buf);
1469 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1470 struct drm_gem_object *gem_obj, int flags);
1472 /* i915_gem_context.c */
1473 void i915_gem_context_init(struct drm_device *dev);
1474 void i915_gem_context_fini(struct drm_device *dev);
1475 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1476 int i915_switch_context(struct intel_ring_buffer *ring,
1477 struct drm_file *file, int to_id);
1478 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1479 struct drm_file *file);
1480 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *file);
1483 /* i915_gem_gtt.c */
1484 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1485 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1486 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1487 struct drm_i915_gem_object *obj,
1488 enum i915_cache_level cache_level);
1489 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1490 struct drm_i915_gem_object *obj);
1492 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1493 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1494 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1495 enum i915_cache_level cache_level);
1496 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1497 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1498 void i915_gem_init_global_gtt(struct drm_device *dev,
1499 unsigned long start,
1500 unsigned long mappable_end,
1503 /* i915_gem_evict.c */
1504 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1506 unsigned cache_level,
1509 int i915_gem_evict_everything(struct drm_device *dev);
1511 /* i915_gem_stolen.c */
1512 int i915_gem_init_stolen(struct drm_device *dev);
1513 void i915_gem_cleanup_stolen(struct drm_device *dev);
1515 /* i915_gem_tiling.c */
1516 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1517 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1518 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1520 /* i915_gem_debug.c */
1521 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1522 const char *where, uint32_t mark);
1524 int i915_verify_lists(struct drm_device *dev);
1526 #define i915_verify_lists(dev) 0
1528 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1530 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1531 const char *where, uint32_t mark);
1533 /* i915_debugfs.c */
1534 int i915_debugfs_init(struct drm_minor *minor);
1535 void i915_debugfs_cleanup(struct drm_minor *minor);
1537 /* i915_suspend.c */
1538 extern int i915_save_state(struct drm_device *dev);
1539 extern int i915_restore_state(struct drm_device *dev);
1541 /* i915_suspend.c */
1542 extern int i915_save_state(struct drm_device *dev);
1543 extern int i915_restore_state(struct drm_device *dev);
1546 void i915_setup_sysfs(struct drm_device *dev_priv);
1547 void i915_teardown_sysfs(struct drm_device *dev_priv);
1550 extern int intel_setup_gmbus(struct drm_device *dev);
1551 extern void intel_teardown_gmbus(struct drm_device *dev);
1552 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1554 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1557 extern struct i2c_adapter *intel_gmbus_get_adapter(
1558 struct drm_i915_private *dev_priv, unsigned port);
1559 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1560 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1561 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1563 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1565 extern void intel_i2c_reset(struct drm_device *dev);
1567 /* intel_opregion.c */
1568 extern int intel_opregion_setup(struct drm_device *dev);
1570 extern void intel_opregion_init(struct drm_device *dev);
1571 extern void intel_opregion_fini(struct drm_device *dev);
1572 extern void intel_opregion_asle_intr(struct drm_device *dev);
1573 extern void intel_opregion_gse_intr(struct drm_device *dev);
1574 extern void intel_opregion_enable_asle(struct drm_device *dev);
1576 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1577 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1578 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1579 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1580 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1585 extern void intel_register_dsm_handler(void);
1586 extern void intel_unregister_dsm_handler(void);
1588 static inline void intel_register_dsm_handler(void) { return; }
1589 static inline void intel_unregister_dsm_handler(void) { return; }
1590 #endif /* CONFIG_ACPI */
1593 extern void intel_modeset_init_hw(struct drm_device *dev);
1594 extern void intel_modeset_init(struct drm_device *dev);
1595 extern void intel_modeset_gem_init(struct drm_device *dev);
1596 extern void intel_modeset_cleanup(struct drm_device *dev);
1597 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1598 extern void intel_modeset_setup_hw_state(struct drm_device *dev);
1599 extern bool intel_fbc_enabled(struct drm_device *dev);
1600 extern void intel_disable_fbc(struct drm_device *dev);
1601 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1602 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1603 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1604 extern void intel_detect_pch(struct drm_device *dev);
1605 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1606 extern int intel_enable_rc6(const struct drm_device *dev);
1608 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1609 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1610 struct drm_file *file);
1613 #ifdef CONFIG_DEBUG_FS
1614 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1615 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1617 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1618 extern void intel_display_print_error_state(struct seq_file *m,
1619 struct drm_device *dev,
1620 struct intel_display_error_state *error);
1623 /* On SNB platform, before reading ring registers forcewake bit
1624 * must be set to prevent GT core from power down and stale values being
1627 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1628 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1629 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1631 #define __i915_read(x, y) \
1632 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1640 #define __i915_write(x, y) \
1641 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1649 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1650 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1652 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1653 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1654 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1655 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1657 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1658 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1659 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1660 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1662 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1663 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1665 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1666 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)