1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170206"
83 #define DRIVER_TIMESTAMP 1486372993
86 /* Many gcc seem to no see through this and fall over :( */
88 #define WARN_ON(x) ({ \
89 bool __i915_warn_cond = (x); \
90 if (__builtin_constant_p(__i915_warn_cond)) \
91 BUILD_BUG_ON(__i915_warn_cond); \
92 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101 (long) (x), __func__);
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 bool __i915_inject_load_failure(const char *func, int line);
122 #define i915_inject_load_failure() \
123 __i915_inject_load_failure(__func__, __LINE__)
127 } uint_fixed_16_16_t;
129 #define FP_16_16_MAX ({ \
130 uint_fixed_16_16_t fp; \
135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
137 uint_fixed_16_16_t fp;
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
147 return DIV_ROUND_UP(fp.val, 1 << 16);
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
156 uint_fixed_16_16_t min2)
158 uint_fixed_16_16_t min;
160 min.val = min(min1.val, min2.val);
164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
165 uint_fixed_16_16_t max2)
167 uint_fixed_16_16_t max;
169 max.val = max(max1.val, max2.val);
173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
176 uint_fixed_16_16_t fp, res;
178 fp = u32_to_fixed_16_16(val);
179 res.val = DIV_ROUND_UP(fp.val, d);
183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
186 uint_fixed_16_16_t res;
189 interm_val = (uint64_t)val << 16;
190 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
191 WARN_ON(interm_val >> 32);
192 res.val = (uint32_t) interm_val;
197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
198 uint_fixed_16_16_t mul)
200 uint64_t intermediate_val;
201 uint_fixed_16_16_t fp;
203 intermediate_val = (uint64_t) val * mul.val;
204 WARN_ON(intermediate_val >> 32);
205 fp.val = (uint32_t) intermediate_val;
209 static inline const char *yesno(bool v)
211 return v ? "yes" : "no";
214 static inline const char *onoff(bool v)
216 return v ? "on" : "off";
219 static inline const char *enableddisabled(bool v)
221 return v ? "enabled" : "disabled";
230 I915_MAX_PIPES = _PIPE_EDP
232 #define pipe_name(p) ((p) + 'A')
244 static inline const char *transcoder_name(enum transcoder transcoder)
246 switch (transcoder) {
255 case TRANSCODER_DSI_A:
257 case TRANSCODER_DSI_C:
264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
266 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
270 * Global legacy plane identifier. Valid only for primary/sprite
271 * planes on pre-g4x, and only for primary planes on g4x+.
278 #define plane_name(p) ((p) + 'A')
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
283 * Per-pipe plane identifier.
284 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285 * number of planes per CRTC. Not all platforms really have this many planes,
286 * which means some arrays of size I915_MAX_PLANES may have unused entries
287 * between the topmost sprite plane and the cursor plane.
289 * This is expected to be passed to various register macros
290 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
301 #define for_each_plane_id_on_crtc(__crtc, __p) \
302 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
303 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
314 #define port_name(p) ((p) + 'A')
316 #define I915_NUM_PHYS_VLV 2
329 enum intel_display_power_domain {
333 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
334 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
335 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
336 POWER_DOMAIN_TRANSCODER_A,
337 POWER_DOMAIN_TRANSCODER_B,
338 POWER_DOMAIN_TRANSCODER_C,
339 POWER_DOMAIN_TRANSCODER_EDP,
340 POWER_DOMAIN_TRANSCODER_DSI_A,
341 POWER_DOMAIN_TRANSCODER_DSI_C,
342 POWER_DOMAIN_PORT_DDI_A_LANES,
343 POWER_DOMAIN_PORT_DDI_B_LANES,
344 POWER_DOMAIN_PORT_DDI_C_LANES,
345 POWER_DOMAIN_PORT_DDI_D_LANES,
346 POWER_DOMAIN_PORT_DDI_E_LANES,
347 POWER_DOMAIN_PORT_DDI_A_IO,
348 POWER_DOMAIN_PORT_DDI_B_IO,
349 POWER_DOMAIN_PORT_DDI_C_IO,
350 POWER_DOMAIN_PORT_DDI_D_IO,
351 POWER_DOMAIN_PORT_DDI_E_IO,
352 POWER_DOMAIN_PORT_DSI,
353 POWER_DOMAIN_PORT_CRT,
354 POWER_DOMAIN_PORT_OTHER,
363 POWER_DOMAIN_MODESET,
369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
371 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
372 #define POWER_DOMAIN_TRANSCODER(tran) \
373 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
374 (tran) + POWER_DOMAIN_TRANSCODER_A)
378 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
390 #define for_each_hpd_pin(__pin) \
391 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
393 #define HPD_STORM_DEFAULT_THRESHOLD 5
395 struct i915_hotplug {
396 struct work_struct hotplug_work;
399 unsigned long last_jiffies;
404 HPD_MARK_DISABLED = 2
406 } stats[HPD_NUM_PINS];
408 struct delayed_work reenable_work;
410 struct intel_digital_port *irq_port[I915_MAX_PORTS];
413 struct work_struct dig_port_work;
415 struct work_struct poll_init_work;
418 unsigned int hpd_storm_threshold;
421 * if we get a HPD irq from DP and a HPD irq from non-DP
422 * the non-DP HPD could block the workqueue on a mode config
423 * mutex getting, that userspace may have taken. However
424 * userspace is waiting on the DP workqueue to run which is
425 * blocked behind the non-DP one.
427 struct workqueue_struct *dp_wq;
430 #define I915_GEM_GPU_DOMAINS \
431 (I915_GEM_DOMAIN_RENDER | \
432 I915_GEM_DOMAIN_SAMPLER | \
433 I915_GEM_DOMAIN_COMMAND | \
434 I915_GEM_DOMAIN_INSTRUCTION | \
435 I915_GEM_DOMAIN_VERTEX)
437 #define for_each_pipe(__dev_priv, __p) \
438 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
440 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
441 for_each_if ((__mask) & (1 << (__p)))
442 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
444 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
446 #define for_each_sprite(__dev_priv, __p, __s) \
448 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
451 #define for_each_port_masked(__port, __ports_mask) \
452 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
453 for_each_if ((__ports_mask) & (1 << (__port)))
455 #define for_each_crtc(dev, crtc) \
456 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
458 #define for_each_intel_plane(dev, intel_plane) \
459 list_for_each_entry(intel_plane, \
460 &(dev)->mode_config.plane_list, \
463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
464 list_for_each_entry(intel_plane, \
465 &(dev)->mode_config.plane_list, \
467 for_each_if ((plane_mask) & \
468 (1 << drm_plane_index(&intel_plane->base)))
470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
471 list_for_each_entry(intel_plane, \
472 &(dev)->mode_config.plane_list, \
474 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
476 #define for_each_intel_crtc(dev, intel_crtc) \
477 list_for_each_entry(intel_crtc, \
478 &(dev)->mode_config.crtc_list, \
481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
482 list_for_each_entry(intel_crtc, \
483 &(dev)->mode_config.crtc_list, \
485 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
487 #define for_each_intel_encoder(dev, intel_encoder) \
488 list_for_each_entry(intel_encoder, \
489 &(dev)->mode_config.encoder_list, \
492 #define for_each_intel_connector(dev, intel_connector) \
493 list_for_each_entry(intel_connector, \
494 &(dev)->mode_config.connector_list, \
497 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
498 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
499 for_each_if ((intel_encoder)->base.crtc == (__crtc))
501 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
502 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
503 for_each_if ((intel_connector)->base.encoder == (__encoder))
505 #define for_each_power_domain(domain, mask) \
506 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
507 for_each_if (BIT_ULL(domain) & (mask))
509 #define for_each_power_well(__dev_priv, __power_well) \
510 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
511 (__power_well) - (__dev_priv)->power_domains.power_wells < \
512 (__dev_priv)->power_domains.power_well_count; \
515 #define for_each_power_well_rev(__dev_priv, __power_well) \
516 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
517 (__dev_priv)->power_domains.power_well_count - 1; \
518 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
521 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
522 for_each_power_well(__dev_priv, __power_well) \
523 for_each_if ((__power_well)->domains & (__domain_mask))
525 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
526 for_each_power_well_rev(__dev_priv, __power_well) \
527 for_each_if ((__power_well)->domains & (__domain_mask))
529 struct drm_i915_private;
530 struct i915_mm_struct;
531 struct i915_mmu_object;
533 struct drm_i915_file_private {
534 struct drm_i915_private *dev_priv;
535 struct drm_file *file;
539 struct list_head request_list;
540 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
541 * chosen to prevent the CPU getting more than a frame ahead of the GPU
542 * (when using lax throttling for the frontbuffer). We also use it to
543 * offer free GPU waitboosts for severely congested workloads.
545 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
547 struct idr context_idr;
549 struct intel_rps_client {
550 struct list_head link;
554 unsigned int bsd_engine;
556 /* Client can have a maximum of 3 contexts banned before
557 * it is denied of creating new contexts. As one context
558 * ban needs 4 consecutive hangs, and more if there is
559 * progress in between, this is a last resort stop gap measure
560 * to limit the badly behaving clients access to gpu.
562 #define I915_MAX_CLIENT_CONTEXT_BANS 3
566 /* Used by dp and fdi links */
567 struct intel_link_m_n {
575 void intel_link_compute_m_n(int bpp, int nlanes,
576 int pixel_clock, int link_clock,
577 struct intel_link_m_n *m_n);
579 /* Interface history:
582 * 1.2: Add Power Management
583 * 1.3: Add vblank support
584 * 1.4: Fix cmdbuffer path, add heap destroy
585 * 1.5: Add vblank pipe configuration
586 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
587 * - Support vertical blank on secondary display pipe
589 #define DRIVER_MAJOR 1
590 #define DRIVER_MINOR 6
591 #define DRIVER_PATCHLEVEL 0
593 struct opregion_header;
594 struct opregion_acpi;
595 struct opregion_swsci;
596 struct opregion_asle;
598 struct intel_opregion {
599 struct opregion_header *header;
600 struct opregion_acpi *acpi;
601 struct opregion_swsci *swsci;
602 u32 swsci_gbda_sub_functions;
603 u32 swsci_sbcb_sub_functions;
604 struct opregion_asle *asle;
609 struct work_struct asle_work;
611 #define OPREGION_SIZE (8*1024)
613 struct intel_overlay;
614 struct intel_overlay_error_state;
616 struct sdvo_device_mapping {
625 struct intel_connector;
626 struct intel_encoder;
627 struct intel_atomic_state;
628 struct intel_crtc_state;
629 struct intel_initial_plane_config;
633 struct intel_cdclk_state;
635 struct drm_i915_display_funcs {
636 void (*get_cdclk)(struct drm_i915_private *dev_priv,
637 struct intel_cdclk_state *cdclk_state);
638 void (*set_cdclk)(struct drm_i915_private *dev_priv,
639 const struct intel_cdclk_state *cdclk_state);
640 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
641 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
642 int (*compute_intermediate_wm)(struct drm_device *dev,
643 struct intel_crtc *intel_crtc,
644 struct intel_crtc_state *newstate);
645 void (*initial_watermarks)(struct intel_atomic_state *state,
646 struct intel_crtc_state *cstate);
647 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
648 struct intel_crtc_state *cstate);
649 void (*optimize_watermarks)(struct intel_atomic_state *state,
650 struct intel_crtc_state *cstate);
651 int (*compute_global_watermarks)(struct drm_atomic_state *state);
652 void (*update_wm)(struct intel_crtc *crtc);
653 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
654 /* Returns the active state of the crtc, and if the crtc is active,
655 * fills out the pipe-config with the hw state. */
656 bool (*get_pipe_config)(struct intel_crtc *,
657 struct intel_crtc_state *);
658 void (*get_initial_plane_config)(struct intel_crtc *,
659 struct intel_initial_plane_config *);
660 int (*crtc_compute_clock)(struct intel_crtc *crtc,
661 struct intel_crtc_state *crtc_state);
662 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
663 struct drm_atomic_state *old_state);
664 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
665 struct drm_atomic_state *old_state);
666 void (*update_crtcs)(struct drm_atomic_state *state,
667 unsigned int *crtc_vblank_mask);
668 void (*audio_codec_enable)(struct drm_connector *connector,
669 struct intel_encoder *encoder,
670 const struct drm_display_mode *adjusted_mode);
671 void (*audio_codec_disable)(struct intel_encoder *encoder);
672 void (*fdi_link_train)(struct drm_crtc *crtc);
673 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
674 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
675 struct drm_framebuffer *fb,
676 struct drm_i915_gem_object *obj,
677 struct drm_i915_gem_request *req,
679 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
680 /* clock updates for mode set */
682 /* render clock increase/decrease */
683 /* display clock increase/decrease */
684 /* pll clock increase/decrease */
686 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
687 void (*load_luts)(struct drm_crtc_state *crtc_state);
690 enum forcewake_domain_id {
691 FW_DOMAIN_ID_RENDER = 0,
692 FW_DOMAIN_ID_BLITTER,
698 enum forcewake_domains {
699 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
700 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
701 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
702 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
707 #define FW_REG_READ (1)
708 #define FW_REG_WRITE (2)
710 enum decoupled_power_domain {
711 GEN9_DECOUPLED_PD_BLITTER = 0,
712 GEN9_DECOUPLED_PD_RENDER,
713 GEN9_DECOUPLED_PD_MEDIA,
714 GEN9_DECOUPLED_PD_ALL
718 GEN9_DECOUPLED_OP_WRITE = 0,
719 GEN9_DECOUPLED_OP_READ
722 enum forcewake_domains
723 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
724 i915_reg_t reg, unsigned int op);
726 struct intel_uncore_funcs {
727 void (*force_wake_get)(struct drm_i915_private *dev_priv,
728 enum forcewake_domains domains);
729 void (*force_wake_put)(struct drm_i915_private *dev_priv,
730 enum forcewake_domains domains);
732 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
733 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
734 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
735 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
737 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
738 uint8_t val, bool trace);
739 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
740 uint16_t val, bool trace);
741 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
742 uint32_t val, bool trace);
745 struct intel_forcewake_range {
749 enum forcewake_domains domains;
752 struct intel_uncore {
753 spinlock_t lock; /** lock is also taken in irq contexts. */
755 const struct intel_forcewake_range *fw_domains_table;
756 unsigned int fw_domains_table_entries;
758 struct intel_uncore_funcs funcs;
762 enum forcewake_domains fw_domains;
763 enum forcewake_domains fw_domains_active;
765 struct intel_uncore_forcewake_domain {
766 struct drm_i915_private *i915;
767 enum forcewake_domain_id id;
768 enum forcewake_domains mask;
770 struct hrtimer timer;
777 } fw_domain[FW_DOMAIN_ID_COUNT];
779 int unclaimed_mmio_check;
782 /* Iterate over initialised fw domains */
783 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
784 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
785 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
787 for_each_if ((mask__) & (domain__)->mask)
789 #define for_each_fw_domain(domain__, dev_priv__) \
790 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
792 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
793 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
794 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
797 struct work_struct work;
799 uint32_t *dmc_payload;
800 uint32_t dmc_fw_size;
803 i915_reg_t mmioaddr[8];
804 uint32_t mmiodata[8];
806 uint32_t allowed_dc_mask;
809 #define DEV_INFO_FOR_EACH_FLAG(func) \
812 func(is_alpha_support); \
813 /* Keep has_* in alphabetical order */ \
814 func(has_64bit_reloc); \
815 func(has_aliasing_ppgtt); \
818 func(has_decoupled_mmio); \
821 func(has_fpga_dbg); \
822 func(has_full_ppgtt); \
823 func(has_full_48bit_ppgtt); \
824 func(has_gmbus_irq); \
825 func(has_gmch_display); \
828 func(has_hw_contexts); \
831 func(has_logical_ring_contexts); \
833 func(has_pipe_cxsr); \
834 func(has_pooled_eu); \
838 func(has_resource_streamer); \
839 func(has_runtime_pm); \
841 func(cursor_needs_physical); \
842 func(hws_needs_physical); \
843 func(overlay_needs_physical); \
846 struct sseu_dev_info {
852 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
855 u8 has_subslice_pg:1;
859 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
861 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
864 /* Keep in gen based order, and chronological order within a gen */
865 enum intel_platform {
866 INTEL_PLATFORM_UNINITIALIZED = 0,
895 struct intel_device_info {
896 u32 display_mmio_offset;
899 u8 num_sprites[I915_MAX_PIPES];
900 u8 num_scalers[I915_MAX_PIPES];
903 enum intel_platform platform;
904 u8 ring_mask; /* Rings supported by the HW */
906 #define DEFINE_FLAG(name) u8 name:1
907 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
909 u16 ddb_size; /* in blocks */
910 /* Register offsets for the various display pipes and transcoders */
911 int pipe_offsets[I915_MAX_TRANSCODERS];
912 int trans_offsets[I915_MAX_TRANSCODERS];
913 int palette_offsets[I915_MAX_PIPES];
914 int cursor_offsets[I915_MAX_PIPES];
916 /* Slice/subslice/EU info */
917 struct sseu_dev_info sseu;
920 u16 degamma_lut_size;
925 struct intel_display_error_state;
927 struct i915_gpu_state {
930 struct timeval boottime;
931 struct timeval uptime;
933 struct drm_i915_private *i915;
940 struct intel_device_info device_info;
941 struct i915_params params;
943 /* Generic register state */
947 u32 gtier[4], ngtier;
951 u32 error; /* gen6+ */
952 u32 err_int; /* gen7 */
953 u32 fault_data0; /* gen8, gen9 */
954 u32 fault_data1; /* gen8, gen9 */
962 u64 fence[I915_MAX_NUM_FENCES];
963 struct intel_overlay_error_state *overlay;
964 struct intel_display_error_state *display;
965 struct drm_i915_error_object *semaphore;
966 struct drm_i915_error_object *guc_log;
968 struct drm_i915_error_engine {
970 /* Software tracked state */
973 unsigned long hangcheck_timestamp;
974 bool hangcheck_stalled;
975 enum intel_engine_hangcheck_action hangcheck_action;
976 struct i915_address_space *vm;
979 /* position of active request inside the ring */
980 u32 rq_head, rq_post, rq_tail;
982 /* our own tracking of ring head and tail */
1005 u32 rc_psmi; /* sleep state */
1006 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1007 struct intel_instdone instdone;
1009 struct drm_i915_error_context {
1010 char comm[TASK_COMM_LEN];
1019 struct drm_i915_error_object {
1025 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1027 struct drm_i915_error_object *wa_ctx;
1029 struct drm_i915_error_request {
1037 } *requests, execlist[2];
1039 struct drm_i915_error_waiter {
1040 char comm[TASK_COMM_LEN];
1052 } engine[I915_NUM_ENGINES];
1054 struct drm_i915_error_buffer {
1057 u32 rseqno[I915_NUM_ENGINES], wseqno;
1061 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1068 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1069 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1070 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1073 enum i915_cache_level {
1074 I915_CACHE_NONE = 0,
1075 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1076 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1077 caches, eg sampler/render caches, and the
1078 large Last-Level-Cache. LLC is coherent with
1079 the CPU, but L3 is only visible to the GPU. */
1080 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1083 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1094 /* This is always the inner lock when overlapping with struct_mutex and
1095 * it's the outer lock when overlapping with stolen_lock. */
1098 unsigned int possible_framebuffer_bits;
1099 unsigned int busy_bits;
1100 unsigned int visible_pipes_mask;
1101 struct intel_crtc *crtc;
1103 struct drm_mm_node compressed_fb;
1104 struct drm_mm_node *compressed_llb;
1111 bool underrun_detected;
1112 struct work_struct underrun_work;
1114 struct intel_fbc_state_cache {
1115 struct i915_vma *vma;
1118 unsigned int mode_flags;
1119 uint32_t hsw_bdw_pixel_rate;
1123 unsigned int rotation;
1130 const struct drm_format_info *format;
1131 unsigned int stride;
1135 struct intel_fbc_reg_params {
1136 struct i915_vma *vma;
1141 unsigned int fence_y_offset;
1145 const struct drm_format_info *format;
1146 unsigned int stride;
1152 struct intel_fbc_work {
1154 u32 scheduled_vblank;
1155 struct work_struct work;
1158 const char *no_fbc_reason;
1162 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1163 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1164 * parsing for same resolution.
1166 enum drrs_refresh_rate_type {
1169 DRRS_MAX_RR, /* RR count */
1172 enum drrs_support_type {
1173 DRRS_NOT_SUPPORTED = 0,
1174 STATIC_DRRS_SUPPORT = 1,
1175 SEAMLESS_DRRS_SUPPORT = 2
1181 struct delayed_work work;
1182 struct intel_dp *dp;
1183 unsigned busy_frontbuffer_bits;
1184 enum drrs_refresh_rate_type refresh_rate_type;
1185 enum drrs_support_type type;
1192 struct intel_dp *enabled;
1194 struct delayed_work work;
1195 unsigned busy_frontbuffer_bits;
1197 bool aux_frame_sync;
1199 bool y_cord_support;
1200 bool colorimetry_support;
1205 PCH_NONE = 0, /* No PCH present */
1206 PCH_IBX, /* Ibexpeak PCH */
1207 PCH_CPT, /* Cougarpoint PCH */
1208 PCH_LPT, /* Lynxpoint PCH */
1209 PCH_SPT, /* Sunrisepoint PCH */
1210 PCH_KBP, /* Kabypoint PCH */
1214 enum intel_sbi_destination {
1219 #define QUIRK_PIPEA_FORCE (1<<0)
1220 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1221 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1222 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1223 #define QUIRK_PIPEB_FORCE (1<<4)
1224 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1227 struct intel_fbc_work;
1229 struct intel_gmbus {
1230 struct i2c_adapter adapter;
1231 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1234 i915_reg_t gpio_reg;
1235 struct i2c_algo_bit_data bit_algo;
1236 struct drm_i915_private *dev_priv;
1239 struct i915_suspend_saved_registers {
1241 u32 saveFBC_CONTROL;
1242 u32 saveCACHE_MODE_0;
1243 u32 saveMI_ARB_STATE;
1247 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1248 u32 savePCH_PORT_HOTPLUG;
1252 struct vlv_s0ix_state {
1259 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1260 u32 media_max_req_count;
1261 u32 gfx_max_req_count;
1287 u32 rp_down_timeout;
1293 /* Display 1 CZ domain */
1298 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1300 /* GT SA CZ domain */
1307 /* Display 2 CZ domain */
1311 u32 clock_gate_dis2;
1314 struct intel_rps_ei {
1320 struct intel_gen6_power_mgmt {
1322 * work, interrupts_enabled and pm_iir are protected by
1323 * dev_priv->irq_lock
1325 struct work_struct work;
1326 bool interrupts_enabled;
1329 /* PM interrupt bits that should never be masked */
1332 /* Frequencies are stored in potentially platform dependent multiples.
1333 * In other words, *_freq needs to be multiplied by X to be interesting.
1334 * Soft limits are those which are used for the dynamic reclocking done
1335 * by the driver (raise frequencies under heavy loads, and lower for
1336 * lighter loads). Hard limits are those imposed by the hardware.
1338 * A distinction is made for overclocking, which is never enabled by
1339 * default, and is considered to be above the hard limit if it's
1342 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1343 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1344 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1345 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1346 u8 min_freq; /* AKA RPn. Minimum frequency */
1347 u8 boost_freq; /* Frequency to request when wait boosting */
1348 u8 idle_freq; /* Frequency to request when we are idle */
1349 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1350 u8 rp1_freq; /* "less than" RP0 power/freqency */
1351 u8 rp0_freq; /* Non-overclocked max frequency. */
1352 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1354 u8 up_threshold; /* Current %busy required to uplock */
1355 u8 down_threshold; /* Current %busy required to downclock */
1358 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1360 spinlock_t client_lock;
1361 struct list_head clients;
1365 struct delayed_work autoenable_work;
1368 /* manual wa residency calculations */
1369 struct intel_rps_ei up_ei, down_ei;
1372 * Protects RPS/RC6 register access and PCU communication.
1373 * Must be taken after struct_mutex if nested. Note that
1374 * this lock may be held for long periods of time when
1375 * talking to hw - so only take it when talking to hw!
1377 struct mutex hw_lock;
1380 /* defined intel_pm.c */
1381 extern spinlock_t mchdev_lock;
1383 struct intel_ilk_power_mgmt {
1391 unsigned long last_time1;
1392 unsigned long chipset_power;
1395 unsigned long gfx_power;
1402 struct drm_i915_private;
1403 struct i915_power_well;
1405 struct i915_power_well_ops {
1407 * Synchronize the well's hw state to match the current sw state, for
1408 * example enable/disable it based on the current refcount. Called
1409 * during driver init and resume time, possibly after first calling
1410 * the enable/disable handlers.
1412 void (*sync_hw)(struct drm_i915_private *dev_priv,
1413 struct i915_power_well *power_well);
1415 * Enable the well and resources that depend on it (for example
1416 * interrupts located on the well). Called after the 0->1 refcount
1419 void (*enable)(struct drm_i915_private *dev_priv,
1420 struct i915_power_well *power_well);
1422 * Disable the well and resources that depend on it. Called after
1423 * the 1->0 refcount transition.
1425 void (*disable)(struct drm_i915_private *dev_priv,
1426 struct i915_power_well *power_well);
1427 /* Returns the hw enabled state. */
1428 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1429 struct i915_power_well *power_well);
1432 /* Power well structure for haswell */
1433 struct i915_power_well {
1436 /* power well enable/disable usage count */
1438 /* cached hw enabled state */
1441 /* unique identifier for this power well */
1444 * Arbitraty data associated with this power well. Platform and power
1448 const struct i915_power_well_ops *ops;
1451 struct i915_power_domains {
1453 * Power wells needed for initialization at driver init and suspend
1454 * time are on. They are kept on until after the first modeset.
1458 int power_well_count;
1461 int domain_use_count[POWER_DOMAIN_NUM];
1462 struct i915_power_well *power_wells;
1465 #define MAX_L3_SLICES 2
1466 struct intel_l3_parity {
1467 u32 *remap_info[MAX_L3_SLICES];
1468 struct work_struct error_work;
1472 struct i915_gem_mm {
1473 /** Memory allocator for GTT stolen memory */
1474 struct drm_mm stolen;
1475 /** Protects the usage of the GTT stolen memory allocator. This is
1476 * always the inner lock when overlapping with struct_mutex. */
1477 struct mutex stolen_lock;
1479 /** List of all objects in gtt_space. Used to restore gtt
1480 * mappings on resume */
1481 struct list_head bound_list;
1483 * List of objects which are not bound to the GTT (thus
1484 * are idle and not used by the GPU). These objects may or may
1485 * not actually have any pages attached.
1487 struct list_head unbound_list;
1489 /** List of all objects in gtt_space, currently mmaped by userspace.
1490 * All objects within this list must also be on bound_list.
1492 struct list_head userfault_list;
1495 * List of objects which are pending destruction.
1497 struct llist_head free_list;
1498 struct work_struct free_work;
1500 /** Usable portion of the GTT for GEM */
1501 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1503 /** PPGTT used for aliasing the PPGTT with the GTT */
1504 struct i915_hw_ppgtt *aliasing_ppgtt;
1506 struct notifier_block oom_notifier;
1507 struct notifier_block vmap_notifier;
1508 struct shrinker shrinker;
1510 /** LRU list of objects with fence regs on them. */
1511 struct list_head fence_list;
1514 * Are we in a non-interruptible section of code like
1519 /* the indicator for dispatch video commands on two BSD rings */
1520 atomic_t bsd_engine_dispatch_index;
1522 /** Bit 6 swizzling required for X tiling */
1523 uint32_t bit_6_swizzle_x;
1524 /** Bit 6 swizzling required for Y tiling */
1525 uint32_t bit_6_swizzle_y;
1527 /* accounting, useful for userland debugging */
1528 spinlock_t object_stat_lock;
1533 struct drm_i915_error_state_buf {
1534 struct drm_i915_private *i915;
1543 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1544 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1546 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1547 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1549 struct i915_gpu_error {
1550 /* For hangcheck timer */
1551 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1552 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1554 struct delayed_work hangcheck_work;
1556 /* For reset and error_state handling. */
1558 /* Protected by the above dev->gpu_error.lock. */
1559 struct i915_gpu_state *first_error;
1561 unsigned long missed_irq_rings;
1564 * State variable controlling the reset flow and count
1566 * This is a counter which gets incremented when reset is triggered,
1568 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1569 * meaning that any waiters holding onto the struct_mutex should
1570 * relinquish the lock immediately in order for the reset to start.
1572 * If reset is not completed succesfully, the I915_WEDGE bit is
1573 * set meaning that hardware is terminally sour and there is no
1574 * recovery. All waiters on the reset_queue will be woken when
1577 * This counter is used by the wait_seqno code to notice that reset
1578 * event happened and it needs to restart the entire ioctl (since most
1579 * likely the seqno it waited for won't ever signal anytime soon).
1581 * This is important for lock-free wait paths, where no contended lock
1582 * naturally enforces the correct ordering between the bail-out of the
1583 * waiter and the gpu reset work code.
1585 unsigned long reset_count;
1587 unsigned long flags;
1588 #define I915_RESET_IN_PROGRESS 0
1589 #define I915_WEDGED (BITS_PER_LONG - 1)
1592 * Waitqueue to signal when a hang is detected. Used to for waiters
1593 * to release the struct_mutex for the reset to procede.
1595 wait_queue_head_t wait_queue;
1598 * Waitqueue to signal when the reset has completed. Used by clients
1599 * that wait for dev_priv->mm.wedged to settle.
1601 wait_queue_head_t reset_queue;
1603 /* For missed irq/seqno simulation. */
1604 unsigned long test_irq_rings;
1607 enum modeset_restore {
1608 MODESET_ON_LID_OPEN,
1613 #define DP_AUX_A 0x40
1614 #define DP_AUX_B 0x10
1615 #define DP_AUX_C 0x20
1616 #define DP_AUX_D 0x30
1618 #define DDC_PIN_B 0x05
1619 #define DDC_PIN_C 0x04
1620 #define DDC_PIN_D 0x06
1622 struct ddi_vbt_port_info {
1624 * This is an index in the HDMI/DVI DDI buffer translation table.
1625 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1626 * populate this field.
1628 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1629 uint8_t hdmi_level_shift;
1631 uint8_t supports_dvi:1;
1632 uint8_t supports_hdmi:1;
1633 uint8_t supports_dp:1;
1634 uint8_t supports_edp:1;
1636 uint8_t alternate_aux_channel;
1637 uint8_t alternate_ddc_pin;
1639 uint8_t dp_boost_level;
1640 uint8_t hdmi_boost_level;
1643 enum psr_lines_to_wait {
1644 PSR_0_LINES_TO_WAIT = 0,
1646 PSR_4_LINES_TO_WAIT,
1650 struct intel_vbt_data {
1651 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1652 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1655 unsigned int int_tv_support:1;
1656 unsigned int lvds_dither:1;
1657 unsigned int lvds_vbt:1;
1658 unsigned int int_crt_support:1;
1659 unsigned int lvds_use_ssc:1;
1660 unsigned int display_clock_mode:1;
1661 unsigned int fdi_rx_polarity_inverted:1;
1662 unsigned int panel_type:4;
1664 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1666 enum drrs_support_type drrs_type;
1677 struct edp_power_seq pps;
1682 bool require_aux_wakeup;
1684 enum psr_lines_to_wait lines_to_wait;
1685 int tp1_wakeup_time;
1686 int tp2_tp3_wakeup_time;
1692 bool active_low_pwm;
1693 u8 min_brightness; /* min_brightness/255 of max */
1694 u8 controller; /* brightness controller number */
1695 enum intel_backlight_type type;
1701 struct mipi_config *config;
1702 struct mipi_pps_data *pps;
1706 const u8 *sequence[MIPI_SEQ_MAX];
1712 union child_device_config *child_dev;
1714 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1715 struct sdvo_device_mapping sdvo_mappings[2];
1718 enum intel_ddb_partitioning {
1720 INTEL_DDB_PART_5_6, /* IVB+ */
1723 struct intel_wm_level {
1731 struct ilk_wm_values {
1732 uint32_t wm_pipe[3];
1734 uint32_t wm_lp_spr[3];
1735 uint32_t wm_linetime[3];
1737 enum intel_ddb_partitioning partitioning;
1740 struct vlv_pipe_wm {
1741 uint16_t plane[I915_MAX_PLANES];
1749 struct vlv_wm_ddl_values {
1750 uint8_t plane[I915_MAX_PLANES];
1753 struct vlv_wm_values {
1754 struct vlv_pipe_wm pipe[3];
1755 struct vlv_sr_wm sr;
1756 struct vlv_wm_ddl_values ddl[3];
1761 struct skl_ddb_entry {
1762 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1765 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1767 return entry->end - entry->start;
1770 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1771 const struct skl_ddb_entry *e2)
1773 if (e1->start == e2->start && e1->end == e2->end)
1779 struct skl_ddb_allocation {
1780 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1781 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1784 struct skl_wm_values {
1785 unsigned dirty_pipes;
1786 struct skl_ddb_allocation ddb;
1789 struct skl_wm_level {
1791 uint16_t plane_res_b;
1792 uint8_t plane_res_l;
1796 * This struct helps tracking the state needed for runtime PM, which puts the
1797 * device in PCI D3 state. Notice that when this happens, nothing on the
1798 * graphics device works, even register access, so we don't get interrupts nor
1801 * Every piece of our code that needs to actually touch the hardware needs to
1802 * either call intel_runtime_pm_get or call intel_display_power_get with the
1803 * appropriate power domain.
1805 * Our driver uses the autosuspend delay feature, which means we'll only really
1806 * suspend if we stay with zero refcount for a certain amount of time. The
1807 * default value is currently very conservative (see intel_runtime_pm_enable), but
1808 * it can be changed with the standard runtime PM files from sysfs.
1810 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1811 * goes back to false exactly before we reenable the IRQs. We use this variable
1812 * to check if someone is trying to enable/disable IRQs while they're supposed
1813 * to be disabled. This shouldn't happen and we'll print some error messages in
1816 * For more, read the Documentation/power/runtime_pm.txt.
1818 struct i915_runtime_pm {
1819 atomic_t wakeref_count;
1824 enum intel_pipe_crc_source {
1825 INTEL_PIPE_CRC_SOURCE_NONE,
1826 INTEL_PIPE_CRC_SOURCE_PLANE1,
1827 INTEL_PIPE_CRC_SOURCE_PLANE2,
1828 INTEL_PIPE_CRC_SOURCE_PF,
1829 INTEL_PIPE_CRC_SOURCE_PIPE,
1830 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1831 INTEL_PIPE_CRC_SOURCE_TV,
1832 INTEL_PIPE_CRC_SOURCE_DP_B,
1833 INTEL_PIPE_CRC_SOURCE_DP_C,
1834 INTEL_PIPE_CRC_SOURCE_DP_D,
1835 INTEL_PIPE_CRC_SOURCE_AUTO,
1836 INTEL_PIPE_CRC_SOURCE_MAX,
1839 struct intel_pipe_crc_entry {
1844 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1845 struct intel_pipe_crc {
1847 bool opened; /* exclusive access to the result file */
1848 struct intel_pipe_crc_entry *entries;
1849 enum intel_pipe_crc_source source;
1851 wait_queue_head_t wq;
1855 struct i915_frontbuffer_tracking {
1859 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1866 struct i915_wa_reg {
1869 /* bitmask representing WA bits */
1874 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1875 * allowing it for RCS as we don't foresee any requirement of having
1876 * a whitelist for other engines. When it is really required for
1877 * other engines then the limit need to be increased.
1879 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1881 struct i915_workarounds {
1882 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1884 u32 hw_whitelist_count[I915_NUM_ENGINES];
1887 struct i915_virtual_gpu {
1891 /* used in computing the new watermarks state */
1892 struct intel_wm_config {
1893 unsigned int num_pipes_active;
1894 bool sprites_enabled;
1895 bool sprites_scaled;
1898 struct i915_oa_format {
1903 struct i915_oa_reg {
1908 struct i915_perf_stream;
1911 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1913 struct i915_perf_stream_ops {
1915 * @enable: Enables the collection of HW samples, either in response to
1916 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1917 * without `I915_PERF_FLAG_DISABLED`.
1919 void (*enable)(struct i915_perf_stream *stream);
1922 * @disable: Disables the collection of HW samples, either in response
1923 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1926 void (*disable)(struct i915_perf_stream *stream);
1929 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1930 * once there is something ready to read() for the stream
1932 void (*poll_wait)(struct i915_perf_stream *stream,
1937 * @wait_unlocked: For handling a blocking read, wait until there is
1938 * something to ready to read() for the stream. E.g. wait on the same
1939 * wait queue that would be passed to poll_wait().
1941 int (*wait_unlocked)(struct i915_perf_stream *stream);
1944 * @read: Copy buffered metrics as records to userspace
1945 * **buf**: the userspace, destination buffer
1946 * **count**: the number of bytes to copy, requested by userspace
1947 * **offset**: zero at the start of the read, updated as the read
1948 * proceeds, it represents how many bytes have been copied so far and
1949 * the buffer offset for copying the next record.
1951 * Copy as many buffered i915 perf samples and records for this stream
1952 * to userspace as will fit in the given buffer.
1954 * Only write complete records; returning -%ENOSPC if there isn't room
1955 * for a complete record.
1957 * Return any error condition that results in a short read such as
1958 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1959 * returning to userspace.
1961 int (*read)(struct i915_perf_stream *stream,
1967 * @destroy: Cleanup any stream specific resources.
1969 * The stream will always be disabled before this is called.
1971 void (*destroy)(struct i915_perf_stream *stream);
1975 * struct i915_perf_stream - state for a single open stream FD
1977 struct i915_perf_stream {
1979 * @dev_priv: i915 drm device
1981 struct drm_i915_private *dev_priv;
1984 * @link: Links the stream into ``&drm_i915_private->streams``
1986 struct list_head link;
1989 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1990 * properties given when opening a stream, representing the contents
1991 * of a single sample as read() by userspace.
1996 * @sample_size: Considering the configured contents of a sample
1997 * combined with the required header size, this is the total size
1998 * of a single sample record.
2003 * @ctx: %NULL if measuring system-wide across all contexts or a
2004 * specific context that is being monitored.
2006 struct i915_gem_context *ctx;
2009 * @enabled: Whether the stream is currently enabled, considering
2010 * whether the stream was opened in a disabled state and based
2011 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2016 * @ops: The callbacks providing the implementation of this specific
2017 * type of configured stream.
2019 const struct i915_perf_stream_ops *ops;
2023 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2025 struct i915_oa_ops {
2027 * @init_oa_buffer: Resets the head and tail pointers of the
2028 * circular buffer for periodic OA reports.
2030 * Called when first opening a stream for OA metrics, but also may be
2031 * called in response to an OA buffer overflow or other error
2034 * Note it may be necessary to clear the full OA buffer here as part of
2035 * maintaining the invariable that new reports must be written to
2036 * zeroed memory for us to be able to reliable detect if an expected
2037 * report has not yet landed in memory. (At least on Haswell the OA
2038 * buffer tail pointer is not synchronized with reports being visible
2041 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2044 * @enable_metric_set: Applies any MUX configuration to set up the
2045 * Boolean and Custom (B/C) counters that are part of the counter
2046 * reports being sampled. May apply system constraints such as
2047 * disabling EU clock gating as required.
2049 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2052 * @disable_metric_set: Remove system constraints associated with using
2055 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2058 * @oa_enable: Enable periodic sampling
2060 void (*oa_enable)(struct drm_i915_private *dev_priv);
2063 * @oa_disable: Disable periodic sampling
2065 void (*oa_disable)(struct drm_i915_private *dev_priv);
2068 * @read: Copy data from the circular OA buffer into a given userspace
2071 int (*read)(struct i915_perf_stream *stream,
2077 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2079 * This is either called via fops or the poll check hrtimer (atomic
2080 * ctx) without any locks taken.
2082 * It's safe to read OA config state here unlocked, assuming that this
2083 * is only called while the stream is enabled, while the global OA
2084 * configuration can't be modified.
2086 * Efficiency is more important than avoiding some false positives
2087 * here, which will be handled gracefully - likely resulting in an
2088 * %EAGAIN error for userspace.
2090 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2093 struct intel_cdclk_state {
2094 unsigned int cdclk, vco, ref;
2097 struct drm_i915_private {
2098 struct drm_device drm;
2100 struct kmem_cache *objects;
2101 struct kmem_cache *vmas;
2102 struct kmem_cache *requests;
2103 struct kmem_cache *dependencies;
2105 const struct intel_device_info info;
2109 struct intel_uncore uncore;
2111 struct i915_virtual_gpu vgpu;
2113 struct intel_gvt *gvt;
2115 struct intel_huc huc;
2116 struct intel_guc guc;
2118 struct intel_csr csr;
2120 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2122 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2123 * controller on different i2c buses. */
2124 struct mutex gmbus_mutex;
2127 * Base address of the gmbus and gpio block.
2129 uint32_t gpio_mmio_base;
2131 /* MMIO base address for MIPI regs */
2132 uint32_t mipi_mmio_base;
2134 uint32_t psr_mmio_base;
2136 uint32_t pps_mmio_base;
2138 wait_queue_head_t gmbus_wait_queue;
2140 struct pci_dev *bridge_dev;
2141 struct i915_gem_context *kernel_context;
2142 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2143 struct i915_vma *semaphore;
2145 struct drm_dma_handle *status_page_dmah;
2146 struct resource mch_res;
2148 /* protects the irq masks */
2149 spinlock_t irq_lock;
2151 /* protects the mmio flip data */
2152 spinlock_t mmio_flip_lock;
2154 bool display_irqs_enabled;
2156 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2157 struct pm_qos_request pm_qos;
2159 /* Sideband mailbox protection */
2160 struct mutex sb_lock;
2162 /** Cached value of IMR to avoid reads in updating the bitfield */
2165 u32 de_irq_mask[I915_MAX_PIPES];
2172 u32 pipestat_irq_mask[I915_MAX_PIPES];
2174 struct i915_hotplug hotplug;
2175 struct intel_fbc fbc;
2176 struct i915_drrs drrs;
2177 struct intel_opregion opregion;
2178 struct intel_vbt_data vbt;
2180 bool preserve_bios_swizzle;
2183 struct intel_overlay *overlay;
2185 /* backlight registers and fields in struct intel_panel */
2186 struct mutex backlight_lock;
2189 bool no_aux_handshake;
2191 /* protects panel power sequencer state */
2192 struct mutex pps_mutex;
2194 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2195 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2197 unsigned int fsb_freq, mem_freq, is_ddr3;
2198 unsigned int skl_preferred_vco_freq;
2199 unsigned int max_cdclk_freq;
2201 unsigned int max_dotclk_freq;
2202 unsigned int rawclk_freq;
2203 unsigned int hpll_freq;
2204 unsigned int czclk_freq;
2208 * The current logical cdclk state.
2209 * See intel_atomic_state.cdclk.logical
2211 * For reading holding any crtc lock is sufficient,
2212 * for writing must hold all of them.
2214 struct intel_cdclk_state logical;
2216 * The current actual cdclk state.
2217 * See intel_atomic_state.cdclk.actual
2219 struct intel_cdclk_state actual;
2220 /* The current hardware cdclk state */
2221 struct intel_cdclk_state hw;
2225 * wq - Driver workqueue for GEM.
2227 * NOTE: Work items scheduled here are not allowed to grab any modeset
2228 * locks, for otherwise the flushing done in the pageflip code will
2229 * result in deadlocks.
2231 struct workqueue_struct *wq;
2233 /* Display functions */
2234 struct drm_i915_display_funcs display;
2236 /* PCH chipset type */
2237 enum intel_pch pch_type;
2238 unsigned short pch_id;
2240 unsigned long quirks;
2242 enum modeset_restore modeset_restore;
2243 struct mutex modeset_restore_lock;
2244 struct drm_atomic_state *modeset_restore_state;
2245 struct drm_modeset_acquire_ctx reset_ctx;
2247 struct list_head vm_list; /* Global list of all address spaces */
2248 struct i915_ggtt ggtt; /* VM representing the global address space */
2250 struct i915_gem_mm mm;
2251 DECLARE_HASHTABLE(mm_structs, 7);
2252 struct mutex mm_lock;
2254 /* The hw wants to have a stable context identifier for the lifetime
2255 * of the context (for OA, PASID, faults, etc). This is limited
2256 * in execlists to 21 bits.
2258 struct ida context_hw_ida;
2259 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2261 /* Kernel Modesetting */
2263 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2264 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2265 wait_queue_head_t pending_flip_queue;
2267 #ifdef CONFIG_DEBUG_FS
2268 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2271 /* dpll and cdclk state is protected by connection_mutex */
2272 int num_shared_dpll;
2273 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2274 const struct intel_dpll_mgr *dpll_mgr;
2277 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2278 * Must be global rather than per dpll, because on some platforms
2279 * plls share registers.
2281 struct mutex dpll_lock;
2283 unsigned int active_crtcs;
2284 unsigned int min_pixclk[I915_MAX_PIPES];
2286 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2288 struct i915_workarounds workarounds;
2290 struct i915_frontbuffer_tracking fb_tracking;
2292 struct intel_atomic_helper {
2293 struct llist_head free_list;
2294 struct work_struct free_work;
2299 bool mchbar_need_disable;
2301 struct intel_l3_parity l3_parity;
2303 /* Cannot be determined by PCIID. You must always read a register. */
2306 /* gen6+ rps state */
2307 struct intel_gen6_power_mgmt rps;
2309 /* ilk-only ips/rps state. Everything in here is protected by the global
2310 * mchdev_lock in intel_pm.c */
2311 struct intel_ilk_power_mgmt ips;
2313 struct i915_power_domains power_domains;
2315 struct i915_psr psr;
2317 struct i915_gpu_error gpu_error;
2319 struct drm_i915_gem_object *vlv_pctx;
2321 #ifdef CONFIG_DRM_FBDEV_EMULATION
2322 /* list of fbdev register on this device */
2323 struct intel_fbdev *fbdev;
2324 struct work_struct fbdev_suspend_work;
2327 struct drm_property *broadcast_rgb_property;
2328 struct drm_property *force_audio_property;
2330 /* hda/i915 audio component */
2331 struct i915_audio_component *audio_component;
2332 bool audio_component_registered;
2334 * av_mutex - mutex for audio/video sync
2337 struct mutex av_mutex;
2339 uint32_t hw_context_size;
2340 struct list_head context_list;
2344 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2345 u32 chv_phy_control;
2347 * Shadows for CHV DPLL_MD regs to keep the state
2348 * checker somewhat working in the presence hardware
2349 * crappiness (can't read out DPLL_MD for pipes B & C).
2351 u32 chv_dpll_md[I915_MAX_PIPES];
2355 bool suspended_to_idle;
2356 struct i915_suspend_saved_registers regfile;
2357 struct vlv_s0ix_state vlv_s0ix_state;
2360 I915_SAGV_UNKNOWN = 0,
2363 I915_SAGV_NOT_CONTROLLED
2367 /* protects DSPARB registers on pre-g4x/vlv/chv */
2368 spinlock_t dsparb_lock;
2371 * Raw watermark latency values:
2372 * in 0.1us units for WM0,
2373 * in 0.5us units for WM1+.
2376 uint16_t pri_latency[5];
2378 uint16_t spr_latency[5];
2380 uint16_t cur_latency[5];
2382 * Raw watermark memory latency values
2383 * for SKL for all 8 levels
2386 uint16_t skl_latency[8];
2388 /* current hardware state */
2390 struct ilk_wm_values hw;
2391 struct skl_wm_values skl_hw;
2392 struct vlv_wm_values vlv;
2398 * Should be held around atomic WM register writing; also
2399 * protects * intel_crtc->wm.active and
2400 * cstate->wm.need_postvbl_update.
2402 struct mutex wm_mutex;
2405 * Set during HW readout of watermarks/DDB. Some platforms
2406 * need to know when we're still using BIOS-provided values
2407 * (which we don't fully trust).
2409 bool distrust_bios_wm;
2412 struct i915_runtime_pm pm;
2417 struct kobject *metrics_kobj;
2418 struct ctl_table_header *sysctl_header;
2421 struct list_head streams;
2423 spinlock_t hook_lock;
2426 struct i915_perf_stream *exclusive_stream;
2428 u32 specific_ctx_id;
2430 struct hrtimer poll_check_timer;
2431 wait_queue_head_t poll_wq;
2435 int period_exponent;
2436 int timestamp_frequency;
2442 const struct i915_oa_reg *mux_regs;
2444 const struct i915_oa_reg *b_counter_regs;
2445 int b_counter_regs_len;
2448 struct i915_vma *vma;
2454 u32 gen7_latched_oastatus1;
2456 struct i915_oa_ops ops;
2457 const struct i915_oa_format *oa_formats;
2462 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2464 void (*resume)(struct drm_i915_private *);
2465 void (*cleanup_engine)(struct intel_engine_cs *engine);
2467 struct list_head timelines;
2468 struct i915_gem_timeline global_timeline;
2469 u32 active_requests;
2472 * Is the GPU currently considered idle, or busy executing
2473 * userspace requests? Whilst idle, we allow runtime power
2474 * management to power down the hardware and display clocks.
2475 * In order to reduce the effect on performance, there
2476 * is a slight delay before we do so.
2481 * We leave the user IRQ off as much as possible,
2482 * but this means that requests will finish and never
2483 * be retired once the system goes idle. Set a timer to
2484 * fire periodically while the ring is running. When it
2485 * fires, go retire requests.
2487 struct delayed_work retire_work;
2490 * When we detect an idle GPU, we want to turn on
2491 * powersaving features. So once we see that there
2492 * are no more requests outstanding and no more
2493 * arrive within a small period of time, we fire
2494 * off the idle_work.
2496 struct delayed_work idle_work;
2498 ktime_t last_init_time;
2501 /* perform PHY state sanity checks? */
2502 bool chv_phy_assert[2];
2506 /* Used to save the pipe-to-encoder mapping for audio */
2507 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2510 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2511 * will be rejected. Instead look for a better place.
2515 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2517 return container_of(dev, struct drm_i915_private, drm);
2520 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2522 return to_i915(dev_get_drvdata(kdev));
2525 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2527 return container_of(guc, struct drm_i915_private, guc);
2530 /* Simple iterator over all initialised engines */
2531 #define for_each_engine(engine__, dev_priv__, id__) \
2533 (id__) < I915_NUM_ENGINES; \
2535 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2537 #define __mask_next_bit(mask) ({ \
2538 int __idx = ffs(mask) - 1; \
2539 mask &= ~BIT(__idx); \
2543 /* Iterator over subset of engines selected by mask */
2544 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2545 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2546 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2548 enum hdmi_force_audio {
2549 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2550 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2551 HDMI_AUDIO_AUTO, /* trust EDID */
2552 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2555 #define I915_GTT_OFFSET_NONE ((u32)-1)
2558 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2559 * considered to be the frontbuffer for the given plane interface-wise. This
2560 * doesn't mean that the hw necessarily already scans it out, but that any
2561 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2563 * We have one bit per pipe and per scanout plane type.
2565 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2566 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2567 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2568 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2569 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2570 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2571 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2572 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2573 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2574 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2575 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2576 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2579 * Optimised SGL iterator for GEM objects
2581 static __always_inline struct sgt_iter {
2582 struct scatterlist *sgp;
2589 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2590 struct sgt_iter s = { .sgp = sgl };
2593 s.max = s.curr = s.sgp->offset;
2594 s.max += s.sgp->length;
2596 s.dma = sg_dma_address(s.sgp);
2598 s.pfn = page_to_pfn(sg_page(s.sgp));
2604 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2607 if (unlikely(sg_is_chain(sg)))
2608 sg = sg_chain_ptr(sg);
2613 * __sg_next - return the next scatterlist entry in a list
2614 * @sg: The current sg entry
2617 * If the entry is the last, return NULL; otherwise, step to the next
2618 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2619 * otherwise just return the pointer to the current element.
2621 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2623 #ifdef CONFIG_DEBUG_SG
2624 BUG_ON(sg->sg_magic != SG_MAGIC);
2626 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2630 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2631 * @__dmap: DMA address (output)
2632 * @__iter: 'struct sgt_iter' (iterator state, internal)
2633 * @__sgt: sg_table to iterate over (input)
2635 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2636 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2637 ((__dmap) = (__iter).dma + (__iter).curr); \
2638 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2639 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2642 * for_each_sgt_page - iterate over the pages of the given sg_table
2643 * @__pp: page pointer (output)
2644 * @__iter: 'struct sgt_iter' (iterator state, internal)
2645 * @__sgt: sg_table to iterate over (input)
2647 #define for_each_sgt_page(__pp, __iter, __sgt) \
2648 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2649 ((__pp) = (__iter).pfn == 0 ? NULL : \
2650 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2651 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2652 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2654 static inline const struct intel_device_info *
2655 intel_info(const struct drm_i915_private *dev_priv)
2657 return &dev_priv->info;
2660 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2662 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2663 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2665 #define REVID_FOREVER 0xff
2666 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2668 #define GEN_FOREVER (0)
2670 * Returns true if Gen is in inclusive range [Start, End].
2672 * Use GEN_FOREVER for unbound start and or end.
2674 #define IS_GEN(dev_priv, s, e) ({ \
2675 unsigned int __s = (s), __e = (e); \
2676 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2677 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2678 if ((__s) != GEN_FOREVER) \
2680 if ((__e) == GEN_FOREVER) \
2681 __e = BITS_PER_LONG - 1; \
2684 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2688 * Return true if revision is in range [since,until] inclusive.
2690 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2692 #define IS_REVID(p, since, until) \
2693 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2695 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2696 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2697 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2698 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2699 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2700 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2701 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2702 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2703 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2704 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2705 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2706 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2707 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2708 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2709 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2710 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2711 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2712 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2713 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2714 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2715 INTEL_DEVID(dev_priv) == 0x0152 || \
2716 INTEL_DEVID(dev_priv) == 0x015a)
2717 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2718 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2719 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2720 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2721 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2722 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2723 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2724 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2725 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2726 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2727 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2728 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2729 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2730 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2731 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2732 /* ULX machines are also considered ULT. */
2733 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2734 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2735 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2736 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2737 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2738 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2739 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2740 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2741 /* ULX machines are also considered ULT. */
2742 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2743 INTEL_DEVID(dev_priv) == 0x0A1E)
2744 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2745 INTEL_DEVID(dev_priv) == 0x1913 || \
2746 INTEL_DEVID(dev_priv) == 0x1916 || \
2747 INTEL_DEVID(dev_priv) == 0x1921 || \
2748 INTEL_DEVID(dev_priv) == 0x1926)
2749 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2750 INTEL_DEVID(dev_priv) == 0x1915 || \
2751 INTEL_DEVID(dev_priv) == 0x191E)
2752 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2753 INTEL_DEVID(dev_priv) == 0x5913 || \
2754 INTEL_DEVID(dev_priv) == 0x5916 || \
2755 INTEL_DEVID(dev_priv) == 0x5921 || \
2756 INTEL_DEVID(dev_priv) == 0x5926)
2757 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2758 INTEL_DEVID(dev_priv) == 0x5915 || \
2759 INTEL_DEVID(dev_priv) == 0x591E)
2760 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2761 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2762 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2763 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2765 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2767 #define SKL_REVID_A0 0x0
2768 #define SKL_REVID_B0 0x1
2769 #define SKL_REVID_C0 0x2
2770 #define SKL_REVID_D0 0x3
2771 #define SKL_REVID_E0 0x4
2772 #define SKL_REVID_F0 0x5
2773 #define SKL_REVID_G0 0x6
2774 #define SKL_REVID_H0 0x7
2776 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2778 #define BXT_REVID_A0 0x0
2779 #define BXT_REVID_A1 0x1
2780 #define BXT_REVID_B0 0x3
2781 #define BXT_REVID_B_LAST 0x8
2782 #define BXT_REVID_C0 0x9
2784 #define IS_BXT_REVID(dev_priv, since, until) \
2785 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2787 #define KBL_REVID_A0 0x0
2788 #define KBL_REVID_B0 0x1
2789 #define KBL_REVID_C0 0x2
2790 #define KBL_REVID_D0 0x3
2791 #define KBL_REVID_E0 0x4
2793 #define IS_KBL_REVID(dev_priv, since, until) \
2794 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2796 #define GLK_REVID_A0 0x0
2797 #define GLK_REVID_A1 0x1
2799 #define IS_GLK_REVID(dev_priv, since, until) \
2800 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2803 * The genX designation typically refers to the render engine, so render
2804 * capability related checks should use IS_GEN, while display and other checks
2805 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2808 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2809 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2810 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2811 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2812 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2813 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2814 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2815 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2817 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2818 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2819 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2821 #define ENGINE_MASK(id) BIT(id)
2822 #define RENDER_RING ENGINE_MASK(RCS)
2823 #define BSD_RING ENGINE_MASK(VCS)
2824 #define BLT_RING ENGINE_MASK(BCS)
2825 #define VEBOX_RING ENGINE_MASK(VECS)
2826 #define BSD2_RING ENGINE_MASK(VCS2)
2827 #define ALL_ENGINES (~0)
2829 #define HAS_ENGINE(dev_priv, id) \
2830 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2832 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2833 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2834 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2835 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2837 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2838 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2839 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2840 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2841 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2843 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2845 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2846 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2847 ((dev_priv)->info.has_logical_ring_contexts)
2848 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2849 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2850 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2852 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2853 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2854 ((dev_priv)->info.overlay_needs_physical)
2856 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2857 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2859 /* WaRsDisableCoarsePowerGating:skl,bxt */
2860 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2861 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2864 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2865 * even when in MSI mode. This results in spurious interrupt warnings if the
2866 * legacy irq no. is shared with another device. The kernel then disables that
2867 * interrupt source and so prevents the other device from working properly.
2869 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2870 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2872 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2873 * rows, which changed the alignment requirements and fence programming.
2875 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2876 !(IS_I915G(dev_priv) || \
2877 IS_I915GM(dev_priv)))
2878 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2879 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2881 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2882 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2883 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2885 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2887 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2889 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2890 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2891 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2892 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2893 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2895 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2897 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2898 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2901 * For now, anything with a GuC requires uCode loading, and then supports
2902 * command submission once loaded. But these are logically independent
2903 * properties, so we have separate macros to test them.
2905 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2906 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2907 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2908 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2910 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2912 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2914 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2915 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2916 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2917 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2918 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2919 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2920 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2921 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2922 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2923 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2924 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2925 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2927 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2928 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2929 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2930 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2931 #define HAS_PCH_LPT_LP(dev_priv) \
2932 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2933 #define HAS_PCH_LPT_H(dev_priv) \
2934 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2935 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2936 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2937 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2938 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2940 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2942 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2944 /* DPF == dynamic parity feature */
2945 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2946 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2947 2 : HAS_L3_DPF(dev_priv))
2949 #define GT_FREQUENCY_MULTIPLIER 50
2950 #define GEN9_FREQ_SCALER 3
2952 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2954 #include "i915_trace.h"
2956 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2958 #ifdef CONFIG_INTEL_IOMMU
2959 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2965 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2968 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2972 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2973 const char *fmt, ...);
2975 #define i915_report_error(dev_priv, fmt, ...) \
2976 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2978 #ifdef CONFIG_COMPAT
2979 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2982 #define i915_compat_ioctl NULL
2984 extern const struct dev_pm_ops i915_pm_ops;
2986 extern int i915_driver_load(struct pci_dev *pdev,
2987 const struct pci_device_id *ent);
2988 extern void i915_driver_unload(struct drm_device *dev);
2989 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2990 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2991 extern void i915_reset(struct drm_i915_private *dev_priv);
2992 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2993 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2994 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2995 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2996 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2997 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2998 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2999 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3001 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3002 int intel_engines_init(struct drm_i915_private *dev_priv);
3004 /* intel_hotplug.c */
3005 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3006 u32 pin_mask, u32 long_mask);
3007 void intel_hpd_init(struct drm_i915_private *dev_priv);
3008 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3009 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3010 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3011 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3012 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3015 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3017 unsigned long delay;
3019 if (unlikely(!i915.enable_hangcheck))
3022 /* Don't continually defer the hangcheck so that it is always run at
3023 * least once after work has been scheduled on any ring. Otherwise,
3024 * we will ignore a hung ring if a second ring is kept busy.
3027 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3028 queue_delayed_work(system_long_wq,
3029 &dev_priv->gpu_error.hangcheck_work, delay);
3033 void i915_handle_error(struct drm_i915_private *dev_priv,
3035 const char *fmt, ...);
3037 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3038 int intel_irq_install(struct drm_i915_private *dev_priv);
3039 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3041 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3042 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3043 bool restore_forcewake);
3044 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3045 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3046 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3047 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3048 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3050 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3051 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3052 enum forcewake_domains domains);
3053 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3054 enum forcewake_domains domains);
3055 /* Like above but the caller must manage the uncore.lock itself.
3056 * Must be used with I915_READ_FW and friends.
3058 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3059 enum forcewake_domains domains);
3060 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3061 enum forcewake_domains domains);
3062 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3064 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3066 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3070 const unsigned long timeout_ms);
3071 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3075 const unsigned long timeout_ms);
3077 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3079 return dev_priv->gvt;
3082 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3084 return dev_priv->vgpu.active;
3088 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3092 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3095 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3096 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3097 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3100 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3101 uint32_t interrupt_mask,
3102 uint32_t enabled_irq_mask);
3104 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3106 ilk_update_display_irq(dev_priv, bits, bits);
3109 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3111 ilk_update_display_irq(dev_priv, bits, 0);
3113 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3115 uint32_t interrupt_mask,
3116 uint32_t enabled_irq_mask);
3117 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3118 enum pipe pipe, uint32_t bits)
3120 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3122 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3123 enum pipe pipe, uint32_t bits)
3125 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3127 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3128 uint32_t interrupt_mask,
3129 uint32_t enabled_irq_mask);
3131 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3133 ibx_display_interrupt_update(dev_priv, bits, bits);
3136 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3138 ibx_display_interrupt_update(dev_priv, bits, 0);
3142 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3143 struct drm_file *file_priv);
3144 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3145 struct drm_file *file_priv);
3146 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3147 struct drm_file *file_priv);
3148 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3149 struct drm_file *file_priv);
3150 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3151 struct drm_file *file_priv);
3152 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3153 struct drm_file *file_priv);
3154 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3155 struct drm_file *file_priv);
3156 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3157 struct drm_file *file_priv);
3158 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3159 struct drm_file *file_priv);
3160 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3161 struct drm_file *file_priv);
3162 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3163 struct drm_file *file);
3164 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3165 struct drm_file *file);
3166 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3167 struct drm_file *file_priv);
3168 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3169 struct drm_file *file_priv);
3170 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3171 struct drm_file *file_priv);
3172 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3173 struct drm_file *file_priv);
3174 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3175 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3176 struct drm_file *file);
3177 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3178 struct drm_file *file_priv);
3179 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3180 struct drm_file *file_priv);
3181 void i915_gem_sanitize(struct drm_i915_private *i915);
3182 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3183 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3184 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3185 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3186 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3188 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3189 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3190 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3191 const struct drm_i915_gem_object_ops *ops);
3192 struct drm_i915_gem_object *
3193 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3194 struct drm_i915_gem_object *
3195 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3196 const void *data, size_t size);
3197 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3198 void i915_gem_free_object(struct drm_gem_object *obj);
3200 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3202 /* A single pass should suffice to release all the freed objects (along
3203 * most call paths) , but be a little more paranoid in that freeing
3204 * the objects does take a little amount of time, during which the rcu
3205 * callbacks could have added new objects into the freed list, and
3206 * armed the work again.
3210 } while (flush_work(&i915->mm.free_work));
3213 struct i915_vma * __must_check
3214 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3215 const struct i915_ggtt_view *view,
3220 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3221 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3223 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3225 static inline int __sg_page_count(const struct scatterlist *sg)
3227 return sg->length >> PAGE_SHIFT;
3230 struct scatterlist *
3231 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3232 unsigned int n, unsigned int *offset);
3235 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3239 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3243 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3246 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3247 struct sg_table *pages);
3248 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3250 static inline int __must_check
3251 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3253 might_lock(&obj->mm.lock);
3255 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3258 return __i915_gem_object_get_pages(obj);
3262 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3264 GEM_BUG_ON(!obj->mm.pages);
3266 atomic_inc(&obj->mm.pages_pin_count);
3270 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3272 return atomic_read(&obj->mm.pages_pin_count);
3276 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3278 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3279 GEM_BUG_ON(!obj->mm.pages);
3281 atomic_dec(&obj->mm.pages_pin_count);
3285 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3287 __i915_gem_object_unpin_pages(obj);
3290 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3295 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3296 enum i915_mm_subclass subclass);
3297 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3299 enum i915_map_type {
3305 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3306 * @obj: the object to map into kernel address space
3307 * @type: the type of mapping, used to select pgprot_t
3309 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3310 * pages and then returns a contiguous mapping of the backing storage into
3311 * the kernel address space. Based on the @type of mapping, the PTE will be
3312 * set to either WriteBack or WriteCombine (via pgprot_t).
3314 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3315 * mapping is no longer required.
3317 * Returns the pointer through which to access the mapped object, or an
3318 * ERR_PTR() on error.
3320 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3321 enum i915_map_type type);
3324 * i915_gem_object_unpin_map - releases an earlier mapping
3325 * @obj: the object to unmap
3327 * After pinning the object and mapping its pages, once you are finished
3328 * with your access, call i915_gem_object_unpin_map() to release the pin
3329 * upon the mapping. Once the pin count reaches zero, that mapping may be
3332 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3334 i915_gem_object_unpin_pages(obj);
3337 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3338 unsigned int *needs_clflush);
3339 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3340 unsigned int *needs_clflush);
3341 #define CLFLUSH_BEFORE 0x1
3342 #define CLFLUSH_AFTER 0x2
3343 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3346 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3348 i915_gem_object_unpin_pages(obj);
3351 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3352 void i915_vma_move_to_active(struct i915_vma *vma,
3353 struct drm_i915_gem_request *req,
3354 unsigned int flags);
3355 int i915_gem_dumb_create(struct drm_file *file_priv,
3356 struct drm_device *dev,
3357 struct drm_mode_create_dumb *args);
3358 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3359 uint32_t handle, uint64_t *offset);
3360 int i915_gem_mmap_gtt_version(void);
3362 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3363 struct drm_i915_gem_object *new,
3364 unsigned frontbuffer_bits);
3366 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3368 struct drm_i915_gem_request *
3369 i915_gem_find_active_request(struct intel_engine_cs *engine);
3371 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3373 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3375 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3378 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3380 return unlikely(test_bit(I915_WEDGED, &error->flags));
3383 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3385 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3388 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3390 return READ_ONCE(error->reset_count);
3393 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3394 void i915_gem_reset(struct drm_i915_private *dev_priv);
3395 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3396 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3398 void i915_gem_init_mmio(struct drm_i915_private *i915);
3399 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3400 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3401 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3402 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3403 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3404 unsigned int flags);
3405 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3406 void i915_gem_resume(struct drm_i915_private *dev_priv);
3407 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3408 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3411 struct intel_rps_client *rps);
3412 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3415 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3418 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3421 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3422 struct i915_vma * __must_check
3423 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3425 const struct i915_ggtt_view *view);
3426 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3427 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3429 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3430 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3432 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3433 enum i915_cache_level cache_level);
3435 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3436 struct dma_buf *dma_buf);
3438 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3439 struct drm_gem_object *gem_obj, int flags);
3441 static inline struct i915_hw_ppgtt *
3442 i915_vm_to_ppgtt(struct i915_address_space *vm)
3444 return container_of(vm, struct i915_hw_ppgtt, base);
3447 /* i915_gem_fence_reg.c */
3448 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3449 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3451 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3452 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3454 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3455 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3456 struct sg_table *pages);
3457 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3458 struct sg_table *pages);
3460 static inline struct i915_gem_context *
3461 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3463 struct i915_gem_context *ctx;
3465 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3467 ctx = idr_find(&file_priv->context_idr, id);
3469 return ERR_PTR(-ENOENT);
3474 static inline struct i915_gem_context *
3475 i915_gem_context_get(struct i915_gem_context *ctx)
3477 kref_get(&ctx->ref);
3481 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3483 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3484 kref_put(&ctx->ref, i915_gem_context_free);
3487 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3489 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3491 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3495 static inline struct intel_timeline *
3496 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3497 struct intel_engine_cs *engine)
3499 struct i915_address_space *vm;
3501 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3502 return &vm->timeline.engine[engine->id];
3505 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3506 struct drm_file *file);
3508 /* i915_gem_evict.c */
3509 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3510 u64 min_size, u64 alignment,
3511 unsigned cache_level,
3514 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3515 struct drm_mm_node *node,
3516 unsigned int flags);
3517 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3519 /* belongs in i915_gem_gtt.h */
3520 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3523 if (INTEL_GEN(dev_priv) < 6)
3524 intel_gtt_chipset_flush();
3527 /* i915_gem_stolen.c */
3528 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3529 struct drm_mm_node *node, u64 size,
3530 unsigned alignment);
3531 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3532 struct drm_mm_node *node, u64 size,
3533 unsigned alignment, u64 start,
3535 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3536 struct drm_mm_node *node);
3537 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3538 void i915_gem_cleanup_stolen(struct drm_device *dev);
3539 struct drm_i915_gem_object *
3540 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3541 struct drm_i915_gem_object *
3542 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3547 /* i915_gem_internal.c */
3548 struct drm_i915_gem_object *
3549 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3552 /* i915_gem_shrinker.c */
3553 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3554 unsigned long target,
3556 #define I915_SHRINK_PURGEABLE 0x1
3557 #define I915_SHRINK_UNBOUND 0x2
3558 #define I915_SHRINK_BOUND 0x4
3559 #define I915_SHRINK_ACTIVE 0x8
3560 #define I915_SHRINK_VMAPS 0x10
3561 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3562 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3563 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3566 /* i915_gem_tiling.c */
3567 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3569 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3571 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3572 i915_gem_object_is_tiled(obj);
3575 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3576 unsigned int tiling, unsigned int stride);
3577 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3578 unsigned int tiling, unsigned int stride);
3580 /* i915_debugfs.c */
3581 #ifdef CONFIG_DEBUG_FS
3582 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3583 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3584 int i915_debugfs_connector_add(struct drm_connector *connector);
3585 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3587 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3588 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3589 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3591 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3594 /* i915_gpu_error.c */
3595 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3598 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3599 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3600 const struct i915_gpu_state *gpu);
3601 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3602 struct drm_i915_private *i915,
3603 size_t count, loff_t pos);
3604 static inline void i915_error_state_buf_release(
3605 struct drm_i915_error_state_buf *eb)
3610 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3611 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3613 const char *error_msg);
3615 static inline struct i915_gpu_state *
3616 i915_gpu_state_get(struct i915_gpu_state *gpu)
3618 kref_get(&gpu->ref);
3622 void __i915_gpu_state_free(struct kref *kref);
3623 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3626 kref_put(&gpu->ref, __i915_gpu_state_free);
3629 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3630 void i915_reset_error_state(struct drm_i915_private *i915);
3634 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3636 const char *error_msg)
3640 static inline struct i915_gpu_state *
3641 i915_first_error_state(struct drm_i915_private *i915)
3646 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3652 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3654 /* i915_cmd_parser.c */
3655 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3656 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3657 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3658 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3659 struct drm_i915_gem_object *batch_obj,
3660 struct drm_i915_gem_object *shadow_batch_obj,
3661 u32 batch_start_offset,
3666 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3667 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3668 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3669 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3671 /* i915_suspend.c */
3672 extern int i915_save_state(struct drm_i915_private *dev_priv);
3673 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3676 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3677 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3680 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3681 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3682 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3685 extern struct i2c_adapter *
3686 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3687 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3688 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3689 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3691 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3693 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3696 int intel_bios_init(struct drm_i915_private *dev_priv);
3697 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3698 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3699 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3700 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3701 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3702 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3703 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3704 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3706 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3710 /* intel_opregion.c */
3712 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3713 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3714 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3715 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3716 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3718 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3720 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3722 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3723 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3724 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3725 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3729 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3734 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3738 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3746 extern void intel_register_dsm_handler(void);
3747 extern void intel_unregister_dsm_handler(void);
3749 static inline void intel_register_dsm_handler(void) { return; }
3750 static inline void intel_unregister_dsm_handler(void) { return; }
3751 #endif /* CONFIG_ACPI */
3753 /* intel_device_info.c */
3754 static inline struct intel_device_info *
3755 mkwrite_device_info(struct drm_i915_private *dev_priv)
3757 return (struct intel_device_info *)&dev_priv->info;
3760 const char *intel_platform_name(enum intel_platform platform);
3761 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3762 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3765 extern void intel_modeset_init_hw(struct drm_device *dev);
3766 extern int intel_modeset_init(struct drm_device *dev);
3767 extern void intel_modeset_gem_init(struct drm_device *dev);
3768 extern void intel_modeset_cleanup(struct drm_device *dev);
3769 extern int intel_connector_register(struct drm_connector *);
3770 extern void intel_connector_unregister(struct drm_connector *);
3771 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3773 extern void intel_display_resume(struct drm_device *dev);
3774 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3775 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3776 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3777 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3778 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3779 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3782 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3783 struct drm_file *file);
3786 extern struct intel_overlay_error_state *
3787 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3788 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3789 struct intel_overlay_error_state *error);
3791 extern struct intel_display_error_state *
3792 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3793 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3794 struct intel_display_error_state *error);
3796 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3797 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3798 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3799 u32 reply_mask, u32 reply, int timeout_base_ms);
3801 /* intel_sideband.c */
3802 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3803 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3804 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3805 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3806 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3807 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3808 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3809 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3810 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3811 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3812 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3813 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3814 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3815 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3816 enum intel_sbi_destination destination);
3817 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3818 enum intel_sbi_destination destination);
3819 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3820 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3822 /* intel_dpio_phy.c */
3823 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3824 enum dpio_phy *phy, enum dpio_channel *ch);
3825 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3826 enum port port, u32 margin, u32 scale,
3827 u32 enable, u32 deemphasis);
3828 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3829 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3830 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3832 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3834 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3835 uint8_t lane_count);
3836 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3837 uint8_t lane_lat_optim_mask);
3838 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3840 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3841 u32 deemph_reg_value, u32 margin_reg_value,
3842 bool uniq_trans_scale);
3843 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3845 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3846 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3847 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3848 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3850 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3851 u32 demph_reg_value, u32 preemph_reg_value,
3852 u32 uniqtranscale_reg_value, u32 tx3_demph);
3853 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3854 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3855 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3857 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3858 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3860 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3861 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3863 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3864 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3865 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3866 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3868 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3869 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3870 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3871 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3873 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3874 * will be implemented using 2 32-bit writes in an arbitrary order with
3875 * an arbitrary delay between them. This can cause the hardware to
3876 * act upon the intermediate value, possibly leading to corruption and
3877 * machine death. For this reason we do not support I915_WRITE64, or
3878 * dev_priv->uncore.funcs.mmio_writeq.
3880 * When reading a 64-bit value as two 32-bit values, the delay may cause
3881 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3882 * occasionally a 64-bit register does not actualy support a full readq
3883 * and must be read using two 32-bit reads.
3885 * You have been warned.
3887 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3889 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3890 u32 upper, lower, old_upper, loop = 0; \
3891 upper = I915_READ(upper_reg); \
3893 old_upper = upper; \
3894 lower = I915_READ(lower_reg); \
3895 upper = I915_READ(upper_reg); \
3896 } while (upper != old_upper && loop++ < 2); \
3897 (u64)upper << 32 | lower; })
3899 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3900 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3902 #define __raw_read(x, s) \
3903 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3906 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3909 #define __raw_write(x, s) \
3910 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3911 i915_reg_t reg, uint##x##_t val) \
3913 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3928 /* These are untraced mmio-accessors that are only valid to be used inside
3929 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3932 * Think twice, and think again, before using these.
3934 * As an example, these accessors can possibly be used between:
3936 * spin_lock_irq(&dev_priv->uncore.lock);
3937 * intel_uncore_forcewake_get__locked();
3941 * intel_uncore_forcewake_put__locked();
3942 * spin_unlock_irq(&dev_priv->uncore.lock);
3945 * Note: some registers may not need forcewake held, so
3946 * intel_uncore_forcewake_{get,put} can be omitted, see
3947 * intel_uncore_forcewake_for_reg().
3949 * Certain architectures will die if the same cacheline is concurrently accessed
3950 * by different clients (e.g. on Ivybridge). Access to registers should
3951 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3952 * a more localised lock guarding all access to that bank of registers.
3954 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3955 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3956 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3957 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3959 /* "Broadcast RGB" property */
3960 #define INTEL_BROADCAST_RGB_AUTO 0
3961 #define INTEL_BROADCAST_RGB_FULL 1
3962 #define INTEL_BROADCAST_RGB_LIMITED 2
3964 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3966 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3967 return VLV_VGACNTRL;
3968 else if (INTEL_GEN(dev_priv) >= 5)
3969 return CPU_VGACNTRL;
3974 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3976 unsigned long j = msecs_to_jiffies(m);
3978 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3981 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3983 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3986 static inline unsigned long
3987 timespec_to_jiffies_timeout(const struct timespec *value)
3989 unsigned long j = timespec_to_jiffies(value);
3991 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3995 * If you need to wait X milliseconds between events A and B, but event B
3996 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3997 * when event A happened, then just before event B you call this function and
3998 * pass the timestamp as the first argument, and X as the second argument.
4001 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4003 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4006 * Don't re-read the value of "jiffies" every time since it may change
4007 * behind our back and break the math.
4009 tmp_jiffies = jiffies;
4010 target_jiffies = timestamp_jiffies +
4011 msecs_to_jiffies_timeout(to_wait_ms);
4013 if (time_after(target_jiffies, tmp_jiffies)) {
4014 remaining_jiffies = target_jiffies - tmp_jiffies;
4015 while (remaining_jiffies)
4017 schedule_timeout_uninterruptible(remaining_jiffies);
4022 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4024 struct intel_engine_cs *engine = req->engine;
4027 /* Note that the engine may have wrapped around the seqno, and
4028 * so our request->global_seqno will be ahead of the hardware,
4029 * even though it completed the request before wrapping. We catch
4030 * this by kicking all the waiters before resetting the seqno
4031 * in hardware, and also signal the fence.
4033 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4036 /* The request was dequeued before we were awoken. We check after
4037 * inspecting the hw to confirm that this was the same request
4038 * that generated the HWS update. The memory barriers within
4039 * the request execution are sufficient to ensure that a check
4040 * after reading the value from hw matches this request.
4042 seqno = i915_gem_request_global_seqno(req);
4046 /* Before we do the heavier coherent read of the seqno,
4047 * check the value (hopefully) in the CPU cacheline.
4049 if (__i915_gem_request_completed(req, seqno))
4052 /* Ensure our read of the seqno is coherent so that we
4053 * do not "miss an interrupt" (i.e. if this is the last
4054 * request and the seqno write from the GPU is not visible
4055 * by the time the interrupt fires, we will see that the
4056 * request is incomplete and go back to sleep awaiting
4057 * another interrupt that will never come.)
4059 * Strictly, we only need to do this once after an interrupt,
4060 * but it is easier and safer to do it every time the waiter
4063 if (engine->irq_seqno_barrier &&
4064 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4065 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4066 unsigned long flags;
4068 /* The ordering of irq_posted versus applying the barrier
4069 * is crucial. The clearing of the current irq_posted must
4070 * be visible before we perform the barrier operation,
4071 * such that if a subsequent interrupt arrives, irq_posted
4072 * is reasserted and our task rewoken (which causes us to
4073 * do another __i915_request_irq_complete() immediately
4074 * and reapply the barrier). Conversely, if the clear
4075 * occurs after the barrier, then an interrupt that arrived
4076 * whilst we waited on the barrier would not trigger a
4077 * barrier on the next pass, and the read may not see the
4080 engine->irq_seqno_barrier(engine);
4082 /* If we consume the irq, but we are no longer the bottom-half,
4083 * the real bottom-half may not have serialised their own
4084 * seqno check with the irq-barrier (i.e. may have inspected
4085 * the seqno before we believe it coherent since they see
4086 * irq_posted == false but we are still running).
4088 spin_lock_irqsave(&b->lock, flags);
4089 if (b->first_wait && b->first_wait->tsk != current)
4090 /* Note that if the bottom-half is changed as we
4091 * are sending the wake-up, the new bottom-half will
4092 * be woken by whomever made the change. We only have
4093 * to worry about when we steal the irq-posted for
4096 wake_up_process(b->first_wait->tsk);
4097 spin_unlock_irqrestore(&b->lock, flags);
4099 if (__i915_gem_request_completed(req, seqno))
4106 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4107 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4109 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4110 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4111 * perform the operation. To check beforehand, pass in the parameters to
4112 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4113 * you only need to pass in the minor offsets, page-aligned pointers are
4116 * For just checking for SSE4.1, in the foreknowledge that the future use
4117 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4119 #define i915_can_memcpy_from_wc(dst, src, len) \
4120 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4122 #define i915_has_memcpy_from_wc() \
4123 i915_memcpy_from_wc(NULL, NULL, 0)
4126 int remap_io_mapping(struct vm_area_struct *vma,
4127 unsigned long addr, unsigned long pfn, unsigned long size,
4128 struct io_mapping *iomap);
4130 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4132 return (obj->cache_level != I915_CACHE_NONE ||
4133 HAS_LLC(to_i915(obj->base.dev)));