1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170206"
83 #define DRIVER_TIMESTAMP 1486372993
86 /* Many gcc seem to no see through this and fall over :( */
88 #define WARN_ON(x) ({ \
89 bool __i915_warn_cond = (x); \
90 if (__builtin_constant_p(__i915_warn_cond)) \
91 BUILD_BUG_ON(__i915_warn_cond); \
92 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101 (long) (x), __func__);
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 bool __i915_inject_load_failure(const char *func, int line);
122 #define i915_inject_load_failure() \
123 __i915_inject_load_failure(__func__, __LINE__)
127 } uint_fixed_16_16_t;
129 #define FP_16_16_MAX ({ \
130 uint_fixed_16_16_t fp; \
135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
137 uint_fixed_16_16_t fp;
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
147 return DIV_ROUND_UP(fp.val, 1 << 16);
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
156 uint_fixed_16_16_t min2)
158 uint_fixed_16_16_t min;
160 min.val = min(min1.val, min2.val);
164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
165 uint_fixed_16_16_t max2)
167 uint_fixed_16_16_t max;
169 max.val = max(max1.val, max2.val);
173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
176 uint_fixed_16_16_t fp, res;
178 fp = u32_to_fixed_16_16(val);
179 res.val = DIV_ROUND_UP(fp.val, d);
183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
186 uint_fixed_16_16_t res;
189 interm_val = (uint64_t)val << 16;
190 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
191 WARN_ON(interm_val >> 32);
192 res.val = (uint32_t) interm_val;
197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
198 uint_fixed_16_16_t mul)
200 uint64_t intermediate_val;
201 uint_fixed_16_16_t fp;
203 intermediate_val = (uint64_t) val * mul.val;
204 WARN_ON(intermediate_val >> 32);
205 fp.val = (uint32_t) intermediate_val;
209 static inline const char *yesno(bool v)
211 return v ? "yes" : "no";
214 static inline const char *onoff(bool v)
216 return v ? "on" : "off";
219 static inline const char *enableddisabled(bool v)
221 return v ? "enabled" : "disabled";
230 I915_MAX_PIPES = _PIPE_EDP
232 #define pipe_name(p) ((p) + 'A')
244 static inline const char *transcoder_name(enum transcoder transcoder)
246 switch (transcoder) {
255 case TRANSCODER_DSI_A:
257 case TRANSCODER_DSI_C:
264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
266 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
270 * Global legacy plane identifier. Valid only for primary/sprite
271 * planes on pre-g4x, and only for primary planes on g4x+.
278 #define plane_name(p) ((p) + 'A')
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
283 * Per-pipe plane identifier.
284 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285 * number of planes per CRTC. Not all platforms really have this many planes,
286 * which means some arrays of size I915_MAX_PLANES may have unused entries
287 * between the topmost sprite plane and the cursor plane.
289 * This is expected to be passed to various register macros
290 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
301 #define for_each_plane_id_on_crtc(__crtc, __p) \
302 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
303 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
314 #define port_name(p) ((p) + 'A')
316 #define I915_NUM_PHYS_VLV 2
329 enum intel_display_power_domain {
333 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
334 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
335 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
336 POWER_DOMAIN_TRANSCODER_A,
337 POWER_DOMAIN_TRANSCODER_B,
338 POWER_DOMAIN_TRANSCODER_C,
339 POWER_DOMAIN_TRANSCODER_EDP,
340 POWER_DOMAIN_TRANSCODER_DSI_A,
341 POWER_DOMAIN_TRANSCODER_DSI_C,
342 POWER_DOMAIN_PORT_DDI_A_LANES,
343 POWER_DOMAIN_PORT_DDI_B_LANES,
344 POWER_DOMAIN_PORT_DDI_C_LANES,
345 POWER_DOMAIN_PORT_DDI_D_LANES,
346 POWER_DOMAIN_PORT_DDI_E_LANES,
347 POWER_DOMAIN_PORT_DDI_A_IO,
348 POWER_DOMAIN_PORT_DDI_B_IO,
349 POWER_DOMAIN_PORT_DDI_C_IO,
350 POWER_DOMAIN_PORT_DDI_D_IO,
351 POWER_DOMAIN_PORT_DDI_E_IO,
352 POWER_DOMAIN_PORT_DSI,
353 POWER_DOMAIN_PORT_CRT,
354 POWER_DOMAIN_PORT_OTHER,
363 POWER_DOMAIN_MODESET,
369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
371 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
372 #define POWER_DOMAIN_TRANSCODER(tran) \
373 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
374 (tran) + POWER_DOMAIN_TRANSCODER_A)
378 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
390 #define for_each_hpd_pin(__pin) \
391 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
393 #define HPD_STORM_DEFAULT_THRESHOLD 5
395 struct i915_hotplug {
396 struct work_struct hotplug_work;
399 unsigned long last_jiffies;
404 HPD_MARK_DISABLED = 2
406 } stats[HPD_NUM_PINS];
408 struct delayed_work reenable_work;
410 struct intel_digital_port *irq_port[I915_MAX_PORTS];
413 struct work_struct dig_port_work;
415 struct work_struct poll_init_work;
418 unsigned int hpd_storm_threshold;
421 * if we get a HPD irq from DP and a HPD irq from non-DP
422 * the non-DP HPD could block the workqueue on a mode config
423 * mutex getting, that userspace may have taken. However
424 * userspace is waiting on the DP workqueue to run which is
425 * blocked behind the non-DP one.
427 struct workqueue_struct *dp_wq;
430 #define I915_GEM_GPU_DOMAINS \
431 (I915_GEM_DOMAIN_RENDER | \
432 I915_GEM_DOMAIN_SAMPLER | \
433 I915_GEM_DOMAIN_COMMAND | \
434 I915_GEM_DOMAIN_INSTRUCTION | \
435 I915_GEM_DOMAIN_VERTEX)
437 #define for_each_pipe(__dev_priv, __p) \
438 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
440 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
441 for_each_if ((__mask) & (1 << (__p)))
442 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
444 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
446 #define for_each_sprite(__dev_priv, __p, __s) \
448 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
451 #define for_each_port_masked(__port, __ports_mask) \
452 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
453 for_each_if ((__ports_mask) & (1 << (__port)))
455 #define for_each_crtc(dev, crtc) \
456 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
458 #define for_each_intel_plane(dev, intel_plane) \
459 list_for_each_entry(intel_plane, \
460 &(dev)->mode_config.plane_list, \
463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
464 list_for_each_entry(intel_plane, \
465 &(dev)->mode_config.plane_list, \
467 for_each_if ((plane_mask) & \
468 (1 << drm_plane_index(&intel_plane->base)))
470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
471 list_for_each_entry(intel_plane, \
472 &(dev)->mode_config.plane_list, \
474 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
476 #define for_each_intel_crtc(dev, intel_crtc) \
477 list_for_each_entry(intel_crtc, \
478 &(dev)->mode_config.crtc_list, \
481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
482 list_for_each_entry(intel_crtc, \
483 &(dev)->mode_config.crtc_list, \
485 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
487 #define for_each_intel_encoder(dev, intel_encoder) \
488 list_for_each_entry(intel_encoder, \
489 &(dev)->mode_config.encoder_list, \
492 #define for_each_intel_connector(dev, intel_connector) \
493 list_for_each_entry(intel_connector, \
494 &(dev)->mode_config.connector_list, \
497 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
498 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
499 for_each_if ((intel_encoder)->base.crtc == (__crtc))
501 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
502 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
503 for_each_if ((intel_connector)->base.encoder == (__encoder))
505 #define for_each_power_domain(domain, mask) \
506 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
507 for_each_if (BIT_ULL(domain) & (mask))
509 #define for_each_power_well(__dev_priv, __power_well) \
510 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
511 (__power_well) - (__dev_priv)->power_domains.power_wells < \
512 (__dev_priv)->power_domains.power_well_count; \
515 #define for_each_power_well_rev(__dev_priv, __power_well) \
516 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
517 (__dev_priv)->power_domains.power_well_count - 1; \
518 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
521 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
522 for_each_power_well(__dev_priv, __power_well) \
523 for_each_if ((__power_well)->domains & (__domain_mask))
525 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
526 for_each_power_well_rev(__dev_priv, __power_well) \
527 for_each_if ((__power_well)->domains & (__domain_mask))
529 struct drm_i915_private;
530 struct i915_mm_struct;
531 struct i915_mmu_object;
533 struct drm_i915_file_private {
534 struct drm_i915_private *dev_priv;
535 struct drm_file *file;
539 struct list_head request_list;
540 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
541 * chosen to prevent the CPU getting more than a frame ahead of the GPU
542 * (when using lax throttling for the frontbuffer). We also use it to
543 * offer free GPU waitboosts for severely congested workloads.
545 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
547 struct idr context_idr;
549 struct intel_rps_client {
550 struct list_head link;
554 unsigned int bsd_engine;
556 /* Client can have a maximum of 3 contexts banned before
557 * it is denied of creating new contexts. As one context
558 * ban needs 4 consecutive hangs, and more if there is
559 * progress in between, this is a last resort stop gap measure
560 * to limit the badly behaving clients access to gpu.
562 #define I915_MAX_CLIENT_CONTEXT_BANS 3
566 /* Used by dp and fdi links */
567 struct intel_link_m_n {
575 void intel_link_compute_m_n(int bpp, int nlanes,
576 int pixel_clock, int link_clock,
577 struct intel_link_m_n *m_n);
579 /* Interface history:
582 * 1.2: Add Power Management
583 * 1.3: Add vblank support
584 * 1.4: Fix cmdbuffer path, add heap destroy
585 * 1.5: Add vblank pipe configuration
586 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
587 * - Support vertical blank on secondary display pipe
589 #define DRIVER_MAJOR 1
590 #define DRIVER_MINOR 6
591 #define DRIVER_PATCHLEVEL 0
593 struct opregion_header;
594 struct opregion_acpi;
595 struct opregion_swsci;
596 struct opregion_asle;
598 struct intel_opregion {
599 struct opregion_header *header;
600 struct opregion_acpi *acpi;
601 struct opregion_swsci *swsci;
602 u32 swsci_gbda_sub_functions;
603 u32 swsci_sbcb_sub_functions;
604 struct opregion_asle *asle;
609 struct work_struct asle_work;
611 #define OPREGION_SIZE (8*1024)
613 struct intel_overlay;
614 struct intel_overlay_error_state;
616 struct sdvo_device_mapping {
625 struct intel_connector;
626 struct intel_encoder;
627 struct intel_atomic_state;
628 struct intel_crtc_state;
629 struct intel_initial_plane_config;
633 struct intel_cdclk_state;
635 struct drm_i915_display_funcs {
636 void (*get_cdclk)(struct drm_i915_private *dev_priv,
637 struct intel_cdclk_state *cdclk_state);
638 void (*set_cdclk)(struct drm_i915_private *dev_priv,
639 const struct intel_cdclk_state *cdclk_state);
640 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
641 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
642 int (*compute_intermediate_wm)(struct drm_device *dev,
643 struct intel_crtc *intel_crtc,
644 struct intel_crtc_state *newstate);
645 void (*initial_watermarks)(struct intel_atomic_state *state,
646 struct intel_crtc_state *cstate);
647 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
648 struct intel_crtc_state *cstate);
649 void (*optimize_watermarks)(struct intel_atomic_state *state,
650 struct intel_crtc_state *cstate);
651 int (*compute_global_watermarks)(struct drm_atomic_state *state);
652 void (*update_wm)(struct intel_crtc *crtc);
653 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
654 /* Returns the active state of the crtc, and if the crtc is active,
655 * fills out the pipe-config with the hw state. */
656 bool (*get_pipe_config)(struct intel_crtc *,
657 struct intel_crtc_state *);
658 void (*get_initial_plane_config)(struct intel_crtc *,
659 struct intel_initial_plane_config *);
660 int (*crtc_compute_clock)(struct intel_crtc *crtc,
661 struct intel_crtc_state *crtc_state);
662 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
663 struct drm_atomic_state *old_state);
664 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
665 struct drm_atomic_state *old_state);
666 void (*update_crtcs)(struct drm_atomic_state *state,
667 unsigned int *crtc_vblank_mask);
668 void (*audio_codec_enable)(struct drm_connector *connector,
669 struct intel_encoder *encoder,
670 const struct drm_display_mode *adjusted_mode);
671 void (*audio_codec_disable)(struct intel_encoder *encoder);
672 void (*fdi_link_train)(struct drm_crtc *crtc);
673 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
674 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
675 struct drm_framebuffer *fb,
676 struct drm_i915_gem_object *obj,
677 struct drm_i915_gem_request *req,
679 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
680 /* clock updates for mode set */
682 /* render clock increase/decrease */
683 /* display clock increase/decrease */
684 /* pll clock increase/decrease */
686 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
687 void (*load_luts)(struct drm_crtc_state *crtc_state);
690 enum forcewake_domain_id {
691 FW_DOMAIN_ID_RENDER = 0,
692 FW_DOMAIN_ID_BLITTER,
698 enum forcewake_domains {
699 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
700 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
701 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
702 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
707 #define FW_REG_READ (1)
708 #define FW_REG_WRITE (2)
710 enum decoupled_power_domain {
711 GEN9_DECOUPLED_PD_BLITTER = 0,
712 GEN9_DECOUPLED_PD_RENDER,
713 GEN9_DECOUPLED_PD_MEDIA,
714 GEN9_DECOUPLED_PD_ALL
718 GEN9_DECOUPLED_OP_WRITE = 0,
719 GEN9_DECOUPLED_OP_READ
722 enum forcewake_domains
723 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
724 i915_reg_t reg, unsigned int op);
726 struct intel_uncore_funcs {
727 void (*force_wake_get)(struct drm_i915_private *dev_priv,
728 enum forcewake_domains domains);
729 void (*force_wake_put)(struct drm_i915_private *dev_priv,
730 enum forcewake_domains domains);
732 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
733 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
734 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
735 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
737 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
738 uint8_t val, bool trace);
739 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
740 uint16_t val, bool trace);
741 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
742 uint32_t val, bool trace);
745 struct intel_forcewake_range {
749 enum forcewake_domains domains;
752 struct intel_uncore {
753 spinlock_t lock; /** lock is also taken in irq contexts. */
755 const struct intel_forcewake_range *fw_domains_table;
756 unsigned int fw_domains_table_entries;
758 struct intel_uncore_funcs funcs;
762 enum forcewake_domains fw_domains;
763 enum forcewake_domains fw_domains_active;
765 struct intel_uncore_forcewake_domain {
766 struct drm_i915_private *i915;
767 enum forcewake_domain_id id;
768 enum forcewake_domains mask;
770 struct hrtimer timer;
777 } fw_domain[FW_DOMAIN_ID_COUNT];
779 int unclaimed_mmio_check;
782 /* Iterate over initialised fw domains */
783 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
784 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
785 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
787 for_each_if ((mask__) & (domain__)->mask)
789 #define for_each_fw_domain(domain__, dev_priv__) \
790 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
792 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
793 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
794 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
797 struct work_struct work;
799 uint32_t *dmc_payload;
800 uint32_t dmc_fw_size;
803 i915_reg_t mmioaddr[8];
804 uint32_t mmiodata[8];
806 uint32_t allowed_dc_mask;
809 #define DEV_INFO_FOR_EACH_FLAG(func) \
812 func(is_alpha_support); \
813 /* Keep has_* in alphabetical order */ \
814 func(has_64bit_reloc); \
815 func(has_aliasing_ppgtt); \
818 func(has_decoupled_mmio); \
821 func(has_fpga_dbg); \
822 func(has_full_ppgtt); \
823 func(has_full_48bit_ppgtt); \
824 func(has_gmbus_irq); \
825 func(has_gmch_display); \
828 func(has_hw_contexts); \
831 func(has_logical_ring_contexts); \
833 func(has_pipe_cxsr); \
834 func(has_pooled_eu); \
838 func(has_resource_streamer); \
839 func(has_runtime_pm); \
841 func(cursor_needs_physical); \
842 func(hws_needs_physical); \
843 func(overlay_needs_physical); \
846 struct sseu_dev_info {
852 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
855 u8 has_subslice_pg:1;
859 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
861 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
864 /* Keep in gen based order, and chronological order within a gen */
865 enum intel_platform {
866 INTEL_PLATFORM_UNINITIALIZED = 0,
894 struct intel_device_info {
895 u32 display_mmio_offset;
898 u8 num_sprites[I915_MAX_PIPES];
899 u8 num_scalers[I915_MAX_PIPES];
902 enum intel_platform platform;
903 u8 ring_mask; /* Rings supported by the HW */
905 #define DEFINE_FLAG(name) u8 name:1
906 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
908 u16 ddb_size; /* in blocks */
909 /* Register offsets for the various display pipes and transcoders */
910 int pipe_offsets[I915_MAX_TRANSCODERS];
911 int trans_offsets[I915_MAX_TRANSCODERS];
912 int palette_offsets[I915_MAX_PIPES];
913 int cursor_offsets[I915_MAX_PIPES];
915 /* Slice/subslice/EU info */
916 struct sseu_dev_info sseu;
919 u16 degamma_lut_size;
924 struct intel_display_error_state;
926 struct i915_gpu_state {
929 struct timeval boottime;
930 struct timeval uptime;
932 struct drm_i915_private *i915;
939 struct intel_device_info device_info;
940 struct i915_params params;
942 /* Generic register state */
946 u32 gtier[4], ngtier;
950 u32 error; /* gen6+ */
951 u32 err_int; /* gen7 */
952 u32 fault_data0; /* gen8, gen9 */
953 u32 fault_data1; /* gen8, gen9 */
961 u64 fence[I915_MAX_NUM_FENCES];
962 struct intel_overlay_error_state *overlay;
963 struct intel_display_error_state *display;
964 struct drm_i915_error_object *semaphore;
965 struct drm_i915_error_object *guc_log;
967 struct drm_i915_error_engine {
969 /* Software tracked state */
972 unsigned long hangcheck_timestamp;
973 bool hangcheck_stalled;
974 enum intel_engine_hangcheck_action hangcheck_action;
975 struct i915_address_space *vm;
978 /* position of active request inside the ring */
979 u32 rq_head, rq_post, rq_tail;
981 /* our own tracking of ring head and tail */
1004 u32 rc_psmi; /* sleep state */
1005 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1006 struct intel_instdone instdone;
1008 struct drm_i915_error_context {
1009 char comm[TASK_COMM_LEN];
1018 struct drm_i915_error_object {
1024 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1026 struct drm_i915_error_object *wa_ctx;
1028 struct drm_i915_error_request {
1036 } *requests, execlist[2];
1038 struct drm_i915_error_waiter {
1039 char comm[TASK_COMM_LEN];
1051 } engine[I915_NUM_ENGINES];
1053 struct drm_i915_error_buffer {
1056 u32 rseqno[I915_NUM_ENGINES], wseqno;
1060 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1067 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1068 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1069 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1072 enum i915_cache_level {
1073 I915_CACHE_NONE = 0,
1074 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1075 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1076 caches, eg sampler/render caches, and the
1077 large Last-Level-Cache. LLC is coherent with
1078 the CPU, but L3 is only visible to the GPU. */
1079 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1082 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1093 /* This is always the inner lock when overlapping with struct_mutex and
1094 * it's the outer lock when overlapping with stolen_lock. */
1097 unsigned int possible_framebuffer_bits;
1098 unsigned int busy_bits;
1099 unsigned int visible_pipes_mask;
1100 struct intel_crtc *crtc;
1102 struct drm_mm_node compressed_fb;
1103 struct drm_mm_node *compressed_llb;
1110 bool underrun_detected;
1111 struct work_struct underrun_work;
1113 struct intel_fbc_state_cache {
1114 struct i915_vma *vma;
1117 unsigned int mode_flags;
1118 uint32_t hsw_bdw_pixel_rate;
1122 unsigned int rotation;
1129 const struct drm_format_info *format;
1130 unsigned int stride;
1134 struct intel_fbc_reg_params {
1135 struct i915_vma *vma;
1140 unsigned int fence_y_offset;
1144 const struct drm_format_info *format;
1145 unsigned int stride;
1151 struct intel_fbc_work {
1153 u32 scheduled_vblank;
1154 struct work_struct work;
1157 const char *no_fbc_reason;
1161 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1162 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1163 * parsing for same resolution.
1165 enum drrs_refresh_rate_type {
1168 DRRS_MAX_RR, /* RR count */
1171 enum drrs_support_type {
1172 DRRS_NOT_SUPPORTED = 0,
1173 STATIC_DRRS_SUPPORT = 1,
1174 SEAMLESS_DRRS_SUPPORT = 2
1180 struct delayed_work work;
1181 struct intel_dp *dp;
1182 unsigned busy_frontbuffer_bits;
1183 enum drrs_refresh_rate_type refresh_rate_type;
1184 enum drrs_support_type type;
1191 struct intel_dp *enabled;
1193 struct delayed_work work;
1194 unsigned busy_frontbuffer_bits;
1196 bool aux_frame_sync;
1198 bool y_cord_support;
1199 bool colorimetry_support;
1204 PCH_NONE = 0, /* No PCH present */
1205 PCH_IBX, /* Ibexpeak PCH */
1206 PCH_CPT, /* Cougarpoint PCH */
1207 PCH_LPT, /* Lynxpoint PCH */
1208 PCH_SPT, /* Sunrisepoint PCH */
1209 PCH_KBP, /* Kabypoint PCH */
1213 enum intel_sbi_destination {
1218 #define QUIRK_PIPEA_FORCE (1<<0)
1219 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1220 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1221 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1222 #define QUIRK_PIPEB_FORCE (1<<4)
1223 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1226 struct intel_fbc_work;
1228 struct intel_gmbus {
1229 struct i2c_adapter adapter;
1230 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1233 i915_reg_t gpio_reg;
1234 struct i2c_algo_bit_data bit_algo;
1235 struct drm_i915_private *dev_priv;
1238 struct i915_suspend_saved_registers {
1240 u32 saveFBC_CONTROL;
1241 u32 saveCACHE_MODE_0;
1242 u32 saveMI_ARB_STATE;
1246 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1247 u32 savePCH_PORT_HOTPLUG;
1251 struct vlv_s0ix_state {
1258 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1259 u32 media_max_req_count;
1260 u32 gfx_max_req_count;
1286 u32 rp_down_timeout;
1292 /* Display 1 CZ domain */
1297 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1299 /* GT SA CZ domain */
1306 /* Display 2 CZ domain */
1310 u32 clock_gate_dis2;
1313 struct intel_rps_ei {
1319 struct intel_gen6_power_mgmt {
1321 * work, interrupts_enabled and pm_iir are protected by
1322 * dev_priv->irq_lock
1324 struct work_struct work;
1325 bool interrupts_enabled;
1328 /* PM interrupt bits that should never be masked */
1331 /* Frequencies are stored in potentially platform dependent multiples.
1332 * In other words, *_freq needs to be multiplied by X to be interesting.
1333 * Soft limits are those which are used for the dynamic reclocking done
1334 * by the driver (raise frequencies under heavy loads, and lower for
1335 * lighter loads). Hard limits are those imposed by the hardware.
1337 * A distinction is made for overclocking, which is never enabled by
1338 * default, and is considered to be above the hard limit if it's
1341 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1342 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1343 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1344 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1345 u8 min_freq; /* AKA RPn. Minimum frequency */
1346 u8 boost_freq; /* Frequency to request when wait boosting */
1347 u8 idle_freq; /* Frequency to request when we are idle */
1348 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1349 u8 rp1_freq; /* "less than" RP0 power/freqency */
1350 u8 rp0_freq; /* Non-overclocked max frequency. */
1351 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1353 u8 up_threshold; /* Current %busy required to uplock */
1354 u8 down_threshold; /* Current %busy required to downclock */
1357 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1359 spinlock_t client_lock;
1360 struct list_head clients;
1364 struct delayed_work autoenable_work;
1367 /* manual wa residency calculations */
1368 struct intel_rps_ei up_ei, down_ei;
1371 * Protects RPS/RC6 register access and PCU communication.
1372 * Must be taken after struct_mutex if nested. Note that
1373 * this lock may be held for long periods of time when
1374 * talking to hw - so only take it when talking to hw!
1376 struct mutex hw_lock;
1379 /* defined intel_pm.c */
1380 extern spinlock_t mchdev_lock;
1382 struct intel_ilk_power_mgmt {
1390 unsigned long last_time1;
1391 unsigned long chipset_power;
1394 unsigned long gfx_power;
1401 struct drm_i915_private;
1402 struct i915_power_well;
1404 struct i915_power_well_ops {
1406 * Synchronize the well's hw state to match the current sw state, for
1407 * example enable/disable it based on the current refcount. Called
1408 * during driver init and resume time, possibly after first calling
1409 * the enable/disable handlers.
1411 void (*sync_hw)(struct drm_i915_private *dev_priv,
1412 struct i915_power_well *power_well);
1414 * Enable the well and resources that depend on it (for example
1415 * interrupts located on the well). Called after the 0->1 refcount
1418 void (*enable)(struct drm_i915_private *dev_priv,
1419 struct i915_power_well *power_well);
1421 * Disable the well and resources that depend on it. Called after
1422 * the 1->0 refcount transition.
1424 void (*disable)(struct drm_i915_private *dev_priv,
1425 struct i915_power_well *power_well);
1426 /* Returns the hw enabled state. */
1427 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1428 struct i915_power_well *power_well);
1431 /* Power well structure for haswell */
1432 struct i915_power_well {
1435 /* power well enable/disable usage count */
1437 /* cached hw enabled state */
1440 /* unique identifier for this power well */
1443 * Arbitraty data associated with this power well. Platform and power
1447 const struct i915_power_well_ops *ops;
1450 struct i915_power_domains {
1452 * Power wells needed for initialization at driver init and suspend
1453 * time are on. They are kept on until after the first modeset.
1457 int power_well_count;
1460 int domain_use_count[POWER_DOMAIN_NUM];
1461 struct i915_power_well *power_wells;
1464 #define MAX_L3_SLICES 2
1465 struct intel_l3_parity {
1466 u32 *remap_info[MAX_L3_SLICES];
1467 struct work_struct error_work;
1471 struct i915_gem_mm {
1472 /** Memory allocator for GTT stolen memory */
1473 struct drm_mm stolen;
1474 /** Protects the usage of the GTT stolen memory allocator. This is
1475 * always the inner lock when overlapping with struct_mutex. */
1476 struct mutex stolen_lock;
1478 /** List of all objects in gtt_space. Used to restore gtt
1479 * mappings on resume */
1480 struct list_head bound_list;
1482 * List of objects which are not bound to the GTT (thus
1483 * are idle and not used by the GPU). These objects may or may
1484 * not actually have any pages attached.
1486 struct list_head unbound_list;
1488 /** List of all objects in gtt_space, currently mmaped by userspace.
1489 * All objects within this list must also be on bound_list.
1491 struct list_head userfault_list;
1494 * List of objects which are pending destruction.
1496 struct llist_head free_list;
1497 struct work_struct free_work;
1499 /** Usable portion of the GTT for GEM */
1500 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1502 /** PPGTT used for aliasing the PPGTT with the GTT */
1503 struct i915_hw_ppgtt *aliasing_ppgtt;
1505 struct notifier_block oom_notifier;
1506 struct notifier_block vmap_notifier;
1507 struct shrinker shrinker;
1509 /** LRU list of objects with fence regs on them. */
1510 struct list_head fence_list;
1513 * Are we in a non-interruptible section of code like
1518 /* the indicator for dispatch video commands on two BSD rings */
1519 atomic_t bsd_engine_dispatch_index;
1521 /** Bit 6 swizzling required for X tiling */
1522 uint32_t bit_6_swizzle_x;
1523 /** Bit 6 swizzling required for Y tiling */
1524 uint32_t bit_6_swizzle_y;
1526 /* accounting, useful for userland debugging */
1527 spinlock_t object_stat_lock;
1532 struct drm_i915_error_state_buf {
1533 struct drm_i915_private *i915;
1542 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1543 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1545 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1546 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1548 struct i915_gpu_error {
1549 /* For hangcheck timer */
1550 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1551 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1553 struct delayed_work hangcheck_work;
1555 /* For reset and error_state handling. */
1557 /* Protected by the above dev->gpu_error.lock. */
1558 struct i915_gpu_state *first_error;
1560 unsigned long missed_irq_rings;
1563 * State variable controlling the reset flow and count
1565 * This is a counter which gets incremented when reset is triggered,
1567 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1568 * meaning that any waiters holding onto the struct_mutex should
1569 * relinquish the lock immediately in order for the reset to start.
1571 * If reset is not completed succesfully, the I915_WEDGE bit is
1572 * set meaning that hardware is terminally sour and there is no
1573 * recovery. All waiters on the reset_queue will be woken when
1576 * This counter is used by the wait_seqno code to notice that reset
1577 * event happened and it needs to restart the entire ioctl (since most
1578 * likely the seqno it waited for won't ever signal anytime soon).
1580 * This is important for lock-free wait paths, where no contended lock
1581 * naturally enforces the correct ordering between the bail-out of the
1582 * waiter and the gpu reset work code.
1584 unsigned long reset_count;
1586 unsigned long flags;
1587 #define I915_RESET_IN_PROGRESS 0
1588 #define I915_WEDGED (BITS_PER_LONG - 1)
1591 * Waitqueue to signal when a hang is detected. Used to for waiters
1592 * to release the struct_mutex for the reset to procede.
1594 wait_queue_head_t wait_queue;
1597 * Waitqueue to signal when the reset has completed. Used by clients
1598 * that wait for dev_priv->mm.wedged to settle.
1600 wait_queue_head_t reset_queue;
1602 /* For missed irq/seqno simulation. */
1603 unsigned long test_irq_rings;
1606 enum modeset_restore {
1607 MODESET_ON_LID_OPEN,
1612 #define DP_AUX_A 0x40
1613 #define DP_AUX_B 0x10
1614 #define DP_AUX_C 0x20
1615 #define DP_AUX_D 0x30
1617 #define DDC_PIN_B 0x05
1618 #define DDC_PIN_C 0x04
1619 #define DDC_PIN_D 0x06
1621 struct ddi_vbt_port_info {
1623 * This is an index in the HDMI/DVI DDI buffer translation table.
1624 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1625 * populate this field.
1627 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1628 uint8_t hdmi_level_shift;
1630 uint8_t supports_dvi:1;
1631 uint8_t supports_hdmi:1;
1632 uint8_t supports_dp:1;
1633 uint8_t supports_edp:1;
1635 uint8_t alternate_aux_channel;
1636 uint8_t alternate_ddc_pin;
1638 uint8_t dp_boost_level;
1639 uint8_t hdmi_boost_level;
1642 enum psr_lines_to_wait {
1643 PSR_0_LINES_TO_WAIT = 0,
1645 PSR_4_LINES_TO_WAIT,
1649 struct intel_vbt_data {
1650 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1651 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1654 unsigned int int_tv_support:1;
1655 unsigned int lvds_dither:1;
1656 unsigned int lvds_vbt:1;
1657 unsigned int int_crt_support:1;
1658 unsigned int lvds_use_ssc:1;
1659 unsigned int display_clock_mode:1;
1660 unsigned int fdi_rx_polarity_inverted:1;
1661 unsigned int panel_type:4;
1663 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1665 enum drrs_support_type drrs_type;
1676 struct edp_power_seq pps;
1681 bool require_aux_wakeup;
1683 enum psr_lines_to_wait lines_to_wait;
1684 int tp1_wakeup_time;
1685 int tp2_tp3_wakeup_time;
1691 bool active_low_pwm;
1692 u8 min_brightness; /* min_brightness/255 of max */
1693 u8 controller; /* brightness controller number */
1694 enum intel_backlight_type type;
1700 struct mipi_config *config;
1701 struct mipi_pps_data *pps;
1705 const u8 *sequence[MIPI_SEQ_MAX];
1711 union child_device_config *child_dev;
1713 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1714 struct sdvo_device_mapping sdvo_mappings[2];
1717 enum intel_ddb_partitioning {
1719 INTEL_DDB_PART_5_6, /* IVB+ */
1722 struct intel_wm_level {
1730 struct ilk_wm_values {
1731 uint32_t wm_pipe[3];
1733 uint32_t wm_lp_spr[3];
1734 uint32_t wm_linetime[3];
1736 enum intel_ddb_partitioning partitioning;
1739 struct vlv_pipe_wm {
1740 uint16_t plane[I915_MAX_PLANES];
1748 struct vlv_wm_ddl_values {
1749 uint8_t plane[I915_MAX_PLANES];
1752 struct vlv_wm_values {
1753 struct vlv_pipe_wm pipe[3];
1754 struct vlv_sr_wm sr;
1755 struct vlv_wm_ddl_values ddl[3];
1760 struct skl_ddb_entry {
1761 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1764 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1766 return entry->end - entry->start;
1769 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1770 const struct skl_ddb_entry *e2)
1772 if (e1->start == e2->start && e1->end == e2->end)
1778 struct skl_ddb_allocation {
1779 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1780 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1783 struct skl_wm_values {
1784 unsigned dirty_pipes;
1785 struct skl_ddb_allocation ddb;
1788 struct skl_wm_level {
1790 uint16_t plane_res_b;
1791 uint8_t plane_res_l;
1795 * This struct helps tracking the state needed for runtime PM, which puts the
1796 * device in PCI D3 state. Notice that when this happens, nothing on the
1797 * graphics device works, even register access, so we don't get interrupts nor
1800 * Every piece of our code that needs to actually touch the hardware needs to
1801 * either call intel_runtime_pm_get or call intel_display_power_get with the
1802 * appropriate power domain.
1804 * Our driver uses the autosuspend delay feature, which means we'll only really
1805 * suspend if we stay with zero refcount for a certain amount of time. The
1806 * default value is currently very conservative (see intel_runtime_pm_enable), but
1807 * it can be changed with the standard runtime PM files from sysfs.
1809 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1810 * goes back to false exactly before we reenable the IRQs. We use this variable
1811 * to check if someone is trying to enable/disable IRQs while they're supposed
1812 * to be disabled. This shouldn't happen and we'll print some error messages in
1815 * For more, read the Documentation/power/runtime_pm.txt.
1817 struct i915_runtime_pm {
1818 atomic_t wakeref_count;
1823 enum intel_pipe_crc_source {
1824 INTEL_PIPE_CRC_SOURCE_NONE,
1825 INTEL_PIPE_CRC_SOURCE_PLANE1,
1826 INTEL_PIPE_CRC_SOURCE_PLANE2,
1827 INTEL_PIPE_CRC_SOURCE_PF,
1828 INTEL_PIPE_CRC_SOURCE_PIPE,
1829 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1830 INTEL_PIPE_CRC_SOURCE_TV,
1831 INTEL_PIPE_CRC_SOURCE_DP_B,
1832 INTEL_PIPE_CRC_SOURCE_DP_C,
1833 INTEL_PIPE_CRC_SOURCE_DP_D,
1834 INTEL_PIPE_CRC_SOURCE_AUTO,
1835 INTEL_PIPE_CRC_SOURCE_MAX,
1838 struct intel_pipe_crc_entry {
1843 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1844 struct intel_pipe_crc {
1846 bool opened; /* exclusive access to the result file */
1847 struct intel_pipe_crc_entry *entries;
1848 enum intel_pipe_crc_source source;
1850 wait_queue_head_t wq;
1854 struct i915_frontbuffer_tracking {
1858 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1865 struct i915_wa_reg {
1868 /* bitmask representing WA bits */
1873 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1874 * allowing it for RCS as we don't foresee any requirement of having
1875 * a whitelist for other engines. When it is really required for
1876 * other engines then the limit need to be increased.
1878 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1880 struct i915_workarounds {
1881 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1883 u32 hw_whitelist_count[I915_NUM_ENGINES];
1886 struct i915_virtual_gpu {
1890 /* used in computing the new watermarks state */
1891 struct intel_wm_config {
1892 unsigned int num_pipes_active;
1893 bool sprites_enabled;
1894 bool sprites_scaled;
1897 struct i915_oa_format {
1902 struct i915_oa_reg {
1907 struct i915_perf_stream;
1910 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1912 struct i915_perf_stream_ops {
1914 * @enable: Enables the collection of HW samples, either in response to
1915 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1916 * without `I915_PERF_FLAG_DISABLED`.
1918 void (*enable)(struct i915_perf_stream *stream);
1921 * @disable: Disables the collection of HW samples, either in response
1922 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1925 void (*disable)(struct i915_perf_stream *stream);
1928 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1929 * once there is something ready to read() for the stream
1931 void (*poll_wait)(struct i915_perf_stream *stream,
1936 * @wait_unlocked: For handling a blocking read, wait until there is
1937 * something to ready to read() for the stream. E.g. wait on the same
1938 * wait queue that would be passed to poll_wait().
1940 int (*wait_unlocked)(struct i915_perf_stream *stream);
1943 * @read: Copy buffered metrics as records to userspace
1944 * **buf**: the userspace, destination buffer
1945 * **count**: the number of bytes to copy, requested by userspace
1946 * **offset**: zero at the start of the read, updated as the read
1947 * proceeds, it represents how many bytes have been copied so far and
1948 * the buffer offset for copying the next record.
1950 * Copy as many buffered i915 perf samples and records for this stream
1951 * to userspace as will fit in the given buffer.
1953 * Only write complete records; returning -%ENOSPC if there isn't room
1954 * for a complete record.
1956 * Return any error condition that results in a short read such as
1957 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1958 * returning to userspace.
1960 int (*read)(struct i915_perf_stream *stream,
1966 * @destroy: Cleanup any stream specific resources.
1968 * The stream will always be disabled before this is called.
1970 void (*destroy)(struct i915_perf_stream *stream);
1974 * struct i915_perf_stream - state for a single open stream FD
1976 struct i915_perf_stream {
1978 * @dev_priv: i915 drm device
1980 struct drm_i915_private *dev_priv;
1983 * @link: Links the stream into ``&drm_i915_private->streams``
1985 struct list_head link;
1988 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1989 * properties given when opening a stream, representing the contents
1990 * of a single sample as read() by userspace.
1995 * @sample_size: Considering the configured contents of a sample
1996 * combined with the required header size, this is the total size
1997 * of a single sample record.
2002 * @ctx: %NULL if measuring system-wide across all contexts or a
2003 * specific context that is being monitored.
2005 struct i915_gem_context *ctx;
2008 * @enabled: Whether the stream is currently enabled, considering
2009 * whether the stream was opened in a disabled state and based
2010 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2015 * @ops: The callbacks providing the implementation of this specific
2016 * type of configured stream.
2018 const struct i915_perf_stream_ops *ops;
2022 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2024 struct i915_oa_ops {
2026 * @init_oa_buffer: Resets the head and tail pointers of the
2027 * circular buffer for periodic OA reports.
2029 * Called when first opening a stream for OA metrics, but also may be
2030 * called in response to an OA buffer overflow or other error
2033 * Note it may be necessary to clear the full OA buffer here as part of
2034 * maintaining the invariable that new reports must be written to
2035 * zeroed memory for us to be able to reliable detect if an expected
2036 * report has not yet landed in memory. (At least on Haswell the OA
2037 * buffer tail pointer is not synchronized with reports being visible
2040 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2043 * @enable_metric_set: Applies any MUX configuration to set up the
2044 * Boolean and Custom (B/C) counters that are part of the counter
2045 * reports being sampled. May apply system constraints such as
2046 * disabling EU clock gating as required.
2048 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2051 * @disable_metric_set: Remove system constraints associated with using
2054 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2057 * @oa_enable: Enable periodic sampling
2059 void (*oa_enable)(struct drm_i915_private *dev_priv);
2062 * @oa_disable: Disable periodic sampling
2064 void (*oa_disable)(struct drm_i915_private *dev_priv);
2067 * @read: Copy data from the circular OA buffer into a given userspace
2070 int (*read)(struct i915_perf_stream *stream,
2076 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2078 * This is either called via fops or the poll check hrtimer (atomic
2079 * ctx) without any locks taken.
2081 * It's safe to read OA config state here unlocked, assuming that this
2082 * is only called while the stream is enabled, while the global OA
2083 * configuration can't be modified.
2085 * Efficiency is more important than avoiding some false positives
2086 * here, which will be handled gracefully - likely resulting in an
2087 * %EAGAIN error for userspace.
2089 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2092 struct intel_cdclk_state {
2093 unsigned int cdclk, vco, ref;
2096 struct drm_i915_private {
2097 struct drm_device drm;
2099 struct kmem_cache *objects;
2100 struct kmem_cache *vmas;
2101 struct kmem_cache *requests;
2102 struct kmem_cache *dependencies;
2104 const struct intel_device_info info;
2108 struct intel_uncore uncore;
2110 struct i915_virtual_gpu vgpu;
2112 struct intel_gvt *gvt;
2114 struct intel_huc huc;
2115 struct intel_guc guc;
2117 struct intel_csr csr;
2119 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2121 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2122 * controller on different i2c buses. */
2123 struct mutex gmbus_mutex;
2126 * Base address of the gmbus and gpio block.
2128 uint32_t gpio_mmio_base;
2130 /* MMIO base address for MIPI regs */
2131 uint32_t mipi_mmio_base;
2133 uint32_t psr_mmio_base;
2135 uint32_t pps_mmio_base;
2137 wait_queue_head_t gmbus_wait_queue;
2139 struct pci_dev *bridge_dev;
2140 struct i915_gem_context *kernel_context;
2141 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2142 struct i915_vma *semaphore;
2144 struct drm_dma_handle *status_page_dmah;
2145 struct resource mch_res;
2147 /* protects the irq masks */
2148 spinlock_t irq_lock;
2150 /* protects the mmio flip data */
2151 spinlock_t mmio_flip_lock;
2153 bool display_irqs_enabled;
2155 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2156 struct pm_qos_request pm_qos;
2158 /* Sideband mailbox protection */
2159 struct mutex sb_lock;
2161 /** Cached value of IMR to avoid reads in updating the bitfield */
2164 u32 de_irq_mask[I915_MAX_PIPES];
2171 u32 pipestat_irq_mask[I915_MAX_PIPES];
2173 struct i915_hotplug hotplug;
2174 struct intel_fbc fbc;
2175 struct i915_drrs drrs;
2176 struct intel_opregion opregion;
2177 struct intel_vbt_data vbt;
2179 bool preserve_bios_swizzle;
2182 struct intel_overlay *overlay;
2184 /* backlight registers and fields in struct intel_panel */
2185 struct mutex backlight_lock;
2188 bool no_aux_handshake;
2190 /* protects panel power sequencer state */
2191 struct mutex pps_mutex;
2193 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2194 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2196 unsigned int fsb_freq, mem_freq, is_ddr3;
2197 unsigned int skl_preferred_vco_freq;
2198 unsigned int max_cdclk_freq;
2200 unsigned int max_dotclk_freq;
2201 unsigned int rawclk_freq;
2202 unsigned int hpll_freq;
2203 unsigned int czclk_freq;
2207 * The current logical cdclk state.
2208 * See intel_atomic_state.cdclk.logical
2210 * For reading holding any crtc lock is sufficient,
2211 * for writing must hold all of them.
2213 struct intel_cdclk_state logical;
2215 * The current actual cdclk state.
2216 * See intel_atomic_state.cdclk.actual
2218 struct intel_cdclk_state actual;
2219 /* The current hardware cdclk state */
2220 struct intel_cdclk_state hw;
2224 * wq - Driver workqueue for GEM.
2226 * NOTE: Work items scheduled here are not allowed to grab any modeset
2227 * locks, for otherwise the flushing done in the pageflip code will
2228 * result in deadlocks.
2230 struct workqueue_struct *wq;
2232 /* Display functions */
2233 struct drm_i915_display_funcs display;
2235 /* PCH chipset type */
2236 enum intel_pch pch_type;
2237 unsigned short pch_id;
2239 unsigned long quirks;
2241 enum modeset_restore modeset_restore;
2242 struct mutex modeset_restore_lock;
2243 struct drm_atomic_state *modeset_restore_state;
2244 struct drm_modeset_acquire_ctx reset_ctx;
2246 struct list_head vm_list; /* Global list of all address spaces */
2247 struct i915_ggtt ggtt; /* VM representing the global address space */
2249 struct i915_gem_mm mm;
2250 DECLARE_HASHTABLE(mm_structs, 7);
2251 struct mutex mm_lock;
2253 /* The hw wants to have a stable context identifier for the lifetime
2254 * of the context (for OA, PASID, faults, etc). This is limited
2255 * in execlists to 21 bits.
2257 struct ida context_hw_ida;
2258 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2260 /* Kernel Modesetting */
2262 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2263 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2264 wait_queue_head_t pending_flip_queue;
2266 #ifdef CONFIG_DEBUG_FS
2267 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2270 /* dpll and cdclk state is protected by connection_mutex */
2271 int num_shared_dpll;
2272 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2273 const struct intel_dpll_mgr *dpll_mgr;
2276 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2277 * Must be global rather than per dpll, because on some platforms
2278 * plls share registers.
2280 struct mutex dpll_lock;
2282 unsigned int active_crtcs;
2283 unsigned int min_pixclk[I915_MAX_PIPES];
2285 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2287 struct i915_workarounds workarounds;
2289 struct i915_frontbuffer_tracking fb_tracking;
2291 struct intel_atomic_helper {
2292 struct llist_head free_list;
2293 struct work_struct free_work;
2298 bool mchbar_need_disable;
2300 struct intel_l3_parity l3_parity;
2302 /* Cannot be determined by PCIID. You must always read a register. */
2305 /* gen6+ rps state */
2306 struct intel_gen6_power_mgmt rps;
2308 /* ilk-only ips/rps state. Everything in here is protected by the global
2309 * mchdev_lock in intel_pm.c */
2310 struct intel_ilk_power_mgmt ips;
2312 struct i915_power_domains power_domains;
2314 struct i915_psr psr;
2316 struct i915_gpu_error gpu_error;
2318 struct drm_i915_gem_object *vlv_pctx;
2320 #ifdef CONFIG_DRM_FBDEV_EMULATION
2321 /* list of fbdev register on this device */
2322 struct intel_fbdev *fbdev;
2323 struct work_struct fbdev_suspend_work;
2326 struct drm_property *broadcast_rgb_property;
2327 struct drm_property *force_audio_property;
2329 /* hda/i915 audio component */
2330 struct i915_audio_component *audio_component;
2331 bool audio_component_registered;
2333 * av_mutex - mutex for audio/video sync
2336 struct mutex av_mutex;
2338 uint32_t hw_context_size;
2339 struct list_head context_list;
2343 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2344 u32 chv_phy_control;
2346 * Shadows for CHV DPLL_MD regs to keep the state
2347 * checker somewhat working in the presence hardware
2348 * crappiness (can't read out DPLL_MD for pipes B & C).
2350 u32 chv_dpll_md[I915_MAX_PIPES];
2354 bool suspended_to_idle;
2355 struct i915_suspend_saved_registers regfile;
2356 struct vlv_s0ix_state vlv_s0ix_state;
2359 I915_SAGV_UNKNOWN = 0,
2362 I915_SAGV_NOT_CONTROLLED
2366 /* protects DSPARB registers on pre-g4x/vlv/chv */
2367 spinlock_t dsparb_lock;
2370 * Raw watermark latency values:
2371 * in 0.1us units for WM0,
2372 * in 0.5us units for WM1+.
2375 uint16_t pri_latency[5];
2377 uint16_t spr_latency[5];
2379 uint16_t cur_latency[5];
2381 * Raw watermark memory latency values
2382 * for SKL for all 8 levels
2385 uint16_t skl_latency[8];
2387 /* current hardware state */
2389 struct ilk_wm_values hw;
2390 struct skl_wm_values skl_hw;
2391 struct vlv_wm_values vlv;
2397 * Should be held around atomic WM register writing; also
2398 * protects * intel_crtc->wm.active and
2399 * cstate->wm.need_postvbl_update.
2401 struct mutex wm_mutex;
2404 * Set during HW readout of watermarks/DDB. Some platforms
2405 * need to know when we're still using BIOS-provided values
2406 * (which we don't fully trust).
2408 bool distrust_bios_wm;
2411 struct i915_runtime_pm pm;
2416 struct kobject *metrics_kobj;
2417 struct ctl_table_header *sysctl_header;
2420 struct list_head streams;
2422 spinlock_t hook_lock;
2425 struct i915_perf_stream *exclusive_stream;
2427 u32 specific_ctx_id;
2429 struct hrtimer poll_check_timer;
2430 wait_queue_head_t poll_wq;
2434 int period_exponent;
2435 int timestamp_frequency;
2441 const struct i915_oa_reg *mux_regs;
2443 const struct i915_oa_reg *b_counter_regs;
2444 int b_counter_regs_len;
2447 struct i915_vma *vma;
2453 u32 gen7_latched_oastatus1;
2455 struct i915_oa_ops ops;
2456 const struct i915_oa_format *oa_formats;
2461 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2463 void (*resume)(struct drm_i915_private *);
2464 void (*cleanup_engine)(struct intel_engine_cs *engine);
2466 struct list_head timelines;
2467 struct i915_gem_timeline global_timeline;
2468 u32 active_requests;
2471 * Is the GPU currently considered idle, or busy executing
2472 * userspace requests? Whilst idle, we allow runtime power
2473 * management to power down the hardware and display clocks.
2474 * In order to reduce the effect on performance, there
2475 * is a slight delay before we do so.
2480 * We leave the user IRQ off as much as possible,
2481 * but this means that requests will finish and never
2482 * be retired once the system goes idle. Set a timer to
2483 * fire periodically while the ring is running. When it
2484 * fires, go retire requests.
2486 struct delayed_work retire_work;
2489 * When we detect an idle GPU, we want to turn on
2490 * powersaving features. So once we see that there
2491 * are no more requests outstanding and no more
2492 * arrive within a small period of time, we fire
2493 * off the idle_work.
2495 struct delayed_work idle_work;
2497 ktime_t last_init_time;
2500 /* perform PHY state sanity checks? */
2501 bool chv_phy_assert[2];
2505 /* Used to save the pipe-to-encoder mapping for audio */
2506 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2509 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2510 * will be rejected. Instead look for a better place.
2514 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2516 return container_of(dev, struct drm_i915_private, drm);
2519 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2521 return to_i915(dev_get_drvdata(kdev));
2524 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2526 return container_of(guc, struct drm_i915_private, guc);
2529 /* Simple iterator over all initialised engines */
2530 #define for_each_engine(engine__, dev_priv__, id__) \
2532 (id__) < I915_NUM_ENGINES; \
2534 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2536 #define __mask_next_bit(mask) ({ \
2537 int __idx = ffs(mask) - 1; \
2538 mask &= ~BIT(__idx); \
2542 /* Iterator over subset of engines selected by mask */
2543 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2544 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2545 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2547 enum hdmi_force_audio {
2548 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2549 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2550 HDMI_AUDIO_AUTO, /* trust EDID */
2551 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2554 #define I915_GTT_OFFSET_NONE ((u32)-1)
2557 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2558 * considered to be the frontbuffer for the given plane interface-wise. This
2559 * doesn't mean that the hw necessarily already scans it out, but that any
2560 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2562 * We have one bit per pipe and per scanout plane type.
2564 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2565 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2566 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2567 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2568 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2569 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2570 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2571 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2572 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2573 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2574 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2575 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2578 * Optimised SGL iterator for GEM objects
2580 static __always_inline struct sgt_iter {
2581 struct scatterlist *sgp;
2588 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2589 struct sgt_iter s = { .sgp = sgl };
2592 s.max = s.curr = s.sgp->offset;
2593 s.max += s.sgp->length;
2595 s.dma = sg_dma_address(s.sgp);
2597 s.pfn = page_to_pfn(sg_page(s.sgp));
2603 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2606 if (unlikely(sg_is_chain(sg)))
2607 sg = sg_chain_ptr(sg);
2612 * __sg_next - return the next scatterlist entry in a list
2613 * @sg: The current sg entry
2616 * If the entry is the last, return NULL; otherwise, step to the next
2617 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2618 * otherwise just return the pointer to the current element.
2620 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2622 #ifdef CONFIG_DEBUG_SG
2623 BUG_ON(sg->sg_magic != SG_MAGIC);
2625 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2629 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2630 * @__dmap: DMA address (output)
2631 * @__iter: 'struct sgt_iter' (iterator state, internal)
2632 * @__sgt: sg_table to iterate over (input)
2634 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2635 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2636 ((__dmap) = (__iter).dma + (__iter).curr); \
2637 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2638 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2641 * for_each_sgt_page - iterate over the pages of the given sg_table
2642 * @__pp: page pointer (output)
2643 * @__iter: 'struct sgt_iter' (iterator state, internal)
2644 * @__sgt: sg_table to iterate over (input)
2646 #define for_each_sgt_page(__pp, __iter, __sgt) \
2647 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2648 ((__pp) = (__iter).pfn == 0 ? NULL : \
2649 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2650 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2651 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2653 static inline const struct intel_device_info *
2654 intel_info(const struct drm_i915_private *dev_priv)
2656 return &dev_priv->info;
2659 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2661 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2662 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2664 #define REVID_FOREVER 0xff
2665 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2667 #define GEN_FOREVER (0)
2669 * Returns true if Gen is in inclusive range [Start, End].
2671 * Use GEN_FOREVER for unbound start and or end.
2673 #define IS_GEN(dev_priv, s, e) ({ \
2674 unsigned int __s = (s), __e = (e); \
2675 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2676 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2677 if ((__s) != GEN_FOREVER) \
2679 if ((__e) == GEN_FOREVER) \
2680 __e = BITS_PER_LONG - 1; \
2683 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2687 * Return true if revision is in range [since,until] inclusive.
2689 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2691 #define IS_REVID(p, since, until) \
2692 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2694 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2695 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2696 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2697 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2698 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2699 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2700 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2701 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2702 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2703 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2704 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2705 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2706 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2707 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2708 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2709 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2710 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2711 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2712 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2713 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2714 INTEL_DEVID(dev_priv) == 0x0152 || \
2715 INTEL_DEVID(dev_priv) == 0x015a)
2716 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2717 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2718 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2719 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2720 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2721 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2722 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2723 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2724 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2725 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2726 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2727 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2728 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2729 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2730 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2731 /* ULX machines are also considered ULT. */
2732 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2733 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2734 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2735 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2736 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2737 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2738 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2739 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2740 /* ULX machines are also considered ULT. */
2741 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2742 INTEL_DEVID(dev_priv) == 0x0A1E)
2743 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2744 INTEL_DEVID(dev_priv) == 0x1913 || \
2745 INTEL_DEVID(dev_priv) == 0x1916 || \
2746 INTEL_DEVID(dev_priv) == 0x1921 || \
2747 INTEL_DEVID(dev_priv) == 0x1926)
2748 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2749 INTEL_DEVID(dev_priv) == 0x1915 || \
2750 INTEL_DEVID(dev_priv) == 0x191E)
2751 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2752 INTEL_DEVID(dev_priv) == 0x5913 || \
2753 INTEL_DEVID(dev_priv) == 0x5916 || \
2754 INTEL_DEVID(dev_priv) == 0x5921 || \
2755 INTEL_DEVID(dev_priv) == 0x5926)
2756 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2757 INTEL_DEVID(dev_priv) == 0x5915 || \
2758 INTEL_DEVID(dev_priv) == 0x591E)
2759 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2760 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2761 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2762 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2764 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2766 #define SKL_REVID_A0 0x0
2767 #define SKL_REVID_B0 0x1
2768 #define SKL_REVID_C0 0x2
2769 #define SKL_REVID_D0 0x3
2770 #define SKL_REVID_E0 0x4
2771 #define SKL_REVID_F0 0x5
2772 #define SKL_REVID_G0 0x6
2773 #define SKL_REVID_H0 0x7
2775 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2777 #define BXT_REVID_A0 0x0
2778 #define BXT_REVID_A1 0x1
2779 #define BXT_REVID_B0 0x3
2780 #define BXT_REVID_B_LAST 0x8
2781 #define BXT_REVID_C0 0x9
2783 #define IS_BXT_REVID(dev_priv, since, until) \
2784 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2786 #define KBL_REVID_A0 0x0
2787 #define KBL_REVID_B0 0x1
2788 #define KBL_REVID_C0 0x2
2789 #define KBL_REVID_D0 0x3
2790 #define KBL_REVID_E0 0x4
2792 #define IS_KBL_REVID(dev_priv, since, until) \
2793 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2795 #define GLK_REVID_A0 0x0
2796 #define GLK_REVID_A1 0x1
2798 #define IS_GLK_REVID(dev_priv, since, until) \
2799 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2802 * The genX designation typically refers to the render engine, so render
2803 * capability related checks should use IS_GEN, while display and other checks
2804 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2807 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2808 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2809 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2810 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2811 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2812 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2813 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2814 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2816 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2817 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2818 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2820 #define ENGINE_MASK(id) BIT(id)
2821 #define RENDER_RING ENGINE_MASK(RCS)
2822 #define BSD_RING ENGINE_MASK(VCS)
2823 #define BLT_RING ENGINE_MASK(BCS)
2824 #define VEBOX_RING ENGINE_MASK(VECS)
2825 #define BSD2_RING ENGINE_MASK(VCS2)
2826 #define ALL_ENGINES (~0)
2828 #define HAS_ENGINE(dev_priv, id) \
2829 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2831 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2832 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2833 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2834 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2836 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2837 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2838 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2839 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2840 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2842 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2844 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2845 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2846 ((dev_priv)->info.has_logical_ring_contexts)
2847 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2848 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2849 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2851 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2852 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2853 ((dev_priv)->info.overlay_needs_physical)
2855 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2856 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2858 /* WaRsDisableCoarsePowerGating:skl,bxt */
2859 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2860 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2863 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2864 * even when in MSI mode. This results in spurious interrupt warnings if the
2865 * legacy irq no. is shared with another device. The kernel then disables that
2866 * interrupt source and so prevents the other device from working properly.
2868 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2869 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2871 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2872 * rows, which changed the alignment requirements and fence programming.
2874 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2875 !(IS_I915G(dev_priv) || \
2876 IS_I915GM(dev_priv)))
2877 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2878 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2880 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2881 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2882 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2884 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2886 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2888 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2889 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2890 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2891 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2892 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2894 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2896 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2897 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2900 * For now, anything with a GuC requires uCode loading, and then supports
2901 * command submission once loaded. But these are logically independent
2902 * properties, so we have separate macros to test them.
2904 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2905 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2906 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2907 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2909 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2911 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2913 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2914 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2915 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2916 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2917 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2918 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2919 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2920 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2921 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2922 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2923 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2924 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2926 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2927 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2928 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2929 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2930 #define HAS_PCH_LPT_LP(dev_priv) \
2931 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2932 #define HAS_PCH_LPT_H(dev_priv) \
2933 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2934 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2935 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2936 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2937 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2939 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2941 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2943 /* DPF == dynamic parity feature */
2944 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2945 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2946 2 : HAS_L3_DPF(dev_priv))
2948 #define GT_FREQUENCY_MULTIPLIER 50
2949 #define GEN9_FREQ_SCALER 3
2951 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2953 #include "i915_trace.h"
2955 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2957 #ifdef CONFIG_INTEL_IOMMU
2958 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2964 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2967 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2971 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2972 const char *fmt, ...);
2974 #define i915_report_error(dev_priv, fmt, ...) \
2975 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2977 #ifdef CONFIG_COMPAT
2978 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2981 #define i915_compat_ioctl NULL
2983 extern const struct dev_pm_ops i915_pm_ops;
2985 extern int i915_driver_load(struct pci_dev *pdev,
2986 const struct pci_device_id *ent);
2987 extern void i915_driver_unload(struct drm_device *dev);
2988 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2989 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2990 extern void i915_reset(struct drm_i915_private *dev_priv);
2991 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2992 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2993 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2994 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2995 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2996 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2997 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2998 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3000 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3001 int intel_engines_init(struct drm_i915_private *dev_priv);
3003 /* intel_hotplug.c */
3004 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3005 u32 pin_mask, u32 long_mask);
3006 void intel_hpd_init(struct drm_i915_private *dev_priv);
3007 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3008 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3009 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3010 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3011 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3014 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3016 unsigned long delay;
3018 if (unlikely(!i915.enable_hangcheck))
3021 /* Don't continually defer the hangcheck so that it is always run at
3022 * least once after work has been scheduled on any ring. Otherwise,
3023 * we will ignore a hung ring if a second ring is kept busy.
3026 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3027 queue_delayed_work(system_long_wq,
3028 &dev_priv->gpu_error.hangcheck_work, delay);
3032 void i915_handle_error(struct drm_i915_private *dev_priv,
3034 const char *fmt, ...);
3036 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3037 int intel_irq_install(struct drm_i915_private *dev_priv);
3038 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3040 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3041 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3042 bool restore_forcewake);
3043 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3044 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3045 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3046 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3047 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3049 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3050 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3051 enum forcewake_domains domains);
3052 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3053 enum forcewake_domains domains);
3054 /* Like above but the caller must manage the uncore.lock itself.
3055 * Must be used with I915_READ_FW and friends.
3057 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3058 enum forcewake_domains domains);
3059 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3060 enum forcewake_domains domains);
3061 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3063 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3065 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3069 const unsigned long timeout_ms);
3070 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3074 const unsigned long timeout_ms);
3076 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3078 return dev_priv->gvt;
3081 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3083 return dev_priv->vgpu.active;
3087 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3091 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3094 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3095 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3096 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3099 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3100 uint32_t interrupt_mask,
3101 uint32_t enabled_irq_mask);
3103 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3105 ilk_update_display_irq(dev_priv, bits, bits);
3108 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3110 ilk_update_display_irq(dev_priv, bits, 0);
3112 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3114 uint32_t interrupt_mask,
3115 uint32_t enabled_irq_mask);
3116 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3117 enum pipe pipe, uint32_t bits)
3119 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3121 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3122 enum pipe pipe, uint32_t bits)
3124 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3126 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3127 uint32_t interrupt_mask,
3128 uint32_t enabled_irq_mask);
3130 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3132 ibx_display_interrupt_update(dev_priv, bits, bits);
3135 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3137 ibx_display_interrupt_update(dev_priv, bits, 0);
3141 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3142 struct drm_file *file_priv);
3143 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3144 struct drm_file *file_priv);
3145 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3146 struct drm_file *file_priv);
3147 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3148 struct drm_file *file_priv);
3149 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3150 struct drm_file *file_priv);
3151 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3152 struct drm_file *file_priv);
3153 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3154 struct drm_file *file_priv);
3155 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3156 struct drm_file *file_priv);
3157 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3158 struct drm_file *file_priv);
3159 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3160 struct drm_file *file_priv);
3161 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3162 struct drm_file *file);
3163 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3164 struct drm_file *file);
3165 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3166 struct drm_file *file_priv);
3167 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3168 struct drm_file *file_priv);
3169 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3170 struct drm_file *file_priv);
3171 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3172 struct drm_file *file_priv);
3173 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3174 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3175 struct drm_file *file);
3176 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3177 struct drm_file *file_priv);
3178 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3179 struct drm_file *file_priv);
3180 void i915_gem_sanitize(struct drm_i915_private *i915);
3181 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3182 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3183 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3184 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3185 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3187 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3188 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3189 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3190 const struct drm_i915_gem_object_ops *ops);
3191 struct drm_i915_gem_object *
3192 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3193 struct drm_i915_gem_object *
3194 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3195 const void *data, size_t size);
3196 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3197 void i915_gem_free_object(struct drm_gem_object *obj);
3199 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3201 /* A single pass should suffice to release all the freed objects (along
3202 * most call paths) , but be a little more paranoid in that freeing
3203 * the objects does take a little amount of time, during which the rcu
3204 * callbacks could have added new objects into the freed list, and
3205 * armed the work again.
3209 } while (flush_work(&i915->mm.free_work));
3212 struct i915_vma * __must_check
3213 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3214 const struct i915_ggtt_view *view,
3219 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3220 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3222 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3224 static inline int __sg_page_count(const struct scatterlist *sg)
3226 return sg->length >> PAGE_SHIFT;
3229 struct scatterlist *
3230 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3231 unsigned int n, unsigned int *offset);
3234 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3238 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3242 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3245 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3246 struct sg_table *pages);
3247 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3249 static inline int __must_check
3250 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3252 might_lock(&obj->mm.lock);
3254 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3257 return __i915_gem_object_get_pages(obj);
3261 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3263 GEM_BUG_ON(!obj->mm.pages);
3265 atomic_inc(&obj->mm.pages_pin_count);
3269 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3271 return atomic_read(&obj->mm.pages_pin_count);
3275 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3277 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3278 GEM_BUG_ON(!obj->mm.pages);
3280 atomic_dec(&obj->mm.pages_pin_count);
3284 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3286 __i915_gem_object_unpin_pages(obj);
3289 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3294 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3295 enum i915_mm_subclass subclass);
3296 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3298 enum i915_map_type {
3304 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3305 * @obj: the object to map into kernel address space
3306 * @type: the type of mapping, used to select pgprot_t
3308 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3309 * pages and then returns a contiguous mapping of the backing storage into
3310 * the kernel address space. Based on the @type of mapping, the PTE will be
3311 * set to either WriteBack or WriteCombine (via pgprot_t).
3313 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3314 * mapping is no longer required.
3316 * Returns the pointer through which to access the mapped object, or an
3317 * ERR_PTR() on error.
3319 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3320 enum i915_map_type type);
3323 * i915_gem_object_unpin_map - releases an earlier mapping
3324 * @obj: the object to unmap
3326 * After pinning the object and mapping its pages, once you are finished
3327 * with your access, call i915_gem_object_unpin_map() to release the pin
3328 * upon the mapping. Once the pin count reaches zero, that mapping may be
3331 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3333 i915_gem_object_unpin_pages(obj);
3336 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3337 unsigned int *needs_clflush);
3338 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3339 unsigned int *needs_clflush);
3340 #define CLFLUSH_BEFORE 0x1
3341 #define CLFLUSH_AFTER 0x2
3342 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3345 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3347 i915_gem_object_unpin_pages(obj);
3350 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3351 void i915_vma_move_to_active(struct i915_vma *vma,
3352 struct drm_i915_gem_request *req,
3353 unsigned int flags);
3354 int i915_gem_dumb_create(struct drm_file *file_priv,
3355 struct drm_device *dev,
3356 struct drm_mode_create_dumb *args);
3357 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3358 uint32_t handle, uint64_t *offset);
3359 int i915_gem_mmap_gtt_version(void);
3361 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3362 struct drm_i915_gem_object *new,
3363 unsigned frontbuffer_bits);
3365 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3367 struct drm_i915_gem_request *
3368 i915_gem_find_active_request(struct intel_engine_cs *engine);
3370 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3372 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3374 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3377 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3379 return unlikely(test_bit(I915_WEDGED, &error->flags));
3382 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3384 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3387 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3389 return READ_ONCE(error->reset_count);
3392 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3393 void i915_gem_reset(struct drm_i915_private *dev_priv);
3394 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3395 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3397 void i915_gem_init_mmio(struct drm_i915_private *i915);
3398 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3399 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3400 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3401 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3402 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3403 unsigned int flags);
3404 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3405 void i915_gem_resume(struct drm_i915_private *dev_priv);
3406 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3407 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3410 struct intel_rps_client *rps);
3411 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3414 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3417 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3420 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3421 struct i915_vma * __must_check
3422 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3424 const struct i915_ggtt_view *view);
3425 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3426 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3428 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3429 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3431 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3432 enum i915_cache_level cache_level);
3434 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3435 struct dma_buf *dma_buf);
3437 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3438 struct drm_gem_object *gem_obj, int flags);
3440 static inline struct i915_hw_ppgtt *
3441 i915_vm_to_ppgtt(struct i915_address_space *vm)
3443 return container_of(vm, struct i915_hw_ppgtt, base);
3446 /* i915_gem_fence_reg.c */
3447 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3448 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3450 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3451 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3453 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3454 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3455 struct sg_table *pages);
3456 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3457 struct sg_table *pages);
3459 static inline struct i915_gem_context *
3460 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3462 struct i915_gem_context *ctx;
3464 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3466 ctx = idr_find(&file_priv->context_idr, id);
3468 return ERR_PTR(-ENOENT);
3473 static inline struct i915_gem_context *
3474 i915_gem_context_get(struct i915_gem_context *ctx)
3476 kref_get(&ctx->ref);
3480 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3482 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3483 kref_put(&ctx->ref, i915_gem_context_free);
3486 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3488 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3490 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3494 static inline struct intel_timeline *
3495 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3496 struct intel_engine_cs *engine)
3498 struct i915_address_space *vm;
3500 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3501 return &vm->timeline.engine[engine->id];
3504 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3505 struct drm_file *file);
3507 /* i915_gem_evict.c */
3508 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3509 u64 min_size, u64 alignment,
3510 unsigned cache_level,
3513 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3514 struct drm_mm_node *node,
3515 unsigned int flags);
3516 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3518 /* belongs in i915_gem_gtt.h */
3519 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3522 if (INTEL_GEN(dev_priv) < 6)
3523 intel_gtt_chipset_flush();
3526 /* i915_gem_stolen.c */
3527 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3528 struct drm_mm_node *node, u64 size,
3529 unsigned alignment);
3530 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3531 struct drm_mm_node *node, u64 size,
3532 unsigned alignment, u64 start,
3534 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3535 struct drm_mm_node *node);
3536 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3537 void i915_gem_cleanup_stolen(struct drm_device *dev);
3538 struct drm_i915_gem_object *
3539 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3540 struct drm_i915_gem_object *
3541 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3546 /* i915_gem_internal.c */
3547 struct drm_i915_gem_object *
3548 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3551 /* i915_gem_shrinker.c */
3552 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3553 unsigned long target,
3555 #define I915_SHRINK_PURGEABLE 0x1
3556 #define I915_SHRINK_UNBOUND 0x2
3557 #define I915_SHRINK_BOUND 0x4
3558 #define I915_SHRINK_ACTIVE 0x8
3559 #define I915_SHRINK_VMAPS 0x10
3560 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3561 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3562 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3565 /* i915_gem_tiling.c */
3566 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3568 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3570 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3571 i915_gem_object_is_tiled(obj);
3574 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3575 unsigned int tiling, unsigned int stride);
3576 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3577 unsigned int tiling, unsigned int stride);
3579 /* i915_debugfs.c */
3580 #ifdef CONFIG_DEBUG_FS
3581 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3582 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3583 int i915_debugfs_connector_add(struct drm_connector *connector);
3584 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3586 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3587 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3588 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3590 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3593 /* i915_gpu_error.c */
3594 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3597 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3598 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3599 const struct i915_gpu_state *gpu);
3600 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3601 struct drm_i915_private *i915,
3602 size_t count, loff_t pos);
3603 static inline void i915_error_state_buf_release(
3604 struct drm_i915_error_state_buf *eb)
3609 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3610 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3612 const char *error_msg);
3614 static inline struct i915_gpu_state *
3615 i915_gpu_state_get(struct i915_gpu_state *gpu)
3617 kref_get(&gpu->ref);
3621 void __i915_gpu_state_free(struct kref *kref);
3622 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3625 kref_put(&gpu->ref, __i915_gpu_state_free);
3628 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3629 void i915_reset_error_state(struct drm_i915_private *i915);
3633 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3635 const char *error_msg)
3639 static inline struct i915_gpu_state *
3640 i915_first_error_state(struct drm_i915_private *i915)
3645 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3651 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3653 /* i915_cmd_parser.c */
3654 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3655 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3656 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3657 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3658 struct drm_i915_gem_object *batch_obj,
3659 struct drm_i915_gem_object *shadow_batch_obj,
3660 u32 batch_start_offset,
3665 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3666 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3667 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3668 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3670 /* i915_suspend.c */
3671 extern int i915_save_state(struct drm_i915_private *dev_priv);
3672 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3675 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3676 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3679 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3680 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3681 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3684 extern struct i2c_adapter *
3685 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3686 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3687 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3688 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3690 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3692 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3695 int intel_bios_init(struct drm_i915_private *dev_priv);
3696 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3697 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3698 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3699 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3700 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3701 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3702 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3703 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3705 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3709 /* intel_opregion.c */
3711 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3712 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3713 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3714 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3715 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3717 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3719 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3721 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3722 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3723 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3724 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3728 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3733 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3737 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3745 extern void intel_register_dsm_handler(void);
3746 extern void intel_unregister_dsm_handler(void);
3748 static inline void intel_register_dsm_handler(void) { return; }
3749 static inline void intel_unregister_dsm_handler(void) { return; }
3750 #endif /* CONFIG_ACPI */
3752 /* intel_device_info.c */
3753 static inline struct intel_device_info *
3754 mkwrite_device_info(struct drm_i915_private *dev_priv)
3756 return (struct intel_device_info *)&dev_priv->info;
3759 const char *intel_platform_name(enum intel_platform platform);
3760 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3761 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3764 extern void intel_modeset_init_hw(struct drm_device *dev);
3765 extern int intel_modeset_init(struct drm_device *dev);
3766 extern void intel_modeset_gem_init(struct drm_device *dev);
3767 extern void intel_modeset_cleanup(struct drm_device *dev);
3768 extern int intel_connector_register(struct drm_connector *);
3769 extern void intel_connector_unregister(struct drm_connector *);
3770 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3772 extern void intel_display_resume(struct drm_device *dev);
3773 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3774 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3775 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3776 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3777 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3778 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3781 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3782 struct drm_file *file);
3785 extern struct intel_overlay_error_state *
3786 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3787 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3788 struct intel_overlay_error_state *error);
3790 extern struct intel_display_error_state *
3791 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3792 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3793 struct intel_display_error_state *error);
3795 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3796 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3797 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3798 u32 reply_mask, u32 reply, int timeout_base_ms);
3800 /* intel_sideband.c */
3801 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3802 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3803 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3804 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3805 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3806 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3807 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3808 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3809 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3810 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3811 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3812 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3813 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3814 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3815 enum intel_sbi_destination destination);
3816 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3817 enum intel_sbi_destination destination);
3818 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3819 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3821 /* intel_dpio_phy.c */
3822 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3823 enum dpio_phy *phy, enum dpio_channel *ch);
3824 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3825 enum port port, u32 margin, u32 scale,
3826 u32 enable, u32 deemphasis);
3827 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3828 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3829 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3831 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3833 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3834 uint8_t lane_count);
3835 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3836 uint8_t lane_lat_optim_mask);
3837 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3839 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3840 u32 deemph_reg_value, u32 margin_reg_value,
3841 bool uniq_trans_scale);
3842 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3844 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3845 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3846 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3847 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3849 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3850 u32 demph_reg_value, u32 preemph_reg_value,
3851 u32 uniqtranscale_reg_value, u32 tx3_demph);
3852 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3853 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3854 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3856 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3857 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3859 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3860 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3862 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3863 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3864 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3865 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3867 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3868 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3869 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3870 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3872 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3873 * will be implemented using 2 32-bit writes in an arbitrary order with
3874 * an arbitrary delay between them. This can cause the hardware to
3875 * act upon the intermediate value, possibly leading to corruption and
3876 * machine death. For this reason we do not support I915_WRITE64, or
3877 * dev_priv->uncore.funcs.mmio_writeq.
3879 * When reading a 64-bit value as two 32-bit values, the delay may cause
3880 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3881 * occasionally a 64-bit register does not actualy support a full readq
3882 * and must be read using two 32-bit reads.
3884 * You have been warned.
3886 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3888 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3889 u32 upper, lower, old_upper, loop = 0; \
3890 upper = I915_READ(upper_reg); \
3892 old_upper = upper; \
3893 lower = I915_READ(lower_reg); \
3894 upper = I915_READ(upper_reg); \
3895 } while (upper != old_upper && loop++ < 2); \
3896 (u64)upper << 32 | lower; })
3898 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3899 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3901 #define __raw_read(x, s) \
3902 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3905 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3908 #define __raw_write(x, s) \
3909 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3910 i915_reg_t reg, uint##x##_t val) \
3912 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3927 /* These are untraced mmio-accessors that are only valid to be used inside
3928 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3931 * Think twice, and think again, before using these.
3933 * As an example, these accessors can possibly be used between:
3935 * spin_lock_irq(&dev_priv->uncore.lock);
3936 * intel_uncore_forcewake_get__locked();
3940 * intel_uncore_forcewake_put__locked();
3941 * spin_unlock_irq(&dev_priv->uncore.lock);
3944 * Note: some registers may not need forcewake held, so
3945 * intel_uncore_forcewake_{get,put} can be omitted, see
3946 * intel_uncore_forcewake_for_reg().
3948 * Certain architectures will die if the same cacheline is concurrently accessed
3949 * by different clients (e.g. on Ivybridge). Access to registers should
3950 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3951 * a more localised lock guarding all access to that bank of registers.
3953 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3954 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3955 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3956 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3958 /* "Broadcast RGB" property */
3959 #define INTEL_BROADCAST_RGB_AUTO 0
3960 #define INTEL_BROADCAST_RGB_FULL 1
3961 #define INTEL_BROADCAST_RGB_LIMITED 2
3963 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3965 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3966 return VLV_VGACNTRL;
3967 else if (INTEL_GEN(dev_priv) >= 5)
3968 return CPU_VGACNTRL;
3973 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3975 unsigned long j = msecs_to_jiffies(m);
3977 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3980 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3982 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3985 static inline unsigned long
3986 timespec_to_jiffies_timeout(const struct timespec *value)
3988 unsigned long j = timespec_to_jiffies(value);
3990 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3994 * If you need to wait X milliseconds between events A and B, but event B
3995 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3996 * when event A happened, then just before event B you call this function and
3997 * pass the timestamp as the first argument, and X as the second argument.
4000 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4002 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4005 * Don't re-read the value of "jiffies" every time since it may change
4006 * behind our back and break the math.
4008 tmp_jiffies = jiffies;
4009 target_jiffies = timestamp_jiffies +
4010 msecs_to_jiffies_timeout(to_wait_ms);
4012 if (time_after(target_jiffies, tmp_jiffies)) {
4013 remaining_jiffies = target_jiffies - tmp_jiffies;
4014 while (remaining_jiffies)
4016 schedule_timeout_uninterruptible(remaining_jiffies);
4021 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4023 struct intel_engine_cs *engine = req->engine;
4026 /* Note that the engine may have wrapped around the seqno, and
4027 * so our request->global_seqno will be ahead of the hardware,
4028 * even though it completed the request before wrapping. We catch
4029 * this by kicking all the waiters before resetting the seqno
4030 * in hardware, and also signal the fence.
4032 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4035 /* The request was dequeued before we were awoken. We check after
4036 * inspecting the hw to confirm that this was the same request
4037 * that generated the HWS update. The memory barriers within
4038 * the request execution are sufficient to ensure that a check
4039 * after reading the value from hw matches this request.
4041 seqno = i915_gem_request_global_seqno(req);
4045 /* Before we do the heavier coherent read of the seqno,
4046 * check the value (hopefully) in the CPU cacheline.
4048 if (__i915_gem_request_completed(req, seqno))
4051 /* Ensure our read of the seqno is coherent so that we
4052 * do not "miss an interrupt" (i.e. if this is the last
4053 * request and the seqno write from the GPU is not visible
4054 * by the time the interrupt fires, we will see that the
4055 * request is incomplete and go back to sleep awaiting
4056 * another interrupt that will never come.)
4058 * Strictly, we only need to do this once after an interrupt,
4059 * but it is easier and safer to do it every time the waiter
4062 if (engine->irq_seqno_barrier &&
4063 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
4064 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4065 struct task_struct *tsk;
4067 /* The ordering of irq_posted versus applying the barrier
4068 * is crucial. The clearing of the current irq_posted must
4069 * be visible before we perform the barrier operation,
4070 * such that if a subsequent interrupt arrives, irq_posted
4071 * is reasserted and our task rewoken (which causes us to
4072 * do another __i915_request_irq_complete() immediately
4073 * and reapply the barrier). Conversely, if the clear
4074 * occurs after the barrier, then an interrupt that arrived
4075 * whilst we waited on the barrier would not trigger a
4076 * barrier on the next pass, and the read may not see the
4079 engine->irq_seqno_barrier(engine);
4081 /* If we consume the irq, but we are no longer the bottom-half,
4082 * the real bottom-half may not have serialised their own
4083 * seqno check with the irq-barrier (i.e. may have inspected
4084 * the seqno before we believe it coherent since they see
4085 * irq_posted == false but we are still running).
4088 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
4089 if (tsk && tsk != current)
4090 /* Note that if the bottom-half is changed as we
4091 * are sending the wake-up, the new bottom-half will
4092 * be woken by whomever made the change. We only have
4093 * to worry about when we steal the irq-posted for
4096 wake_up_process(tsk);
4099 if (__i915_gem_request_completed(req, seqno))
4106 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4107 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4109 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4110 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4111 * perform the operation. To check beforehand, pass in the parameters to
4112 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4113 * you only need to pass in the minor offsets, page-aligned pointers are
4116 * For just checking for SSE4.1, in the foreknowledge that the future use
4117 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4119 #define i915_can_memcpy_from_wc(dst, src, len) \
4120 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4122 #define i915_has_memcpy_from_wc() \
4123 i915_memcpy_from_wc(NULL, NULL, 0)
4126 int remap_io_mapping(struct vm_area_struct *vma,
4127 unsigned long addr, unsigned long pfn, unsigned long size,
4128 struct io_mapping *iomap);
4130 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4132 return (obj->cache_level != I915_CACHE_NONE ||
4133 HAS_LLC(to_i915(obj->base.dev)));