drm/i915: Update DRIVER_DATE to 20170306
[platform/kernel/linux-starfive.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
35
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
46
47 #include <drm/drmP.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
53
54 #include "i915_params.h"
55 #include "i915_reg.h"
56 #include "i915_utils.h"
57
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
60 #include "intel_uc.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
63
64 #include "i915_gem.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
72
73 #include "i915_vma.h"
74
75 #include "intel_gvt.h"
76
77 /* General customization:
78  */
79
80 #define DRIVER_NAME             "i915"
81 #define DRIVER_DESC             "Intel Graphics"
82 #define DRIVER_DATE             "20170306"
83 #define DRIVER_TIMESTAMP        1488785683
84
85 #undef WARN_ON
86 /* Many gcc seem to no see through this and fall over :( */
87 #if 0
88 #define WARN_ON(x) ({ \
89         bool __i915_warn_cond = (x); \
90         if (__builtin_constant_p(__i915_warn_cond)) \
91                 BUILD_BUG_ON(__i915_warn_cond); \
92         WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
93 #else
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #endif
96
97 #undef WARN_ON_ONCE
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
99
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101                              (long) (x), __func__);
102
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105  * which may not necessarily be a user visible problem.  This will either
106  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107  * enable distros and users to tailor their preferred amount of i915 abrt
108  * spam.
109  */
110 #define I915_STATE_WARN(condition, format...) ({                        \
111         int __ret_warn_on = !!(condition);                              \
112         if (unlikely(__ret_warn_on))                                    \
113                 if (!WARN(i915.verbose_state_checks, format))           \
114                         DRM_ERROR(format);                              \
115         unlikely(__ret_warn_on);                                        \
116 })
117
118 #define I915_STATE_WARN_ON(x)                                           \
119         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
120
121 bool __i915_inject_load_failure(const char *func, int line);
122 #define i915_inject_load_failure() \
123         __i915_inject_load_failure(__func__, __LINE__)
124
125 typedef struct {
126         uint32_t val;
127 } uint_fixed_16_16_t;
128
129 #define FP_16_16_MAX ({ \
130         uint_fixed_16_16_t fp; \
131         fp.val = UINT_MAX; \
132         fp; \
133 })
134
135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
136 {
137         uint_fixed_16_16_t fp;
138
139         WARN_ON(val >> 16);
140
141         fp.val = val << 16;
142         return fp;
143 }
144
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
146 {
147         return DIV_ROUND_UP(fp.val, 1 << 16);
148 }
149
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
151 {
152         return fp.val >> 16;
153 }
154
155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
156                                                  uint_fixed_16_16_t min2)
157 {
158         uint_fixed_16_16_t min;
159
160         min.val = min(min1.val, min2.val);
161         return min;
162 }
163
164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
165                                                  uint_fixed_16_16_t max2)
166 {
167         uint_fixed_16_16_t max;
168
169         max.val = max(max1.val, max2.val);
170         return max;
171 }
172
173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
174                                                           uint32_t d)
175 {
176         uint_fixed_16_16_t fp, res;
177
178         fp = u32_to_fixed_16_16(val);
179         res.val = DIV_ROUND_UP(fp.val, d);
180         return res;
181 }
182
183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
184                                                               uint32_t d)
185 {
186         uint_fixed_16_16_t res;
187         uint64_t interm_val;
188
189         interm_val = (uint64_t)val << 16;
190         interm_val = DIV_ROUND_UP_ULL(interm_val, d);
191         WARN_ON(interm_val >> 32);
192         res.val = (uint32_t) interm_val;
193
194         return res;
195 }
196
197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
198                                                      uint_fixed_16_16_t mul)
199 {
200         uint64_t intermediate_val;
201         uint_fixed_16_16_t fp;
202
203         intermediate_val = (uint64_t) val * mul.val;
204         WARN_ON(intermediate_val >> 32);
205         fp.val = (uint32_t) intermediate_val;
206         return fp;
207 }
208
209 static inline const char *yesno(bool v)
210 {
211         return v ? "yes" : "no";
212 }
213
214 static inline const char *onoff(bool v)
215 {
216         return v ? "on" : "off";
217 }
218
219 static inline const char *enableddisabled(bool v)
220 {
221         return v ? "enabled" : "disabled";
222 }
223
224 enum pipe {
225         INVALID_PIPE = -1,
226         PIPE_A = 0,
227         PIPE_B,
228         PIPE_C,
229         _PIPE_EDP,
230         I915_MAX_PIPES = _PIPE_EDP
231 };
232 #define pipe_name(p) ((p) + 'A')
233
234 enum transcoder {
235         TRANSCODER_A = 0,
236         TRANSCODER_B,
237         TRANSCODER_C,
238         TRANSCODER_EDP,
239         TRANSCODER_DSI_A,
240         TRANSCODER_DSI_C,
241         I915_MAX_TRANSCODERS
242 };
243
244 static inline const char *transcoder_name(enum transcoder transcoder)
245 {
246         switch (transcoder) {
247         case TRANSCODER_A:
248                 return "A";
249         case TRANSCODER_B:
250                 return "B";
251         case TRANSCODER_C:
252                 return "C";
253         case TRANSCODER_EDP:
254                 return "EDP";
255         case TRANSCODER_DSI_A:
256                 return "DSI A";
257         case TRANSCODER_DSI_C:
258                 return "DSI C";
259         default:
260                 return "<invalid>";
261         }
262 }
263
264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
265 {
266         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
267 }
268
269 /*
270  * Global legacy plane identifier. Valid only for primary/sprite
271  * planes on pre-g4x, and only for primary planes on g4x+.
272  */
273 enum plane {
274         PLANE_A,
275         PLANE_B,
276         PLANE_C,
277 };
278 #define plane_name(p) ((p) + 'A')
279
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
281
282 /*
283  * Per-pipe plane identifier.
284  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285  * number of planes per CRTC.  Not all platforms really have this many planes,
286  * which means some arrays of size I915_MAX_PLANES may have unused entries
287  * between the topmost sprite plane and the cursor plane.
288  *
289  * This is expected to be passed to various register macros
290  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
291  */
292 enum plane_id {
293         PLANE_PRIMARY,
294         PLANE_SPRITE0,
295         PLANE_SPRITE1,
296         PLANE_SPRITE2,
297         PLANE_CURSOR,
298         I915_MAX_PLANES,
299 };
300
301 #define for_each_plane_id_on_crtc(__crtc, __p) \
302         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
303                 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
304
305 enum port {
306         PORT_NONE = -1,
307         PORT_A = 0,
308         PORT_B,
309         PORT_C,
310         PORT_D,
311         PORT_E,
312         I915_MAX_PORTS
313 };
314 #define port_name(p) ((p) + 'A')
315
316 #define I915_NUM_PHYS_VLV 2
317
318 enum dpio_channel {
319         DPIO_CH0,
320         DPIO_CH1
321 };
322
323 enum dpio_phy {
324         DPIO_PHY0,
325         DPIO_PHY1,
326         DPIO_PHY2,
327 };
328
329 enum intel_display_power_domain {
330         POWER_DOMAIN_PIPE_A,
331         POWER_DOMAIN_PIPE_B,
332         POWER_DOMAIN_PIPE_C,
333         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
334         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
335         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
336         POWER_DOMAIN_TRANSCODER_A,
337         POWER_DOMAIN_TRANSCODER_B,
338         POWER_DOMAIN_TRANSCODER_C,
339         POWER_DOMAIN_TRANSCODER_EDP,
340         POWER_DOMAIN_TRANSCODER_DSI_A,
341         POWER_DOMAIN_TRANSCODER_DSI_C,
342         POWER_DOMAIN_PORT_DDI_A_LANES,
343         POWER_DOMAIN_PORT_DDI_B_LANES,
344         POWER_DOMAIN_PORT_DDI_C_LANES,
345         POWER_DOMAIN_PORT_DDI_D_LANES,
346         POWER_DOMAIN_PORT_DDI_E_LANES,
347         POWER_DOMAIN_PORT_DDI_A_IO,
348         POWER_DOMAIN_PORT_DDI_B_IO,
349         POWER_DOMAIN_PORT_DDI_C_IO,
350         POWER_DOMAIN_PORT_DDI_D_IO,
351         POWER_DOMAIN_PORT_DDI_E_IO,
352         POWER_DOMAIN_PORT_DSI,
353         POWER_DOMAIN_PORT_CRT,
354         POWER_DOMAIN_PORT_OTHER,
355         POWER_DOMAIN_VGA,
356         POWER_DOMAIN_AUDIO,
357         POWER_DOMAIN_PLLS,
358         POWER_DOMAIN_AUX_A,
359         POWER_DOMAIN_AUX_B,
360         POWER_DOMAIN_AUX_C,
361         POWER_DOMAIN_AUX_D,
362         POWER_DOMAIN_GMBUS,
363         POWER_DOMAIN_MODESET,
364         POWER_DOMAIN_INIT,
365
366         POWER_DOMAIN_NUM,
367 };
368
369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
371                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
372 #define POWER_DOMAIN_TRANSCODER(tran) \
373         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
374          (tran) + POWER_DOMAIN_TRANSCODER_A)
375
376 enum hpd_pin {
377         HPD_NONE = 0,
378         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
379         HPD_CRT,
380         HPD_SDVO_B,
381         HPD_SDVO_C,
382         HPD_PORT_A,
383         HPD_PORT_B,
384         HPD_PORT_C,
385         HPD_PORT_D,
386         HPD_PORT_E,
387         HPD_NUM_PINS
388 };
389
390 #define for_each_hpd_pin(__pin) \
391         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
392
393 #define HPD_STORM_DEFAULT_THRESHOLD 5
394
395 struct i915_hotplug {
396         struct work_struct hotplug_work;
397
398         struct {
399                 unsigned long last_jiffies;
400                 int count;
401                 enum {
402                         HPD_ENABLED = 0,
403                         HPD_DISABLED = 1,
404                         HPD_MARK_DISABLED = 2
405                 } state;
406         } stats[HPD_NUM_PINS];
407         u32 event_bits;
408         struct delayed_work reenable_work;
409
410         struct intel_digital_port *irq_port[I915_MAX_PORTS];
411         u32 long_port_mask;
412         u32 short_port_mask;
413         struct work_struct dig_port_work;
414
415         struct work_struct poll_init_work;
416         bool poll_enabled;
417
418         unsigned int hpd_storm_threshold;
419
420         /*
421          * if we get a HPD irq from DP and a HPD irq from non-DP
422          * the non-DP HPD could block the workqueue on a mode config
423          * mutex getting, that userspace may have taken. However
424          * userspace is waiting on the DP workqueue to run which is
425          * blocked behind the non-DP one.
426          */
427         struct workqueue_struct *dp_wq;
428 };
429
430 #define I915_GEM_GPU_DOMAINS \
431         (I915_GEM_DOMAIN_RENDER | \
432          I915_GEM_DOMAIN_SAMPLER | \
433          I915_GEM_DOMAIN_COMMAND | \
434          I915_GEM_DOMAIN_INSTRUCTION | \
435          I915_GEM_DOMAIN_VERTEX)
436
437 #define for_each_pipe(__dev_priv, __p) \
438         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
440         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
441                 for_each_if ((__mask) & (1 << (__p)))
442 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
443         for ((__p) = 0;                                                 \
444              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
445              (__p)++)
446 #define for_each_sprite(__dev_priv, __p, __s)                           \
447         for ((__s) = 0;                                                 \
448              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
449              (__s)++)
450
451 #define for_each_port_masked(__port, __ports_mask) \
452         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
453                 for_each_if ((__ports_mask) & (1 << (__port)))
454
455 #define for_each_crtc(dev, crtc) \
456         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
457
458 #define for_each_intel_plane(dev, intel_plane) \
459         list_for_each_entry(intel_plane,                        \
460                             &(dev)->mode_config.plane_list,     \
461                             base.head)
462
463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
464         list_for_each_entry(intel_plane,                                \
465                             &(dev)->mode_config.plane_list,             \
466                             base.head)                                  \
467                 for_each_if ((plane_mask) &                             \
468                              (1 << drm_plane_index(&intel_plane->base)))
469
470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
471         list_for_each_entry(intel_plane,                                \
472                             &(dev)->mode_config.plane_list,             \
473                             base.head)                                  \
474                 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
475
476 #define for_each_intel_crtc(dev, intel_crtc)                            \
477         list_for_each_entry(intel_crtc,                                 \
478                             &(dev)->mode_config.crtc_list,              \
479                             base.head)
480
481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
482         list_for_each_entry(intel_crtc,                                 \
483                             &(dev)->mode_config.crtc_list,              \
484                             base.head)                                  \
485                 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
486
487 #define for_each_intel_encoder(dev, intel_encoder)              \
488         list_for_each_entry(intel_encoder,                      \
489                             &(dev)->mode_config.encoder_list,   \
490                             base.head)
491
492 #define for_each_intel_connector(dev, intel_connector)          \
493         list_for_each_entry(intel_connector,                    \
494                             &(dev)->mode_config.connector_list, \
495                             base.head)
496
497 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
498         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
499                 for_each_if ((intel_encoder)->base.crtc == (__crtc))
500
501 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
502         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
503                 for_each_if ((intel_connector)->base.encoder == (__encoder))
504
505 #define for_each_power_domain(domain, mask)                             \
506         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
507                 for_each_if (BIT_ULL(domain) & (mask))
508
509 #define for_each_power_well(__dev_priv, __power_well)                           \
510         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
511              (__power_well) - (__dev_priv)->power_domains.power_wells < \
512                 (__dev_priv)->power_domains.power_well_count;           \
513              (__power_well)++)
514
515 #define for_each_power_well_rev(__dev_priv, __power_well)                       \
516         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
517                               (__dev_priv)->power_domains.power_well_count - 1; \
518              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
519              (__power_well)--)
520
521 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
522         for_each_power_well(__dev_priv, __power_well)                           \
523                 for_each_if ((__power_well)->domains & (__domain_mask))
524
525 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
526         for_each_power_well_rev(__dev_priv, __power_well)                       \
527                 for_each_if ((__power_well)->domains & (__domain_mask))
528
529 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
530         for ((__i) = 0; \
531              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
532                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
533                       (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
534              (__i)++) \
535                 for_each_if (plane_state)
536
537 struct drm_i915_private;
538 struct i915_mm_struct;
539 struct i915_mmu_object;
540
541 struct drm_i915_file_private {
542         struct drm_i915_private *dev_priv;
543         struct drm_file *file;
544
545         struct {
546                 spinlock_t lock;
547                 struct list_head request_list;
548 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
549  * chosen to prevent the CPU getting more than a frame ahead of the GPU
550  * (when using lax throttling for the frontbuffer). We also use it to
551  * offer free GPU waitboosts for severely congested workloads.
552  */
553 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
554         } mm;
555         struct idr context_idr;
556
557         struct intel_rps_client {
558                 struct list_head link;
559                 unsigned boosts;
560         } rps;
561
562         unsigned int bsd_engine;
563
564 /* Client can have a maximum of 3 contexts banned before
565  * it is denied of creating new contexts. As one context
566  * ban needs 4 consecutive hangs, and more if there is
567  * progress in between, this is a last resort stop gap measure
568  * to limit the badly behaving clients access to gpu.
569  */
570 #define I915_MAX_CLIENT_CONTEXT_BANS 3
571         int context_bans;
572 };
573
574 /* Used by dp and fdi links */
575 struct intel_link_m_n {
576         uint32_t        tu;
577         uint32_t        gmch_m;
578         uint32_t        gmch_n;
579         uint32_t        link_m;
580         uint32_t        link_n;
581 };
582
583 void intel_link_compute_m_n(int bpp, int nlanes,
584                             int pixel_clock, int link_clock,
585                             struct intel_link_m_n *m_n);
586
587 /* Interface history:
588  *
589  * 1.1: Original.
590  * 1.2: Add Power Management
591  * 1.3: Add vblank support
592  * 1.4: Fix cmdbuffer path, add heap destroy
593  * 1.5: Add vblank pipe configuration
594  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
595  *      - Support vertical blank on secondary display pipe
596  */
597 #define DRIVER_MAJOR            1
598 #define DRIVER_MINOR            6
599 #define DRIVER_PATCHLEVEL       0
600
601 struct opregion_header;
602 struct opregion_acpi;
603 struct opregion_swsci;
604 struct opregion_asle;
605
606 struct intel_opregion {
607         struct opregion_header *header;
608         struct opregion_acpi *acpi;
609         struct opregion_swsci *swsci;
610         u32 swsci_gbda_sub_functions;
611         u32 swsci_sbcb_sub_functions;
612         struct opregion_asle *asle;
613         void *rvda;
614         const void *vbt;
615         u32 vbt_size;
616         u32 *lid_state;
617         struct work_struct asle_work;
618 };
619 #define OPREGION_SIZE            (8*1024)
620
621 struct intel_overlay;
622 struct intel_overlay_error_state;
623
624 struct sdvo_device_mapping {
625         u8 initialized;
626         u8 dvo_port;
627         u8 slave_addr;
628         u8 dvo_wiring;
629         u8 i2c_pin;
630         u8 ddc_pin;
631 };
632
633 struct intel_connector;
634 struct intel_encoder;
635 struct intel_atomic_state;
636 struct intel_crtc_state;
637 struct intel_initial_plane_config;
638 struct intel_crtc;
639 struct intel_limit;
640 struct dpll;
641 struct intel_cdclk_state;
642
643 struct drm_i915_display_funcs {
644         void (*get_cdclk)(struct drm_i915_private *dev_priv,
645                           struct intel_cdclk_state *cdclk_state);
646         void (*set_cdclk)(struct drm_i915_private *dev_priv,
647                           const struct intel_cdclk_state *cdclk_state);
648         int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
649         int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
650         int (*compute_intermediate_wm)(struct drm_device *dev,
651                                        struct intel_crtc *intel_crtc,
652                                        struct intel_crtc_state *newstate);
653         void (*initial_watermarks)(struct intel_atomic_state *state,
654                                    struct intel_crtc_state *cstate);
655         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
656                                          struct intel_crtc_state *cstate);
657         void (*optimize_watermarks)(struct intel_atomic_state *state,
658                                     struct intel_crtc_state *cstate);
659         int (*compute_global_watermarks)(struct drm_atomic_state *state);
660         void (*update_wm)(struct intel_crtc *crtc);
661         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
662         /* Returns the active state of the crtc, and if the crtc is active,
663          * fills out the pipe-config with the hw state. */
664         bool (*get_pipe_config)(struct intel_crtc *,
665                                 struct intel_crtc_state *);
666         void (*get_initial_plane_config)(struct intel_crtc *,
667                                          struct intel_initial_plane_config *);
668         int (*crtc_compute_clock)(struct intel_crtc *crtc,
669                                   struct intel_crtc_state *crtc_state);
670         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
671                             struct drm_atomic_state *old_state);
672         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
673                              struct drm_atomic_state *old_state);
674         void (*update_crtcs)(struct drm_atomic_state *state,
675                              unsigned int *crtc_vblank_mask);
676         void (*audio_codec_enable)(struct drm_connector *connector,
677                                    struct intel_encoder *encoder,
678                                    const struct drm_display_mode *adjusted_mode);
679         void (*audio_codec_disable)(struct intel_encoder *encoder);
680         void (*fdi_link_train)(struct intel_crtc *crtc,
681                                const struct intel_crtc_state *crtc_state);
682         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
683         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
684                           struct drm_framebuffer *fb,
685                           struct drm_i915_gem_object *obj,
686                           struct drm_i915_gem_request *req,
687                           uint32_t flags);
688         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
689         /* clock updates for mode set */
690         /* cursor updates */
691         /* render clock increase/decrease */
692         /* display clock increase/decrease */
693         /* pll clock increase/decrease */
694
695         void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
696         void (*load_luts)(struct drm_crtc_state *crtc_state);
697 };
698
699 enum forcewake_domain_id {
700         FW_DOMAIN_ID_RENDER = 0,
701         FW_DOMAIN_ID_BLITTER,
702         FW_DOMAIN_ID_MEDIA,
703
704         FW_DOMAIN_ID_COUNT
705 };
706
707 enum forcewake_domains {
708         FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
709         FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
710         FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
711         FORCEWAKE_ALL = (FORCEWAKE_RENDER |
712                          FORCEWAKE_BLITTER |
713                          FORCEWAKE_MEDIA)
714 };
715
716 #define FW_REG_READ  (1)
717 #define FW_REG_WRITE (2)
718
719 enum decoupled_power_domain {
720         GEN9_DECOUPLED_PD_BLITTER = 0,
721         GEN9_DECOUPLED_PD_RENDER,
722         GEN9_DECOUPLED_PD_MEDIA,
723         GEN9_DECOUPLED_PD_ALL
724 };
725
726 enum decoupled_ops {
727         GEN9_DECOUPLED_OP_WRITE = 0,
728         GEN9_DECOUPLED_OP_READ
729 };
730
731 enum forcewake_domains
732 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
733                                i915_reg_t reg, unsigned int op);
734
735 struct intel_uncore_funcs {
736         void (*force_wake_get)(struct drm_i915_private *dev_priv,
737                                                         enum forcewake_domains domains);
738         void (*force_wake_put)(struct drm_i915_private *dev_priv,
739                                                         enum forcewake_domains domains);
740
741         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
742         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
743         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
744         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
745
746         void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
747                                 uint8_t val, bool trace);
748         void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
749                                 uint16_t val, bool trace);
750         void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
751                                 uint32_t val, bool trace);
752 };
753
754 struct intel_forcewake_range {
755         u32 start;
756         u32 end;
757
758         enum forcewake_domains domains;
759 };
760
761 struct intel_uncore {
762         spinlock_t lock; /** lock is also taken in irq contexts. */
763
764         const struct intel_forcewake_range *fw_domains_table;
765         unsigned int fw_domains_table_entries;
766
767         struct intel_uncore_funcs funcs;
768
769         unsigned fifo_count;
770
771         enum forcewake_domains fw_domains;
772         enum forcewake_domains fw_domains_active;
773
774         struct intel_uncore_forcewake_domain {
775                 struct drm_i915_private *i915;
776                 enum forcewake_domain_id id;
777                 enum forcewake_domains mask;
778                 unsigned wake_count;
779                 struct hrtimer timer;
780                 i915_reg_t reg_set;
781                 u32 val_set;
782                 u32 val_clear;
783                 i915_reg_t reg_ack;
784                 i915_reg_t reg_post;
785                 u32 val_reset;
786         } fw_domain[FW_DOMAIN_ID_COUNT];
787
788         int unclaimed_mmio_check;
789 };
790
791 /* Iterate over initialised fw domains */
792 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
793         for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
794              (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
795              (domain__)++) \
796                 for_each_if ((mask__) & (domain__)->mask)
797
798 #define for_each_fw_domain(domain__, dev_priv__) \
799         for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
800
801 #define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
802 #define CSR_VERSION_MAJOR(version)      ((version) >> 16)
803 #define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
804
805 struct intel_csr {
806         struct work_struct work;
807         const char *fw_path;
808         uint32_t *dmc_payload;
809         uint32_t dmc_fw_size;
810         uint32_t version;
811         uint32_t mmio_count;
812         i915_reg_t mmioaddr[8];
813         uint32_t mmiodata[8];
814         uint32_t dc_state;
815         uint32_t allowed_dc_mask;
816 };
817
818 #define DEV_INFO_FOR_EACH_FLAG(func) \
819         func(is_mobile); \
820         func(is_lp); \
821         func(is_alpha_support); \
822         /* Keep has_* in alphabetical order */ \
823         func(has_64bit_reloc); \
824         func(has_aliasing_ppgtt); \
825         func(has_csr); \
826         func(has_ddi); \
827         func(has_decoupled_mmio); \
828         func(has_dp_mst); \
829         func(has_fbc); \
830         func(has_fpga_dbg); \
831         func(has_full_ppgtt); \
832         func(has_full_48bit_ppgtt); \
833         func(has_gmbus_irq); \
834         func(has_gmch_display); \
835         func(has_guc); \
836         func(has_hotplug); \
837         func(has_hw_contexts); \
838         func(has_l3_dpf); \
839         func(has_llc); \
840         func(has_logical_ring_contexts); \
841         func(has_overlay); \
842         func(has_pipe_cxsr); \
843         func(has_pooled_eu); \
844         func(has_psr); \
845         func(has_rc6); \
846         func(has_rc6p); \
847         func(has_resource_streamer); \
848         func(has_runtime_pm); \
849         func(has_snoop); \
850         func(cursor_needs_physical); \
851         func(hws_needs_physical); \
852         func(overlay_needs_physical); \
853         func(supports_tv);
854
855 struct sseu_dev_info {
856         u8 slice_mask;
857         u8 subslice_mask;
858         u8 eu_total;
859         u8 eu_per_subslice;
860         u8 min_eu_in_pool;
861         /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
862         u8 subslice_7eu[3];
863         u8 has_slice_pg:1;
864         u8 has_subslice_pg:1;
865         u8 has_eu_pg:1;
866 };
867
868 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
869 {
870         return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
871 }
872
873 /* Keep in gen based order, and chronological order within a gen */
874 enum intel_platform {
875         INTEL_PLATFORM_UNINITIALIZED = 0,
876         INTEL_I830,
877         INTEL_I845G,
878         INTEL_I85X,
879         INTEL_I865G,
880         INTEL_I915G,
881         INTEL_I915GM,
882         INTEL_I945G,
883         INTEL_I945GM,
884         INTEL_G33,
885         INTEL_PINEVIEW,
886         INTEL_I965G,
887         INTEL_I965GM,
888         INTEL_G45,
889         INTEL_GM45,
890         INTEL_IRONLAKE,
891         INTEL_SANDYBRIDGE,
892         INTEL_IVYBRIDGE,
893         INTEL_VALLEYVIEW,
894         INTEL_HASWELL,
895         INTEL_BROADWELL,
896         INTEL_CHERRYVIEW,
897         INTEL_SKYLAKE,
898         INTEL_BROXTON,
899         INTEL_KABYLAKE,
900         INTEL_GEMINILAKE,
901         INTEL_MAX_PLATFORMS
902 };
903
904 struct intel_device_info {
905         u32 display_mmio_offset;
906         u16 device_id;
907         u8 num_pipes;
908         u8 num_sprites[I915_MAX_PIPES];
909         u8 num_scalers[I915_MAX_PIPES];
910         u8 gen;
911         u16 gen_mask;
912         enum intel_platform platform;
913         u8 ring_mask; /* Rings supported by the HW */
914         u8 num_rings;
915 #define DEFINE_FLAG(name) u8 name:1
916         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
917 #undef DEFINE_FLAG
918         u16 ddb_size; /* in blocks */
919         /* Register offsets for the various display pipes and transcoders */
920         int pipe_offsets[I915_MAX_TRANSCODERS];
921         int trans_offsets[I915_MAX_TRANSCODERS];
922         int palette_offsets[I915_MAX_PIPES];
923         int cursor_offsets[I915_MAX_PIPES];
924
925         /* Slice/subslice/EU info */
926         struct sseu_dev_info sseu;
927
928         struct color_luts {
929                 u16 degamma_lut_size;
930                 u16 gamma_lut_size;
931         } color;
932 };
933
934 struct intel_display_error_state;
935
936 struct i915_gpu_state {
937         struct kref ref;
938         struct timeval time;
939         struct timeval boottime;
940         struct timeval uptime;
941
942         struct drm_i915_private *i915;
943
944         char error_msg[128];
945         bool simulated;
946         bool awake;
947         bool wakelock;
948         bool suspended;
949         int iommu;
950         u32 reset_count;
951         u32 suspend_count;
952         struct intel_device_info device_info;
953         struct i915_params params;
954
955         /* Generic register state */
956         u32 eir;
957         u32 pgtbl_er;
958         u32 ier;
959         u32 gtier[4], ngtier;
960         u32 ccid;
961         u32 derrmr;
962         u32 forcewake;
963         u32 error; /* gen6+ */
964         u32 err_int; /* gen7 */
965         u32 fault_data0; /* gen8, gen9 */
966         u32 fault_data1; /* gen8, gen9 */
967         u32 done_reg;
968         u32 gac_eco;
969         u32 gam_ecochk;
970         u32 gab_ctl;
971         u32 gfx_mode;
972
973         u32 nfence;
974         u64 fence[I915_MAX_NUM_FENCES];
975         struct intel_overlay_error_state *overlay;
976         struct intel_display_error_state *display;
977         struct drm_i915_error_object *semaphore;
978         struct drm_i915_error_object *guc_log;
979
980         struct drm_i915_error_engine {
981                 int engine_id;
982                 /* Software tracked state */
983                 bool waiting;
984                 int num_waiters;
985                 unsigned long hangcheck_timestamp;
986                 bool hangcheck_stalled;
987                 enum intel_engine_hangcheck_action hangcheck_action;
988                 struct i915_address_space *vm;
989                 int num_requests;
990
991                 /* position of active request inside the ring */
992                 u32 rq_head, rq_post, rq_tail;
993
994                 /* our own tracking of ring head and tail */
995                 u32 cpu_ring_head;
996                 u32 cpu_ring_tail;
997
998                 u32 last_seqno;
999
1000                 /* Register state */
1001                 u32 start;
1002                 u32 tail;
1003                 u32 head;
1004                 u32 ctl;
1005                 u32 mode;
1006                 u32 hws;
1007                 u32 ipeir;
1008                 u32 ipehr;
1009                 u32 bbstate;
1010                 u32 instpm;
1011                 u32 instps;
1012                 u32 seqno;
1013                 u64 bbaddr;
1014                 u64 acthd;
1015                 u32 fault_reg;
1016                 u64 faddr;
1017                 u32 rc_psmi; /* sleep state */
1018                 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1019                 struct intel_instdone instdone;
1020
1021                 struct drm_i915_error_context {
1022                         char comm[TASK_COMM_LEN];
1023                         pid_t pid;
1024                         u32 handle;
1025                         u32 hw_id;
1026                         int ban_score;
1027                         int active;
1028                         int guilty;
1029                 } context;
1030
1031                 struct drm_i915_error_object {
1032                         u64 gtt_offset;
1033                         u64 gtt_size;
1034                         int page_count;
1035                         int unused;
1036                         u32 *pages[0];
1037                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1038
1039                 struct drm_i915_error_object *wa_ctx;
1040
1041                 struct drm_i915_error_request {
1042                         long jiffies;
1043                         pid_t pid;
1044                         u32 context;
1045                         int ban_score;
1046                         u32 seqno;
1047                         u32 head;
1048                         u32 tail;
1049                 } *requests, execlist[2];
1050
1051                 struct drm_i915_error_waiter {
1052                         char comm[TASK_COMM_LEN];
1053                         pid_t pid;
1054                         u32 seqno;
1055                 } *waiters;
1056
1057                 struct {
1058                         u32 gfx_mode;
1059                         union {
1060                                 u64 pdp[4];
1061                                 u32 pp_dir_base;
1062                         };
1063                 } vm_info;
1064         } engine[I915_NUM_ENGINES];
1065
1066         struct drm_i915_error_buffer {
1067                 u32 size;
1068                 u32 name;
1069                 u32 rseqno[I915_NUM_ENGINES], wseqno;
1070                 u64 gtt_offset;
1071                 u32 read_domains;
1072                 u32 write_domain;
1073                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1074                 u32 tiling:2;
1075                 u32 dirty:1;
1076                 u32 purgeable:1;
1077                 u32 userptr:1;
1078                 s32 engine:4;
1079                 u32 cache_level:3;
1080         } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1081         u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1082         struct i915_address_space *active_vm[I915_NUM_ENGINES];
1083 };
1084
1085 enum i915_cache_level {
1086         I915_CACHE_NONE = 0,
1087         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1088         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1089                               caches, eg sampler/render caches, and the
1090                               large Last-Level-Cache. LLC is coherent with
1091                               the CPU, but L3 is only visible to the GPU. */
1092         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1093 };
1094
1095 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1096
1097 enum fb_op_origin {
1098         ORIGIN_GTT,
1099         ORIGIN_CPU,
1100         ORIGIN_CS,
1101         ORIGIN_FLIP,
1102         ORIGIN_DIRTYFB,
1103 };
1104
1105 struct intel_fbc {
1106         /* This is always the inner lock when overlapping with struct_mutex and
1107          * it's the outer lock when overlapping with stolen_lock. */
1108         struct mutex lock;
1109         unsigned threshold;
1110         unsigned int possible_framebuffer_bits;
1111         unsigned int busy_bits;
1112         unsigned int visible_pipes_mask;
1113         struct intel_crtc *crtc;
1114
1115         struct drm_mm_node compressed_fb;
1116         struct drm_mm_node *compressed_llb;
1117
1118         bool false_color;
1119
1120         bool enabled;
1121         bool active;
1122
1123         bool underrun_detected;
1124         struct work_struct underrun_work;
1125
1126         struct intel_fbc_state_cache {
1127                 struct i915_vma *vma;
1128
1129                 struct {
1130                         unsigned int mode_flags;
1131                         uint32_t hsw_bdw_pixel_rate;
1132                 } crtc;
1133
1134                 struct {
1135                         unsigned int rotation;
1136                         int src_w;
1137                         int src_h;
1138                         bool visible;
1139                 } plane;
1140
1141                 struct {
1142                         const struct drm_format_info *format;
1143                         unsigned int stride;
1144                 } fb;
1145         } state_cache;
1146
1147         struct intel_fbc_reg_params {
1148                 struct i915_vma *vma;
1149
1150                 struct {
1151                         enum pipe pipe;
1152                         enum plane plane;
1153                         unsigned int fence_y_offset;
1154                 } crtc;
1155
1156                 struct {
1157                         const struct drm_format_info *format;
1158                         unsigned int stride;
1159                 } fb;
1160
1161                 int cfb_size;
1162         } params;
1163
1164         struct intel_fbc_work {
1165                 bool scheduled;
1166                 u32 scheduled_vblank;
1167                 struct work_struct work;
1168         } work;
1169
1170         const char *no_fbc_reason;
1171 };
1172
1173 /*
1174  * HIGH_RR is the highest eDP panel refresh rate read from EDID
1175  * LOW_RR is the lowest eDP panel refresh rate found from EDID
1176  * parsing for same resolution.
1177  */
1178 enum drrs_refresh_rate_type {
1179         DRRS_HIGH_RR,
1180         DRRS_LOW_RR,
1181         DRRS_MAX_RR, /* RR count */
1182 };
1183
1184 enum drrs_support_type {
1185         DRRS_NOT_SUPPORTED = 0,
1186         STATIC_DRRS_SUPPORT = 1,
1187         SEAMLESS_DRRS_SUPPORT = 2
1188 };
1189
1190 struct intel_dp;
1191 struct i915_drrs {
1192         struct mutex mutex;
1193         struct delayed_work work;
1194         struct intel_dp *dp;
1195         unsigned busy_frontbuffer_bits;
1196         enum drrs_refresh_rate_type refresh_rate_type;
1197         enum drrs_support_type type;
1198 };
1199
1200 struct i915_psr {
1201         struct mutex lock;
1202         bool sink_support;
1203         bool source_ok;
1204         struct intel_dp *enabled;
1205         bool active;
1206         struct delayed_work work;
1207         unsigned busy_frontbuffer_bits;
1208         bool psr2_support;
1209         bool aux_frame_sync;
1210         bool link_standby;
1211         bool y_cord_support;
1212         bool colorimetry_support;
1213         bool alpm;
1214 };
1215
1216 enum intel_pch {
1217         PCH_NONE = 0,   /* No PCH present */
1218         PCH_IBX,        /* Ibexpeak PCH */
1219         PCH_CPT,        /* Cougarpoint PCH */
1220         PCH_LPT,        /* Lynxpoint PCH */
1221         PCH_SPT,        /* Sunrisepoint PCH */
1222         PCH_KBP,        /* Kabypoint PCH */
1223         PCH_NOP,
1224 };
1225
1226 enum intel_sbi_destination {
1227         SBI_ICLK,
1228         SBI_MPHY,
1229 };
1230
1231 #define QUIRK_PIPEA_FORCE (1<<0)
1232 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1233 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1234 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1235 #define QUIRK_PIPEB_FORCE (1<<4)
1236 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1237
1238 struct intel_fbdev;
1239 struct intel_fbc_work;
1240
1241 struct intel_gmbus {
1242         struct i2c_adapter adapter;
1243 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1244         u32 force_bit;
1245         u32 reg0;
1246         i915_reg_t gpio_reg;
1247         struct i2c_algo_bit_data bit_algo;
1248         struct drm_i915_private *dev_priv;
1249 };
1250
1251 struct i915_suspend_saved_registers {
1252         u32 saveDSPARB;
1253         u32 saveFBC_CONTROL;
1254         u32 saveCACHE_MODE_0;
1255         u32 saveMI_ARB_STATE;
1256         u32 saveSWF0[16];
1257         u32 saveSWF1[16];
1258         u32 saveSWF3[3];
1259         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1260         u32 savePCH_PORT_HOTPLUG;
1261         u16 saveGCDGMBUS;
1262 };
1263
1264 struct vlv_s0ix_state {
1265         /* GAM */
1266         u32 wr_watermark;
1267         u32 gfx_prio_ctrl;
1268         u32 arb_mode;
1269         u32 gfx_pend_tlb0;
1270         u32 gfx_pend_tlb1;
1271         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1272         u32 media_max_req_count;
1273         u32 gfx_max_req_count;
1274         u32 render_hwsp;
1275         u32 ecochk;
1276         u32 bsd_hwsp;
1277         u32 blt_hwsp;
1278         u32 tlb_rd_addr;
1279
1280         /* MBC */
1281         u32 g3dctl;
1282         u32 gsckgctl;
1283         u32 mbctl;
1284
1285         /* GCP */
1286         u32 ucgctl1;
1287         u32 ucgctl3;
1288         u32 rcgctl1;
1289         u32 rcgctl2;
1290         u32 rstctl;
1291         u32 misccpctl;
1292
1293         /* GPM */
1294         u32 gfxpause;
1295         u32 rpdeuhwtc;
1296         u32 rpdeuc;
1297         u32 ecobus;
1298         u32 pwrdwnupctl;
1299         u32 rp_down_timeout;
1300         u32 rp_deucsw;
1301         u32 rcubmabdtmr;
1302         u32 rcedata;
1303         u32 spare2gh;
1304
1305         /* Display 1 CZ domain */
1306         u32 gt_imr;
1307         u32 gt_ier;
1308         u32 pm_imr;
1309         u32 pm_ier;
1310         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1311
1312         /* GT SA CZ domain */
1313         u32 tilectl;
1314         u32 gt_fifoctl;
1315         u32 gtlc_wake_ctrl;
1316         u32 gtlc_survive;
1317         u32 pmwgicz;
1318
1319         /* Display 2 CZ domain */
1320         u32 gu_ctl0;
1321         u32 gu_ctl1;
1322         u32 pcbr;
1323         u32 clock_gate_dis2;
1324 };
1325
1326 struct intel_rps_ei {
1327         u32 cz_clock;
1328         u32 render_c0;
1329         u32 media_c0;
1330 };
1331
1332 struct intel_gen6_power_mgmt {
1333         /*
1334          * work, interrupts_enabled and pm_iir are protected by
1335          * dev_priv->irq_lock
1336          */
1337         struct work_struct work;
1338         bool interrupts_enabled;
1339         u32 pm_iir;
1340
1341         /* PM interrupt bits that should never be masked */
1342         u32 pm_intr_keep;
1343
1344         /* Frequencies are stored in potentially platform dependent multiples.
1345          * In other words, *_freq needs to be multiplied by X to be interesting.
1346          * Soft limits are those which are used for the dynamic reclocking done
1347          * by the driver (raise frequencies under heavy loads, and lower for
1348          * lighter loads). Hard limits are those imposed by the hardware.
1349          *
1350          * A distinction is made for overclocking, which is never enabled by
1351          * default, and is considered to be above the hard limit if it's
1352          * possible at all.
1353          */
1354         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1355         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1356         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1357         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1358         u8 min_freq;            /* AKA RPn. Minimum frequency */
1359         u8 boost_freq;          /* Frequency to request when wait boosting */
1360         u8 idle_freq;           /* Frequency to request when we are idle */
1361         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1362         u8 rp1_freq;            /* "less than" RP0 power/freqency */
1363         u8 rp0_freq;            /* Non-overclocked max frequency. */
1364         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
1365
1366         u8 up_threshold; /* Current %busy required to uplock */
1367         u8 down_threshold; /* Current %busy required to downclock */
1368
1369         int last_adj;
1370         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1371
1372         spinlock_t client_lock;
1373         struct list_head clients;
1374         bool client_boost;
1375
1376         bool enabled;
1377         struct delayed_work autoenable_work;
1378         unsigned boosts;
1379
1380         /* manual wa residency calculations */
1381         struct intel_rps_ei up_ei, down_ei;
1382
1383         /*
1384          * Protects RPS/RC6 register access and PCU communication.
1385          * Must be taken after struct_mutex if nested. Note that
1386          * this lock may be held for long periods of time when
1387          * talking to hw - so only take it when talking to hw!
1388          */
1389         struct mutex hw_lock;
1390 };
1391
1392 /* defined intel_pm.c */
1393 extern spinlock_t mchdev_lock;
1394
1395 struct intel_ilk_power_mgmt {
1396         u8 cur_delay;
1397         u8 min_delay;
1398         u8 max_delay;
1399         u8 fmax;
1400         u8 fstart;
1401
1402         u64 last_count1;
1403         unsigned long last_time1;
1404         unsigned long chipset_power;
1405         u64 last_count2;
1406         u64 last_time2;
1407         unsigned long gfx_power;
1408         u8 corr;
1409
1410         int c_m;
1411         int r_t;
1412 };
1413
1414 struct drm_i915_private;
1415 struct i915_power_well;
1416
1417 struct i915_power_well_ops {
1418         /*
1419          * Synchronize the well's hw state to match the current sw state, for
1420          * example enable/disable it based on the current refcount. Called
1421          * during driver init and resume time, possibly after first calling
1422          * the enable/disable handlers.
1423          */
1424         void (*sync_hw)(struct drm_i915_private *dev_priv,
1425                         struct i915_power_well *power_well);
1426         /*
1427          * Enable the well and resources that depend on it (for example
1428          * interrupts located on the well). Called after the 0->1 refcount
1429          * transition.
1430          */
1431         void (*enable)(struct drm_i915_private *dev_priv,
1432                        struct i915_power_well *power_well);
1433         /*
1434          * Disable the well and resources that depend on it. Called after
1435          * the 1->0 refcount transition.
1436          */
1437         void (*disable)(struct drm_i915_private *dev_priv,
1438                         struct i915_power_well *power_well);
1439         /* Returns the hw enabled state. */
1440         bool (*is_enabled)(struct drm_i915_private *dev_priv,
1441                            struct i915_power_well *power_well);
1442 };
1443
1444 /* Power well structure for haswell */
1445 struct i915_power_well {
1446         const char *name;
1447         bool always_on;
1448         /* power well enable/disable usage count */
1449         int count;
1450         /* cached hw enabled state */
1451         bool hw_enabled;
1452         u64 domains;
1453         /* unique identifier for this power well */
1454         unsigned long id;
1455         /*
1456          * Arbitraty data associated with this power well. Platform and power
1457          * well specific.
1458          */
1459         unsigned long data;
1460         const struct i915_power_well_ops *ops;
1461 };
1462
1463 struct i915_power_domains {
1464         /*
1465          * Power wells needed for initialization at driver init and suspend
1466          * time are on. They are kept on until after the first modeset.
1467          */
1468         bool init_power_on;
1469         bool initializing;
1470         int power_well_count;
1471
1472         struct mutex lock;
1473         int domain_use_count[POWER_DOMAIN_NUM];
1474         struct i915_power_well *power_wells;
1475 };
1476
1477 #define MAX_L3_SLICES 2
1478 struct intel_l3_parity {
1479         u32 *remap_info[MAX_L3_SLICES];
1480         struct work_struct error_work;
1481         int which_slice;
1482 };
1483
1484 struct i915_gem_mm {
1485         /** Memory allocator for GTT stolen memory */
1486         struct drm_mm stolen;
1487         /** Protects the usage of the GTT stolen memory allocator. This is
1488          * always the inner lock when overlapping with struct_mutex. */
1489         struct mutex stolen_lock;
1490
1491         /** List of all objects in gtt_space. Used to restore gtt
1492          * mappings on resume */
1493         struct list_head bound_list;
1494         /**
1495          * List of objects which are not bound to the GTT (thus
1496          * are idle and not used by the GPU). These objects may or may
1497          * not actually have any pages attached.
1498          */
1499         struct list_head unbound_list;
1500
1501         /** List of all objects in gtt_space, currently mmaped by userspace.
1502          * All objects within this list must also be on bound_list.
1503          */
1504         struct list_head userfault_list;
1505
1506         /**
1507          * List of objects which are pending destruction.
1508          */
1509         struct llist_head free_list;
1510         struct work_struct free_work;
1511
1512         /** Usable portion of the GTT for GEM */
1513         dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1514
1515         /** PPGTT used for aliasing the PPGTT with the GTT */
1516         struct i915_hw_ppgtt *aliasing_ppgtt;
1517
1518         struct notifier_block oom_notifier;
1519         struct notifier_block vmap_notifier;
1520         struct shrinker shrinker;
1521
1522         /** LRU list of objects with fence regs on them. */
1523         struct list_head fence_list;
1524
1525         /**
1526          * Are we in a non-interruptible section of code like
1527          * modesetting?
1528          */
1529         bool interruptible;
1530
1531         /* the indicator for dispatch video commands on two BSD rings */
1532         atomic_t bsd_engine_dispatch_index;
1533
1534         /** Bit 6 swizzling required for X tiling */
1535         uint32_t bit_6_swizzle_x;
1536         /** Bit 6 swizzling required for Y tiling */
1537         uint32_t bit_6_swizzle_y;
1538
1539         /* accounting, useful for userland debugging */
1540         spinlock_t object_stat_lock;
1541         u64 object_memory;
1542         u32 object_count;
1543 };
1544
1545 struct drm_i915_error_state_buf {
1546         struct drm_i915_private *i915;
1547         unsigned bytes;
1548         unsigned size;
1549         int err;
1550         u8 *buf;
1551         loff_t start;
1552         loff_t pos;
1553 };
1554
1555 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1556 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1557
1558 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
1559 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
1560
1561 struct i915_gpu_error {
1562         /* For hangcheck timer */
1563 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1564 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1565
1566         struct delayed_work hangcheck_work;
1567
1568         /* For reset and error_state handling. */
1569         spinlock_t lock;
1570         /* Protected by the above dev->gpu_error.lock. */
1571         struct i915_gpu_state *first_error;
1572
1573         unsigned long missed_irq_rings;
1574
1575         /**
1576          * State variable controlling the reset flow and count
1577          *
1578          * This is a counter which gets incremented when reset is triggered,
1579          *
1580          * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1581          * meaning that any waiters holding onto the struct_mutex should
1582          * relinquish the lock immediately in order for the reset to start.
1583          *
1584          * If reset is not completed succesfully, the I915_WEDGE bit is
1585          * set meaning that hardware is terminally sour and there is no
1586          * recovery. All waiters on the reset_queue will be woken when
1587          * that happens.
1588          *
1589          * This counter is used by the wait_seqno code to notice that reset
1590          * event happened and it needs to restart the entire ioctl (since most
1591          * likely the seqno it waited for won't ever signal anytime soon).
1592          *
1593          * This is important for lock-free wait paths, where no contended lock
1594          * naturally enforces the correct ordering between the bail-out of the
1595          * waiter and the gpu reset work code.
1596          */
1597         unsigned long reset_count;
1598
1599         unsigned long flags;
1600 #define I915_RESET_IN_PROGRESS  0
1601 #define I915_WEDGED             (BITS_PER_LONG - 1)
1602
1603         /**
1604          * Waitqueue to signal when a hang is detected. Used to for waiters
1605          * to release the struct_mutex for the reset to procede.
1606          */
1607         wait_queue_head_t wait_queue;
1608
1609         /**
1610          * Waitqueue to signal when the reset has completed. Used by clients
1611          * that wait for dev_priv->mm.wedged to settle.
1612          */
1613         wait_queue_head_t reset_queue;
1614
1615         /* For missed irq/seqno simulation. */
1616         unsigned long test_irq_rings;
1617 };
1618
1619 enum modeset_restore {
1620         MODESET_ON_LID_OPEN,
1621         MODESET_DONE,
1622         MODESET_SUSPENDED,
1623 };
1624
1625 #define DP_AUX_A 0x40
1626 #define DP_AUX_B 0x10
1627 #define DP_AUX_C 0x20
1628 #define DP_AUX_D 0x30
1629
1630 #define DDC_PIN_B  0x05
1631 #define DDC_PIN_C  0x04
1632 #define DDC_PIN_D  0x06
1633
1634 struct ddi_vbt_port_info {
1635         /*
1636          * This is an index in the HDMI/DVI DDI buffer translation table.
1637          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1638          * populate this field.
1639          */
1640 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1641         uint8_t hdmi_level_shift;
1642
1643         uint8_t supports_dvi:1;
1644         uint8_t supports_hdmi:1;
1645         uint8_t supports_dp:1;
1646         uint8_t supports_edp:1;
1647
1648         uint8_t alternate_aux_channel;
1649         uint8_t alternate_ddc_pin;
1650
1651         uint8_t dp_boost_level;
1652         uint8_t hdmi_boost_level;
1653 };
1654
1655 enum psr_lines_to_wait {
1656         PSR_0_LINES_TO_WAIT = 0,
1657         PSR_1_LINE_TO_WAIT,
1658         PSR_4_LINES_TO_WAIT,
1659         PSR_8_LINES_TO_WAIT
1660 };
1661
1662 struct intel_vbt_data {
1663         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1664         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1665
1666         /* Feature bits */
1667         unsigned int int_tv_support:1;
1668         unsigned int lvds_dither:1;
1669         unsigned int lvds_vbt:1;
1670         unsigned int int_crt_support:1;
1671         unsigned int lvds_use_ssc:1;
1672         unsigned int display_clock_mode:1;
1673         unsigned int fdi_rx_polarity_inverted:1;
1674         unsigned int panel_type:4;
1675         int lvds_ssc_freq;
1676         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1677
1678         enum drrs_support_type drrs_type;
1679
1680         struct {
1681                 int rate;
1682                 int lanes;
1683                 int preemphasis;
1684                 int vswing;
1685                 bool low_vswing;
1686                 bool initialized;
1687                 bool support;
1688                 int bpp;
1689                 struct edp_power_seq pps;
1690         } edp;
1691
1692         struct {
1693                 bool full_link;
1694                 bool require_aux_wakeup;
1695                 int idle_frames;
1696                 enum psr_lines_to_wait lines_to_wait;
1697                 int tp1_wakeup_time;
1698                 int tp2_tp3_wakeup_time;
1699         } psr;
1700
1701         struct {
1702                 u16 pwm_freq_hz;
1703                 bool present;
1704                 bool active_low_pwm;
1705                 u8 min_brightness;      /* min_brightness/255 of max */
1706                 u8 controller;          /* brightness controller number */
1707                 enum intel_backlight_type type;
1708         } backlight;
1709
1710         /* MIPI DSI */
1711         struct {
1712                 u16 panel_id;
1713                 struct mipi_config *config;
1714                 struct mipi_pps_data *pps;
1715                 u8 seq_version;
1716                 u32 size;
1717                 u8 *data;
1718                 const u8 *sequence[MIPI_SEQ_MAX];
1719         } dsi;
1720
1721         int crt_ddc_pin;
1722
1723         int child_dev_num;
1724         union child_device_config *child_dev;
1725
1726         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1727         struct sdvo_device_mapping sdvo_mappings[2];
1728 };
1729
1730 enum intel_ddb_partitioning {
1731         INTEL_DDB_PART_1_2,
1732         INTEL_DDB_PART_5_6, /* IVB+ */
1733 };
1734
1735 struct intel_wm_level {
1736         bool enable;
1737         uint32_t pri_val;
1738         uint32_t spr_val;
1739         uint32_t cur_val;
1740         uint32_t fbc_val;
1741 };
1742
1743 struct ilk_wm_values {
1744         uint32_t wm_pipe[3];
1745         uint32_t wm_lp[3];
1746         uint32_t wm_lp_spr[3];
1747         uint32_t wm_linetime[3];
1748         bool enable_fbc_wm;
1749         enum intel_ddb_partitioning partitioning;
1750 };
1751
1752 struct vlv_pipe_wm {
1753         uint16_t plane[I915_MAX_PLANES];
1754 };
1755
1756 struct vlv_sr_wm {
1757         uint16_t plane;
1758         uint16_t cursor;
1759 };
1760
1761 struct vlv_wm_ddl_values {
1762         uint8_t plane[I915_MAX_PLANES];
1763 };
1764
1765 struct vlv_wm_values {
1766         struct vlv_pipe_wm pipe[3];
1767         struct vlv_sr_wm sr;
1768         struct vlv_wm_ddl_values ddl[3];
1769         uint8_t level;
1770         bool cxsr;
1771 };
1772
1773 struct skl_ddb_entry {
1774         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1775 };
1776
1777 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1778 {
1779         return entry->end - entry->start;
1780 }
1781
1782 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1783                                        const struct skl_ddb_entry *e2)
1784 {
1785         if (e1->start == e2->start && e1->end == e2->end)
1786                 return true;
1787
1788         return false;
1789 }
1790
1791 struct skl_ddb_allocation {
1792         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1793         struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1794 };
1795
1796 struct skl_wm_values {
1797         unsigned dirty_pipes;
1798         struct skl_ddb_allocation ddb;
1799 };
1800
1801 struct skl_wm_level {
1802         bool plane_en;
1803         uint16_t plane_res_b;
1804         uint8_t plane_res_l;
1805 };
1806
1807 /*
1808  * This struct helps tracking the state needed for runtime PM, which puts the
1809  * device in PCI D3 state. Notice that when this happens, nothing on the
1810  * graphics device works, even register access, so we don't get interrupts nor
1811  * anything else.
1812  *
1813  * Every piece of our code that needs to actually touch the hardware needs to
1814  * either call intel_runtime_pm_get or call intel_display_power_get with the
1815  * appropriate power domain.
1816  *
1817  * Our driver uses the autosuspend delay feature, which means we'll only really
1818  * suspend if we stay with zero refcount for a certain amount of time. The
1819  * default value is currently very conservative (see intel_runtime_pm_enable), but
1820  * it can be changed with the standard runtime PM files from sysfs.
1821  *
1822  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1823  * goes back to false exactly before we reenable the IRQs. We use this variable
1824  * to check if someone is trying to enable/disable IRQs while they're supposed
1825  * to be disabled. This shouldn't happen and we'll print some error messages in
1826  * case it happens.
1827  *
1828  * For more, read the Documentation/power/runtime_pm.txt.
1829  */
1830 struct i915_runtime_pm {
1831         atomic_t wakeref_count;
1832         bool suspended;
1833         bool irqs_enabled;
1834 };
1835
1836 enum intel_pipe_crc_source {
1837         INTEL_PIPE_CRC_SOURCE_NONE,
1838         INTEL_PIPE_CRC_SOURCE_PLANE1,
1839         INTEL_PIPE_CRC_SOURCE_PLANE2,
1840         INTEL_PIPE_CRC_SOURCE_PF,
1841         INTEL_PIPE_CRC_SOURCE_PIPE,
1842         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1843         INTEL_PIPE_CRC_SOURCE_TV,
1844         INTEL_PIPE_CRC_SOURCE_DP_B,
1845         INTEL_PIPE_CRC_SOURCE_DP_C,
1846         INTEL_PIPE_CRC_SOURCE_DP_D,
1847         INTEL_PIPE_CRC_SOURCE_AUTO,
1848         INTEL_PIPE_CRC_SOURCE_MAX,
1849 };
1850
1851 struct intel_pipe_crc_entry {
1852         uint32_t frame;
1853         uint32_t crc[5];
1854 };
1855
1856 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1857 struct intel_pipe_crc {
1858         spinlock_t lock;
1859         bool opened;            /* exclusive access to the result file */
1860         struct intel_pipe_crc_entry *entries;
1861         enum intel_pipe_crc_source source;
1862         int head, tail;
1863         wait_queue_head_t wq;
1864         int skipped;
1865 };
1866
1867 struct i915_frontbuffer_tracking {
1868         spinlock_t lock;
1869
1870         /*
1871          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1872          * scheduled flips.
1873          */
1874         unsigned busy_bits;
1875         unsigned flip_bits;
1876 };
1877
1878 struct i915_wa_reg {
1879         i915_reg_t addr;
1880         u32 value;
1881         /* bitmask representing WA bits */
1882         u32 mask;
1883 };
1884
1885 /*
1886  * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1887  * allowing it for RCS as we don't foresee any requirement of having
1888  * a whitelist for other engines. When it is really required for
1889  * other engines then the limit need to be increased.
1890  */
1891 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1892
1893 struct i915_workarounds {
1894         struct i915_wa_reg reg[I915_MAX_WA_REGS];
1895         u32 count;
1896         u32 hw_whitelist_count[I915_NUM_ENGINES];
1897 };
1898
1899 struct i915_virtual_gpu {
1900         bool active;
1901 };
1902
1903 /* used in computing the new watermarks state */
1904 struct intel_wm_config {
1905         unsigned int num_pipes_active;
1906         bool sprites_enabled;
1907         bool sprites_scaled;
1908 };
1909
1910 struct i915_oa_format {
1911         u32 format;
1912         int size;
1913 };
1914
1915 struct i915_oa_reg {
1916         i915_reg_t addr;
1917         u32 value;
1918 };
1919
1920 struct i915_perf_stream;
1921
1922 /**
1923  * struct i915_perf_stream_ops - the OPs to support a specific stream type
1924  */
1925 struct i915_perf_stream_ops {
1926         /**
1927          * @enable: Enables the collection of HW samples, either in response to
1928          * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1929          * without `I915_PERF_FLAG_DISABLED`.
1930          */
1931         void (*enable)(struct i915_perf_stream *stream);
1932
1933         /**
1934          * @disable: Disables the collection of HW samples, either in response
1935          * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1936          * the stream.
1937          */
1938         void (*disable)(struct i915_perf_stream *stream);
1939
1940         /**
1941          * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1942          * once there is something ready to read() for the stream
1943          */
1944         void (*poll_wait)(struct i915_perf_stream *stream,
1945                           struct file *file,
1946                           poll_table *wait);
1947
1948         /**
1949          * @wait_unlocked: For handling a blocking read, wait until there is
1950          * something to ready to read() for the stream. E.g. wait on the same
1951          * wait queue that would be passed to poll_wait().
1952          */
1953         int (*wait_unlocked)(struct i915_perf_stream *stream);
1954
1955         /**
1956          * @read: Copy buffered metrics as records to userspace
1957          * **buf**: the userspace, destination buffer
1958          * **count**: the number of bytes to copy, requested by userspace
1959          * **offset**: zero at the start of the read, updated as the read
1960          * proceeds, it represents how many bytes have been copied so far and
1961          * the buffer offset for copying the next record.
1962          *
1963          * Copy as many buffered i915 perf samples and records for this stream
1964          * to userspace as will fit in the given buffer.
1965          *
1966          * Only write complete records; returning -%ENOSPC if there isn't room
1967          * for a complete record.
1968          *
1969          * Return any error condition that results in a short read such as
1970          * -%ENOSPC or -%EFAULT, even though these may be squashed before
1971          * returning to userspace.
1972          */
1973         int (*read)(struct i915_perf_stream *stream,
1974                     char __user *buf,
1975                     size_t count,
1976                     size_t *offset);
1977
1978         /**
1979          * @destroy: Cleanup any stream specific resources.
1980          *
1981          * The stream will always be disabled before this is called.
1982          */
1983         void (*destroy)(struct i915_perf_stream *stream);
1984 };
1985
1986 /**
1987  * struct i915_perf_stream - state for a single open stream FD
1988  */
1989 struct i915_perf_stream {
1990         /**
1991          * @dev_priv: i915 drm device
1992          */
1993         struct drm_i915_private *dev_priv;
1994
1995         /**
1996          * @link: Links the stream into ``&drm_i915_private->streams``
1997          */
1998         struct list_head link;
1999
2000         /**
2001          * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2002          * properties given when opening a stream, representing the contents
2003          * of a single sample as read() by userspace.
2004          */
2005         u32 sample_flags;
2006
2007         /**
2008          * @sample_size: Considering the configured contents of a sample
2009          * combined with the required header size, this is the total size
2010          * of a single sample record.
2011          */
2012         int sample_size;
2013
2014         /**
2015          * @ctx: %NULL if measuring system-wide across all contexts or a
2016          * specific context that is being monitored.
2017          */
2018         struct i915_gem_context *ctx;
2019
2020         /**
2021          * @enabled: Whether the stream is currently enabled, considering
2022          * whether the stream was opened in a disabled state and based
2023          * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2024          */
2025         bool enabled;
2026
2027         /**
2028          * @ops: The callbacks providing the implementation of this specific
2029          * type of configured stream.
2030          */
2031         const struct i915_perf_stream_ops *ops;
2032 };
2033
2034 /**
2035  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2036  */
2037 struct i915_oa_ops {
2038         /**
2039          * @init_oa_buffer: Resets the head and tail pointers of the
2040          * circular buffer for periodic OA reports.
2041          *
2042          * Called when first opening a stream for OA metrics, but also may be
2043          * called in response to an OA buffer overflow or other error
2044          * condition.
2045          *
2046          * Note it may be necessary to clear the full OA buffer here as part of
2047          * maintaining the invariable that new reports must be written to
2048          * zeroed memory for us to be able to reliable detect if an expected
2049          * report has not yet landed in memory.  (At least on Haswell the OA
2050          * buffer tail pointer is not synchronized with reports being visible
2051          * to the CPU)
2052          */
2053         void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2054
2055         /**
2056          * @enable_metric_set: Applies any MUX configuration to set up the
2057          * Boolean and Custom (B/C) counters that are part of the counter
2058          * reports being sampled. May apply system constraints such as
2059          * disabling EU clock gating as required.
2060          */
2061         int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2062
2063         /**
2064          * @disable_metric_set: Remove system constraints associated with using
2065          * the OA unit.
2066          */
2067         void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2068
2069         /**
2070          * @oa_enable: Enable periodic sampling
2071          */
2072         void (*oa_enable)(struct drm_i915_private *dev_priv);
2073
2074         /**
2075          * @oa_disable: Disable periodic sampling
2076          */
2077         void (*oa_disable)(struct drm_i915_private *dev_priv);
2078
2079         /**
2080          * @read: Copy data from the circular OA buffer into a given userspace
2081          * buffer.
2082          */
2083         int (*read)(struct i915_perf_stream *stream,
2084                     char __user *buf,
2085                     size_t count,
2086                     size_t *offset);
2087
2088         /**
2089          * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2090          *
2091          * This is either called via fops or the poll check hrtimer (atomic
2092          * ctx) without any locks taken.
2093          *
2094          * It's safe to read OA config state here unlocked, assuming that this
2095          * is only called while the stream is enabled, while the global OA
2096          * configuration can't be modified.
2097          *
2098          * Efficiency is more important than avoiding some false positives
2099          * here, which will be handled gracefully - likely resulting in an
2100          * %EAGAIN error for userspace.
2101          */
2102         bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2103 };
2104
2105 struct intel_cdclk_state {
2106         unsigned int cdclk, vco, ref;
2107 };
2108
2109 struct drm_i915_private {
2110         struct drm_device drm;
2111
2112         struct kmem_cache *objects;
2113         struct kmem_cache *vmas;
2114         struct kmem_cache *requests;
2115         struct kmem_cache *dependencies;
2116
2117         const struct intel_device_info info;
2118
2119         void __iomem *regs;
2120
2121         struct intel_uncore uncore;
2122
2123         struct i915_virtual_gpu vgpu;
2124
2125         struct intel_gvt *gvt;
2126
2127         struct intel_huc huc;
2128         struct intel_guc guc;
2129
2130         struct intel_csr csr;
2131
2132         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2133
2134         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2135          * controller on different i2c buses. */
2136         struct mutex gmbus_mutex;
2137
2138         /**
2139          * Base address of the gmbus and gpio block.
2140          */
2141         uint32_t gpio_mmio_base;
2142
2143         /* MMIO base address for MIPI regs */
2144         uint32_t mipi_mmio_base;
2145
2146         uint32_t psr_mmio_base;
2147
2148         uint32_t pps_mmio_base;
2149
2150         wait_queue_head_t gmbus_wait_queue;
2151
2152         struct pci_dev *bridge_dev;
2153         struct i915_gem_context *kernel_context;
2154         struct intel_engine_cs *engine[I915_NUM_ENGINES];
2155         struct i915_vma *semaphore;
2156
2157         struct drm_dma_handle *status_page_dmah;
2158         struct resource mch_res;
2159
2160         /* protects the irq masks */
2161         spinlock_t irq_lock;
2162
2163         /* protects the mmio flip data */
2164         spinlock_t mmio_flip_lock;
2165
2166         bool display_irqs_enabled;
2167
2168         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2169         struct pm_qos_request pm_qos;
2170
2171         /* Sideband mailbox protection */
2172         struct mutex sb_lock;
2173
2174         /** Cached value of IMR to avoid reads in updating the bitfield */
2175         union {
2176                 u32 irq_mask;
2177                 u32 de_irq_mask[I915_MAX_PIPES];
2178         };
2179         u32 gt_irq_mask;
2180         u32 pm_imr;
2181         u32 pm_ier;
2182         u32 pm_rps_events;
2183         u32 pm_guc_events;
2184         u32 pipestat_irq_mask[I915_MAX_PIPES];
2185
2186         struct i915_hotplug hotplug;
2187         struct intel_fbc fbc;
2188         struct i915_drrs drrs;
2189         struct intel_opregion opregion;
2190         struct intel_vbt_data vbt;
2191
2192         bool preserve_bios_swizzle;
2193
2194         /* overlay */
2195         struct intel_overlay *overlay;
2196
2197         /* backlight registers and fields in struct intel_panel */
2198         struct mutex backlight_lock;
2199
2200         /* LVDS info */
2201         bool no_aux_handshake;
2202
2203         /* protects panel power sequencer state */
2204         struct mutex pps_mutex;
2205
2206         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2207         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2208
2209         unsigned int fsb_freq, mem_freq, is_ddr3;
2210         unsigned int skl_preferred_vco_freq;
2211         unsigned int max_cdclk_freq;
2212
2213         unsigned int max_dotclk_freq;
2214         unsigned int rawclk_freq;
2215         unsigned int hpll_freq;
2216         unsigned int czclk_freq;
2217
2218         struct {
2219                 /*
2220                  * The current logical cdclk state.
2221                  * See intel_atomic_state.cdclk.logical
2222                  *
2223                  * For reading holding any crtc lock is sufficient,
2224                  * for writing must hold all of them.
2225                  */
2226                 struct intel_cdclk_state logical;
2227                 /*
2228                  * The current actual cdclk state.
2229                  * See intel_atomic_state.cdclk.actual
2230                  */
2231                 struct intel_cdclk_state actual;
2232                 /* The current hardware cdclk state */
2233                 struct intel_cdclk_state hw;
2234         } cdclk;
2235
2236         /**
2237          * wq - Driver workqueue for GEM.
2238          *
2239          * NOTE: Work items scheduled here are not allowed to grab any modeset
2240          * locks, for otherwise the flushing done in the pageflip code will
2241          * result in deadlocks.
2242          */
2243         struct workqueue_struct *wq;
2244
2245         /* Display functions */
2246         struct drm_i915_display_funcs display;
2247
2248         /* PCH chipset type */
2249         enum intel_pch pch_type;
2250         unsigned short pch_id;
2251
2252         unsigned long quirks;
2253
2254         enum modeset_restore modeset_restore;
2255         struct mutex modeset_restore_lock;
2256         struct drm_atomic_state *modeset_restore_state;
2257         struct drm_modeset_acquire_ctx reset_ctx;
2258
2259         struct list_head vm_list; /* Global list of all address spaces */
2260         struct i915_ggtt ggtt; /* VM representing the global address space */
2261
2262         struct i915_gem_mm mm;
2263         DECLARE_HASHTABLE(mm_structs, 7);
2264         struct mutex mm_lock;
2265
2266         /* The hw wants to have a stable context identifier for the lifetime
2267          * of the context (for OA, PASID, faults, etc). This is limited
2268          * in execlists to 21 bits.
2269          */
2270         struct ida context_hw_ida;
2271 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2272
2273         /* Kernel Modesetting */
2274
2275         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2276         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2277         wait_queue_head_t pending_flip_queue;
2278
2279 #ifdef CONFIG_DEBUG_FS
2280         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2281 #endif
2282
2283         /* dpll and cdclk state is protected by connection_mutex */
2284         int num_shared_dpll;
2285         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2286         const struct intel_dpll_mgr *dpll_mgr;
2287
2288         /*
2289          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2290          * Must be global rather than per dpll, because on some platforms
2291          * plls share registers.
2292          */
2293         struct mutex dpll_lock;
2294
2295         unsigned int active_crtcs;
2296         unsigned int min_pixclk[I915_MAX_PIPES];
2297
2298         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2299
2300         struct i915_workarounds workarounds;
2301
2302         struct i915_frontbuffer_tracking fb_tracking;
2303
2304         struct intel_atomic_helper {
2305                 struct llist_head free_list;
2306                 struct work_struct free_work;
2307         } atomic_helper;
2308
2309         u16 orig_clock;
2310
2311         bool mchbar_need_disable;
2312
2313         struct intel_l3_parity l3_parity;
2314
2315         /* Cannot be determined by PCIID. You must always read a register. */
2316         u32 edram_cap;
2317
2318         /* gen6+ rps state */
2319         struct intel_gen6_power_mgmt rps;
2320
2321         /* ilk-only ips/rps state. Everything in here is protected by the global
2322          * mchdev_lock in intel_pm.c */
2323         struct intel_ilk_power_mgmt ips;
2324
2325         struct i915_power_domains power_domains;
2326
2327         struct i915_psr psr;
2328
2329         struct i915_gpu_error gpu_error;
2330
2331         struct drm_i915_gem_object *vlv_pctx;
2332
2333 #ifdef CONFIG_DRM_FBDEV_EMULATION
2334         /* list of fbdev register on this device */
2335         struct intel_fbdev *fbdev;
2336         struct work_struct fbdev_suspend_work;
2337 #endif
2338
2339         struct drm_property *broadcast_rgb_property;
2340         struct drm_property *force_audio_property;
2341
2342         /* hda/i915 audio component */
2343         struct i915_audio_component *audio_component;
2344         bool audio_component_registered;
2345         /**
2346          * av_mutex - mutex for audio/video sync
2347          *
2348          */
2349         struct mutex av_mutex;
2350
2351         uint32_t hw_context_size;
2352         struct list_head context_list;
2353
2354         u32 fdi_rx_config;
2355
2356         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2357         u32 chv_phy_control;
2358         /*
2359          * Shadows for CHV DPLL_MD regs to keep the state
2360          * checker somewhat working in the presence hardware
2361          * crappiness (can't read out DPLL_MD for pipes B & C).
2362          */
2363         u32 chv_dpll_md[I915_MAX_PIPES];
2364         u32 bxt_phy_grc;
2365
2366         u32 suspend_count;
2367         bool suspended_to_idle;
2368         struct i915_suspend_saved_registers regfile;
2369         struct vlv_s0ix_state vlv_s0ix_state;
2370
2371         enum {
2372                 I915_SAGV_UNKNOWN = 0,
2373                 I915_SAGV_DISABLED,
2374                 I915_SAGV_ENABLED,
2375                 I915_SAGV_NOT_CONTROLLED
2376         } sagv_status;
2377
2378         struct {
2379                 /* protects DSPARB registers on pre-g4x/vlv/chv */
2380                 spinlock_t dsparb_lock;
2381
2382                 /*
2383                  * Raw watermark latency values:
2384                  * in 0.1us units for WM0,
2385                  * in 0.5us units for WM1+.
2386                  */
2387                 /* primary */
2388                 uint16_t pri_latency[5];
2389                 /* sprite */
2390                 uint16_t spr_latency[5];
2391                 /* cursor */
2392                 uint16_t cur_latency[5];
2393                 /*
2394                  * Raw watermark memory latency values
2395                  * for SKL for all 8 levels
2396                  * in 1us units.
2397                  */
2398                 uint16_t skl_latency[8];
2399
2400                 /* current hardware state */
2401                 union {
2402                         struct ilk_wm_values hw;
2403                         struct skl_wm_values skl_hw;
2404                         struct vlv_wm_values vlv;
2405                 };
2406
2407                 uint8_t max_level;
2408
2409                 /*
2410                  * Should be held around atomic WM register writing; also
2411                  * protects * intel_crtc->wm.active and
2412                  * cstate->wm.need_postvbl_update.
2413                  */
2414                 struct mutex wm_mutex;
2415
2416                 /*
2417                  * Set during HW readout of watermarks/DDB.  Some platforms
2418                  * need to know when we're still using BIOS-provided values
2419                  * (which we don't fully trust).
2420                  */
2421                 bool distrust_bios_wm;
2422         } wm;
2423
2424         struct i915_runtime_pm pm;
2425
2426         struct {
2427                 bool initialized;
2428
2429                 struct kobject *metrics_kobj;
2430                 struct ctl_table_header *sysctl_header;
2431
2432                 struct mutex lock;
2433                 struct list_head streams;
2434
2435                 spinlock_t hook_lock;
2436
2437                 struct {
2438                         struct i915_perf_stream *exclusive_stream;
2439
2440                         u32 specific_ctx_id;
2441
2442                         struct hrtimer poll_check_timer;
2443                         wait_queue_head_t poll_wq;
2444                         bool pollin;
2445
2446                         bool periodic;
2447                         int period_exponent;
2448                         int timestamp_frequency;
2449
2450                         int tail_margin;
2451
2452                         int metrics_set;
2453
2454                         const struct i915_oa_reg *mux_regs;
2455                         int mux_regs_len;
2456                         const struct i915_oa_reg *b_counter_regs;
2457                         int b_counter_regs_len;
2458
2459                         struct {
2460                                 struct i915_vma *vma;
2461                                 u8 *vaddr;
2462                                 int format;
2463                                 int format_size;
2464                         } oa_buffer;
2465
2466                         u32 gen7_latched_oastatus1;
2467
2468                         struct i915_oa_ops ops;
2469                         const struct i915_oa_format *oa_formats;
2470                         int n_builtin_sets;
2471                 } oa;
2472         } perf;
2473
2474         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2475         struct {
2476                 void (*resume)(struct drm_i915_private *);
2477                 void (*cleanup_engine)(struct intel_engine_cs *engine);
2478
2479                 struct list_head timelines;
2480                 struct i915_gem_timeline global_timeline;
2481                 u32 active_requests;
2482
2483                 /**
2484                  * Is the GPU currently considered idle, or busy executing
2485                  * userspace requests? Whilst idle, we allow runtime power
2486                  * management to power down the hardware and display clocks.
2487                  * In order to reduce the effect on performance, there
2488                  * is a slight delay before we do so.
2489                  */
2490                 bool awake;
2491
2492                 /**
2493                  * We leave the user IRQ off as much as possible,
2494                  * but this means that requests will finish and never
2495                  * be retired once the system goes idle. Set a timer to
2496                  * fire periodically while the ring is running. When it
2497                  * fires, go retire requests.
2498                  */
2499                 struct delayed_work retire_work;
2500
2501                 /**
2502                  * When we detect an idle GPU, we want to turn on
2503                  * powersaving features. So once we see that there
2504                  * are no more requests outstanding and no more
2505                  * arrive within a small period of time, we fire
2506                  * off the idle_work.
2507                  */
2508                 struct delayed_work idle_work;
2509
2510                 ktime_t last_init_time;
2511         } gt;
2512
2513         /* perform PHY state sanity checks? */
2514         bool chv_phy_assert[2];
2515
2516         bool ipc_enabled;
2517
2518         /* Used to save the pipe-to-encoder mapping for audio */
2519         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2520
2521         /*
2522          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2523          * will be rejected. Instead look for a better place.
2524          */
2525 };
2526
2527 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2528 {
2529         return container_of(dev, struct drm_i915_private, drm);
2530 }
2531
2532 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2533 {
2534         return to_i915(dev_get_drvdata(kdev));
2535 }
2536
2537 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2538 {
2539         return container_of(guc, struct drm_i915_private, guc);
2540 }
2541
2542 /* Simple iterator over all initialised engines */
2543 #define for_each_engine(engine__, dev_priv__, id__) \
2544         for ((id__) = 0; \
2545              (id__) < I915_NUM_ENGINES; \
2546              (id__)++) \
2547                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2548
2549 #define __mask_next_bit(mask) ({                                        \
2550         int __idx = ffs(mask) - 1;                                      \
2551         mask &= ~BIT(__idx);                                            \
2552         __idx;                                                          \
2553 })
2554
2555 /* Iterator over subset of engines selected by mask */
2556 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2557         for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;        \
2558              tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2559
2560 enum hdmi_force_audio {
2561         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2562         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2563         HDMI_AUDIO_AUTO,                /* trust EDID */
2564         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2565 };
2566
2567 #define I915_GTT_OFFSET_NONE ((u32)-1)
2568
2569 /*
2570  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2571  * considered to be the frontbuffer for the given plane interface-wise. This
2572  * doesn't mean that the hw necessarily already scans it out, but that any
2573  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2574  *
2575  * We have one bit per pipe and per scanout plane type.
2576  */
2577 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2578 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2579 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2580         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2581 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2582         (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2583 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2584         (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2585 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2586         (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2587 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2588         (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2589
2590 /*
2591  * Optimised SGL iterator for GEM objects
2592  */
2593 static __always_inline struct sgt_iter {
2594         struct scatterlist *sgp;
2595         union {
2596                 unsigned long pfn;
2597                 dma_addr_t dma;
2598         };
2599         unsigned int curr;
2600         unsigned int max;
2601 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2602         struct sgt_iter s = { .sgp = sgl };
2603
2604         if (s.sgp) {
2605                 s.max = s.curr = s.sgp->offset;
2606                 s.max += s.sgp->length;
2607                 if (dma)
2608                         s.dma = sg_dma_address(s.sgp);
2609                 else
2610                         s.pfn = page_to_pfn(sg_page(s.sgp));
2611         }
2612
2613         return s;
2614 }
2615
2616 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2617 {
2618         ++sg;
2619         if (unlikely(sg_is_chain(sg)))
2620                 sg = sg_chain_ptr(sg);
2621         return sg;
2622 }
2623
2624 /**
2625  * __sg_next - return the next scatterlist entry in a list
2626  * @sg:         The current sg entry
2627  *
2628  * Description:
2629  *   If the entry is the last, return NULL; otherwise, step to the next
2630  *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2631  *   otherwise just return the pointer to the current element.
2632  **/
2633 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2634 {
2635 #ifdef CONFIG_DEBUG_SG
2636         BUG_ON(sg->sg_magic != SG_MAGIC);
2637 #endif
2638         return sg_is_last(sg) ? NULL : ____sg_next(sg);
2639 }
2640
2641 /**
2642  * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2643  * @__dmap:     DMA address (output)
2644  * @__iter:     'struct sgt_iter' (iterator state, internal)
2645  * @__sgt:      sg_table to iterate over (input)
2646  */
2647 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2648         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2649              ((__dmap) = (__iter).dma + (__iter).curr);                 \
2650              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2651              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2652
2653 /**
2654  * for_each_sgt_page - iterate over the pages of the given sg_table
2655  * @__pp:       page pointer (output)
2656  * @__iter:     'struct sgt_iter' (iterator state, internal)
2657  * @__sgt:      sg_table to iterate over (input)
2658  */
2659 #define for_each_sgt_page(__pp, __iter, __sgt)                          \
2660         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2661              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2662               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2663              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2664              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2665
2666 static inline const struct intel_device_info *
2667 intel_info(const struct drm_i915_private *dev_priv)
2668 {
2669         return &dev_priv->info;
2670 }
2671
2672 #define INTEL_INFO(dev_priv)    intel_info((dev_priv))
2673
2674 #define INTEL_GEN(dev_priv)     ((dev_priv)->info.gen)
2675 #define INTEL_DEVID(dev_priv)   ((dev_priv)->info.device_id)
2676
2677 #define REVID_FOREVER           0xff
2678 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
2679
2680 #define GEN_FOREVER (0)
2681 /*
2682  * Returns true if Gen is in inclusive range [Start, End].
2683  *
2684  * Use GEN_FOREVER for unbound start and or end.
2685  */
2686 #define IS_GEN(dev_priv, s, e) ({ \
2687         unsigned int __s = (s), __e = (e); \
2688         BUILD_BUG_ON(!__builtin_constant_p(s)); \
2689         BUILD_BUG_ON(!__builtin_constant_p(e)); \
2690         if ((__s) != GEN_FOREVER) \
2691                 __s = (s) - 1; \
2692         if ((__e) == GEN_FOREVER) \
2693                 __e = BITS_PER_LONG - 1; \
2694         else \
2695                 __e = (e) - 1; \
2696         !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2697 })
2698
2699 /*
2700  * Return true if revision is in range [since,until] inclusive.
2701  *
2702  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2703  */
2704 #define IS_REVID(p, since, until) \
2705         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2706
2707 #define IS_I830(dev_priv)       ((dev_priv)->info.platform == INTEL_I830)
2708 #define IS_I845G(dev_priv)      ((dev_priv)->info.platform == INTEL_I845G)
2709 #define IS_I85X(dev_priv)       ((dev_priv)->info.platform == INTEL_I85X)
2710 #define IS_I865G(dev_priv)      ((dev_priv)->info.platform == INTEL_I865G)
2711 #define IS_I915G(dev_priv)      ((dev_priv)->info.platform == INTEL_I915G)
2712 #define IS_I915GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I915GM)
2713 #define IS_I945G(dev_priv)      ((dev_priv)->info.platform == INTEL_I945G)
2714 #define IS_I945GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I945GM)
2715 #define IS_I965G(dev_priv)      ((dev_priv)->info.platform == INTEL_I965G)
2716 #define IS_I965GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I965GM)
2717 #define IS_G45(dev_priv)        ((dev_priv)->info.platform == INTEL_G45)
2718 #define IS_GM45(dev_priv)       ((dev_priv)->info.platform == INTEL_GM45)
2719 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
2720 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2721 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2722 #define IS_PINEVIEW(dev_priv)   ((dev_priv)->info.platform == INTEL_PINEVIEW)
2723 #define IS_G33(dev_priv)        ((dev_priv)->info.platform == INTEL_G33)
2724 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2725 #define IS_IVYBRIDGE(dev_priv)  ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2726 #define IS_IVB_GT1(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0156 || \
2727                                  INTEL_DEVID(dev_priv) == 0x0152 || \
2728                                  INTEL_DEVID(dev_priv) == 0x015a)
2729 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2730 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2731 #define IS_HASWELL(dev_priv)    ((dev_priv)->info.platform == INTEL_HASWELL)
2732 #define IS_BROADWELL(dev_priv)  ((dev_priv)->info.platform == INTEL_BROADWELL)
2733 #define IS_SKYLAKE(dev_priv)    ((dev_priv)->info.platform == INTEL_SKYLAKE)
2734 #define IS_BROXTON(dev_priv)    ((dev_priv)->info.platform == INTEL_BROXTON)
2735 #define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.platform == INTEL_KABYLAKE)
2736 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2737 #define IS_MOBILE(dev_priv)     ((dev_priv)->info.is_mobile)
2738 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2739                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2740 #define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
2741                                  ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||       \
2742                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||        \
2743                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2744 /* ULX machines are also considered ULT. */
2745 #define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
2746                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2747 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
2748                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2749 #define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
2750                                  (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2751 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
2752                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2753 /* ULX machines are also considered ULT. */
2754 #define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
2755                                  INTEL_DEVID(dev_priv) == 0x0A1E)
2756 #define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
2757                                  INTEL_DEVID(dev_priv) == 0x1913 || \
2758                                  INTEL_DEVID(dev_priv) == 0x1916 || \
2759                                  INTEL_DEVID(dev_priv) == 0x1921 || \
2760                                  INTEL_DEVID(dev_priv) == 0x1926)
2761 #define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
2762                                  INTEL_DEVID(dev_priv) == 0x1915 || \
2763                                  INTEL_DEVID(dev_priv) == 0x191E)
2764 #define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
2765                                  INTEL_DEVID(dev_priv) == 0x5913 || \
2766                                  INTEL_DEVID(dev_priv) == 0x5916 || \
2767                                  INTEL_DEVID(dev_priv) == 0x5921 || \
2768                                  INTEL_DEVID(dev_priv) == 0x5926)
2769 #define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
2770                                  INTEL_DEVID(dev_priv) == 0x5915 || \
2771                                  INTEL_DEVID(dev_priv) == 0x591E)
2772 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2773                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2774 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2775                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2776
2777 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2778
2779 #define SKL_REVID_A0            0x0
2780 #define SKL_REVID_B0            0x1
2781 #define SKL_REVID_C0            0x2
2782 #define SKL_REVID_D0            0x3
2783 #define SKL_REVID_E0            0x4
2784 #define SKL_REVID_F0            0x5
2785 #define SKL_REVID_G0            0x6
2786 #define SKL_REVID_H0            0x7
2787
2788 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2789
2790 #define BXT_REVID_A0            0x0
2791 #define BXT_REVID_A1            0x1
2792 #define BXT_REVID_B0            0x3
2793 #define BXT_REVID_B_LAST        0x8
2794 #define BXT_REVID_C0            0x9
2795
2796 #define IS_BXT_REVID(dev_priv, since, until) \
2797         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2798
2799 #define KBL_REVID_A0            0x0
2800 #define KBL_REVID_B0            0x1
2801 #define KBL_REVID_C0            0x2
2802 #define KBL_REVID_D0            0x3
2803 #define KBL_REVID_E0            0x4
2804
2805 #define IS_KBL_REVID(dev_priv, since, until) \
2806         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2807
2808 #define GLK_REVID_A0            0x0
2809 #define GLK_REVID_A1            0x1
2810
2811 #define IS_GLK_REVID(dev_priv, since, until) \
2812         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2813
2814 /*
2815  * The genX designation typically refers to the render engine, so render
2816  * capability related checks should use IS_GEN, while display and other checks
2817  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2818  * chips, etc.).
2819  */
2820 #define IS_GEN2(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(1)))
2821 #define IS_GEN3(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(2)))
2822 #define IS_GEN4(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(3)))
2823 #define IS_GEN5(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(4)))
2824 #define IS_GEN6(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(5)))
2825 #define IS_GEN7(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(6)))
2826 #define IS_GEN8(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(7)))
2827 #define IS_GEN9(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(8)))
2828
2829 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2830 #define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2831 #define IS_GEN9_BC(dev_priv)    (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2832
2833 #define ENGINE_MASK(id) BIT(id)
2834 #define RENDER_RING     ENGINE_MASK(RCS)
2835 #define BSD_RING        ENGINE_MASK(VCS)
2836 #define BLT_RING        ENGINE_MASK(BCS)
2837 #define VEBOX_RING      ENGINE_MASK(VECS)
2838 #define BSD2_RING       ENGINE_MASK(VCS2)
2839 #define ALL_ENGINES     (~0)
2840
2841 #define HAS_ENGINE(dev_priv, id) \
2842         (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2843
2844 #define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2845 #define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2846 #define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2847 #define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2848
2849 #define HAS_LLC(dev_priv)       ((dev_priv)->info.has_llc)
2850 #define HAS_SNOOP(dev_priv)     ((dev_priv)->info.has_snoop)
2851 #define HAS_EDRAM(dev_priv)     (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2852 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
2853                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2854
2855 #define HWS_NEEDS_PHYSICAL(dev_priv)    ((dev_priv)->info.hws_needs_physical)
2856
2857 #define HAS_HW_CONTEXTS(dev_priv)           ((dev_priv)->info.has_hw_contexts)
2858 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2859                 ((dev_priv)->info.has_logical_ring_contexts)
2860 #define USES_PPGTT(dev_priv)            (i915.enable_ppgtt)
2861 #define USES_FULL_PPGTT(dev_priv)       (i915.enable_ppgtt >= 2)
2862 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2863
2864 #define HAS_OVERLAY(dev_priv)            ((dev_priv)->info.has_overlay)
2865 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2866                 ((dev_priv)->info.overlay_needs_physical)
2867
2868 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2869 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
2870
2871 /* WaRsDisableCoarsePowerGating:skl,bxt */
2872 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2873         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2874
2875 /*
2876  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2877  * even when in MSI mode. This results in spurious interrupt warnings if the
2878  * legacy irq no. is shared with another device. The kernel then disables that
2879  * interrupt source and so prevents the other device from working properly.
2880  */
2881 #define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
2882 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2883
2884 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2885  * rows, which changed the alignment requirements and fence programming.
2886  */
2887 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2888                                          !(IS_I915G(dev_priv) || \
2889                                          IS_I915GM(dev_priv)))
2890 #define SUPPORTS_TV(dev_priv)           ((dev_priv)->info.supports_tv)
2891 #define I915_HAS_HOTPLUG(dev_priv)      ((dev_priv)->info.has_hotplug)
2892
2893 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
2894 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2895 #define HAS_FBC(dev_priv)       ((dev_priv)->info.has_fbc)
2896
2897 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2898
2899 #define HAS_DP_MST(dev_priv)    ((dev_priv)->info.has_dp_mst)
2900
2901 #define HAS_DDI(dev_priv)                ((dev_priv)->info.has_ddi)
2902 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2903 #define HAS_PSR(dev_priv)                ((dev_priv)->info.has_psr)
2904 #define HAS_RC6(dev_priv)                ((dev_priv)->info.has_rc6)
2905 #define HAS_RC6p(dev_priv)               ((dev_priv)->info.has_rc6p)
2906
2907 #define HAS_CSR(dev_priv)       ((dev_priv)->info.has_csr)
2908
2909 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2910 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2911
2912 /*
2913  * For now, anything with a GuC requires uCode loading, and then supports
2914  * command submission once loaded. But these are logically independent
2915  * properties, so we have separate macros to test them.
2916  */
2917 #define HAS_GUC(dev_priv)       ((dev_priv)->info.has_guc)
2918 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2919 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2920 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2921
2922 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2923
2924 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2925
2926 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2927 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2928 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2929 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2930 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2931 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2932 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2933 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2934 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA200
2935 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2936 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2937 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2938
2939 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2940 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2941 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2942 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2943 #define HAS_PCH_LPT_LP(dev_priv) \
2944         ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2945 #define HAS_PCH_LPT_H(dev_priv) \
2946         ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2947 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2948 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2949 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2950 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2951
2952 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2953
2954 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2955
2956 /* DPF == dynamic parity feature */
2957 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2958 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2959                                  2 : HAS_L3_DPF(dev_priv))
2960
2961 #define GT_FREQUENCY_MULTIPLIER 50
2962 #define GEN9_FREQ_SCALER 3
2963
2964 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2965
2966 #include "i915_trace.h"
2967
2968 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2969 {
2970 #ifdef CONFIG_INTEL_IOMMU
2971         if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2972                 return true;
2973 #endif
2974         return false;
2975 }
2976
2977 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2978                                 int enable_ppgtt);
2979
2980 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2981
2982 /* i915_drv.c */
2983 void __printf(3, 4)
2984 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2985               const char *fmt, ...);
2986
2987 #define i915_report_error(dev_priv, fmt, ...)                              \
2988         __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2989
2990 #ifdef CONFIG_COMPAT
2991 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2992                               unsigned long arg);
2993 #else
2994 #define i915_compat_ioctl NULL
2995 #endif
2996 extern const struct dev_pm_ops i915_pm_ops;
2997
2998 extern int i915_driver_load(struct pci_dev *pdev,
2999                             const struct pci_device_id *ent);
3000 extern void i915_driver_unload(struct drm_device *dev);
3001 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3002 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3003 extern void i915_reset(struct drm_i915_private *dev_priv);
3004 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3005 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3006 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3007 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3008 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3009 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3010 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3011 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3012
3013 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3014 int intel_engines_init(struct drm_i915_private *dev_priv);
3015
3016 /* intel_hotplug.c */
3017 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3018                            u32 pin_mask, u32 long_mask);
3019 void intel_hpd_init(struct drm_i915_private *dev_priv);
3020 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3021 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3022 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3023 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3024 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3025
3026 /* i915_irq.c */
3027 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3028 {
3029         unsigned long delay;
3030
3031         if (unlikely(!i915.enable_hangcheck))
3032                 return;
3033
3034         /* Don't continually defer the hangcheck so that it is always run at
3035          * least once after work has been scheduled on any ring. Otherwise,
3036          * we will ignore a hung ring if a second ring is kept busy.
3037          */
3038
3039         delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3040         queue_delayed_work(system_long_wq,
3041                            &dev_priv->gpu_error.hangcheck_work, delay);
3042 }
3043
3044 __printf(3, 4)
3045 void i915_handle_error(struct drm_i915_private *dev_priv,
3046                        u32 engine_mask,
3047                        const char *fmt, ...);
3048
3049 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3050 int intel_irq_install(struct drm_i915_private *dev_priv);
3051 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3052
3053 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3054 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3055                                         bool restore_forcewake);
3056 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3057 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3058 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3059 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3060 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3061                                          bool restore);
3062 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3063 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3064                                 enum forcewake_domains domains);
3065 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3066                                 enum forcewake_domains domains);
3067 /* Like above but the caller must manage the uncore.lock itself.
3068  * Must be used with I915_READ_FW and friends.
3069  */
3070 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3071                                         enum forcewake_domains domains);
3072 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3073                                         enum forcewake_domains domains);
3074 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3075
3076 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3077
3078 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3079                             i915_reg_t reg,
3080                             const u32 mask,
3081                             const u32 value,
3082                             const unsigned long timeout_ms);
3083 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3084                                i915_reg_t reg,
3085                                const u32 mask,
3086                                const u32 value,
3087                                const unsigned long timeout_ms);
3088
3089 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3090 {
3091         return dev_priv->gvt;
3092 }
3093
3094 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3095 {
3096         return dev_priv->vgpu.active;
3097 }
3098
3099 void
3100 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3101                      u32 status_mask);
3102
3103 void
3104 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3105                       u32 status_mask);
3106
3107 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3108 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3109 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3110                                    uint32_t mask,
3111                                    uint32_t bits);
3112 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3113                             uint32_t interrupt_mask,
3114                             uint32_t enabled_irq_mask);
3115 static inline void
3116 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3117 {
3118         ilk_update_display_irq(dev_priv, bits, bits);
3119 }
3120 static inline void
3121 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3122 {
3123         ilk_update_display_irq(dev_priv, bits, 0);
3124 }
3125 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3126                          enum pipe pipe,
3127                          uint32_t interrupt_mask,
3128                          uint32_t enabled_irq_mask);
3129 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3130                                        enum pipe pipe, uint32_t bits)
3131 {
3132         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3133 }
3134 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3135                                         enum pipe pipe, uint32_t bits)
3136 {
3137         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3138 }
3139 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3140                                   uint32_t interrupt_mask,
3141                                   uint32_t enabled_irq_mask);
3142 static inline void
3143 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3144 {
3145         ibx_display_interrupt_update(dev_priv, bits, bits);
3146 }
3147 static inline void
3148 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3149 {
3150         ibx_display_interrupt_update(dev_priv, bits, 0);
3151 }
3152
3153 /* i915_gem.c */
3154 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3155                           struct drm_file *file_priv);
3156 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3157                          struct drm_file *file_priv);
3158 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3159                           struct drm_file *file_priv);
3160 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3161                         struct drm_file *file_priv);
3162 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3163                         struct drm_file *file_priv);
3164 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3165                               struct drm_file *file_priv);
3166 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3167                              struct drm_file *file_priv);
3168 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3169                         struct drm_file *file_priv);
3170 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3171                          struct drm_file *file_priv);
3172 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3173                         struct drm_file *file_priv);
3174 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3175                                struct drm_file *file);
3176 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3177                                struct drm_file *file);
3178 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3179                             struct drm_file *file_priv);
3180 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3181                            struct drm_file *file_priv);
3182 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3183                               struct drm_file *file_priv);
3184 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3185                               struct drm_file *file_priv);
3186 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3187 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3188                            struct drm_file *file);
3189 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3190                                 struct drm_file *file_priv);
3191 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3192                         struct drm_file *file_priv);
3193 void i915_gem_sanitize(struct drm_i915_private *i915);
3194 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3195 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3196 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3197 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3198 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3199
3200 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3201 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3202 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3203                          const struct drm_i915_gem_object_ops *ops);
3204 struct drm_i915_gem_object *
3205 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3206 struct drm_i915_gem_object *
3207 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3208                                  const void *data, size_t size);
3209 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3210 void i915_gem_free_object(struct drm_gem_object *obj);
3211
3212 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3213 {
3214         /* A single pass should suffice to release all the freed objects (along
3215          * most call paths) , but be a little more paranoid in that freeing
3216          * the objects does take a little amount of time, during which the rcu
3217          * callbacks could have added new objects into the freed list, and
3218          * armed the work again.
3219          */
3220         do {
3221                 rcu_barrier();
3222         } while (flush_work(&i915->mm.free_work));
3223 }
3224
3225 struct i915_vma * __must_check
3226 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3227                          const struct i915_ggtt_view *view,
3228                          u64 size,
3229                          u64 alignment,
3230                          u64 flags);
3231
3232 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3233 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3234
3235 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3236
3237 static inline int __sg_page_count(const struct scatterlist *sg)
3238 {
3239         return sg->length >> PAGE_SHIFT;
3240 }
3241
3242 struct scatterlist *
3243 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3244                        unsigned int n, unsigned int *offset);
3245
3246 struct page *
3247 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3248                          unsigned int n);
3249
3250 struct page *
3251 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3252                                unsigned int n);
3253
3254 dma_addr_t
3255 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3256                                 unsigned long n);
3257
3258 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3259                                  struct sg_table *pages);
3260 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3261
3262 static inline int __must_check
3263 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3264 {
3265         might_lock(&obj->mm.lock);
3266
3267         if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3268                 return 0;
3269
3270         return __i915_gem_object_get_pages(obj);
3271 }
3272
3273 static inline void
3274 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3275 {
3276         GEM_BUG_ON(!obj->mm.pages);
3277
3278         atomic_inc(&obj->mm.pages_pin_count);
3279 }
3280
3281 static inline bool
3282 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3283 {
3284         return atomic_read(&obj->mm.pages_pin_count);
3285 }
3286
3287 static inline void
3288 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3289 {
3290         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3291         GEM_BUG_ON(!obj->mm.pages);
3292
3293         atomic_dec(&obj->mm.pages_pin_count);
3294 }
3295
3296 static inline void
3297 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3298 {
3299         __i915_gem_object_unpin_pages(obj);
3300 }
3301
3302 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3303         I915_MM_NORMAL = 0,
3304         I915_MM_SHRINKER
3305 };
3306
3307 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3308                                  enum i915_mm_subclass subclass);
3309 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3310
3311 enum i915_map_type {
3312         I915_MAP_WB = 0,
3313         I915_MAP_WC,
3314 };
3315
3316 /**
3317  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3318  * @obj: the object to map into kernel address space
3319  * @type: the type of mapping, used to select pgprot_t
3320  *
3321  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3322  * pages and then returns a contiguous mapping of the backing storage into
3323  * the kernel address space. Based on the @type of mapping, the PTE will be
3324  * set to either WriteBack or WriteCombine (via pgprot_t).
3325  *
3326  * The caller is responsible for calling i915_gem_object_unpin_map() when the
3327  * mapping is no longer required.
3328  *
3329  * Returns the pointer through which to access the mapped object, or an
3330  * ERR_PTR() on error.
3331  */
3332 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3333                                            enum i915_map_type type);
3334
3335 /**
3336  * i915_gem_object_unpin_map - releases an earlier mapping
3337  * @obj: the object to unmap
3338  *
3339  * After pinning the object and mapping its pages, once you are finished
3340  * with your access, call i915_gem_object_unpin_map() to release the pin
3341  * upon the mapping. Once the pin count reaches zero, that mapping may be
3342  * removed.
3343  */
3344 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3345 {
3346         i915_gem_object_unpin_pages(obj);
3347 }
3348
3349 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3350                                     unsigned int *needs_clflush);
3351 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3352                                      unsigned int *needs_clflush);
3353 #define CLFLUSH_BEFORE 0x1
3354 #define CLFLUSH_AFTER 0x2
3355 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3356
3357 static inline void
3358 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3359 {
3360         i915_gem_object_unpin_pages(obj);
3361 }
3362
3363 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3364 void i915_vma_move_to_active(struct i915_vma *vma,
3365                              struct drm_i915_gem_request *req,
3366                              unsigned int flags);
3367 int i915_gem_dumb_create(struct drm_file *file_priv,
3368                          struct drm_device *dev,
3369                          struct drm_mode_create_dumb *args);
3370 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3371                       uint32_t handle, uint64_t *offset);
3372 int i915_gem_mmap_gtt_version(void);
3373
3374 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3375                        struct drm_i915_gem_object *new,
3376                        unsigned frontbuffer_bits);
3377
3378 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3379
3380 struct drm_i915_gem_request *
3381 i915_gem_find_active_request(struct intel_engine_cs *engine);
3382
3383 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3384
3385 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3386 {
3387         return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3388 }
3389
3390 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3391 {
3392         return unlikely(test_bit(I915_WEDGED, &error->flags));
3393 }
3394
3395 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3396 {
3397         return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3398 }
3399
3400 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3401 {
3402         return READ_ONCE(error->reset_count);
3403 }
3404
3405 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3406 void i915_gem_reset(struct drm_i915_private *dev_priv);
3407 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3408 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3409
3410 void i915_gem_init_mmio(struct drm_i915_private *i915);
3411 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3412 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3413 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3414 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3415 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3416                            unsigned int flags);
3417 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3418 void i915_gem_resume(struct drm_i915_private *dev_priv);
3419 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3420 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3421                          unsigned int flags,
3422                          long timeout,
3423                          struct intel_rps_client *rps);
3424 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3425                                   unsigned int flags,
3426                                   int priority);
3427 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3428
3429 int __must_check
3430 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3431                                   bool write);
3432 int __must_check
3433 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3434 struct i915_vma * __must_check
3435 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3436                                      u32 alignment,
3437                                      const struct i915_ggtt_view *view);
3438 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3439 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3440                                 int align);
3441 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3442 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3443
3444 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3445                                     enum i915_cache_level cache_level);
3446
3447 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3448                                 struct dma_buf *dma_buf);
3449
3450 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3451                                 struct drm_gem_object *gem_obj, int flags);
3452
3453 static inline struct i915_hw_ppgtt *
3454 i915_vm_to_ppgtt(struct i915_address_space *vm)
3455 {
3456         return container_of(vm, struct i915_hw_ppgtt, base);
3457 }
3458
3459 /* i915_gem_fence_reg.c */
3460 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3461 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3462
3463 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3464 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3465
3466 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3467 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3468                                        struct sg_table *pages);
3469 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3470                                          struct sg_table *pages);
3471
3472 static inline struct i915_gem_context *
3473 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3474 {
3475         struct i915_gem_context *ctx;
3476
3477         lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3478
3479         ctx = idr_find(&file_priv->context_idr, id);
3480         if (!ctx)
3481                 return ERR_PTR(-ENOENT);
3482
3483         return ctx;
3484 }
3485
3486 static inline struct i915_gem_context *
3487 i915_gem_context_get(struct i915_gem_context *ctx)
3488 {
3489         kref_get(&ctx->ref);
3490         return ctx;
3491 }
3492
3493 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3494 {
3495         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3496         kref_put(&ctx->ref, i915_gem_context_free);
3497 }
3498
3499 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3500 {
3501         struct mutex *lock = &ctx->i915->drm.struct_mutex;
3502
3503         if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3504                 mutex_unlock(lock);
3505 }
3506
3507 static inline struct intel_timeline *
3508 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3509                                  struct intel_engine_cs *engine)
3510 {
3511         struct i915_address_space *vm;
3512
3513         vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3514         return &vm->timeline.engine[engine->id];
3515 }
3516
3517 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3518                          struct drm_file *file);
3519
3520 /* i915_gem_evict.c */
3521 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3522                                           u64 min_size, u64 alignment,
3523                                           unsigned cache_level,
3524                                           u64 start, u64 end,
3525                                           unsigned flags);
3526 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3527                                          struct drm_mm_node *node,
3528                                          unsigned int flags);
3529 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3530
3531 /* belongs in i915_gem_gtt.h */
3532 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3533 {
3534         wmb();
3535         if (INTEL_GEN(dev_priv) < 6)
3536                 intel_gtt_chipset_flush();
3537 }
3538
3539 /* i915_gem_stolen.c */
3540 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3541                                 struct drm_mm_node *node, u64 size,
3542                                 unsigned alignment);
3543 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3544                                          struct drm_mm_node *node, u64 size,
3545                                          unsigned alignment, u64 start,
3546                                          u64 end);
3547 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3548                                  struct drm_mm_node *node);
3549 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3550 void i915_gem_cleanup_stolen(struct drm_device *dev);
3551 struct drm_i915_gem_object *
3552 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3553 struct drm_i915_gem_object *
3554 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3555                                                u32 stolen_offset,
3556                                                u32 gtt_offset,
3557                                                u32 size);
3558
3559 /* i915_gem_internal.c */
3560 struct drm_i915_gem_object *
3561 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3562                                 phys_addr_t size);
3563
3564 /* i915_gem_shrinker.c */
3565 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3566                               unsigned long target,
3567                               unsigned flags);
3568 #define I915_SHRINK_PURGEABLE 0x1
3569 #define I915_SHRINK_UNBOUND 0x2
3570 #define I915_SHRINK_BOUND 0x4
3571 #define I915_SHRINK_ACTIVE 0x8
3572 #define I915_SHRINK_VMAPS 0x10
3573 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3574 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3575 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3576
3577
3578 /* i915_gem_tiling.c */
3579 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3580 {
3581         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3582
3583         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3584                 i915_gem_object_is_tiled(obj);
3585 }
3586
3587 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3588                         unsigned int tiling, unsigned int stride);
3589 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3590                              unsigned int tiling, unsigned int stride);
3591
3592 /* i915_debugfs.c */
3593 #ifdef CONFIG_DEBUG_FS
3594 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3595 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3596 int i915_debugfs_connector_add(struct drm_connector *connector);
3597 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3598 #else
3599 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3600 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3601 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3602 { return 0; }
3603 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3604 #endif
3605
3606 /* i915_gpu_error.c */
3607 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3608
3609 __printf(2, 3)
3610 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3611 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3612                             const struct i915_gpu_state *gpu);
3613 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3614                               struct drm_i915_private *i915,
3615                               size_t count, loff_t pos);
3616 static inline void i915_error_state_buf_release(
3617         struct drm_i915_error_state_buf *eb)
3618 {
3619         kfree(eb->buf);
3620 }
3621
3622 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3623 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3624                               u32 engine_mask,
3625                               const char *error_msg);
3626
3627 static inline struct i915_gpu_state *
3628 i915_gpu_state_get(struct i915_gpu_state *gpu)
3629 {
3630         kref_get(&gpu->ref);
3631         return gpu;
3632 }
3633
3634 void __i915_gpu_state_free(struct kref *kref);
3635 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3636 {
3637         if (gpu)
3638                 kref_put(&gpu->ref, __i915_gpu_state_free);
3639 }
3640
3641 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3642 void i915_reset_error_state(struct drm_i915_private *i915);
3643
3644 #else
3645
3646 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3647                                             u32 engine_mask,
3648                                             const char *error_msg)
3649 {
3650 }
3651
3652 static inline struct i915_gpu_state *
3653 i915_first_error_state(struct drm_i915_private *i915)
3654 {
3655         return NULL;
3656 }
3657
3658 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3659 {
3660 }
3661
3662 #endif
3663
3664 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3665
3666 /* i915_cmd_parser.c */
3667 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3668 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3669 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3670 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3671                             struct drm_i915_gem_object *batch_obj,
3672                             struct drm_i915_gem_object *shadow_batch_obj,
3673                             u32 batch_start_offset,
3674                             u32 batch_len,
3675                             bool is_master);
3676
3677 /* i915_perf.c */
3678 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3679 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3680 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3681 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3682
3683 /* i915_suspend.c */
3684 extern int i915_save_state(struct drm_i915_private *dev_priv);
3685 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3686
3687 /* i915_sysfs.c */
3688 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3689 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3690
3691 /* intel_i2c.c */
3692 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3693 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3694 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3695                                      unsigned int pin);
3696
3697 extern struct i2c_adapter *
3698 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3699 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3700 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3701 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3702 {
3703         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3704 }
3705 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3706
3707 /* intel_bios.c */
3708 int intel_bios_init(struct drm_i915_private *dev_priv);
3709 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3710 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3711 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3712 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3713 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3714 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3715 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3716 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3717                                      enum port port);
3718 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3719                                 enum port port);
3720
3721
3722 /* intel_opregion.c */
3723 #ifdef CONFIG_ACPI
3724 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3725 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3726 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3727 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3728 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3729                                          bool enable);
3730 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3731                                          pci_power_t state);
3732 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3733 #else
3734 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3735 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3736 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3737 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3738 {
3739 }
3740 static inline int
3741 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3742 {
3743         return 0;
3744 }
3745 static inline int
3746 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3747 {
3748         return 0;
3749 }
3750 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3751 {
3752         return -ENODEV;
3753 }
3754 #endif
3755
3756 /* intel_acpi.c */
3757 #ifdef CONFIG_ACPI
3758 extern void intel_register_dsm_handler(void);
3759 extern void intel_unregister_dsm_handler(void);
3760 #else
3761 static inline void intel_register_dsm_handler(void) { return; }
3762 static inline void intel_unregister_dsm_handler(void) { return; }
3763 #endif /* CONFIG_ACPI */
3764
3765 /* intel_device_info.c */
3766 static inline struct intel_device_info *
3767 mkwrite_device_info(struct drm_i915_private *dev_priv)
3768 {
3769         return (struct intel_device_info *)&dev_priv->info;
3770 }
3771
3772 const char *intel_platform_name(enum intel_platform platform);
3773 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3774 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3775
3776 /* modesetting */
3777 extern void intel_modeset_init_hw(struct drm_device *dev);
3778 extern int intel_modeset_init(struct drm_device *dev);
3779 extern void intel_modeset_gem_init(struct drm_device *dev);
3780 extern void intel_modeset_cleanup(struct drm_device *dev);
3781 extern int intel_connector_register(struct drm_connector *);
3782 extern void intel_connector_unregister(struct drm_connector *);
3783 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3784                                        bool state);
3785 extern void intel_display_resume(struct drm_device *dev);
3786 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3787 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3788 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3789 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3790 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3791 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3792                                   bool enable);
3793
3794 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3795                         struct drm_file *file);
3796
3797 /* overlay */
3798 extern struct intel_overlay_error_state *
3799 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3800 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3801                                             struct intel_overlay_error_state *error);
3802
3803 extern struct intel_display_error_state *
3804 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3805 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3806                                             struct intel_display_error_state *error);
3807
3808 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3809 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3810 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3811                       u32 reply_mask, u32 reply, int timeout_base_ms);
3812
3813 /* intel_sideband.c */
3814 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3815 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3816 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3817 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3818 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3819 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3820 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3821 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3822 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3823 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3824 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3825 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3826 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3827 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3828                    enum intel_sbi_destination destination);
3829 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3830                      enum intel_sbi_destination destination);
3831 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3832 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3833
3834 /* intel_dpio_phy.c */
3835 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3836                              enum dpio_phy *phy, enum dpio_channel *ch);
3837 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3838                                   enum port port, u32 margin, u32 scale,
3839                                   u32 enable, u32 deemphasis);
3840 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3841 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3842 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3843                             enum dpio_phy phy);
3844 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3845                               enum dpio_phy phy);
3846 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3847                                              uint8_t lane_count);
3848 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3849                                      uint8_t lane_lat_optim_mask);
3850 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3851
3852 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3853                               u32 deemph_reg_value, u32 margin_reg_value,
3854                               bool uniq_trans_scale);
3855 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3856                               bool reset);
3857 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3858 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3859 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3860 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3861
3862 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3863                               u32 demph_reg_value, u32 preemph_reg_value,
3864                               u32 uniqtranscale_reg_value, u32 tx3_demph);
3865 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3866 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3867 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3868
3869 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3870 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3871
3872 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3873 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3874
3875 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3876 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3877 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3878 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3879
3880 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3881 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3882 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3883 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3884
3885 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3886  * will be implemented using 2 32-bit writes in an arbitrary order with
3887  * an arbitrary delay between them. This can cause the hardware to
3888  * act upon the intermediate value, possibly leading to corruption and
3889  * machine death. For this reason we do not support I915_WRITE64, or
3890  * dev_priv->uncore.funcs.mmio_writeq.
3891  *
3892  * When reading a 64-bit value as two 32-bit values, the delay may cause
3893  * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3894  * occasionally a 64-bit register does not actualy support a full readq
3895  * and must be read using two 32-bit reads.
3896  *
3897  * You have been warned.
3898  */
3899 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3900
3901 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3902         u32 upper, lower, old_upper, loop = 0;                          \
3903         upper = I915_READ(upper_reg);                                   \
3904         do {                                                            \
3905                 old_upper = upper;                                      \
3906                 lower = I915_READ(lower_reg);                           \
3907                 upper = I915_READ(upper_reg);                           \
3908         } while (upper != old_upper && loop++ < 2);                     \
3909         (u64)upper << 32 | lower; })
3910
3911 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3912 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3913
3914 #define __raw_read(x, s) \
3915 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3916                                              i915_reg_t reg) \
3917 { \
3918         return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3919 }
3920
3921 #define __raw_write(x, s) \
3922 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3923                                        i915_reg_t reg, uint##x##_t val) \
3924 { \
3925         write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3926 }
3927 __raw_read(8, b)
3928 __raw_read(16, w)
3929 __raw_read(32, l)
3930 __raw_read(64, q)
3931
3932 __raw_write(8, b)
3933 __raw_write(16, w)
3934 __raw_write(32, l)
3935 __raw_write(64, q)
3936
3937 #undef __raw_read
3938 #undef __raw_write
3939
3940 /* These are untraced mmio-accessors that are only valid to be used inside
3941  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3942  * controlled.
3943  *
3944  * Think twice, and think again, before using these.
3945  *
3946  * As an example, these accessors can possibly be used between:
3947  *
3948  * spin_lock_irq(&dev_priv->uncore.lock);
3949  * intel_uncore_forcewake_get__locked();
3950  *
3951  * and
3952  *
3953  * intel_uncore_forcewake_put__locked();
3954  * spin_unlock_irq(&dev_priv->uncore.lock);
3955  *
3956  *
3957  * Note: some registers may not need forcewake held, so
3958  * intel_uncore_forcewake_{get,put} can be omitted, see
3959  * intel_uncore_forcewake_for_reg().
3960  *
3961  * Certain architectures will die if the same cacheline is concurrently accessed
3962  * by different clients (e.g. on Ivybridge). Access to registers should
3963  * therefore generally be serialised, by either the dev_priv->uncore.lock or
3964  * a more localised lock guarding all access to that bank of registers.
3965  */
3966 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3967 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3968 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3969 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3970
3971 /* "Broadcast RGB" property */
3972 #define INTEL_BROADCAST_RGB_AUTO 0
3973 #define INTEL_BROADCAST_RGB_FULL 1
3974 #define INTEL_BROADCAST_RGB_LIMITED 2
3975
3976 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3977 {
3978         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3979                 return VLV_VGACNTRL;
3980         else if (INTEL_GEN(dev_priv) >= 5)
3981                 return CPU_VGACNTRL;
3982         else
3983                 return VGACNTRL;
3984 }
3985
3986 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3987 {
3988         unsigned long j = msecs_to_jiffies(m);
3989
3990         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3991 }
3992
3993 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3994 {
3995         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3996 }
3997
3998 static inline unsigned long
3999 timespec_to_jiffies_timeout(const struct timespec *value)
4000 {
4001         unsigned long j = timespec_to_jiffies(value);
4002
4003         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4004 }
4005
4006 /*
4007  * If you need to wait X milliseconds between events A and B, but event B
4008  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4009  * when event A happened, then just before event B you call this function and
4010  * pass the timestamp as the first argument, and X as the second argument.
4011  */
4012 static inline void
4013 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4014 {
4015         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4016
4017         /*
4018          * Don't re-read the value of "jiffies" every time since it may change
4019          * behind our back and break the math.
4020          */
4021         tmp_jiffies = jiffies;
4022         target_jiffies = timestamp_jiffies +
4023                          msecs_to_jiffies_timeout(to_wait_ms);
4024
4025         if (time_after(target_jiffies, tmp_jiffies)) {
4026                 remaining_jiffies = target_jiffies - tmp_jiffies;
4027                 while (remaining_jiffies)
4028                         remaining_jiffies =
4029                             schedule_timeout_uninterruptible(remaining_jiffies);
4030         }
4031 }
4032
4033 static inline bool
4034 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4035 {
4036         struct intel_engine_cs *engine = req->engine;
4037         u32 seqno;
4038
4039         /* Note that the engine may have wrapped around the seqno, and
4040          * so our request->global_seqno will be ahead of the hardware,
4041          * even though it completed the request before wrapping. We catch
4042          * this by kicking all the waiters before resetting the seqno
4043          * in hardware, and also signal the fence.
4044          */
4045         if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4046                 return true;
4047
4048         /* The request was dequeued before we were awoken. We check after
4049          * inspecting the hw to confirm that this was the same request
4050          * that generated the HWS update. The memory barriers within
4051          * the request execution are sufficient to ensure that a check
4052          * after reading the value from hw matches this request.
4053          */
4054         seqno = i915_gem_request_global_seqno(req);
4055         if (!seqno)
4056                 return false;
4057
4058         /* Before we do the heavier coherent read of the seqno,
4059          * check the value (hopefully) in the CPU cacheline.
4060          */
4061         if (__i915_gem_request_completed(req, seqno))
4062                 return true;
4063
4064         /* Ensure our read of the seqno is coherent so that we
4065          * do not "miss an interrupt" (i.e. if this is the last
4066          * request and the seqno write from the GPU is not visible
4067          * by the time the interrupt fires, we will see that the
4068          * request is incomplete and go back to sleep awaiting
4069          * another interrupt that will never come.)
4070          *
4071          * Strictly, we only need to do this once after an interrupt,
4072          * but it is easier and safer to do it every time the waiter
4073          * is woken.
4074          */
4075         if (engine->irq_seqno_barrier &&
4076             test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4077                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4078                 unsigned long flags;
4079
4080                 /* The ordering of irq_posted versus applying the barrier
4081                  * is crucial. The clearing of the current irq_posted must
4082                  * be visible before we perform the barrier operation,
4083                  * such that if a subsequent interrupt arrives, irq_posted
4084                  * is reasserted and our task rewoken (which causes us to
4085                  * do another __i915_request_irq_complete() immediately
4086                  * and reapply the barrier). Conversely, if the clear
4087                  * occurs after the barrier, then an interrupt that arrived
4088                  * whilst we waited on the barrier would not trigger a
4089                  * barrier on the next pass, and the read may not see the
4090                  * seqno update.
4091                  */
4092                 engine->irq_seqno_barrier(engine);
4093
4094                 /* If we consume the irq, but we are no longer the bottom-half,
4095                  * the real bottom-half may not have serialised their own
4096                  * seqno check with the irq-barrier (i.e. may have inspected
4097                  * the seqno before we believe it coherent since they see
4098                  * irq_posted == false but we are still running).
4099                  */
4100                 spin_lock_irqsave(&b->irq_lock, flags);
4101                 if (b->irq_wait && b->irq_wait->tsk != current)
4102                         /* Note that if the bottom-half is changed as we
4103                          * are sending the wake-up, the new bottom-half will
4104                          * be woken by whomever made the change. We only have
4105                          * to worry about when we steal the irq-posted for
4106                          * ourself.
4107                          */
4108                         wake_up_process(b->irq_wait->tsk);
4109                 spin_unlock_irqrestore(&b->irq_lock, flags);
4110
4111                 if (__i915_gem_request_completed(req, seqno))
4112                         return true;
4113         }
4114
4115         return false;
4116 }
4117
4118 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4119 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4120
4121 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4122  * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4123  * perform the operation. To check beforehand, pass in the parameters to
4124  * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4125  * you only need to pass in the minor offsets, page-aligned pointers are
4126  * always valid.
4127  *
4128  * For just checking for SSE4.1, in the foreknowledge that the future use
4129  * will be correctly aligned, just use i915_has_memcpy_from_wc().
4130  */
4131 #define i915_can_memcpy_from_wc(dst, src, len) \
4132         i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4133
4134 #define i915_has_memcpy_from_wc() \
4135         i915_memcpy_from_wc(NULL, NULL, 0)
4136
4137 /* i915_mm.c */
4138 int remap_io_mapping(struct vm_area_struct *vma,
4139                      unsigned long addr, unsigned long pfn, unsigned long size,
4140                      struct io_mapping *iomap);
4141
4142 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4143 {
4144         return (obj->cache_level != I915_CACHE_NONE ||
4145                 HAS_LLC(to_i915(obj->base.dev)));
4146 }
4147
4148 #endif