1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170123"
83 #define DRIVER_TIMESTAMP 1485156432
86 /* Many gcc seem to no see through this and fall over :( */
88 #define WARN_ON(x) ({ \
89 bool __i915_warn_cond = (x); \
90 if (__builtin_constant_p(__i915_warn_cond)) \
91 BUILD_BUG_ON(__i915_warn_cond); \
92 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101 (long) (x), __func__);
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 bool __i915_inject_load_failure(const char *func, int line);
122 #define i915_inject_load_failure() \
123 __i915_inject_load_failure(__func__, __LINE__)
127 } uint_fixed_16_16_t;
129 #define FP_16_16_MAX ({ \
130 uint_fixed_16_16_t fp; \
135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
137 uint_fixed_16_16_t fp;
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
147 return DIV_ROUND_UP(fp.val, 1 << 16);
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
156 uint_fixed_16_16_t min2)
158 uint_fixed_16_16_t min;
160 min.val = min(min1.val, min2.val);
164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
165 uint_fixed_16_16_t max2)
167 uint_fixed_16_16_t max;
169 max.val = max(max1.val, max2.val);
173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
176 uint_fixed_16_16_t fp, res;
178 fp = u32_to_fixed_16_16(val);
179 res.val = DIV_ROUND_UP(fp.val, d);
183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
186 uint_fixed_16_16_t res;
189 interm_val = (uint64_t)val << 16;
190 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
191 WARN_ON(interm_val >> 32);
192 res.val = (uint32_t) interm_val;
197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
198 uint_fixed_16_16_t mul)
200 uint64_t intermediate_val;
201 uint_fixed_16_16_t fp;
203 intermediate_val = (uint64_t) val * mul.val;
204 WARN_ON(intermediate_val >> 32);
205 fp.val = (uint32_t) intermediate_val;
209 static inline const char *yesno(bool v)
211 return v ? "yes" : "no";
214 static inline const char *onoff(bool v)
216 return v ? "on" : "off";
219 static inline const char *enableddisabled(bool v)
221 return v ? "enabled" : "disabled";
230 I915_MAX_PIPES = _PIPE_EDP
232 #define pipe_name(p) ((p) + 'A')
244 static inline const char *transcoder_name(enum transcoder transcoder)
246 switch (transcoder) {
255 case TRANSCODER_DSI_A:
257 case TRANSCODER_DSI_C:
264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
266 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
270 * Global legacy plane identifier. Valid only for primary/sprite
271 * planes on pre-g4x, and only for primary planes on g4x+.
278 #define plane_name(p) ((p) + 'A')
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
283 * Per-pipe plane identifier.
284 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285 * number of planes per CRTC. Not all platforms really have this many planes,
286 * which means some arrays of size I915_MAX_PLANES may have unused entries
287 * between the topmost sprite plane and the cursor plane.
289 * This is expected to be passed to various register macros
290 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
300 #define for_each_plane_id_on_crtc(__crtc, __p) \
301 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
302 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
313 #define port_name(p) ((p) + 'A')
315 #define I915_NUM_PHYS_VLV 2
328 enum intel_display_power_domain {
332 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
333 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
334 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
335 POWER_DOMAIN_TRANSCODER_A,
336 POWER_DOMAIN_TRANSCODER_B,
337 POWER_DOMAIN_TRANSCODER_C,
338 POWER_DOMAIN_TRANSCODER_EDP,
339 POWER_DOMAIN_TRANSCODER_DSI_A,
340 POWER_DOMAIN_TRANSCODER_DSI_C,
341 POWER_DOMAIN_PORT_DDI_A_LANES,
342 POWER_DOMAIN_PORT_DDI_B_LANES,
343 POWER_DOMAIN_PORT_DDI_C_LANES,
344 POWER_DOMAIN_PORT_DDI_D_LANES,
345 POWER_DOMAIN_PORT_DDI_E_LANES,
346 POWER_DOMAIN_PORT_DSI,
347 POWER_DOMAIN_PORT_CRT,
348 POWER_DOMAIN_PORT_OTHER,
357 POWER_DOMAIN_MODESET,
363 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
364 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
365 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
366 #define POWER_DOMAIN_TRANSCODER(tran) \
367 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
368 (tran) + POWER_DOMAIN_TRANSCODER_A)
372 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
384 #define for_each_hpd_pin(__pin) \
385 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
387 struct i915_hotplug {
388 struct work_struct hotplug_work;
391 unsigned long last_jiffies;
396 HPD_MARK_DISABLED = 2
398 } stats[HPD_NUM_PINS];
400 struct delayed_work reenable_work;
402 struct intel_digital_port *irq_port[I915_MAX_PORTS];
405 struct work_struct dig_port_work;
407 struct work_struct poll_init_work;
411 * if we get a HPD irq from DP and a HPD irq from non-DP
412 * the non-DP HPD could block the workqueue on a mode config
413 * mutex getting, that userspace may have taken. However
414 * userspace is waiting on the DP workqueue to run which is
415 * blocked behind the non-DP one.
417 struct workqueue_struct *dp_wq;
420 #define I915_GEM_GPU_DOMAINS \
421 (I915_GEM_DOMAIN_RENDER | \
422 I915_GEM_DOMAIN_SAMPLER | \
423 I915_GEM_DOMAIN_COMMAND | \
424 I915_GEM_DOMAIN_INSTRUCTION | \
425 I915_GEM_DOMAIN_VERTEX)
427 #define for_each_pipe(__dev_priv, __p) \
428 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
429 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
430 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
431 for_each_if ((__mask) & (1 << (__p)))
432 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
434 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
436 #define for_each_sprite(__dev_priv, __p, __s) \
438 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
441 #define for_each_port_masked(__port, __ports_mask) \
442 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
443 for_each_if ((__ports_mask) & (1 << (__port)))
445 #define for_each_crtc(dev, crtc) \
446 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
448 #define for_each_intel_plane(dev, intel_plane) \
449 list_for_each_entry(intel_plane, \
450 &(dev)->mode_config.plane_list, \
453 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
454 list_for_each_entry(intel_plane, \
455 &(dev)->mode_config.plane_list, \
457 for_each_if ((plane_mask) & \
458 (1 << drm_plane_index(&intel_plane->base)))
460 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
461 list_for_each_entry(intel_plane, \
462 &(dev)->mode_config.plane_list, \
464 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
466 #define for_each_intel_crtc(dev, intel_crtc) \
467 list_for_each_entry(intel_crtc, \
468 &(dev)->mode_config.crtc_list, \
471 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
472 list_for_each_entry(intel_crtc, \
473 &(dev)->mode_config.crtc_list, \
475 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
477 #define for_each_intel_encoder(dev, intel_encoder) \
478 list_for_each_entry(intel_encoder, \
479 &(dev)->mode_config.encoder_list, \
482 #define for_each_intel_connector(dev, intel_connector) \
483 list_for_each_entry(intel_connector, \
484 &(dev)->mode_config.connector_list, \
487 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
488 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
489 for_each_if ((intel_encoder)->base.crtc == (__crtc))
491 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
492 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
493 for_each_if ((intel_connector)->base.encoder == (__encoder))
495 #define for_each_power_domain(domain, mask) \
496 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
497 for_each_if ((1 << (domain)) & (mask))
499 struct drm_i915_private;
500 struct i915_mm_struct;
501 struct i915_mmu_object;
503 struct drm_i915_file_private {
504 struct drm_i915_private *dev_priv;
505 struct drm_file *file;
509 struct list_head request_list;
510 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
511 * chosen to prevent the CPU getting more than a frame ahead of the GPU
512 * (when using lax throttling for the frontbuffer). We also use it to
513 * offer free GPU waitboosts for severely congested workloads.
515 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
517 struct idr context_idr;
519 struct intel_rps_client {
520 struct list_head link;
524 unsigned int bsd_engine;
526 /* Client can have a maximum of 3 contexts banned before
527 * it is denied of creating new contexts. As one context
528 * ban needs 4 consecutive hangs, and more if there is
529 * progress in between, this is a last resort stop gap measure
530 * to limit the badly behaving clients access to gpu.
532 #define I915_MAX_CLIENT_CONTEXT_BANS 3
536 /* Used by dp and fdi links */
537 struct intel_link_m_n {
545 void intel_link_compute_m_n(int bpp, int nlanes,
546 int pixel_clock, int link_clock,
547 struct intel_link_m_n *m_n);
549 /* Interface history:
552 * 1.2: Add Power Management
553 * 1.3: Add vblank support
554 * 1.4: Fix cmdbuffer path, add heap destroy
555 * 1.5: Add vblank pipe configuration
556 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
557 * - Support vertical blank on secondary display pipe
559 #define DRIVER_MAJOR 1
560 #define DRIVER_MINOR 6
561 #define DRIVER_PATCHLEVEL 0
563 struct opregion_header;
564 struct opregion_acpi;
565 struct opregion_swsci;
566 struct opregion_asle;
568 struct intel_opregion {
569 struct opregion_header *header;
570 struct opregion_acpi *acpi;
571 struct opregion_swsci *swsci;
572 u32 swsci_gbda_sub_functions;
573 u32 swsci_sbcb_sub_functions;
574 struct opregion_asle *asle;
579 struct work_struct asle_work;
581 #define OPREGION_SIZE (8*1024)
583 struct intel_overlay;
584 struct intel_overlay_error_state;
586 struct sdvo_device_mapping {
595 struct intel_connector;
596 struct intel_encoder;
597 struct intel_atomic_state;
598 struct intel_crtc_state;
599 struct intel_initial_plane_config;
604 struct drm_i915_display_funcs {
605 int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
606 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
607 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
608 int (*compute_intermediate_wm)(struct drm_device *dev,
609 struct intel_crtc *intel_crtc,
610 struct intel_crtc_state *newstate);
611 void (*initial_watermarks)(struct intel_atomic_state *state,
612 struct intel_crtc_state *cstate);
613 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
614 struct intel_crtc_state *cstate);
615 void (*optimize_watermarks)(struct intel_atomic_state *state,
616 struct intel_crtc_state *cstate);
617 int (*compute_global_watermarks)(struct drm_atomic_state *state);
618 void (*update_wm)(struct intel_crtc *crtc);
619 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
620 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
621 /* Returns the active state of the crtc, and if the crtc is active,
622 * fills out the pipe-config with the hw state. */
623 bool (*get_pipe_config)(struct intel_crtc *,
624 struct intel_crtc_state *);
625 void (*get_initial_plane_config)(struct intel_crtc *,
626 struct intel_initial_plane_config *);
627 int (*crtc_compute_clock)(struct intel_crtc *crtc,
628 struct intel_crtc_state *crtc_state);
629 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
630 struct drm_atomic_state *old_state);
631 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
632 struct drm_atomic_state *old_state);
633 void (*update_crtcs)(struct drm_atomic_state *state,
634 unsigned int *crtc_vblank_mask);
635 void (*audio_codec_enable)(struct drm_connector *connector,
636 struct intel_encoder *encoder,
637 const struct drm_display_mode *adjusted_mode);
638 void (*audio_codec_disable)(struct intel_encoder *encoder);
639 void (*fdi_link_train)(struct drm_crtc *crtc);
640 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
641 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
642 struct drm_framebuffer *fb,
643 struct drm_i915_gem_object *obj,
644 struct drm_i915_gem_request *req,
646 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
647 /* clock updates for mode set */
649 /* render clock increase/decrease */
650 /* display clock increase/decrease */
651 /* pll clock increase/decrease */
653 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
654 void (*load_luts)(struct drm_crtc_state *crtc_state);
657 enum forcewake_domain_id {
658 FW_DOMAIN_ID_RENDER = 0,
659 FW_DOMAIN_ID_BLITTER,
665 enum forcewake_domains {
666 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
667 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
668 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
669 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
674 #define FW_REG_READ (1)
675 #define FW_REG_WRITE (2)
677 enum decoupled_power_domain {
678 GEN9_DECOUPLED_PD_BLITTER = 0,
679 GEN9_DECOUPLED_PD_RENDER,
680 GEN9_DECOUPLED_PD_MEDIA,
681 GEN9_DECOUPLED_PD_ALL
685 GEN9_DECOUPLED_OP_WRITE = 0,
686 GEN9_DECOUPLED_OP_READ
689 enum forcewake_domains
690 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
691 i915_reg_t reg, unsigned int op);
693 struct intel_uncore_funcs {
694 void (*force_wake_get)(struct drm_i915_private *dev_priv,
695 enum forcewake_domains domains);
696 void (*force_wake_put)(struct drm_i915_private *dev_priv,
697 enum forcewake_domains domains);
699 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
700 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
701 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
702 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
704 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
705 uint8_t val, bool trace);
706 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
707 uint16_t val, bool trace);
708 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
709 uint32_t val, bool trace);
712 struct intel_forcewake_range {
716 enum forcewake_domains domains;
719 struct intel_uncore {
720 spinlock_t lock; /** lock is also taken in irq contexts. */
722 const struct intel_forcewake_range *fw_domains_table;
723 unsigned int fw_domains_table_entries;
725 struct notifier_block pmic_bus_access_nb;
726 struct intel_uncore_funcs funcs;
730 enum forcewake_domains fw_domains;
731 enum forcewake_domains fw_domains_active;
733 struct intel_uncore_forcewake_domain {
734 struct drm_i915_private *i915;
735 enum forcewake_domain_id id;
736 enum forcewake_domains mask;
738 struct hrtimer timer;
745 } fw_domain[FW_DOMAIN_ID_COUNT];
747 int unclaimed_mmio_check;
750 /* Iterate over initialised fw domains */
751 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
752 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
753 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
755 for_each_if ((mask__) & (domain__)->mask)
757 #define for_each_fw_domain(domain__, dev_priv__) \
758 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
760 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
761 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
762 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
765 struct work_struct work;
767 uint32_t *dmc_payload;
768 uint32_t dmc_fw_size;
771 i915_reg_t mmioaddr[8];
772 uint32_t mmiodata[8];
774 uint32_t allowed_dc_mask;
777 #define DEV_INFO_FOR_EACH_FLAG(func) \
780 func(is_alpha_support); \
781 /* Keep has_* in alphabetical order */ \
782 func(has_64bit_reloc); \
783 func(has_aliasing_ppgtt); \
786 func(has_decoupled_mmio); \
789 func(has_fpga_dbg); \
790 func(has_full_ppgtt); \
791 func(has_full_48bit_ppgtt); \
792 func(has_gmbus_irq); \
793 func(has_gmch_display); \
796 func(has_hw_contexts); \
799 func(has_logical_ring_contexts); \
801 func(has_pipe_cxsr); \
802 func(has_pooled_eu); \
806 func(has_resource_streamer); \
807 func(has_runtime_pm); \
809 func(cursor_needs_physical); \
810 func(hws_needs_physical); \
811 func(overlay_needs_physical); \
814 struct sseu_dev_info {
820 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
823 u8 has_subslice_pg:1;
827 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
829 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
832 /* Keep in gen based order, and chronological order within a gen */
833 enum intel_platform {
834 INTEL_PLATFORM_UNINITIALIZED = 0,
862 struct intel_device_info {
863 u32 display_mmio_offset;
866 u8 num_sprites[I915_MAX_PIPES];
867 u8 num_scalers[I915_MAX_PIPES];
870 enum intel_platform platform;
871 u8 ring_mask; /* Rings supported by the HW */
873 #define DEFINE_FLAG(name) u8 name:1
874 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
876 u16 ddb_size; /* in blocks */
877 /* Register offsets for the various display pipes and transcoders */
878 int pipe_offsets[I915_MAX_TRANSCODERS];
879 int trans_offsets[I915_MAX_TRANSCODERS];
880 int palette_offsets[I915_MAX_PIPES];
881 int cursor_offsets[I915_MAX_PIPES];
883 /* Slice/subslice/EU info */
884 struct sseu_dev_info sseu;
887 u16 degamma_lut_size;
892 struct intel_display_error_state;
894 struct drm_i915_error_state {
897 struct timeval boottime;
898 struct timeval uptime;
900 struct drm_i915_private *i915;
907 struct intel_device_info device_info;
909 /* Generic register state */
917 u32 error; /* gen6+ */
918 u32 err_int; /* gen7 */
919 u32 fault_data0; /* gen8, gen9 */
920 u32 fault_data1; /* gen8, gen9 */
927 u64 fence[I915_MAX_NUM_FENCES];
928 struct intel_overlay_error_state *overlay;
929 struct intel_display_error_state *display;
930 struct drm_i915_error_object *semaphore;
931 struct drm_i915_error_object *guc_log;
933 struct drm_i915_error_engine {
935 /* Software tracked state */
938 unsigned long hangcheck_timestamp;
939 bool hangcheck_stalled;
940 enum intel_engine_hangcheck_action hangcheck_action;
941 struct i915_address_space *vm;
944 /* position of active request inside the ring */
945 u32 rq_head, rq_post, rq_tail;
947 /* our own tracking of ring head and tail */
970 u32 rc_psmi; /* sleep state */
971 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
972 struct intel_instdone instdone;
974 struct drm_i915_error_object {
980 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
982 struct drm_i915_error_object *wa_ctx;
984 struct drm_i915_error_request {
992 } *requests, execlist[2];
994 struct drm_i915_error_waiter {
995 char comm[TASK_COMM_LEN];
1009 char comm[TASK_COMM_LEN];
1011 } engine[I915_NUM_ENGINES];
1013 struct drm_i915_error_buffer {
1016 u32 rseqno[I915_NUM_ENGINES], wseqno;
1020 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1027 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1028 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1029 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1032 enum i915_cache_level {
1033 I915_CACHE_NONE = 0,
1034 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1035 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1036 caches, eg sampler/render caches, and the
1037 large Last-Level-Cache. LLC is coherent with
1038 the CPU, but L3 is only visible to the GPU. */
1039 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1042 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1053 /* This is always the inner lock when overlapping with struct_mutex and
1054 * it's the outer lock when overlapping with stolen_lock. */
1057 unsigned int possible_framebuffer_bits;
1058 unsigned int busy_bits;
1059 unsigned int visible_pipes_mask;
1060 struct intel_crtc *crtc;
1062 struct drm_mm_node compressed_fb;
1063 struct drm_mm_node *compressed_llb;
1070 bool underrun_detected;
1071 struct work_struct underrun_work;
1073 struct intel_fbc_state_cache {
1074 struct i915_vma *vma;
1077 unsigned int mode_flags;
1078 uint32_t hsw_bdw_pixel_rate;
1082 unsigned int rotation;
1089 const struct drm_format_info *format;
1090 unsigned int stride;
1094 struct intel_fbc_reg_params {
1095 struct i915_vma *vma;
1100 unsigned int fence_y_offset;
1104 const struct drm_format_info *format;
1105 unsigned int stride;
1111 struct intel_fbc_work {
1113 u32 scheduled_vblank;
1114 struct work_struct work;
1117 const char *no_fbc_reason;
1121 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1122 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1123 * parsing for same resolution.
1125 enum drrs_refresh_rate_type {
1128 DRRS_MAX_RR, /* RR count */
1131 enum drrs_support_type {
1132 DRRS_NOT_SUPPORTED = 0,
1133 STATIC_DRRS_SUPPORT = 1,
1134 SEAMLESS_DRRS_SUPPORT = 2
1140 struct delayed_work work;
1141 struct intel_dp *dp;
1142 unsigned busy_frontbuffer_bits;
1143 enum drrs_refresh_rate_type refresh_rate_type;
1144 enum drrs_support_type type;
1151 struct intel_dp *enabled;
1153 struct delayed_work work;
1154 unsigned busy_frontbuffer_bits;
1156 bool aux_frame_sync;
1158 bool y_cord_support;
1159 bool colorimetry_support;
1164 PCH_NONE = 0, /* No PCH present */
1165 PCH_IBX, /* Ibexpeak PCH */
1166 PCH_CPT, /* Cougarpoint PCH */
1167 PCH_LPT, /* Lynxpoint PCH */
1168 PCH_SPT, /* Sunrisepoint PCH */
1169 PCH_KBP, /* Kabypoint PCH */
1173 enum intel_sbi_destination {
1178 #define QUIRK_PIPEA_FORCE (1<<0)
1179 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1180 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1181 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1182 #define QUIRK_PIPEB_FORCE (1<<4)
1183 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1186 struct intel_fbc_work;
1188 struct intel_gmbus {
1189 struct i2c_adapter adapter;
1190 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1193 i915_reg_t gpio_reg;
1194 struct i2c_algo_bit_data bit_algo;
1195 struct drm_i915_private *dev_priv;
1198 struct i915_suspend_saved_registers {
1200 u32 saveFBC_CONTROL;
1201 u32 saveCACHE_MODE_0;
1202 u32 saveMI_ARB_STATE;
1206 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1207 u32 savePCH_PORT_HOTPLUG;
1211 struct vlv_s0ix_state {
1218 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1219 u32 media_max_req_count;
1220 u32 gfx_max_req_count;
1246 u32 rp_down_timeout;
1252 /* Display 1 CZ domain */
1257 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1259 /* GT SA CZ domain */
1266 /* Display 2 CZ domain */
1270 u32 clock_gate_dis2;
1273 struct intel_rps_ei {
1279 struct intel_gen6_power_mgmt {
1281 * work, interrupts_enabled and pm_iir are protected by
1282 * dev_priv->irq_lock
1284 struct work_struct work;
1285 bool interrupts_enabled;
1288 /* PM interrupt bits that should never be masked */
1291 /* Frequencies are stored in potentially platform dependent multiples.
1292 * In other words, *_freq needs to be multiplied by X to be interesting.
1293 * Soft limits are those which are used for the dynamic reclocking done
1294 * by the driver (raise frequencies under heavy loads, and lower for
1295 * lighter loads). Hard limits are those imposed by the hardware.
1297 * A distinction is made for overclocking, which is never enabled by
1298 * default, and is considered to be above the hard limit if it's
1301 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1302 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1303 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1304 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1305 u8 min_freq; /* AKA RPn. Minimum frequency */
1306 u8 boost_freq; /* Frequency to request when wait boosting */
1307 u8 idle_freq; /* Frequency to request when we are idle */
1308 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1309 u8 rp1_freq; /* "less than" RP0 power/freqency */
1310 u8 rp0_freq; /* Non-overclocked max frequency. */
1311 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1313 u8 up_threshold; /* Current %busy required to uplock */
1314 u8 down_threshold; /* Current %busy required to downclock */
1317 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1319 spinlock_t client_lock;
1320 struct list_head clients;
1324 struct delayed_work autoenable_work;
1327 /* manual wa residency calculations */
1328 struct intel_rps_ei up_ei, down_ei;
1331 * Protects RPS/RC6 register access and PCU communication.
1332 * Must be taken after struct_mutex if nested. Note that
1333 * this lock may be held for long periods of time when
1334 * talking to hw - so only take it when talking to hw!
1336 struct mutex hw_lock;
1339 /* defined intel_pm.c */
1340 extern spinlock_t mchdev_lock;
1342 struct intel_ilk_power_mgmt {
1350 unsigned long last_time1;
1351 unsigned long chipset_power;
1354 unsigned long gfx_power;
1361 struct drm_i915_private;
1362 struct i915_power_well;
1364 struct i915_power_well_ops {
1366 * Synchronize the well's hw state to match the current sw state, for
1367 * example enable/disable it based on the current refcount. Called
1368 * during driver init and resume time, possibly after first calling
1369 * the enable/disable handlers.
1371 void (*sync_hw)(struct drm_i915_private *dev_priv,
1372 struct i915_power_well *power_well);
1374 * Enable the well and resources that depend on it (for example
1375 * interrupts located on the well). Called after the 0->1 refcount
1378 void (*enable)(struct drm_i915_private *dev_priv,
1379 struct i915_power_well *power_well);
1381 * Disable the well and resources that depend on it. Called after
1382 * the 1->0 refcount transition.
1384 void (*disable)(struct drm_i915_private *dev_priv,
1385 struct i915_power_well *power_well);
1386 /* Returns the hw enabled state. */
1387 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1388 struct i915_power_well *power_well);
1391 /* Power well structure for haswell */
1392 struct i915_power_well {
1395 /* power well enable/disable usage count */
1397 /* cached hw enabled state */
1399 unsigned long domains;
1400 /* unique identifier for this power well */
1403 * Arbitraty data associated with this power well. Platform and power
1407 const struct i915_power_well_ops *ops;
1410 struct i915_power_domains {
1412 * Power wells needed for initialization at driver init and suspend
1413 * time are on. They are kept on until after the first modeset.
1417 int power_well_count;
1420 int domain_use_count[POWER_DOMAIN_NUM];
1421 struct i915_power_well *power_wells;
1424 #define MAX_L3_SLICES 2
1425 struct intel_l3_parity {
1426 u32 *remap_info[MAX_L3_SLICES];
1427 struct work_struct error_work;
1431 struct i915_gem_mm {
1432 /** Memory allocator for GTT stolen memory */
1433 struct drm_mm stolen;
1434 /** Protects the usage of the GTT stolen memory allocator. This is
1435 * always the inner lock when overlapping with struct_mutex. */
1436 struct mutex stolen_lock;
1438 /** List of all objects in gtt_space. Used to restore gtt
1439 * mappings on resume */
1440 struct list_head bound_list;
1442 * List of objects which are not bound to the GTT (thus
1443 * are idle and not used by the GPU). These objects may or may
1444 * not actually have any pages attached.
1446 struct list_head unbound_list;
1448 /** List of all objects in gtt_space, currently mmaped by userspace.
1449 * All objects within this list must also be on bound_list.
1451 struct list_head userfault_list;
1454 * List of objects which are pending destruction.
1456 struct llist_head free_list;
1457 struct work_struct free_work;
1459 /** Usable portion of the GTT for GEM */
1460 phys_addr_t stolen_base; /* limited to low memory (32-bit) */
1462 /** PPGTT used for aliasing the PPGTT with the GTT */
1463 struct i915_hw_ppgtt *aliasing_ppgtt;
1465 struct notifier_block oom_notifier;
1466 struct notifier_block vmap_notifier;
1467 struct shrinker shrinker;
1469 /** LRU list of objects with fence regs on them. */
1470 struct list_head fence_list;
1473 * Are we in a non-interruptible section of code like
1478 /* the indicator for dispatch video commands on two BSD rings */
1479 atomic_t bsd_engine_dispatch_index;
1481 /** Bit 6 swizzling required for X tiling */
1482 uint32_t bit_6_swizzle_x;
1483 /** Bit 6 swizzling required for Y tiling */
1484 uint32_t bit_6_swizzle_y;
1486 /* accounting, useful for userland debugging */
1487 spinlock_t object_stat_lock;
1492 struct drm_i915_error_state_buf {
1493 struct drm_i915_private *i915;
1502 struct i915_error_state_file_priv {
1503 struct drm_i915_private *i915;
1504 struct drm_i915_error_state *error;
1507 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1508 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1510 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1511 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1513 struct i915_gpu_error {
1514 /* For hangcheck timer */
1515 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1516 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1518 struct delayed_work hangcheck_work;
1520 /* For reset and error_state handling. */
1522 /* Protected by the above dev->gpu_error.lock. */
1523 struct drm_i915_error_state *first_error;
1525 unsigned long missed_irq_rings;
1528 * State variable controlling the reset flow and count
1530 * This is a counter which gets incremented when reset is triggered,
1532 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1533 * meaning that any waiters holding onto the struct_mutex should
1534 * relinquish the lock immediately in order for the reset to start.
1536 * If reset is not completed succesfully, the I915_WEDGE bit is
1537 * set meaning that hardware is terminally sour and there is no
1538 * recovery. All waiters on the reset_queue will be woken when
1541 * This counter is used by the wait_seqno code to notice that reset
1542 * event happened and it needs to restart the entire ioctl (since most
1543 * likely the seqno it waited for won't ever signal anytime soon).
1545 * This is important for lock-free wait paths, where no contended lock
1546 * naturally enforces the correct ordering between the bail-out of the
1547 * waiter and the gpu reset work code.
1549 unsigned long reset_count;
1551 unsigned long flags;
1552 #define I915_RESET_IN_PROGRESS 0
1553 #define I915_WEDGED (BITS_PER_LONG - 1)
1556 * Waitqueue to signal when a hang is detected. Used to for waiters
1557 * to release the struct_mutex for the reset to procede.
1559 wait_queue_head_t wait_queue;
1562 * Waitqueue to signal when the reset has completed. Used by clients
1563 * that wait for dev_priv->mm.wedged to settle.
1565 wait_queue_head_t reset_queue;
1567 /* For missed irq/seqno simulation. */
1568 unsigned long test_irq_rings;
1571 enum modeset_restore {
1572 MODESET_ON_LID_OPEN,
1577 #define DP_AUX_A 0x40
1578 #define DP_AUX_B 0x10
1579 #define DP_AUX_C 0x20
1580 #define DP_AUX_D 0x30
1582 #define DDC_PIN_B 0x05
1583 #define DDC_PIN_C 0x04
1584 #define DDC_PIN_D 0x06
1586 struct ddi_vbt_port_info {
1588 * This is an index in the HDMI/DVI DDI buffer translation table.
1589 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1590 * populate this field.
1592 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1593 uint8_t hdmi_level_shift;
1595 uint8_t supports_dvi:1;
1596 uint8_t supports_hdmi:1;
1597 uint8_t supports_dp:1;
1598 uint8_t supports_edp:1;
1600 uint8_t alternate_aux_channel;
1601 uint8_t alternate_ddc_pin;
1603 uint8_t dp_boost_level;
1604 uint8_t hdmi_boost_level;
1607 enum psr_lines_to_wait {
1608 PSR_0_LINES_TO_WAIT = 0,
1610 PSR_4_LINES_TO_WAIT,
1614 struct intel_vbt_data {
1615 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1616 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1619 unsigned int int_tv_support:1;
1620 unsigned int lvds_dither:1;
1621 unsigned int lvds_vbt:1;
1622 unsigned int int_crt_support:1;
1623 unsigned int lvds_use_ssc:1;
1624 unsigned int display_clock_mode:1;
1625 unsigned int fdi_rx_polarity_inverted:1;
1626 unsigned int panel_type:4;
1628 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1630 enum drrs_support_type drrs_type;
1641 struct edp_power_seq pps;
1646 bool require_aux_wakeup;
1648 enum psr_lines_to_wait lines_to_wait;
1649 int tp1_wakeup_time;
1650 int tp2_tp3_wakeup_time;
1656 bool active_low_pwm;
1657 u8 min_brightness; /* min_brightness/255 of max */
1658 u8 controller; /* brightness controller number */
1659 enum intel_backlight_type type;
1665 struct mipi_config *config;
1666 struct mipi_pps_data *pps;
1670 const u8 *sequence[MIPI_SEQ_MAX];
1676 union child_device_config *child_dev;
1678 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1679 struct sdvo_device_mapping sdvo_mappings[2];
1682 enum intel_ddb_partitioning {
1684 INTEL_DDB_PART_5_6, /* IVB+ */
1687 struct intel_wm_level {
1695 struct ilk_wm_values {
1696 uint32_t wm_pipe[3];
1698 uint32_t wm_lp_spr[3];
1699 uint32_t wm_linetime[3];
1701 enum intel_ddb_partitioning partitioning;
1704 struct vlv_pipe_wm {
1705 uint16_t plane[I915_MAX_PLANES];
1713 struct vlv_wm_ddl_values {
1714 uint8_t plane[I915_MAX_PLANES];
1717 struct vlv_wm_values {
1718 struct vlv_pipe_wm pipe[3];
1719 struct vlv_sr_wm sr;
1720 struct vlv_wm_ddl_values ddl[3];
1725 struct skl_ddb_entry {
1726 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1729 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1731 return entry->end - entry->start;
1734 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1735 const struct skl_ddb_entry *e2)
1737 if (e1->start == e2->start && e1->end == e2->end)
1743 struct skl_ddb_allocation {
1744 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1745 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1748 struct skl_wm_values {
1749 unsigned dirty_pipes;
1750 struct skl_ddb_allocation ddb;
1753 struct skl_wm_level {
1755 uint16_t plane_res_b;
1756 uint8_t plane_res_l;
1760 * This struct helps tracking the state needed for runtime PM, which puts the
1761 * device in PCI D3 state. Notice that when this happens, nothing on the
1762 * graphics device works, even register access, so we don't get interrupts nor
1765 * Every piece of our code that needs to actually touch the hardware needs to
1766 * either call intel_runtime_pm_get or call intel_display_power_get with the
1767 * appropriate power domain.
1769 * Our driver uses the autosuspend delay feature, which means we'll only really
1770 * suspend if we stay with zero refcount for a certain amount of time. The
1771 * default value is currently very conservative (see intel_runtime_pm_enable), but
1772 * it can be changed with the standard runtime PM files from sysfs.
1774 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1775 * goes back to false exactly before we reenable the IRQs. We use this variable
1776 * to check if someone is trying to enable/disable IRQs while they're supposed
1777 * to be disabled. This shouldn't happen and we'll print some error messages in
1780 * For more, read the Documentation/power/runtime_pm.txt.
1782 struct i915_runtime_pm {
1783 atomic_t wakeref_count;
1788 enum intel_pipe_crc_source {
1789 INTEL_PIPE_CRC_SOURCE_NONE,
1790 INTEL_PIPE_CRC_SOURCE_PLANE1,
1791 INTEL_PIPE_CRC_SOURCE_PLANE2,
1792 INTEL_PIPE_CRC_SOURCE_PF,
1793 INTEL_PIPE_CRC_SOURCE_PIPE,
1794 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1795 INTEL_PIPE_CRC_SOURCE_TV,
1796 INTEL_PIPE_CRC_SOURCE_DP_B,
1797 INTEL_PIPE_CRC_SOURCE_DP_C,
1798 INTEL_PIPE_CRC_SOURCE_DP_D,
1799 INTEL_PIPE_CRC_SOURCE_AUTO,
1800 INTEL_PIPE_CRC_SOURCE_MAX,
1803 struct intel_pipe_crc_entry {
1808 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1809 struct intel_pipe_crc {
1811 bool opened; /* exclusive access to the result file */
1812 struct intel_pipe_crc_entry *entries;
1813 enum intel_pipe_crc_source source;
1815 wait_queue_head_t wq;
1819 struct i915_frontbuffer_tracking {
1823 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1830 struct i915_wa_reg {
1833 /* bitmask representing WA bits */
1838 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1839 * allowing it for RCS as we don't foresee any requirement of having
1840 * a whitelist for other engines. When it is really required for
1841 * other engines then the limit need to be increased.
1843 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1845 struct i915_workarounds {
1846 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1848 u32 hw_whitelist_count[I915_NUM_ENGINES];
1851 struct i915_virtual_gpu {
1855 /* used in computing the new watermarks state */
1856 struct intel_wm_config {
1857 unsigned int num_pipes_active;
1858 bool sprites_enabled;
1859 bool sprites_scaled;
1862 struct i915_oa_format {
1867 struct i915_oa_reg {
1872 struct i915_perf_stream;
1875 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1877 struct i915_perf_stream_ops {
1879 * @enable: Enables the collection of HW samples, either in response to
1880 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1881 * without `I915_PERF_FLAG_DISABLED`.
1883 void (*enable)(struct i915_perf_stream *stream);
1886 * @disable: Disables the collection of HW samples, either in response
1887 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1890 void (*disable)(struct i915_perf_stream *stream);
1893 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1894 * once there is something ready to read() for the stream
1896 void (*poll_wait)(struct i915_perf_stream *stream,
1901 * @wait_unlocked: For handling a blocking read, wait until there is
1902 * something to ready to read() for the stream. E.g. wait on the same
1903 * wait queue that would be passed to poll_wait().
1905 int (*wait_unlocked)(struct i915_perf_stream *stream);
1908 * @read: Copy buffered metrics as records to userspace
1909 * **buf**: the userspace, destination buffer
1910 * **count**: the number of bytes to copy, requested by userspace
1911 * **offset**: zero at the start of the read, updated as the read
1912 * proceeds, it represents how many bytes have been copied so far and
1913 * the buffer offset for copying the next record.
1915 * Copy as many buffered i915 perf samples and records for this stream
1916 * to userspace as will fit in the given buffer.
1918 * Only write complete records; returning -%ENOSPC if there isn't room
1919 * for a complete record.
1921 * Return any error condition that results in a short read such as
1922 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1923 * returning to userspace.
1925 int (*read)(struct i915_perf_stream *stream,
1931 * @destroy: Cleanup any stream specific resources.
1933 * The stream will always be disabled before this is called.
1935 void (*destroy)(struct i915_perf_stream *stream);
1939 * struct i915_perf_stream - state for a single open stream FD
1941 struct i915_perf_stream {
1943 * @dev_priv: i915 drm device
1945 struct drm_i915_private *dev_priv;
1948 * @link: Links the stream into ``&drm_i915_private->streams``
1950 struct list_head link;
1953 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1954 * properties given when opening a stream, representing the contents
1955 * of a single sample as read() by userspace.
1960 * @sample_size: Considering the configured contents of a sample
1961 * combined with the required header size, this is the total size
1962 * of a single sample record.
1967 * @ctx: %NULL if measuring system-wide across all contexts or a
1968 * specific context that is being monitored.
1970 struct i915_gem_context *ctx;
1973 * @enabled: Whether the stream is currently enabled, considering
1974 * whether the stream was opened in a disabled state and based
1975 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1980 * @ops: The callbacks providing the implementation of this specific
1981 * type of configured stream.
1983 const struct i915_perf_stream_ops *ops;
1987 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1989 struct i915_oa_ops {
1991 * @init_oa_buffer: Resets the head and tail pointers of the
1992 * circular buffer for periodic OA reports.
1994 * Called when first opening a stream for OA metrics, but also may be
1995 * called in response to an OA buffer overflow or other error
1998 * Note it may be necessary to clear the full OA buffer here as part of
1999 * maintaining the invariable that new reports must be written to
2000 * zeroed memory for us to be able to reliable detect if an expected
2001 * report has not yet landed in memory. (At least on Haswell the OA
2002 * buffer tail pointer is not synchronized with reports being visible
2005 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2008 * @enable_metric_set: Applies any MUX configuration to set up the
2009 * Boolean and Custom (B/C) counters that are part of the counter
2010 * reports being sampled. May apply system constraints such as
2011 * disabling EU clock gating as required.
2013 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2016 * @disable_metric_set: Remove system constraints associated with using
2019 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2022 * @oa_enable: Enable periodic sampling
2024 void (*oa_enable)(struct drm_i915_private *dev_priv);
2027 * @oa_disable: Disable periodic sampling
2029 void (*oa_disable)(struct drm_i915_private *dev_priv);
2032 * @read: Copy data from the circular OA buffer into a given userspace
2035 int (*read)(struct i915_perf_stream *stream,
2041 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2043 * This is either called via fops or the poll check hrtimer (atomic
2044 * ctx) without any locks taken.
2046 * It's safe to read OA config state here unlocked, assuming that this
2047 * is only called while the stream is enabled, while the global OA
2048 * configuration can't be modified.
2050 * Efficiency is more important than avoiding some false positives
2051 * here, which will be handled gracefully - likely resulting in an
2052 * %EAGAIN error for userspace.
2054 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2057 struct drm_i915_private {
2058 struct drm_device drm;
2060 struct kmem_cache *objects;
2061 struct kmem_cache *vmas;
2062 struct kmem_cache *requests;
2063 struct kmem_cache *dependencies;
2065 const struct intel_device_info info;
2067 int relative_constants_mode;
2071 struct intel_uncore uncore;
2073 struct i915_virtual_gpu vgpu;
2075 struct intel_gvt *gvt;
2077 struct intel_huc huc;
2078 struct intel_guc guc;
2080 struct intel_csr csr;
2082 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2084 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2085 * controller on different i2c buses. */
2086 struct mutex gmbus_mutex;
2089 * Base address of the gmbus and gpio block.
2091 uint32_t gpio_mmio_base;
2093 /* MMIO base address for MIPI regs */
2094 uint32_t mipi_mmio_base;
2096 uint32_t psr_mmio_base;
2098 uint32_t pps_mmio_base;
2100 wait_queue_head_t gmbus_wait_queue;
2102 struct pci_dev *bridge_dev;
2103 struct i915_gem_context *kernel_context;
2104 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2105 struct i915_vma *semaphore;
2107 struct drm_dma_handle *status_page_dmah;
2108 struct resource mch_res;
2110 /* protects the irq masks */
2111 spinlock_t irq_lock;
2113 /* protects the mmio flip data */
2114 spinlock_t mmio_flip_lock;
2116 bool display_irqs_enabled;
2118 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2119 struct pm_qos_request pm_qos;
2121 /* Sideband mailbox protection */
2122 struct mutex sb_lock;
2124 /** Cached value of IMR to avoid reads in updating the bitfield */
2127 u32 de_irq_mask[I915_MAX_PIPES];
2134 u32 pipestat_irq_mask[I915_MAX_PIPES];
2136 struct i915_hotplug hotplug;
2137 struct intel_fbc fbc;
2138 struct i915_drrs drrs;
2139 struct intel_opregion opregion;
2140 struct intel_vbt_data vbt;
2142 bool preserve_bios_swizzle;
2145 struct intel_overlay *overlay;
2147 /* backlight registers and fields in struct intel_panel */
2148 struct mutex backlight_lock;
2151 bool no_aux_handshake;
2153 /* protects panel power sequencer state */
2154 struct mutex pps_mutex;
2156 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2157 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2159 unsigned int fsb_freq, mem_freq, is_ddr3;
2160 unsigned int skl_preferred_vco_freq;
2161 unsigned int cdclk_freq, max_cdclk_freq;
2164 * For reading holding any crtc lock is sufficient,
2165 * for writing must hold all of them.
2167 unsigned int atomic_cdclk_freq;
2169 unsigned int max_dotclk_freq;
2170 unsigned int rawclk_freq;
2171 unsigned int hpll_freq;
2172 unsigned int czclk_freq;
2175 unsigned int vco, ref;
2179 * wq - Driver workqueue for GEM.
2181 * NOTE: Work items scheduled here are not allowed to grab any modeset
2182 * locks, for otherwise the flushing done in the pageflip code will
2183 * result in deadlocks.
2185 struct workqueue_struct *wq;
2187 /* Display functions */
2188 struct drm_i915_display_funcs display;
2190 /* PCH chipset type */
2191 enum intel_pch pch_type;
2192 unsigned short pch_id;
2194 unsigned long quirks;
2196 enum modeset_restore modeset_restore;
2197 struct mutex modeset_restore_lock;
2198 struct drm_atomic_state *modeset_restore_state;
2199 struct drm_modeset_acquire_ctx reset_ctx;
2201 struct list_head vm_list; /* Global list of all address spaces */
2202 struct i915_ggtt ggtt; /* VM representing the global address space */
2204 struct i915_gem_mm mm;
2205 DECLARE_HASHTABLE(mm_structs, 7);
2206 struct mutex mm_lock;
2208 /* The hw wants to have a stable context identifier for the lifetime
2209 * of the context (for OA, PASID, faults, etc). This is limited
2210 * in execlists to 21 bits.
2212 struct ida context_hw_ida;
2213 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2215 /* Kernel Modesetting */
2217 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2218 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2219 wait_queue_head_t pending_flip_queue;
2221 #ifdef CONFIG_DEBUG_FS
2222 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2225 /* dpll and cdclk state is protected by connection_mutex */
2226 int num_shared_dpll;
2227 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2228 const struct intel_dpll_mgr *dpll_mgr;
2231 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2232 * Must be global rather than per dpll, because on some platforms
2233 * plls share registers.
2235 struct mutex dpll_lock;
2237 unsigned int active_crtcs;
2238 unsigned int min_pixclk[I915_MAX_PIPES];
2240 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2242 struct i915_workarounds workarounds;
2244 struct i915_frontbuffer_tracking fb_tracking;
2246 struct intel_atomic_helper {
2247 struct llist_head free_list;
2248 struct work_struct free_work;
2253 bool mchbar_need_disable;
2255 struct intel_l3_parity l3_parity;
2257 /* Cannot be determined by PCIID. You must always read a register. */
2260 /* gen6+ rps state */
2261 struct intel_gen6_power_mgmt rps;
2263 /* ilk-only ips/rps state. Everything in here is protected by the global
2264 * mchdev_lock in intel_pm.c */
2265 struct intel_ilk_power_mgmt ips;
2267 struct i915_power_domains power_domains;
2269 struct i915_psr psr;
2271 struct i915_gpu_error gpu_error;
2273 struct drm_i915_gem_object *vlv_pctx;
2275 #ifdef CONFIG_DRM_FBDEV_EMULATION
2276 /* list of fbdev register on this device */
2277 struct intel_fbdev *fbdev;
2278 struct work_struct fbdev_suspend_work;
2281 struct drm_property *broadcast_rgb_property;
2282 struct drm_property *force_audio_property;
2284 /* hda/i915 audio component */
2285 struct i915_audio_component *audio_component;
2286 bool audio_component_registered;
2288 * av_mutex - mutex for audio/video sync
2291 struct mutex av_mutex;
2293 uint32_t hw_context_size;
2294 struct list_head context_list;
2298 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2299 u32 chv_phy_control;
2301 * Shadows for CHV DPLL_MD regs to keep the state
2302 * checker somewhat working in the presence hardware
2303 * crappiness (can't read out DPLL_MD for pipes B & C).
2305 u32 chv_dpll_md[I915_MAX_PIPES];
2309 bool suspended_to_idle;
2310 struct i915_suspend_saved_registers regfile;
2311 struct vlv_s0ix_state vlv_s0ix_state;
2314 I915_SAGV_UNKNOWN = 0,
2317 I915_SAGV_NOT_CONTROLLED
2321 /* protects DSPARB registers on pre-g4x/vlv/chv */
2322 spinlock_t dsparb_lock;
2325 * Raw watermark latency values:
2326 * in 0.1us units for WM0,
2327 * in 0.5us units for WM1+.
2330 uint16_t pri_latency[5];
2332 uint16_t spr_latency[5];
2334 uint16_t cur_latency[5];
2336 * Raw watermark memory latency values
2337 * for SKL for all 8 levels
2340 uint16_t skl_latency[8];
2342 /* current hardware state */
2344 struct ilk_wm_values hw;
2345 struct skl_wm_values skl_hw;
2346 struct vlv_wm_values vlv;
2352 * Should be held around atomic WM register writing; also
2353 * protects * intel_crtc->wm.active and
2354 * cstate->wm.need_postvbl_update.
2356 struct mutex wm_mutex;
2359 * Set during HW readout of watermarks/DDB. Some platforms
2360 * need to know when we're still using BIOS-provided values
2361 * (which we don't fully trust).
2363 bool distrust_bios_wm;
2366 struct i915_runtime_pm pm;
2371 struct kobject *metrics_kobj;
2372 struct ctl_table_header *sysctl_header;
2375 struct list_head streams;
2377 spinlock_t hook_lock;
2380 struct i915_perf_stream *exclusive_stream;
2382 u32 specific_ctx_id;
2384 struct hrtimer poll_check_timer;
2385 wait_queue_head_t poll_wq;
2389 int period_exponent;
2390 int timestamp_frequency;
2396 const struct i915_oa_reg *mux_regs;
2398 const struct i915_oa_reg *b_counter_regs;
2399 int b_counter_regs_len;
2402 struct i915_vma *vma;
2408 u32 gen7_latched_oastatus1;
2410 struct i915_oa_ops ops;
2411 const struct i915_oa_format *oa_formats;
2416 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2418 void (*resume)(struct drm_i915_private *);
2419 void (*cleanup_engine)(struct intel_engine_cs *engine);
2421 struct list_head timelines;
2422 struct i915_gem_timeline global_timeline;
2423 u32 active_requests;
2426 * Is the GPU currently considered idle, or busy executing
2427 * userspace requests? Whilst idle, we allow runtime power
2428 * management to power down the hardware and display clocks.
2429 * In order to reduce the effect on performance, there
2430 * is a slight delay before we do so.
2435 * We leave the user IRQ off as much as possible,
2436 * but this means that requests will finish and never
2437 * be retired once the system goes idle. Set a timer to
2438 * fire periodically while the ring is running. When it
2439 * fires, go retire requests.
2441 struct delayed_work retire_work;
2444 * When we detect an idle GPU, we want to turn on
2445 * powersaving features. So once we see that there
2446 * are no more requests outstanding and no more
2447 * arrive within a small period of time, we fire
2448 * off the idle_work.
2450 struct delayed_work idle_work;
2452 ktime_t last_init_time;
2455 /* perform PHY state sanity checks? */
2456 bool chv_phy_assert[2];
2460 /* Used to save the pipe-to-encoder mapping for audio */
2461 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2464 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2465 * will be rejected. Instead look for a better place.
2469 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2471 return container_of(dev, struct drm_i915_private, drm);
2474 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2476 return to_i915(dev_get_drvdata(kdev));
2479 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2481 return container_of(guc, struct drm_i915_private, guc);
2484 /* Simple iterator over all initialised engines */
2485 #define for_each_engine(engine__, dev_priv__, id__) \
2487 (id__) < I915_NUM_ENGINES; \
2489 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2491 #define __mask_next_bit(mask) ({ \
2492 int __idx = ffs(mask) - 1; \
2493 mask &= ~BIT(__idx); \
2497 /* Iterator over subset of engines selected by mask */
2498 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2499 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2500 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2502 enum hdmi_force_audio {
2503 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2504 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2505 HDMI_AUDIO_AUTO, /* trust EDID */
2506 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2509 #define I915_GTT_OFFSET_NONE ((u32)-1)
2512 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2513 * considered to be the frontbuffer for the given plane interface-wise. This
2514 * doesn't mean that the hw necessarily already scans it out, but that any
2515 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2517 * We have one bit per pipe and per scanout plane type.
2519 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2520 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2521 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2522 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2523 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2524 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2525 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2526 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2527 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2528 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2529 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2530 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2533 * Optimised SGL iterator for GEM objects
2535 static __always_inline struct sgt_iter {
2536 struct scatterlist *sgp;
2543 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2544 struct sgt_iter s = { .sgp = sgl };
2547 s.max = s.curr = s.sgp->offset;
2548 s.max += s.sgp->length;
2550 s.dma = sg_dma_address(s.sgp);
2552 s.pfn = page_to_pfn(sg_page(s.sgp));
2558 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2561 if (unlikely(sg_is_chain(sg)))
2562 sg = sg_chain_ptr(sg);
2567 * __sg_next - return the next scatterlist entry in a list
2568 * @sg: The current sg entry
2571 * If the entry is the last, return NULL; otherwise, step to the next
2572 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2573 * otherwise just return the pointer to the current element.
2575 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2577 #ifdef CONFIG_DEBUG_SG
2578 BUG_ON(sg->sg_magic != SG_MAGIC);
2580 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2584 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2585 * @__dmap: DMA address (output)
2586 * @__iter: 'struct sgt_iter' (iterator state, internal)
2587 * @__sgt: sg_table to iterate over (input)
2589 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2590 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2591 ((__dmap) = (__iter).dma + (__iter).curr); \
2592 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2593 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2596 * for_each_sgt_page - iterate over the pages of the given sg_table
2597 * @__pp: page pointer (output)
2598 * @__iter: 'struct sgt_iter' (iterator state, internal)
2599 * @__sgt: sg_table to iterate over (input)
2601 #define for_each_sgt_page(__pp, __iter, __sgt) \
2602 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2603 ((__pp) = (__iter).pfn == 0 ? NULL : \
2604 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2605 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2606 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2608 static inline const struct intel_device_info *
2609 intel_info(const struct drm_i915_private *dev_priv)
2611 return &dev_priv->info;
2614 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2616 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2617 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2619 #define REVID_FOREVER 0xff
2620 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2622 #define GEN_FOREVER (0)
2624 * Returns true if Gen is in inclusive range [Start, End].
2626 * Use GEN_FOREVER for unbound start and or end.
2628 #define IS_GEN(dev_priv, s, e) ({ \
2629 unsigned int __s = (s), __e = (e); \
2630 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2631 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2632 if ((__s) != GEN_FOREVER) \
2634 if ((__e) == GEN_FOREVER) \
2635 __e = BITS_PER_LONG - 1; \
2638 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2642 * Return true if revision is in range [since,until] inclusive.
2644 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2646 #define IS_REVID(p, since, until) \
2647 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2649 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2650 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2651 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2652 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2653 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2654 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2655 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2656 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2657 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2658 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2659 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2660 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2661 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2662 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2663 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2664 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2665 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2666 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2667 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2668 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2669 INTEL_DEVID(dev_priv) == 0x0152 || \
2670 INTEL_DEVID(dev_priv) == 0x015a)
2671 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2672 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2673 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2674 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2675 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2676 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2677 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2678 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2679 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2680 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2681 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2682 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2683 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2684 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2685 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2686 /* ULX machines are also considered ULT. */
2687 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2688 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2689 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2690 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2691 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2692 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2693 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2694 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2695 /* ULX machines are also considered ULT. */
2696 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2697 INTEL_DEVID(dev_priv) == 0x0A1E)
2698 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2699 INTEL_DEVID(dev_priv) == 0x1913 || \
2700 INTEL_DEVID(dev_priv) == 0x1916 || \
2701 INTEL_DEVID(dev_priv) == 0x1921 || \
2702 INTEL_DEVID(dev_priv) == 0x1926)
2703 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2704 INTEL_DEVID(dev_priv) == 0x1915 || \
2705 INTEL_DEVID(dev_priv) == 0x191E)
2706 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2707 INTEL_DEVID(dev_priv) == 0x5913 || \
2708 INTEL_DEVID(dev_priv) == 0x5916 || \
2709 INTEL_DEVID(dev_priv) == 0x5921 || \
2710 INTEL_DEVID(dev_priv) == 0x5926)
2711 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2712 INTEL_DEVID(dev_priv) == 0x5915 || \
2713 INTEL_DEVID(dev_priv) == 0x591E)
2714 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2715 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2716 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2717 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2719 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2721 #define SKL_REVID_A0 0x0
2722 #define SKL_REVID_B0 0x1
2723 #define SKL_REVID_C0 0x2
2724 #define SKL_REVID_D0 0x3
2725 #define SKL_REVID_E0 0x4
2726 #define SKL_REVID_F0 0x5
2727 #define SKL_REVID_G0 0x6
2728 #define SKL_REVID_H0 0x7
2730 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2732 #define BXT_REVID_A0 0x0
2733 #define BXT_REVID_A1 0x1
2734 #define BXT_REVID_B0 0x3
2735 #define BXT_REVID_B_LAST 0x8
2736 #define BXT_REVID_C0 0x9
2738 #define IS_BXT_REVID(dev_priv, since, until) \
2739 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2741 #define KBL_REVID_A0 0x0
2742 #define KBL_REVID_B0 0x1
2743 #define KBL_REVID_C0 0x2
2744 #define KBL_REVID_D0 0x3
2745 #define KBL_REVID_E0 0x4
2747 #define IS_KBL_REVID(dev_priv, since, until) \
2748 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2751 * The genX designation typically refers to the render engine, so render
2752 * capability related checks should use IS_GEN, while display and other checks
2753 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2756 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2757 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2758 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2759 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2760 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2761 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2762 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2763 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2765 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2766 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2768 #define ENGINE_MASK(id) BIT(id)
2769 #define RENDER_RING ENGINE_MASK(RCS)
2770 #define BSD_RING ENGINE_MASK(VCS)
2771 #define BLT_RING ENGINE_MASK(BCS)
2772 #define VEBOX_RING ENGINE_MASK(VECS)
2773 #define BSD2_RING ENGINE_MASK(VCS2)
2774 #define ALL_ENGINES (~0)
2776 #define HAS_ENGINE(dev_priv, id) \
2777 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2779 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2780 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2781 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2782 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2784 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2785 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2786 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2787 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2788 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2790 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2792 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2793 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2794 ((dev_priv)->info.has_logical_ring_contexts)
2795 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2796 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2797 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2799 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2800 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2801 ((dev_priv)->info.overlay_needs_physical)
2803 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2804 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2806 /* WaRsDisableCoarsePowerGating:skl,bxt */
2807 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2808 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2809 IS_SKL_GT3(dev_priv) || \
2810 IS_SKL_GT4(dev_priv))
2813 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2814 * even when in MSI mode. This results in spurious interrupt warnings if the
2815 * legacy irq no. is shared with another device. The kernel then disables that
2816 * interrupt source and so prevents the other device from working properly.
2818 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2819 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2821 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2822 * rows, which changed the alignment requirements and fence programming.
2824 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2825 !(IS_I915G(dev_priv) || \
2826 IS_I915GM(dev_priv)))
2827 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2828 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2830 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2831 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2832 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2834 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2836 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2838 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2839 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2840 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2841 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2842 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2844 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2846 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2847 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2850 * For now, anything with a GuC requires uCode loading, and then supports
2851 * command submission once loaded. But these are logically independent
2852 * properties, so we have separate macros to test them.
2854 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2855 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2856 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2857 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2859 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2861 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2863 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2864 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2865 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2866 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2867 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2868 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2869 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2870 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2871 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2872 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2873 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2874 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2876 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2877 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2878 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2879 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2880 #define HAS_PCH_LPT_LP(dev_priv) \
2881 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2882 #define HAS_PCH_LPT_H(dev_priv) \
2883 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2884 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2885 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2886 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2887 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2889 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2891 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2893 /* DPF == dynamic parity feature */
2894 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2895 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2896 2 : HAS_L3_DPF(dev_priv))
2898 #define GT_FREQUENCY_MULTIPLIER 50
2899 #define GEN9_FREQ_SCALER 3
2901 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2903 #include "i915_trace.h"
2905 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2907 #ifdef CONFIG_INTEL_IOMMU
2908 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2914 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2917 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2921 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2922 const char *fmt, ...);
2924 #define i915_report_error(dev_priv, fmt, ...) \
2925 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2927 #ifdef CONFIG_COMPAT
2928 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2931 #define i915_compat_ioctl NULL
2933 extern const struct dev_pm_ops i915_pm_ops;
2935 extern int i915_driver_load(struct pci_dev *pdev,
2936 const struct pci_device_id *ent);
2937 extern void i915_driver_unload(struct drm_device *dev);
2938 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2939 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2940 extern void i915_reset(struct drm_i915_private *dev_priv);
2941 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2942 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2943 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2944 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2945 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2946 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2947 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2948 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2950 /* intel_hotplug.c */
2951 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2952 u32 pin_mask, u32 long_mask);
2953 void intel_hpd_init(struct drm_i915_private *dev_priv);
2954 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2955 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2956 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2957 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2958 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2961 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2963 unsigned long delay;
2965 if (unlikely(!i915.enable_hangcheck))
2968 /* Don't continually defer the hangcheck so that it is always run at
2969 * least once after work has been scheduled on any ring. Otherwise,
2970 * we will ignore a hung ring if a second ring is kept busy.
2973 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2974 queue_delayed_work(system_long_wq,
2975 &dev_priv->gpu_error.hangcheck_work, delay);
2979 void i915_handle_error(struct drm_i915_private *dev_priv,
2981 const char *fmt, ...);
2983 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2984 int intel_irq_install(struct drm_i915_private *dev_priv);
2985 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2987 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2988 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2989 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2990 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2991 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2992 extern void intel_uncore_suspend(struct drm_i915_private *dev_priv);
2993 extern void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
2994 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2995 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2996 enum forcewake_domains domains);
2997 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2998 enum forcewake_domains domains);
2999 /* Like above but the caller must manage the uncore.lock itself.
3000 * Must be used with I915_READ_FW and friends.
3002 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3003 enum forcewake_domains domains);
3004 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3005 enum forcewake_domains domains);
3006 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3008 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3010 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3014 const unsigned long timeout_ms);
3015 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3019 const unsigned long timeout_ms);
3021 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3023 return dev_priv->gvt;
3026 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3028 return dev_priv->vgpu.active;
3032 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3036 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3039 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3040 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3041 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3044 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3045 uint32_t interrupt_mask,
3046 uint32_t enabled_irq_mask);
3048 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3050 ilk_update_display_irq(dev_priv, bits, bits);
3053 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3055 ilk_update_display_irq(dev_priv, bits, 0);
3057 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3059 uint32_t interrupt_mask,
3060 uint32_t enabled_irq_mask);
3061 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3062 enum pipe pipe, uint32_t bits)
3064 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3066 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3067 enum pipe pipe, uint32_t bits)
3069 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3071 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3072 uint32_t interrupt_mask,
3073 uint32_t enabled_irq_mask);
3075 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3077 ibx_display_interrupt_update(dev_priv, bits, bits);
3080 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3082 ibx_display_interrupt_update(dev_priv, bits, 0);
3086 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3087 struct drm_file *file_priv);
3088 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3089 struct drm_file *file_priv);
3090 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3091 struct drm_file *file_priv);
3092 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3093 struct drm_file *file_priv);
3094 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3095 struct drm_file *file_priv);
3096 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3097 struct drm_file *file_priv);
3098 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3099 struct drm_file *file_priv);
3100 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3101 struct drm_file *file_priv);
3102 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3103 struct drm_file *file_priv);
3104 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3105 struct drm_file *file_priv);
3106 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3107 struct drm_file *file);
3108 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3109 struct drm_file *file);
3110 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3111 struct drm_file *file_priv);
3112 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3113 struct drm_file *file_priv);
3114 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3115 struct drm_file *file_priv);
3116 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3117 struct drm_file *file_priv);
3118 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3119 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3120 struct drm_file *file);
3121 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3122 struct drm_file *file_priv);
3123 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3124 struct drm_file *file_priv);
3125 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3126 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3127 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3128 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3129 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3131 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3132 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3133 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3134 const struct drm_i915_gem_object_ops *ops);
3135 struct drm_i915_gem_object *
3136 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3137 struct drm_i915_gem_object *
3138 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3139 const void *data, size_t size);
3140 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3141 void i915_gem_free_object(struct drm_gem_object *obj);
3143 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3145 /* A single pass should suffice to release all the freed objects (along
3146 * most call paths) , but be a little more paranoid in that freeing
3147 * the objects does take a little amount of time, during which the rcu
3148 * callbacks could have added new objects into the freed list, and
3149 * armed the work again.
3153 } while (flush_work(&i915->mm.free_work));
3156 struct i915_vma * __must_check
3157 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3158 const struct i915_ggtt_view *view,
3163 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3164 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3166 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3168 static inline int __sg_page_count(const struct scatterlist *sg)
3170 return sg->length >> PAGE_SHIFT;
3173 struct scatterlist *
3174 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3175 unsigned int n, unsigned int *offset);
3178 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3182 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3186 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3189 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3190 struct sg_table *pages);
3191 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3193 static inline int __must_check
3194 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3196 might_lock(&obj->mm.lock);
3198 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3201 return __i915_gem_object_get_pages(obj);
3205 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3207 GEM_BUG_ON(!obj->mm.pages);
3209 atomic_inc(&obj->mm.pages_pin_count);
3213 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3215 return atomic_read(&obj->mm.pages_pin_count);
3219 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3221 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3222 GEM_BUG_ON(!obj->mm.pages);
3224 atomic_dec(&obj->mm.pages_pin_count);
3228 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3230 __i915_gem_object_unpin_pages(obj);
3233 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3238 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3239 enum i915_mm_subclass subclass);
3240 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3242 enum i915_map_type {
3248 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3249 * @obj: the object to map into kernel address space
3250 * @type: the type of mapping, used to select pgprot_t
3252 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3253 * pages and then returns a contiguous mapping of the backing storage into
3254 * the kernel address space. Based on the @type of mapping, the PTE will be
3255 * set to either WriteBack or WriteCombine (via pgprot_t).
3257 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3258 * mapping is no longer required.
3260 * Returns the pointer through which to access the mapped object, or an
3261 * ERR_PTR() on error.
3263 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3264 enum i915_map_type type);
3267 * i915_gem_object_unpin_map - releases an earlier mapping
3268 * @obj: the object to unmap
3270 * After pinning the object and mapping its pages, once you are finished
3271 * with your access, call i915_gem_object_unpin_map() to release the pin
3272 * upon the mapping. Once the pin count reaches zero, that mapping may be
3275 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3277 i915_gem_object_unpin_pages(obj);
3280 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3281 unsigned int *needs_clflush);
3282 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3283 unsigned int *needs_clflush);
3284 #define CLFLUSH_BEFORE 0x1
3285 #define CLFLUSH_AFTER 0x2
3286 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3289 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3291 i915_gem_object_unpin_pages(obj);
3294 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3295 void i915_vma_move_to_active(struct i915_vma *vma,
3296 struct drm_i915_gem_request *req,
3297 unsigned int flags);
3298 int i915_gem_dumb_create(struct drm_file *file_priv,
3299 struct drm_device *dev,
3300 struct drm_mode_create_dumb *args);
3301 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3302 uint32_t handle, uint64_t *offset);
3303 int i915_gem_mmap_gtt_version(void);
3305 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3306 struct drm_i915_gem_object *new,
3307 unsigned frontbuffer_bits);
3309 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3311 struct drm_i915_gem_request *
3312 i915_gem_find_active_request(struct intel_engine_cs *engine);
3314 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3316 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3318 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3321 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3323 return unlikely(test_bit(I915_WEDGED, &error->flags));
3326 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3328 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3331 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3333 return READ_ONCE(error->reset_count);
3336 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3337 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3338 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3339 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3340 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3341 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3342 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3343 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3344 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3345 unsigned int flags);
3346 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3347 void i915_gem_resume(struct drm_i915_private *dev_priv);
3348 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3349 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3352 struct intel_rps_client *rps);
3353 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3356 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3359 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3362 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3363 struct i915_vma * __must_check
3364 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3366 const struct i915_ggtt_view *view);
3367 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3368 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3370 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3371 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3373 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3374 enum i915_cache_level cache_level);
3376 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3377 struct dma_buf *dma_buf);
3379 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3380 struct drm_gem_object *gem_obj, int flags);
3382 static inline struct i915_hw_ppgtt *
3383 i915_vm_to_ppgtt(struct i915_address_space *vm)
3385 return container_of(vm, struct i915_hw_ppgtt, base);
3388 /* i915_gem_fence_reg.c */
3389 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3390 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3392 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3393 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3395 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3396 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3397 struct sg_table *pages);
3398 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3399 struct sg_table *pages);
3401 static inline struct i915_gem_context *
3402 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3404 struct i915_gem_context *ctx;
3406 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3408 ctx = idr_find(&file_priv->context_idr, id);
3410 return ERR_PTR(-ENOENT);
3415 static inline struct i915_gem_context *
3416 i915_gem_context_get(struct i915_gem_context *ctx)
3418 kref_get(&ctx->ref);
3422 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3424 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3425 kref_put(&ctx->ref, i915_gem_context_free);
3428 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3430 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3432 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3436 static inline struct intel_timeline *
3437 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3438 struct intel_engine_cs *engine)
3440 struct i915_address_space *vm;
3442 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3443 return &vm->timeline.engine[engine->id];
3446 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3447 struct drm_file *file);
3449 /* i915_gem_evict.c */
3450 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3451 u64 min_size, u64 alignment,
3452 unsigned cache_level,
3455 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3456 struct drm_mm_node *node,
3457 unsigned int flags);
3458 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3460 /* belongs in i915_gem_gtt.h */
3461 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3464 if (INTEL_GEN(dev_priv) < 6)
3465 intel_gtt_chipset_flush();
3468 /* i915_gem_stolen.c */
3469 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3470 struct drm_mm_node *node, u64 size,
3471 unsigned alignment);
3472 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3473 struct drm_mm_node *node, u64 size,
3474 unsigned alignment, u64 start,
3476 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3477 struct drm_mm_node *node);
3478 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3479 void i915_gem_cleanup_stolen(struct drm_device *dev);
3480 struct drm_i915_gem_object *
3481 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3482 struct drm_i915_gem_object *
3483 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3488 /* i915_gem_internal.c */
3489 struct drm_i915_gem_object *
3490 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3493 /* i915_gem_shrinker.c */
3494 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3495 unsigned long target,
3497 #define I915_SHRINK_PURGEABLE 0x1
3498 #define I915_SHRINK_UNBOUND 0x2
3499 #define I915_SHRINK_BOUND 0x4
3500 #define I915_SHRINK_ACTIVE 0x8
3501 #define I915_SHRINK_VMAPS 0x10
3502 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3503 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3504 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3507 /* i915_gem_tiling.c */
3508 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3510 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3512 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3513 i915_gem_object_is_tiled(obj);
3516 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3517 unsigned int tiling, unsigned int stride);
3518 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3519 unsigned int tiling, unsigned int stride);
3521 /* i915_debugfs.c */
3522 #ifdef CONFIG_DEBUG_FS
3523 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3524 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3525 int i915_debugfs_connector_add(struct drm_connector *connector);
3526 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3528 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3529 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3530 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3532 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3535 /* i915_gpu_error.c */
3536 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3539 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3540 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3541 const struct i915_error_state_file_priv *error);
3542 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3543 struct drm_i915_private *i915,
3544 size_t count, loff_t pos);
3545 static inline void i915_error_state_buf_release(
3546 struct drm_i915_error_state_buf *eb)
3550 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3552 const char *error_msg);
3553 void i915_error_state_get(struct drm_device *dev,
3554 struct i915_error_state_file_priv *error_priv);
3555 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3556 void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3560 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3562 const char *error_msg)
3566 static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3572 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3574 /* i915_cmd_parser.c */
3575 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3576 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3577 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3578 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3579 struct drm_i915_gem_object *batch_obj,
3580 struct drm_i915_gem_object *shadow_batch_obj,
3581 u32 batch_start_offset,
3586 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3587 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3588 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3589 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3591 /* i915_suspend.c */
3592 extern int i915_save_state(struct drm_i915_private *dev_priv);
3593 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3596 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3597 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3600 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3601 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3602 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3605 extern struct i2c_adapter *
3606 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3607 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3608 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3609 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3611 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3613 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3616 int intel_bios_init(struct drm_i915_private *dev_priv);
3617 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3618 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3619 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3620 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3621 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3622 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3623 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3624 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3626 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3630 /* intel_opregion.c */
3632 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3633 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3634 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3635 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3636 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3638 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3640 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3642 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3643 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3644 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3645 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3649 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3654 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3658 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3666 extern void intel_register_dsm_handler(void);
3667 extern void intel_unregister_dsm_handler(void);
3669 static inline void intel_register_dsm_handler(void) { return; }
3670 static inline void intel_unregister_dsm_handler(void) { return; }
3671 #endif /* CONFIG_ACPI */
3673 /* intel_device_info.c */
3674 static inline struct intel_device_info *
3675 mkwrite_device_info(struct drm_i915_private *dev_priv)
3677 return (struct intel_device_info *)&dev_priv->info;
3680 const char *intel_platform_name(enum intel_platform platform);
3681 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3682 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3685 extern void intel_modeset_init_hw(struct drm_device *dev);
3686 extern int intel_modeset_init(struct drm_device *dev);
3687 extern void intel_modeset_gem_init(struct drm_device *dev);
3688 extern void intel_modeset_cleanup(struct drm_device *dev);
3689 extern int intel_connector_register(struct drm_connector *);
3690 extern void intel_connector_unregister(struct drm_connector *);
3691 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3693 extern void intel_display_resume(struct drm_device *dev);
3694 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3695 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3696 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3697 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3698 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3699 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3702 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3703 struct drm_file *file);
3706 extern struct intel_overlay_error_state *
3707 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3708 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3709 struct intel_overlay_error_state *error);
3711 extern struct intel_display_error_state *
3712 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3713 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3714 struct drm_i915_private *dev_priv,
3715 struct intel_display_error_state *error);
3717 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3718 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3719 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3720 u32 reply_mask, u32 reply, int timeout_base_ms);
3722 /* intel_sideband.c */
3723 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3724 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3725 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3726 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3727 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3728 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3729 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3730 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3731 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3732 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3733 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3734 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3735 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3736 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3737 enum intel_sbi_destination destination);
3738 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3739 enum intel_sbi_destination destination);
3740 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3741 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3743 /* intel_dpio_phy.c */
3744 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3745 enum dpio_phy *phy, enum dpio_channel *ch);
3746 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3747 enum port port, u32 margin, u32 scale,
3748 u32 enable, u32 deemphasis);
3749 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3750 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3751 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3753 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3755 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3756 uint8_t lane_count);
3757 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3758 uint8_t lane_lat_optim_mask);
3759 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3761 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3762 u32 deemph_reg_value, u32 margin_reg_value,
3763 bool uniq_trans_scale);
3764 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3766 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3767 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3768 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3769 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3771 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3772 u32 demph_reg_value, u32 preemph_reg_value,
3773 u32 uniqtranscale_reg_value, u32 tx3_demph);
3774 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3775 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3776 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3778 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3779 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3781 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3782 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3784 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3785 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3786 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3787 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3789 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3790 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3791 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3792 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3794 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3795 * will be implemented using 2 32-bit writes in an arbitrary order with
3796 * an arbitrary delay between them. This can cause the hardware to
3797 * act upon the intermediate value, possibly leading to corruption and
3798 * machine death. For this reason we do not support I915_WRITE64, or
3799 * dev_priv->uncore.funcs.mmio_writeq.
3801 * When reading a 64-bit value as two 32-bit values, the delay may cause
3802 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3803 * occasionally a 64-bit register does not actualy support a full readq
3804 * and must be read using two 32-bit reads.
3806 * You have been warned.
3808 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3810 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3811 u32 upper, lower, old_upper, loop = 0; \
3812 upper = I915_READ(upper_reg); \
3814 old_upper = upper; \
3815 lower = I915_READ(lower_reg); \
3816 upper = I915_READ(upper_reg); \
3817 } while (upper != old_upper && loop++ < 2); \
3818 (u64)upper << 32 | lower; })
3820 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3821 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3823 #define __raw_read(x, s) \
3824 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3827 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3830 #define __raw_write(x, s) \
3831 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3832 i915_reg_t reg, uint##x##_t val) \
3834 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3849 /* These are untraced mmio-accessors that are only valid to be used inside
3850 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3853 * Think twice, and think again, before using these.
3855 * As an example, these accessors can possibly be used between:
3857 * spin_lock_irq(&dev_priv->uncore.lock);
3858 * intel_uncore_forcewake_get__locked();
3862 * intel_uncore_forcewake_put__locked();
3863 * spin_unlock_irq(&dev_priv->uncore.lock);
3866 * Note: some registers may not need forcewake held, so
3867 * intel_uncore_forcewake_{get,put} can be omitted, see
3868 * intel_uncore_forcewake_for_reg().
3870 * Certain architectures will die if the same cacheline is concurrently accessed
3871 * by different clients (e.g. on Ivybridge). Access to registers should
3872 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3873 * a more localised lock guarding all access to that bank of registers.
3875 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3876 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3877 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3878 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3880 /* "Broadcast RGB" property */
3881 #define INTEL_BROADCAST_RGB_AUTO 0
3882 #define INTEL_BROADCAST_RGB_FULL 1
3883 #define INTEL_BROADCAST_RGB_LIMITED 2
3885 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3887 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3888 return VLV_VGACNTRL;
3889 else if (INTEL_GEN(dev_priv) >= 5)
3890 return CPU_VGACNTRL;
3895 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3897 unsigned long j = msecs_to_jiffies(m);
3899 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3902 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3904 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3907 static inline unsigned long
3908 timespec_to_jiffies_timeout(const struct timespec *value)
3910 unsigned long j = timespec_to_jiffies(value);
3912 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3916 * If you need to wait X milliseconds between events A and B, but event B
3917 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3918 * when event A happened, then just before event B you call this function and
3919 * pass the timestamp as the first argument, and X as the second argument.
3922 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3924 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3927 * Don't re-read the value of "jiffies" every time since it may change
3928 * behind our back and break the math.
3930 tmp_jiffies = jiffies;
3931 target_jiffies = timestamp_jiffies +
3932 msecs_to_jiffies_timeout(to_wait_ms);
3934 if (time_after(target_jiffies, tmp_jiffies)) {
3935 remaining_jiffies = target_jiffies - tmp_jiffies;
3936 while (remaining_jiffies)
3938 schedule_timeout_uninterruptible(remaining_jiffies);
3943 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3945 struct intel_engine_cs *engine = req->engine;
3947 /* Before we do the heavier coherent read of the seqno,
3948 * check the value (hopefully) in the CPU cacheline.
3950 if (__i915_gem_request_completed(req))
3953 /* Ensure our read of the seqno is coherent so that we
3954 * do not "miss an interrupt" (i.e. if this is the last
3955 * request and the seqno write from the GPU is not visible
3956 * by the time the interrupt fires, we will see that the
3957 * request is incomplete and go back to sleep awaiting
3958 * another interrupt that will never come.)
3960 * Strictly, we only need to do this once after an interrupt,
3961 * but it is easier and safer to do it every time the waiter
3964 if (engine->irq_seqno_barrier &&
3965 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3966 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3967 struct task_struct *tsk;
3969 /* The ordering of irq_posted versus applying the barrier
3970 * is crucial. The clearing of the current irq_posted must
3971 * be visible before we perform the barrier operation,
3972 * such that if a subsequent interrupt arrives, irq_posted
3973 * is reasserted and our task rewoken (which causes us to
3974 * do another __i915_request_irq_complete() immediately
3975 * and reapply the barrier). Conversely, if the clear
3976 * occurs after the barrier, then an interrupt that arrived
3977 * whilst we waited on the barrier would not trigger a
3978 * barrier on the next pass, and the read may not see the
3981 engine->irq_seqno_barrier(engine);
3983 /* If we consume the irq, but we are no longer the bottom-half,
3984 * the real bottom-half may not have serialised their own
3985 * seqno check with the irq-barrier (i.e. may have inspected
3986 * the seqno before we believe it coherent since they see
3987 * irq_posted == false but we are still running).
3990 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3991 if (tsk && tsk != current)
3992 /* Note that if the bottom-half is changed as we
3993 * are sending the wake-up, the new bottom-half will
3994 * be woken by whomever made the change. We only have
3995 * to worry about when we steal the irq-posted for
3998 wake_up_process(tsk);
4001 if (__i915_gem_request_completed(req))
4008 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4009 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4011 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4012 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4013 * perform the operation. To check beforehand, pass in the parameters to
4014 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4015 * you only need to pass in the minor offsets, page-aligned pointers are
4018 * For just checking for SSE4.1, in the foreknowledge that the future use
4019 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4021 #define i915_can_memcpy_from_wc(dst, src, len) \
4022 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4024 #define i915_has_memcpy_from_wc() \
4025 i915_memcpy_from_wc(NULL, NULL, 0)
4028 int remap_io_mapping(struct vm_area_struct *vma,
4029 unsigned long addr, unsigned long pfn, unsigned long size,
4030 struct io_mapping *iomap);