1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct intel_pch_pll {
136 int refcount; /* count of number of CRTCs sharing this PLL */
137 int active; /* count of number of active CRTCs (i.e. DPMS on) */
138 bool on; /* is the PLL actually active? Disabled during modeset */
143 #define I915_NUM_PLLS 2
145 /* Used by dp and fdi links */
146 struct intel_link_m_n {
154 void intel_link_compute_m_n(int bpp, int nlanes,
155 int pixel_clock, int link_clock,
156 struct intel_link_m_n *m_n);
158 struct intel_ddi_plls {
164 /* Interface history:
167 * 1.2: Add Power Management
168 * 1.3: Add vblank support
169 * 1.4: Fix cmdbuffer path, add heap destroy
170 * 1.5: Add vblank pipe configuration
171 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
172 * - Support vertical blank on secondary display pipe
174 #define DRIVER_MAJOR 1
175 #define DRIVER_MINOR 6
176 #define DRIVER_PATCHLEVEL 0
178 #define WATCH_COHERENCY 0
179 #define WATCH_LISTS 0
182 #define I915_GEM_PHYS_CURSOR_0 1
183 #define I915_GEM_PHYS_CURSOR_1 2
184 #define I915_GEM_PHYS_OVERLAY_REGS 3
185 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
187 struct drm_i915_gem_phys_object {
189 struct page **page_list;
190 drm_dma_handle_t *handle;
191 struct drm_i915_gem_object *cur_obj;
194 struct opregion_header;
195 struct opregion_acpi;
196 struct opregion_swsci;
197 struct opregion_asle;
198 struct drm_i915_private;
200 struct intel_opregion {
201 struct opregion_header __iomem *header;
202 struct opregion_acpi __iomem *acpi;
203 struct opregion_swsci __iomem *swsci;
204 struct opregion_asle __iomem *asle;
206 u32 __iomem *lid_state;
208 #define OPREGION_SIZE (8*1024)
210 struct intel_overlay;
211 struct intel_overlay_error_state;
213 struct drm_i915_master_private {
214 drm_local_map_t *sarea;
215 struct _drm_i915_sarea *sarea_priv;
217 #define I915_FENCE_REG_NONE -1
218 #define I915_MAX_NUM_FENCES 32
219 /* 32 fences + sign bit for FENCE_REG_NONE */
220 #define I915_MAX_NUM_FENCE_BITS 6
222 struct drm_i915_fence_reg {
223 struct list_head lru_list;
224 struct drm_i915_gem_object *obj;
228 struct sdvo_device_mapping {
237 struct intel_display_error_state;
239 struct drm_i915_error_state {
247 bool waiting[I915_NUM_RINGS];
248 u32 pipestat[I915_MAX_PIPES];
249 u32 tail[I915_NUM_RINGS];
250 u32 head[I915_NUM_RINGS];
251 u32 ctl[I915_NUM_RINGS];
252 u32 ipeir[I915_NUM_RINGS];
253 u32 ipehr[I915_NUM_RINGS];
254 u32 instdone[I915_NUM_RINGS];
255 u32 acthd[I915_NUM_RINGS];
256 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
257 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
258 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
259 /* our own tracking of ring head and tail */
260 u32 cpu_ring_head[I915_NUM_RINGS];
261 u32 cpu_ring_tail[I915_NUM_RINGS];
262 u32 error; /* gen6+ */
263 u32 err_int; /* gen7 */
264 u32 instpm[I915_NUM_RINGS];
265 u32 instps[I915_NUM_RINGS];
266 u32 extra_instdone[I915_NUM_INSTDONE_REG];
267 u32 seqno[I915_NUM_RINGS];
269 u32 fault_reg[I915_NUM_RINGS];
271 u32 faddr[I915_NUM_RINGS];
272 u64 fence[I915_MAX_NUM_FENCES];
274 struct drm_i915_error_ring {
275 struct drm_i915_error_object {
279 } *ringbuffer, *batchbuffer, *ctx;
280 struct drm_i915_error_request {
286 } ring[I915_NUM_RINGS];
287 struct drm_i915_error_buffer {
294 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
301 } *active_bo, *pinned_bo;
302 u32 active_bo_count, pinned_bo_count;
303 struct intel_overlay_error_state *overlay;
304 struct intel_display_error_state *display;
307 struct intel_crtc_config;
310 struct drm_i915_display_funcs {
311 bool (*fbc_enabled)(struct drm_device *dev);
312 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
313 void (*disable_fbc)(struct drm_device *dev);
314 int (*get_display_clock_speed)(struct drm_device *dev);
315 int (*get_fifo_size)(struct drm_device *dev, int plane);
316 void (*update_wm)(struct drm_device *dev);
317 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
318 uint32_t sprite_width, int pixel_size);
319 void (*modeset_global_resources)(struct drm_device *dev);
320 /* Returns the active state of the crtc, and if the crtc is active,
321 * fills out the pipe-config with the hw state. */
322 bool (*get_pipe_config)(struct intel_crtc *,
323 struct intel_crtc_config *);
324 int (*crtc_mode_set)(struct drm_crtc *crtc,
326 struct drm_framebuffer *old_fb);
327 void (*crtc_enable)(struct drm_crtc *crtc);
328 void (*crtc_disable)(struct drm_crtc *crtc);
329 void (*off)(struct drm_crtc *crtc);
330 void (*write_eld)(struct drm_connector *connector,
331 struct drm_crtc *crtc);
332 void (*fdi_link_train)(struct drm_crtc *crtc);
333 void (*init_clock_gating)(struct drm_device *dev);
334 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
335 struct drm_framebuffer *fb,
336 struct drm_i915_gem_object *obj);
337 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
339 void (*hpd_irq_setup)(struct drm_device *dev);
340 /* clock updates for mode set */
342 /* render clock increase/decrease */
343 /* display clock increase/decrease */
344 /* pll clock increase/decrease */
347 struct drm_i915_gt_funcs {
348 void (*force_wake_get)(struct drm_i915_private *dev_priv);
349 void (*force_wake_put)(struct drm_i915_private *dev_priv);
352 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
353 func(is_mobile) sep \
356 func(is_i945gm) sep \
358 func(need_gfx_hws) sep \
360 func(is_pineview) sep \
361 func(is_broadwater) sep \
362 func(is_crestline) sep \
363 func(is_ivybridge) sep \
364 func(is_valleyview) sep \
365 func(is_haswell) sep \
366 func(has_force_wake) sep \
368 func(has_pipe_cxsr) sep \
369 func(has_hotplug) sep \
370 func(cursor_needs_physical) sep \
371 func(has_overlay) sep \
372 func(overlay_needs_physical) sep \
373 func(supports_tv) sep \
374 func(has_bsd_ring) sep \
375 func(has_blt_ring) sep \
380 #define DEFINE_FLAG(name) u8 name:1
381 #define SEP_SEMICOLON ;
383 struct intel_device_info {
384 u32 display_mmio_offset;
387 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
393 enum i915_cache_level {
396 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
399 typedef uint32_t gen6_gtt_pte_t;
401 /* The Graphics Translation Table is the way in which GEN hardware translates a
402 * Graphics Virtual Address into a Physical Address. In addition to the normal
403 * collateral associated with any va->pa translations GEN hardware also has a
404 * portion of the GTT which can be mapped by the CPU and remain both coherent
405 * and correct (in cases like swizzling). That region is referred to as GMADR in
409 unsigned long start; /* Start offset of used GTT */
410 size_t total; /* Total size GTT can map */
411 size_t stolen_size; /* Total size of stolen memory */
413 unsigned long mappable_end; /* End offset that we can CPU map */
414 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
415 phys_addr_t mappable_base; /* PA of our GMADR */
417 /** "Graphics Stolen Memory" holds the global PTEs */
421 dma_addr_t scratch_page_dma;
422 struct page *scratch_page;
425 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
426 size_t *stolen, phys_addr_t *mappable_base,
427 unsigned long *mappable_end);
428 void (*gtt_remove)(struct drm_device *dev);
429 void (*gtt_clear_range)(struct drm_device *dev,
430 unsigned int first_entry,
431 unsigned int num_entries);
432 void (*gtt_insert_entries)(struct drm_device *dev,
434 unsigned int pg_start,
435 enum i915_cache_level cache_level);
436 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
438 enum i915_cache_level level);
440 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
442 #define I915_PPGTT_PD_ENTRIES 512
443 #define I915_PPGTT_PT_ENTRIES 1024
444 struct i915_hw_ppgtt {
445 struct drm_device *dev;
446 unsigned num_pd_entries;
447 struct page **pt_pages;
449 dma_addr_t *pt_dma_addr;
450 dma_addr_t scratch_page_dma_addr;
452 /* pte functions, mirroring the interface of the global gtt. */
453 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
454 unsigned int first_entry,
455 unsigned int num_entries);
456 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
458 unsigned int pg_start,
459 enum i915_cache_level cache_level);
460 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
462 enum i915_cache_level level);
463 int (*enable)(struct drm_device *dev);
464 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
468 /* This must match up with the value previously used for execbuf2.rsvd1. */
469 #define DEFAULT_CONTEXT_ID 0
470 struct i915_hw_context {
474 struct drm_i915_file_private *file_priv;
475 struct intel_ring_buffer *ring;
476 struct drm_i915_gem_object *obj;
480 FBC_NO_OUTPUT, /* no outputs enabled to compress */
481 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
482 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
483 FBC_MODE_TOO_LARGE, /* mode too large for compression */
484 FBC_BAD_PLANE, /* fbc not supported on plane */
485 FBC_NOT_TILED, /* buffer not tiled */
486 FBC_MULTIPLE_PIPES, /* more than one pipe active */
491 PCH_NONE = 0, /* No PCH present */
492 PCH_IBX, /* Ibexpeak PCH */
493 PCH_CPT, /* Cougarpoint PCH */
494 PCH_LPT, /* Lynxpoint PCH */
498 enum intel_sbi_destination {
503 #define QUIRK_PIPEA_FORCE (1<<0)
504 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
505 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
508 struct intel_fbc_work;
511 struct i2c_adapter adapter;
515 struct i2c_algo_bit_data bit_algo;
516 struct drm_i915_private *dev_priv;
519 struct i915_suspend_saved_registers {
540 u32 saveTRANS_HTOTAL_A;
541 u32 saveTRANS_HBLANK_A;
542 u32 saveTRANS_HSYNC_A;
543 u32 saveTRANS_VTOTAL_A;
544 u32 saveTRANS_VBLANK_A;
545 u32 saveTRANS_VSYNC_A;
553 u32 savePFIT_PGM_RATIOS;
554 u32 saveBLC_HIST_CTL;
556 u32 saveBLC_PWM_CTL2;
557 u32 saveBLC_CPU_PWM_CTL;
558 u32 saveBLC_CPU_PWM_CTL2;
571 u32 saveTRANS_HTOTAL_B;
572 u32 saveTRANS_HBLANK_B;
573 u32 saveTRANS_HSYNC_B;
574 u32 saveTRANS_VTOTAL_B;
575 u32 saveTRANS_VBLANK_B;
576 u32 saveTRANS_VSYNC_B;
590 u32 savePP_ON_DELAYS;
591 u32 savePP_OFF_DELAYS;
599 u32 savePFIT_CONTROL;
600 u32 save_palette_a[256];
601 u32 save_palette_b[256];
602 u32 saveDPFC_CB_BASE;
603 u32 saveFBC_CFB_BASE;
606 u32 saveFBC_CONTROL2;
616 u32 saveCACHE_MODE_0;
617 u32 saveMI_ARB_STATE;
628 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
639 u32 savePIPEA_GMCH_DATA_M;
640 u32 savePIPEB_GMCH_DATA_M;
641 u32 savePIPEA_GMCH_DATA_N;
642 u32 savePIPEB_GMCH_DATA_N;
643 u32 savePIPEA_DP_LINK_M;
644 u32 savePIPEB_DP_LINK_M;
645 u32 savePIPEA_DP_LINK_N;
646 u32 savePIPEB_DP_LINK_N;
657 u32 savePCH_DREF_CONTROL;
658 u32 saveDISP_ARB_CTL;
659 u32 savePIPEA_DATA_M1;
660 u32 savePIPEA_DATA_N1;
661 u32 savePIPEA_LINK_M1;
662 u32 savePIPEA_LINK_N1;
663 u32 savePIPEB_DATA_M1;
664 u32 savePIPEB_DATA_N1;
665 u32 savePIPEB_LINK_M1;
666 u32 savePIPEB_LINK_N1;
667 u32 saveMCHBAR_RENDER_STANDBY;
668 u32 savePCH_PORT_HOTPLUG;
671 struct intel_gen6_power_mgmt {
672 struct work_struct work;
673 struct delayed_work vlv_work;
675 /* lock - irqsave spinlock that protectects the work_struct and
679 /* The below variables an all the rps hw state are protected by
680 * dev->struct mutext. */
687 struct delayed_work delayed_resume_work;
690 * Protects RPS/RC6 register access and PCU communication.
691 * Must be taken after struct_mutex if nested.
693 struct mutex hw_lock;
696 /* defined intel_pm.c */
697 extern spinlock_t mchdev_lock;
699 struct intel_ilk_power_mgmt {
707 unsigned long last_time1;
708 unsigned long chipset_power;
710 struct timespec last_time2;
711 unsigned long gfx_power;
717 struct drm_i915_gem_object *pwrctx;
718 struct drm_i915_gem_object *renderctx;
721 struct i915_dri1_state {
722 unsigned allow_batchbuffer : 1;
723 u32 __iomem *gfx_hws_cpu_addr;
734 struct intel_l3_parity {
736 struct work_struct error_work;
740 /** Memory allocator for GTT stolen memory */
741 struct drm_mm stolen;
742 /** Memory allocator for GTT */
743 struct drm_mm gtt_space;
744 /** List of all objects in gtt_space. Used to restore gtt
745 * mappings on resume */
746 struct list_head bound_list;
748 * List of objects which are not bound to the GTT (thus
749 * are idle and not used by the GPU) but still have
750 * (presumably uncached) pages still attached.
752 struct list_head unbound_list;
754 /** Usable portion of the GTT for GEM */
755 unsigned long stolen_base; /* limited to low memory (32-bit) */
759 /** PPGTT used for aliasing the PPGTT with the GTT */
760 struct i915_hw_ppgtt *aliasing_ppgtt;
762 struct shrinker inactive_shrinker;
763 bool shrinker_no_lock_stealing;
766 * List of objects currently involved in rendering.
768 * Includes buffers having the contents of their GPU caches
769 * flushed, not necessarily primitives. last_rendering_seqno
770 * represents when the rendering involved will be completed.
772 * A reference is held on the buffer while on this list.
774 struct list_head active_list;
777 * LRU list of objects which are not in the ringbuffer and
778 * are ready to unbind, but are still in the GTT.
780 * last_rendering_seqno is 0 while an object is in this list.
782 * A reference is not held on the buffer while on this list,
783 * as merely being GTT-bound shouldn't prevent its being
784 * freed, and we'll pull it off the list in the free path.
786 struct list_head inactive_list;
788 /** LRU list of objects with fence regs on them. */
789 struct list_head fence_list;
792 * We leave the user IRQ off as much as possible,
793 * but this means that requests will finish and never
794 * be retired once the system goes idle. Set a timer to
795 * fire periodically while the ring is running. When it
796 * fires, go retire requests.
798 struct delayed_work retire_work;
801 * Are we in a non-interruptible section of code like
807 * Flag if the X Server, and thus DRM, is not currently in
808 * control of the device.
810 * This is set between LeaveVT and EnterVT. It needs to be
811 * replaced with a semaphore. It also needs to be
812 * transitioned away from for kernel modesetting.
816 /** Bit 6 swizzling required for X tiling */
817 uint32_t bit_6_swizzle_x;
818 /** Bit 6 swizzling required for Y tiling */
819 uint32_t bit_6_swizzle_y;
821 /* storage for physical objects */
822 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
824 /* accounting, useful for userland debugging */
825 size_t object_memory;
829 struct drm_i915_error_state_buf {
838 struct i915_gpu_error {
839 /* For hangcheck timer */
840 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
841 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
842 struct timer_list hangcheck_timer;
844 uint32_t last_acthd[I915_NUM_RINGS];
845 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
847 /* For reset and error_state handling. */
849 /* Protected by the above dev->gpu_error.lock. */
850 struct drm_i915_error_state *first_error;
851 struct work_struct work;
853 unsigned long last_reset;
856 * State variable and reset counter controlling the reset flow
858 * Upper bits are for the reset counter. This counter is used by the
859 * wait_seqno code to race-free noticed that a reset event happened and
860 * that it needs to restart the entire ioctl (since most likely the
861 * seqno it waited for won't ever signal anytime soon).
863 * This is important for lock-free wait paths, where no contended lock
864 * naturally enforces the correct ordering between the bail-out of the
865 * waiter and the gpu reset work code.
867 * Lowest bit controls the reset state machine: Set means a reset is in
868 * progress. This state will (presuming we don't have any bugs) decay
869 * into either unset (successful reset) or the special WEDGED value (hw
870 * terminally sour). All waiters on the reset_queue will be woken when
873 atomic_t reset_counter;
876 * Special values/flags for reset_counter
878 * Note that the code relies on
879 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
882 #define I915_RESET_IN_PROGRESS_FLAG 1
883 #define I915_WEDGED 0xffffffff
886 * Waitqueue to signal when the reset has completed. Used by clients
887 * that wait for dev_priv->mm.wedged to settle.
889 wait_queue_head_t reset_queue;
891 /* For gpu hang simulation. */
892 unsigned int stop_rings;
895 enum modeset_restore {
901 struct intel_vbt_data {
902 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
903 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
906 unsigned int int_tv_support:1;
907 unsigned int lvds_dither:1;
908 unsigned int lvds_vbt:1;
909 unsigned int int_crt_support:1;
910 unsigned int lvds_use_ssc:1;
911 unsigned int display_clock_mode:1;
912 unsigned int fdi_rx_polarity_inverted:1;
914 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
921 bool edp_initialized;
924 struct edp_power_seq edp_pps;
929 struct child_device_config *child_dev;
932 typedef struct drm_i915_private {
933 struct drm_device *dev;
934 struct kmem_cache *slab;
936 const struct intel_device_info *info;
938 int relative_constants_mode;
942 struct drm_i915_gt_funcs gt;
943 /** gt_fifo_count and the subsequent register write are synchronized
944 * with dev->struct_mutex. */
945 unsigned gt_fifo_count;
946 /** forcewake_count is protected by gt_lock */
947 unsigned forcewake_count;
948 /** gt_lock is also taken in irq contexts. */
951 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
954 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
955 * controller on different i2c buses. */
956 struct mutex gmbus_mutex;
959 * Base address of the gmbus and gpio block.
961 uint32_t gpio_mmio_base;
963 wait_queue_head_t gmbus_wait_queue;
965 struct pci_dev *bridge_dev;
966 struct intel_ring_buffer ring[I915_NUM_RINGS];
967 uint32_t last_seqno, next_seqno;
969 drm_dma_handle_t *status_page_dmah;
970 struct resource mch_res;
972 atomic_t irq_received;
974 /* protects the irq masks */
977 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
978 struct pm_qos_request pm_qos;
980 /* DPIO indirect register protection */
981 struct mutex dpio_lock;
983 /** Cached value of IMR to avoid reads in updating the bitfield */
987 struct work_struct hotplug_work;
988 bool enable_hotplug_processing;
990 unsigned long hpd_last_jiffies;
995 HPD_MARK_DISABLED = 2
997 } hpd_stats[HPD_NUM_PINS];
999 struct timer_list hotplug_reenable_timer;
1004 unsigned long cfb_size;
1005 unsigned int cfb_fb;
1006 enum plane cfb_plane;
1008 struct intel_fbc_work *fbc_work;
1010 struct intel_opregion opregion;
1011 struct intel_vbt_data vbt;
1014 struct intel_overlay *overlay;
1015 unsigned int sprite_scaling_enabled;
1021 spinlock_t lock; /* bl registers and the above bl fields */
1022 struct backlight_device *device;
1026 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1027 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1028 bool no_aux_handshake;
1030 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1031 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1032 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1034 unsigned int fsb_freq, mem_freq, is_ddr3;
1036 struct workqueue_struct *wq;
1038 /* Display functions */
1039 struct drm_i915_display_funcs display;
1041 /* PCH chipset type */
1042 enum intel_pch pch_type;
1043 unsigned short pch_id;
1045 unsigned long quirks;
1047 enum modeset_restore modeset_restore;
1048 struct mutex modeset_restore_lock;
1050 struct i915_gtt gtt;
1052 struct i915_gem_mm mm;
1054 /* Kernel Modesetting */
1056 struct sdvo_device_mapping sdvo_mappings[2];
1058 struct drm_crtc *plane_to_crtc_mapping[3];
1059 struct drm_crtc *pipe_to_crtc_mapping[3];
1060 wait_queue_head_t pending_flip_queue;
1062 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1063 struct intel_ddi_plls ddi_plls;
1065 /* Reclocking support */
1066 bool render_reclock_avail;
1067 bool lvds_downclock_avail;
1068 /* indicates the reduced downclock for LVDS*/
1072 bool mchbar_need_disable;
1074 struct intel_l3_parity l3_parity;
1076 /* gen6+ rps state */
1077 struct intel_gen6_power_mgmt rps;
1079 /* ilk-only ips/rps state. Everything in here is protected by the global
1080 * mchdev_lock in intel_pm.c */
1081 struct intel_ilk_power_mgmt ips;
1083 enum no_fbc_reason no_fbc_reason;
1085 struct drm_mm_node *compressed_fb;
1086 struct drm_mm_node *compressed_llb;
1088 struct i915_gpu_error gpu_error;
1090 struct drm_i915_gem_object *vlv_pctx;
1092 /* list of fbdev register on this device */
1093 struct intel_fbdev *fbdev;
1096 * The console may be contended at resume, but we don't
1097 * want it to block on it.
1099 struct work_struct console_resume_work;
1101 struct drm_property *broadcast_rgb_property;
1102 struct drm_property *force_audio_property;
1104 bool hw_contexts_disabled;
1105 uint32_t hw_context_size;
1109 struct i915_suspend_saved_registers regfile;
1111 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1113 struct i915_dri1_state dri1;
1114 } drm_i915_private_t;
1116 /* Iterate over initialised rings */
1117 #define for_each_ring(ring__, dev_priv__, i__) \
1118 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1119 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1121 enum hdmi_force_audio {
1122 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1123 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1124 HDMI_AUDIO_AUTO, /* trust EDID */
1125 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1128 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1130 struct drm_i915_gem_object_ops {
1131 /* Interface between the GEM object and its backing storage.
1132 * get_pages() is called once prior to the use of the associated set
1133 * of pages before to binding them into the GTT, and put_pages() is
1134 * called after we no longer need them. As we expect there to be
1135 * associated cost with migrating pages between the backing storage
1136 * and making them available for the GPU (e.g. clflush), we may hold
1137 * onto the pages after they are no longer referenced by the GPU
1138 * in case they may be used again shortly (for example migrating the
1139 * pages to a different memory domain within the GTT). put_pages()
1140 * will therefore most likely be called when the object itself is
1141 * being released or under memory pressure (where we attempt to
1142 * reap pages for the shrinker).
1144 int (*get_pages)(struct drm_i915_gem_object *);
1145 void (*put_pages)(struct drm_i915_gem_object *);
1148 struct drm_i915_gem_object {
1149 struct drm_gem_object base;
1151 const struct drm_i915_gem_object_ops *ops;
1153 /** Current space allocated to this object in the GTT, if any. */
1154 struct drm_mm_node *gtt_space;
1155 /** Stolen memory for this object, instead of being backed by shmem. */
1156 struct drm_mm_node *stolen;
1157 struct list_head gtt_list;
1159 /** This object's place on the active/inactive lists */
1160 struct list_head ring_list;
1161 struct list_head mm_list;
1162 /** This object's place in the batchbuffer or on the eviction list */
1163 struct list_head exec_list;
1166 * This is set if the object is on the active lists (has pending
1167 * rendering and so a non-zero seqno), and is not set if it i s on
1168 * inactive (ready to be unbound) list.
1170 unsigned int active:1;
1173 * This is set if the object has been written to since last bound
1176 unsigned int dirty:1;
1179 * Fence register bits (if any) for this object. Will be set
1180 * as needed when mapped into the GTT.
1181 * Protected by dev->struct_mutex.
1183 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1186 * Advice: are the backing pages purgeable?
1188 unsigned int madv:2;
1191 * Current tiling mode for the object.
1193 unsigned int tiling_mode:2;
1195 * Whether the tiling parameters for the currently associated fence
1196 * register have changed. Note that for the purposes of tracking
1197 * tiling changes we also treat the unfenced register, the register
1198 * slot that the object occupies whilst it executes a fenced
1199 * command (such as BLT on gen2/3), as a "fence".
1201 unsigned int fence_dirty:1;
1203 /** How many users have pinned this object in GTT space. The following
1204 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1205 * (via user_pin_count), execbuffer (objects are not allowed multiple
1206 * times for the same batchbuffer), and the framebuffer code. When
1207 * switching/pageflipping, the framebuffer code has at most two buffers
1210 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1211 * bits with absolutely no headroom. So use 4 bits. */
1212 unsigned int pin_count:4;
1213 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1216 * Is the object at the current location in the gtt mappable and
1217 * fenceable? Used to avoid costly recalculations.
1219 unsigned int map_and_fenceable:1;
1222 * Whether the current gtt mapping needs to be mappable (and isn't just
1223 * mappable by accident). Track pin and fault separate for a more
1224 * accurate mappable working set.
1226 unsigned int fault_mappable:1;
1227 unsigned int pin_mappable:1;
1230 * Is the GPU currently using a fence to access this buffer,
1232 unsigned int pending_fenced_gpu_access:1;
1233 unsigned int fenced_gpu_access:1;
1235 unsigned int cache_level:2;
1237 unsigned int has_aliasing_ppgtt_mapping:1;
1238 unsigned int has_global_gtt_mapping:1;
1239 unsigned int has_dma_mapping:1;
1241 struct sg_table *pages;
1242 int pages_pin_count;
1244 /* prime dma-buf support */
1245 void *dma_buf_vmapping;
1249 * Used for performing relocations during execbuffer insertion.
1251 struct hlist_node exec_node;
1252 unsigned long exec_handle;
1253 struct drm_i915_gem_exec_object2 *exec_entry;
1256 * Current offset of the object in GTT space.
1258 * This is the same as gtt_space->start
1260 uint32_t gtt_offset;
1262 struct intel_ring_buffer *ring;
1264 /** Breadcrumb of last rendering to the buffer. */
1265 uint32_t last_read_seqno;
1266 uint32_t last_write_seqno;
1267 /** Breadcrumb of last fenced GPU access to the buffer. */
1268 uint32_t last_fenced_seqno;
1270 /** Current tiling stride for the object, if it's tiled. */
1273 /** Record of address bit 17 of each page at last unbind. */
1274 unsigned long *bit_17;
1276 /** User space pin count and filp owning the pin */
1277 uint32_t user_pin_count;
1278 struct drm_file *pin_filp;
1280 /** for phy allocated objects */
1281 struct drm_i915_gem_phys_object *phys_obj;
1283 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1285 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1288 * Request queue structure.
1290 * The request queue allows us to note sequence numbers that have been emitted
1291 * and may be associated with active buffers to be retired.
1293 * By keeping this list, we can avoid having to do questionable
1294 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1295 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1297 struct drm_i915_gem_request {
1298 /** On Which ring this request was generated */
1299 struct intel_ring_buffer *ring;
1301 /** GEM sequence number associated with this request. */
1304 /** Postion in the ringbuffer of the end of the request */
1307 /** Context related to this request */
1308 struct i915_hw_context *ctx;
1310 /** Time at which this request was emitted, in jiffies. */
1311 unsigned long emitted_jiffies;
1313 /** global list entry for this request */
1314 struct list_head list;
1316 struct drm_i915_file_private *file_priv;
1317 /** file_priv list entry for this request */
1318 struct list_head client_list;
1321 struct drm_i915_file_private {
1324 struct list_head request_list;
1326 struct idr context_idr;
1329 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1331 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1332 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1333 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1334 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1335 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1336 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1337 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1338 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1339 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1340 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1341 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1342 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1343 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1344 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1345 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1346 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1347 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1348 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1349 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1350 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1351 (dev)->pci_device == 0x0152 || \
1352 (dev)->pci_device == 0x015a)
1353 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1354 (dev)->pci_device == 0x0106 || \
1355 (dev)->pci_device == 0x010A)
1356 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1357 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1358 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1359 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1360 ((dev)->pci_device & 0xFF00) == 0x0A00)
1363 * The genX designation typically refers to the render engine, so render
1364 * capability related checks should use IS_GEN, while display and other checks
1365 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1368 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1369 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1370 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1371 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1372 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1373 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1375 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1376 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1377 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1378 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1380 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1381 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1383 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1384 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1386 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1387 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1389 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1390 * rows, which changed the alignment requirements and fence programming.
1392 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1394 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1395 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1396 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1397 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1398 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1399 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1400 /* dsparb controlled by hw only */
1401 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1403 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1404 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1405 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1407 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1409 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1410 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1411 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1413 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1414 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1415 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1416 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1417 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1418 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1420 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1421 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1422 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1423 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1424 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1425 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1427 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1429 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1431 #define GT_FREQUENCY_MULTIPLIER 50
1433 #include "i915_trace.h"
1436 * RC6 is a special power stage which allows the GPU to enter an very
1437 * low-voltage mode when idle, using down to 0V while at this stage. This
1438 * stage is entered automatically when the GPU is idle when RC6 support is
1439 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1441 * There are different RC6 modes available in Intel GPU, which differentiate
1442 * among each other with the latency required to enter and leave RC6 and
1443 * voltage consumed by the GPU in different states.
1445 * The combination of the following flags define which states GPU is allowed
1446 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1447 * RC6pp is deepest RC6. Their support by hardware varies according to the
1448 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1449 * which brings the most power savings; deeper states save more power, but
1450 * require higher latency to switch to and wake up.
1452 #define INTEL_RC6_ENABLE (1<<0)
1453 #define INTEL_RC6p_ENABLE (1<<1)
1454 #define INTEL_RC6pp_ENABLE (1<<2)
1456 extern struct drm_ioctl_desc i915_ioctls[];
1457 extern int i915_max_ioctl;
1458 extern unsigned int i915_fbpercrtc __always_unused;
1459 extern int i915_panel_ignore_lid __read_mostly;
1460 extern unsigned int i915_powersave __read_mostly;
1461 extern int i915_semaphores __read_mostly;
1462 extern unsigned int i915_lvds_downclock __read_mostly;
1463 extern int i915_lvds_channel_mode __read_mostly;
1464 extern int i915_panel_use_ssc __read_mostly;
1465 extern int i915_vbt_sdvo_panel_type __read_mostly;
1466 extern int i915_enable_rc6 __read_mostly;
1467 extern int i915_enable_fbc __read_mostly;
1468 extern bool i915_enable_hangcheck __read_mostly;
1469 extern int i915_enable_ppgtt __read_mostly;
1470 extern unsigned int i915_preliminary_hw_support __read_mostly;
1471 extern int i915_disable_power_well __read_mostly;
1473 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1474 extern int i915_resume(struct drm_device *dev);
1475 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1476 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1479 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1480 extern void i915_kernel_lost_context(struct drm_device * dev);
1481 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1482 extern int i915_driver_unload(struct drm_device *);
1483 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1484 extern void i915_driver_lastclose(struct drm_device * dev);
1485 extern void i915_driver_preclose(struct drm_device *dev,
1486 struct drm_file *file_priv);
1487 extern void i915_driver_postclose(struct drm_device *dev,
1488 struct drm_file *file_priv);
1489 extern int i915_driver_device_is_agp(struct drm_device * dev);
1490 #ifdef CONFIG_COMPAT
1491 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1494 extern int i915_emit_box(struct drm_device *dev,
1495 struct drm_clip_rect *box,
1497 extern int intel_gpu_reset(struct drm_device *dev);
1498 extern int i915_reset(struct drm_device *dev);
1499 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1500 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1501 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1502 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1504 extern void intel_console_resume(struct work_struct *work);
1507 void i915_hangcheck_elapsed(unsigned long data);
1508 void i915_handle_error(struct drm_device *dev, bool wedged);
1510 extern void intel_irq_init(struct drm_device *dev);
1511 extern void intel_hpd_init(struct drm_device *dev);
1512 extern void intel_gt_init(struct drm_device *dev);
1513 extern void intel_gt_reset(struct drm_device *dev);
1515 void i915_error_state_free(struct kref *error_ref);
1518 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1521 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1523 #ifdef CONFIG_DEBUG_FS
1524 extern void i915_destroy_error_state(struct drm_device *dev);
1526 #define i915_destroy_error_state(x)
1531 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
1533 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1534 struct drm_file *file_priv);
1535 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1536 struct drm_file *file_priv);
1537 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1538 struct drm_file *file_priv);
1539 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1540 struct drm_file *file_priv);
1541 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *file_priv);
1543 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1544 struct drm_file *file_priv);
1545 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1546 struct drm_file *file_priv);
1547 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1548 struct drm_file *file_priv);
1549 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1550 struct drm_file *file_priv);
1551 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1552 struct drm_file *file_priv);
1553 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1554 struct drm_file *file_priv);
1555 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1556 struct drm_file *file_priv);
1557 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1558 struct drm_file *file);
1559 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1560 struct drm_file *file);
1561 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1562 struct drm_file *file_priv);
1563 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1564 struct drm_file *file_priv);
1565 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1566 struct drm_file *file_priv);
1567 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1568 struct drm_file *file_priv);
1569 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1570 struct drm_file *file_priv);
1571 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1572 struct drm_file *file_priv);
1573 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1574 struct drm_file *file_priv);
1575 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1576 struct drm_file *file_priv);
1577 void i915_gem_load(struct drm_device *dev);
1578 void *i915_gem_object_alloc(struct drm_device *dev);
1579 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1580 int i915_gem_init_object(struct drm_gem_object *obj);
1581 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1582 const struct drm_i915_gem_object_ops *ops);
1583 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1585 void i915_gem_free_object(struct drm_gem_object *obj);
1587 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1589 bool map_and_fenceable,
1591 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1592 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1593 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1594 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1595 void i915_gem_lastclose(struct drm_device *dev);
1597 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1598 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1600 struct sg_page_iter sg_iter;
1602 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1603 return sg_page_iter_page(&sg_iter);
1607 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1609 BUG_ON(obj->pages == NULL);
1610 obj->pages_pin_count++;
1612 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1614 BUG_ON(obj->pages_pin_count == 0);
1615 obj->pages_pin_count--;
1618 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1619 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1620 struct intel_ring_buffer *to);
1621 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1622 struct intel_ring_buffer *ring);
1624 int i915_gem_dumb_create(struct drm_file *file_priv,
1625 struct drm_device *dev,
1626 struct drm_mode_create_dumb *args);
1627 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1628 uint32_t handle, uint64_t *offset);
1629 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1632 * Returns true if seq1 is later than seq2.
1635 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1637 return (int32_t)(seq1 - seq2) >= 0;
1640 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1641 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1642 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1643 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1646 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1648 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1649 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1650 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1657 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1659 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1660 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1661 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1665 void i915_gem_retire_requests(struct drm_device *dev);
1666 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1667 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1668 bool interruptible);
1669 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1671 return unlikely(atomic_read(&error->reset_counter)
1672 & I915_RESET_IN_PROGRESS_FLAG);
1675 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1677 return atomic_read(&error->reset_counter) == I915_WEDGED;
1680 void i915_gem_reset(struct drm_device *dev);
1681 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1682 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1683 uint32_t read_domains,
1684 uint32_t write_domain);
1685 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1686 int __must_check i915_gem_init(struct drm_device *dev);
1687 int __must_check i915_gem_init_hw(struct drm_device *dev);
1688 void i915_gem_l3_remap(struct drm_device *dev);
1689 void i915_gem_init_swizzling(struct drm_device *dev);
1690 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1691 int __must_check i915_gpu_idle(struct drm_device *dev);
1692 int __must_check i915_gem_idle(struct drm_device *dev);
1693 int i915_add_request(struct intel_ring_buffer *ring,
1694 struct drm_file *file,
1696 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1698 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1700 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1703 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1705 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1707 struct intel_ring_buffer *pipelined);
1708 int i915_gem_attach_phys_object(struct drm_device *dev,
1709 struct drm_i915_gem_object *obj,
1712 void i915_gem_detach_phys_object(struct drm_device *dev,
1713 struct drm_i915_gem_object *obj);
1714 void i915_gem_free_all_phys_object(struct drm_device *dev);
1715 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1718 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1720 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1721 int tiling_mode, bool fenced);
1723 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1724 enum i915_cache_level cache_level);
1726 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1727 struct dma_buf *dma_buf);
1729 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1730 struct drm_gem_object *gem_obj, int flags);
1732 /* i915_gem_context.c */
1733 void i915_gem_context_init(struct drm_device *dev);
1734 void i915_gem_context_fini(struct drm_device *dev);
1735 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1736 int i915_switch_context(struct intel_ring_buffer *ring,
1737 struct drm_file *file, int to_id);
1738 void i915_gem_context_free(struct kref *ctx_ref);
1739 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1741 kref_get(&ctx->ref);
1744 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1746 kref_put(&ctx->ref, i915_gem_context_free);
1749 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1750 struct drm_file *file);
1751 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1752 struct drm_file *file);
1754 /* i915_gem_gtt.c */
1755 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1756 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1757 struct drm_i915_gem_object *obj,
1758 enum i915_cache_level cache_level);
1759 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1760 struct drm_i915_gem_object *obj);
1762 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1763 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1764 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1765 enum i915_cache_level cache_level);
1766 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1767 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1768 void i915_gem_init_global_gtt(struct drm_device *dev);
1769 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1770 unsigned long mappable_end, unsigned long end);
1771 int i915_gem_gtt_init(struct drm_device *dev);
1772 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1774 if (INTEL_INFO(dev)->gen < 6)
1775 intel_gtt_chipset_flush();
1779 /* i915_gem_evict.c */
1780 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1782 unsigned cache_level,
1785 int i915_gem_evict_everything(struct drm_device *dev);
1787 /* i915_gem_stolen.c */
1788 int i915_gem_init_stolen(struct drm_device *dev);
1789 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1790 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1791 void i915_gem_cleanup_stolen(struct drm_device *dev);
1792 struct drm_i915_gem_object *
1793 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1794 struct drm_i915_gem_object *
1795 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1799 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1801 /* i915_gem_tiling.c */
1802 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1804 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1806 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1807 obj->tiling_mode != I915_TILING_NONE;
1810 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1811 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1812 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1814 /* i915_gem_debug.c */
1815 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1816 const char *where, uint32_t mark);
1818 int i915_verify_lists(struct drm_device *dev);
1820 #define i915_verify_lists(dev) 0
1822 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1824 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1825 const char *where, uint32_t mark);
1827 /* i915_debugfs.c */
1828 int i915_debugfs_init(struct drm_minor *minor);
1829 void i915_debugfs_cleanup(struct drm_minor *minor);
1831 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1833 /* i915_suspend.c */
1834 extern int i915_save_state(struct drm_device *dev);
1835 extern int i915_restore_state(struct drm_device *dev);
1838 void i915_save_display_reg(struct drm_device *dev);
1839 void i915_restore_display_reg(struct drm_device *dev);
1842 void i915_setup_sysfs(struct drm_device *dev_priv);
1843 void i915_teardown_sysfs(struct drm_device *dev_priv);
1846 extern int intel_setup_gmbus(struct drm_device *dev);
1847 extern void intel_teardown_gmbus(struct drm_device *dev);
1848 static inline bool intel_gmbus_is_port_valid(unsigned port)
1850 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1853 extern struct i2c_adapter *intel_gmbus_get_adapter(
1854 struct drm_i915_private *dev_priv, unsigned port);
1855 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1856 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1857 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1859 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1861 extern void intel_i2c_reset(struct drm_device *dev);
1863 /* intel_opregion.c */
1864 extern int intel_opregion_setup(struct drm_device *dev);
1866 extern void intel_opregion_init(struct drm_device *dev);
1867 extern void intel_opregion_fini(struct drm_device *dev);
1868 extern void intel_opregion_asle_intr(struct drm_device *dev);
1870 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1871 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1872 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1877 extern void intel_register_dsm_handler(void);
1878 extern void intel_unregister_dsm_handler(void);
1880 static inline void intel_register_dsm_handler(void) { return; }
1881 static inline void intel_unregister_dsm_handler(void) { return; }
1882 #endif /* CONFIG_ACPI */
1885 extern void intel_modeset_init_hw(struct drm_device *dev);
1886 extern void intel_modeset_suspend_hw(struct drm_device *dev);
1887 extern void intel_modeset_init(struct drm_device *dev);
1888 extern void intel_modeset_gem_init(struct drm_device *dev);
1889 extern void intel_modeset_cleanup(struct drm_device *dev);
1890 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1891 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1892 bool force_restore);
1893 extern void i915_redisable_vga(struct drm_device *dev);
1894 extern bool intel_fbc_enabled(struct drm_device *dev);
1895 extern void intel_disable_fbc(struct drm_device *dev);
1896 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1897 extern void intel_init_pch_refclk(struct drm_device *dev);
1898 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1899 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1900 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1901 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1902 extern void intel_detect_pch(struct drm_device *dev);
1903 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1904 extern int intel_enable_rc6(const struct drm_device *dev);
1906 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1907 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1908 struct drm_file *file);
1911 #ifdef CONFIG_DEBUG_FS
1912 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1913 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
1914 struct intel_overlay_error_state *error);
1916 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1917 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
1918 struct drm_device *dev,
1919 struct intel_display_error_state *error);
1922 /* On SNB platform, before reading ring registers forcewake bit
1923 * must be set to prevent GT core from power down and stale values being
1926 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1927 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1928 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1930 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1931 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1933 /* intel_sideband.c */
1934 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1935 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1936 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1937 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
1938 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
1939 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1940 enum intel_sbi_destination destination);
1941 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1942 enum intel_sbi_destination destination);
1944 int vlv_gpu_freq(int ddr_freq, int val);
1945 int vlv_freq_opcode(int ddr_freq, int val);
1947 #define __i915_read(x, y) \
1948 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1956 #define __i915_write(x, y) \
1957 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1965 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1966 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1968 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1969 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1970 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1971 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1973 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1974 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1975 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1976 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1978 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1979 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1981 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1982 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1984 /* "Broadcast RGB" property */
1985 #define INTEL_BROADCAST_RGB_AUTO 0
1986 #define INTEL_BROADCAST_RGB_FULL 1
1987 #define INTEL_BROADCAST_RGB_LIMITED 2
1989 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1991 if (HAS_PCH_SPLIT(dev))
1992 return CPU_VGACNTRL;
1993 else if (IS_VALLEYVIEW(dev))
1994 return VLV_VGACNTRL;
1999 static inline void __user *to_user_ptr(u64 address)
2001 return (void __user *)(uintptr_t)address;