1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
63 #define pipe_name(p) ((p) + 'A')
71 #define transcoder_name(t) ((t) + 'A')
78 #define plane_name(p) ((p) + 'A')
80 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
90 #define port_name(p) ((p) + 'A')
92 #define I915_NUM_PHYS_VLV 1
104 enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
109 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
110 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
111 POWER_DOMAIN_TRANSCODER_A,
112 POWER_DOMAIN_TRANSCODER_B,
113 POWER_DOMAIN_TRANSCODER_C,
114 POWER_DOMAIN_TRANSCODER_EDP,
122 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
124 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
125 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
126 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
127 #define POWER_DOMAIN_TRANSCODER(tran) \
128 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
129 (tran) + POWER_DOMAIN_TRANSCODER_A)
131 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
132 BIT(POWER_DOMAIN_PIPE_A) | \
133 BIT(POWER_DOMAIN_TRANSCODER_EDP))
134 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
135 BIT(POWER_DOMAIN_PIPE_A) | \
136 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
137 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
141 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
142 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
152 #define I915_GEM_GPU_DOMAINS \
153 (I915_GEM_DOMAIN_RENDER | \
154 I915_GEM_DOMAIN_SAMPLER | \
155 I915_GEM_DOMAIN_COMMAND | \
156 I915_GEM_DOMAIN_INSTRUCTION | \
157 I915_GEM_DOMAIN_VERTEX)
159 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
161 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
162 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
163 if ((intel_encoder)->base.crtc == (__crtc))
165 struct drm_i915_private;
168 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
169 /* real shared dpll ids must be >= 0 */
173 #define I915_NUM_PLLS 2
175 struct intel_dpll_hw_state {
182 struct intel_shared_dpll {
183 int refcount; /* count of number of CRTCs sharing this PLL */
184 int active; /* count of number of active CRTCs (i.e. DPMS on) */
185 bool on; /* is the PLL actually active? Disabled during modeset */
187 /* should match the index in the dev_priv->shared_dplls array */
188 enum intel_dpll_id id;
189 struct intel_dpll_hw_state hw_state;
190 void (*mode_set)(struct drm_i915_private *dev_priv,
191 struct intel_shared_dpll *pll);
192 void (*enable)(struct drm_i915_private *dev_priv,
193 struct intel_shared_dpll *pll);
194 void (*disable)(struct drm_i915_private *dev_priv,
195 struct intel_shared_dpll *pll);
196 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
197 struct intel_shared_dpll *pll,
198 struct intel_dpll_hw_state *hw_state);
201 /* Used by dp and fdi links */
202 struct intel_link_m_n {
210 void intel_link_compute_m_n(int bpp, int nlanes,
211 int pixel_clock, int link_clock,
212 struct intel_link_m_n *m_n);
214 struct intel_ddi_plls {
220 /* Interface history:
223 * 1.2: Add Power Management
224 * 1.3: Add vblank support
225 * 1.4: Fix cmdbuffer path, add heap destroy
226 * 1.5: Add vblank pipe configuration
227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
228 * - Support vertical blank on secondary display pipe
230 #define DRIVER_MAJOR 1
231 #define DRIVER_MINOR 6
232 #define DRIVER_PATCHLEVEL 0
234 #define WATCH_LISTS 0
237 #define I915_GEM_PHYS_CURSOR_0 1
238 #define I915_GEM_PHYS_CURSOR_1 2
239 #define I915_GEM_PHYS_OVERLAY_REGS 3
240 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
242 struct drm_i915_gem_phys_object {
244 struct page **page_list;
245 drm_dma_handle_t *handle;
246 struct drm_i915_gem_object *cur_obj;
249 struct opregion_header;
250 struct opregion_acpi;
251 struct opregion_swsci;
252 struct opregion_asle;
254 struct intel_opregion {
255 struct opregion_header __iomem *header;
256 struct opregion_acpi __iomem *acpi;
257 struct opregion_swsci __iomem *swsci;
258 u32 swsci_gbda_sub_functions;
259 u32 swsci_sbcb_sub_functions;
260 struct opregion_asle __iomem *asle;
262 u32 __iomem *lid_state;
263 struct work_struct asle_work;
265 #define OPREGION_SIZE (8*1024)
267 struct intel_overlay;
268 struct intel_overlay_error_state;
270 struct drm_i915_master_private {
271 drm_local_map_t *sarea;
272 struct _drm_i915_sarea *sarea_priv;
274 #define I915_FENCE_REG_NONE -1
275 #define I915_MAX_NUM_FENCES 32
276 /* 32 fences + sign bit for FENCE_REG_NONE */
277 #define I915_MAX_NUM_FENCE_BITS 6
279 struct drm_i915_fence_reg {
280 struct list_head lru_list;
281 struct drm_i915_gem_object *obj;
285 struct sdvo_device_mapping {
294 struct intel_display_error_state;
296 struct drm_i915_error_state {
304 bool waiting[I915_NUM_RINGS];
305 u32 pipestat[I915_MAX_PIPES];
306 u32 tail[I915_NUM_RINGS];
307 u32 head[I915_NUM_RINGS];
308 u32 ctl[I915_NUM_RINGS];
309 u32 ipeir[I915_NUM_RINGS];
310 u32 ipehr[I915_NUM_RINGS];
311 u32 instdone[I915_NUM_RINGS];
312 u32 acthd[I915_NUM_RINGS];
313 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
314 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
315 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
316 /* our own tracking of ring head and tail */
317 u32 cpu_ring_head[I915_NUM_RINGS];
318 u32 cpu_ring_tail[I915_NUM_RINGS];
319 u32 error; /* gen6+ */
320 u32 err_int; /* gen7 */
321 u32 bbstate[I915_NUM_RINGS];
322 u32 instpm[I915_NUM_RINGS];
323 u32 instps[I915_NUM_RINGS];
324 u32 extra_instdone[I915_NUM_INSTDONE_REG];
325 u32 seqno[I915_NUM_RINGS];
327 u32 fault_reg[I915_NUM_RINGS];
329 u32 faddr[I915_NUM_RINGS];
330 u64 fence[I915_MAX_NUM_FENCES];
332 struct drm_i915_error_ring {
333 struct drm_i915_error_object {
337 } *ringbuffer, *batchbuffer, *ctx;
338 struct drm_i915_error_request {
344 } ring[I915_NUM_RINGS];
345 struct drm_i915_error_buffer {
352 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
359 } **active_bo, **pinned_bo;
360 u32 *active_bo_count, *pinned_bo_count;
361 struct intel_overlay_error_state *overlay;
362 struct intel_display_error_state *display;
363 int hangcheck_score[I915_NUM_RINGS];
364 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
367 struct intel_connector;
368 struct intel_crtc_config;
373 struct drm_i915_display_funcs {
374 bool (*fbc_enabled)(struct drm_device *dev);
375 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
376 void (*disable_fbc)(struct drm_device *dev);
377 int (*get_display_clock_speed)(struct drm_device *dev);
378 int (*get_fifo_size)(struct drm_device *dev, int plane);
380 * find_dpll() - Find the best values for the PLL
381 * @limit: limits for the PLL
382 * @crtc: current CRTC
383 * @target: target frequency in kHz
384 * @refclk: reference clock frequency in kHz
385 * @match_clock: if provided, @best_clock P divider must
386 * match the P divider from @match_clock
387 * used for LVDS downclocking
388 * @best_clock: best PLL values found
390 * Returns true on success, false on failure.
392 bool (*find_dpll)(const struct intel_limit *limit,
393 struct drm_crtc *crtc,
394 int target, int refclk,
395 struct dpll *match_clock,
396 struct dpll *best_clock);
397 void (*update_wm)(struct drm_crtc *crtc);
398 void (*update_sprite_wm)(struct drm_plane *plane,
399 struct drm_crtc *crtc,
400 uint32_t sprite_width, int pixel_size,
401 bool enable, bool scaled);
402 void (*modeset_global_resources)(struct drm_device *dev);
403 /* Returns the active state of the crtc, and if the crtc is active,
404 * fills out the pipe-config with the hw state. */
405 bool (*get_pipe_config)(struct intel_crtc *,
406 struct intel_crtc_config *);
407 int (*crtc_mode_set)(struct drm_crtc *crtc,
409 struct drm_framebuffer *old_fb);
410 void (*crtc_enable)(struct drm_crtc *crtc);
411 void (*crtc_disable)(struct drm_crtc *crtc);
412 void (*off)(struct drm_crtc *crtc);
413 void (*write_eld)(struct drm_connector *connector,
414 struct drm_crtc *crtc,
415 struct drm_display_mode *mode);
416 void (*fdi_link_train)(struct drm_crtc *crtc);
417 void (*init_clock_gating)(struct drm_device *dev);
418 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
419 struct drm_framebuffer *fb,
420 struct drm_i915_gem_object *obj,
422 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
424 void (*hpd_irq_setup)(struct drm_device *dev);
425 /* clock updates for mode set */
427 /* render clock increase/decrease */
428 /* display clock increase/decrease */
429 /* pll clock increase/decrease */
431 int (*setup_backlight)(struct intel_connector *connector);
432 uint32_t (*get_backlight)(struct intel_connector *connector);
433 void (*set_backlight)(struct intel_connector *connector,
435 void (*disable_backlight)(struct intel_connector *connector);
436 void (*enable_backlight)(struct intel_connector *connector);
439 struct intel_uncore_funcs {
440 void (*force_wake_get)(struct drm_i915_private *dev_priv);
441 void (*force_wake_put)(struct drm_i915_private *dev_priv);
443 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
444 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
445 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
446 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
448 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
449 uint8_t val, bool trace);
450 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
451 uint16_t val, bool trace);
452 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
453 uint32_t val, bool trace);
454 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
455 uint64_t val, bool trace);
458 struct intel_uncore {
459 spinlock_t lock; /** lock is also taken in irq contexts. */
461 struct intel_uncore_funcs funcs;
464 unsigned forcewake_count;
466 struct delayed_work force_wake_work;
469 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
470 func(is_mobile) sep \
473 func(is_i945gm) sep \
475 func(need_gfx_hws) sep \
477 func(is_pineview) sep \
478 func(is_broadwater) sep \
479 func(is_crestline) sep \
480 func(is_ivybridge) sep \
481 func(is_valleyview) sep \
482 func(is_haswell) sep \
483 func(is_preliminary) sep \
485 func(has_pipe_cxsr) sep \
486 func(has_hotplug) sep \
487 func(cursor_needs_physical) sep \
488 func(has_overlay) sep \
489 func(overlay_needs_physical) sep \
490 func(supports_tv) sep \
495 #define DEFINE_FLAG(name) u8 name:1
496 #define SEP_SEMICOLON ;
498 struct intel_device_info {
499 u32 display_mmio_offset;
502 u8 ring_mask; /* Rings supported by the HW */
503 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
509 enum i915_cache_level {
511 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
512 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
513 caches, eg sampler/render caches, and the
514 large Last-Level-Cache. LLC is coherent with
515 the CPU, but L3 is only visible to the GPU. */
516 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
519 typedef uint32_t gen6_gtt_pte_t;
521 struct i915_address_space {
523 struct drm_device *dev;
524 struct list_head global_link;
525 unsigned long start; /* Start offset always 0 for dri2 */
526 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
534 * List of objects currently involved in rendering.
536 * Includes buffers having the contents of their GPU caches
537 * flushed, not necessarily primitives. last_rendering_seqno
538 * represents when the rendering involved will be completed.
540 * A reference is held on the buffer while on this list.
542 struct list_head active_list;
545 * LRU list of objects which are not in the ringbuffer and
546 * are ready to unbind, but are still in the GTT.
548 * last_rendering_seqno is 0 while an object is in this list.
550 * A reference is not held on the buffer while on this list,
551 * as merely being GTT-bound shouldn't prevent its being
552 * freed, and we'll pull it off the list in the free path.
554 struct list_head inactive_list;
556 /* FIXME: Need a more generic return type */
557 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
558 enum i915_cache_level level,
559 bool valid); /* Create a valid PTE */
560 void (*clear_range)(struct i915_address_space *vm,
561 unsigned int first_entry,
562 unsigned int num_entries,
564 void (*insert_entries)(struct i915_address_space *vm,
566 unsigned int first_entry,
567 enum i915_cache_level cache_level);
568 void (*cleanup)(struct i915_address_space *vm);
571 /* The Graphics Translation Table is the way in which GEN hardware translates a
572 * Graphics Virtual Address into a Physical Address. In addition to the normal
573 * collateral associated with any va->pa translations GEN hardware also has a
574 * portion of the GTT which can be mapped by the CPU and remain both coherent
575 * and correct (in cases like swizzling). That region is referred to as GMADR in
579 struct i915_address_space base;
580 size_t stolen_size; /* Total size of stolen memory */
582 unsigned long mappable_end; /* End offset that we can CPU map */
583 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
584 phys_addr_t mappable_base; /* PA of our GMADR */
586 /** "Graphics Stolen Memory" holds the global PTEs */
594 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
595 size_t *stolen, phys_addr_t *mappable_base,
596 unsigned long *mappable_end);
598 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
600 struct i915_hw_ppgtt {
601 struct i915_address_space base;
602 unsigned num_pd_entries;
604 struct page **pt_pages;
605 struct page *gen8_pt_pages;
607 struct page *pd_pages;
612 dma_addr_t pd_dma_addr[4];
615 dma_addr_t *pt_dma_addr;
616 dma_addr_t *gen8_pt_dma_addr[4];
618 int (*enable)(struct drm_device *dev);
622 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
623 * VMA's presence cannot be guaranteed before binding, or after unbinding the
624 * object into/from the address space.
626 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
627 * will always be <= an objects lifetime. So object refcounting should cover us.
630 struct drm_mm_node node;
631 struct drm_i915_gem_object *obj;
632 struct i915_address_space *vm;
634 /** This object's place on the active/inactive lists */
635 struct list_head mm_list;
637 struct list_head vma_link; /* Link in the object's VMA list */
639 /** This vma's place in the batchbuffer or on the eviction list */
640 struct list_head exec_list;
643 * Used for performing relocations during execbuffer insertion.
645 struct hlist_node exec_node;
646 unsigned long exec_handle;
647 struct drm_i915_gem_exec_object2 *exec_entry;
651 struct i915_ctx_hang_stats {
652 /* This context had batch pending when hang was declared */
653 unsigned batch_pending;
655 /* This context had batch active when hang was declared */
656 unsigned batch_active;
658 /* Time when this context was last blamed for a GPU reset */
659 unsigned long guilty_ts;
661 /* This context is banned to submit more work */
665 /* This must match up with the value previously used for execbuf2.rsvd1. */
666 #define DEFAULT_CONTEXT_ID 0
667 struct i915_hw_context {
672 struct drm_i915_file_private *file_priv;
673 struct intel_ring_buffer *ring;
674 struct drm_i915_gem_object *obj;
675 struct i915_ctx_hang_stats hang_stats;
677 struct list_head link;
686 struct drm_mm_node *compressed_fb;
687 struct drm_mm_node *compressed_llb;
689 struct intel_fbc_work {
690 struct delayed_work work;
691 struct drm_crtc *crtc;
692 struct drm_framebuffer *fb;
697 FBC_OK, /* FBC is enabled */
698 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
699 FBC_NO_OUTPUT, /* no outputs enabled to compress */
700 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
701 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
702 FBC_MODE_TOO_LARGE, /* mode too large for compression */
703 FBC_BAD_PLANE, /* fbc not supported on plane */
704 FBC_NOT_TILED, /* buffer not tiled */
705 FBC_MULTIPLE_PIPES, /* more than one pipe active */
707 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
717 PCH_NONE = 0, /* No PCH present */
718 PCH_IBX, /* Ibexpeak PCH */
719 PCH_CPT, /* Cougarpoint PCH */
720 PCH_LPT, /* Lynxpoint PCH */
724 enum intel_sbi_destination {
729 #define QUIRK_PIPEA_FORCE (1<<0)
730 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
731 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
734 struct intel_fbc_work;
737 struct i2c_adapter adapter;
741 struct i2c_algo_bit_data bit_algo;
742 struct drm_i915_private *dev_priv;
745 struct i915_suspend_saved_registers {
766 u32 saveTRANS_HTOTAL_A;
767 u32 saveTRANS_HBLANK_A;
768 u32 saveTRANS_HSYNC_A;
769 u32 saveTRANS_VTOTAL_A;
770 u32 saveTRANS_VBLANK_A;
771 u32 saveTRANS_VSYNC_A;
779 u32 savePFIT_PGM_RATIOS;
780 u32 saveBLC_HIST_CTL;
782 u32 saveBLC_PWM_CTL2;
783 u32 saveBLC_HIST_CTL_B;
784 u32 saveBLC_CPU_PWM_CTL;
785 u32 saveBLC_CPU_PWM_CTL2;
798 u32 saveTRANS_HTOTAL_B;
799 u32 saveTRANS_HBLANK_B;
800 u32 saveTRANS_HSYNC_B;
801 u32 saveTRANS_VTOTAL_B;
802 u32 saveTRANS_VBLANK_B;
803 u32 saveTRANS_VSYNC_B;
817 u32 savePP_ON_DELAYS;
818 u32 savePP_OFF_DELAYS;
826 u32 savePFIT_CONTROL;
827 u32 save_palette_a[256];
828 u32 save_palette_b[256];
829 u32 saveDPFC_CB_BASE;
830 u32 saveFBC_CFB_BASE;
833 u32 saveFBC_CONTROL2;
843 u32 saveCACHE_MODE_0;
844 u32 saveMI_ARB_STATE;
855 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
866 u32 savePIPEA_GMCH_DATA_M;
867 u32 savePIPEB_GMCH_DATA_M;
868 u32 savePIPEA_GMCH_DATA_N;
869 u32 savePIPEB_GMCH_DATA_N;
870 u32 savePIPEA_DP_LINK_M;
871 u32 savePIPEB_DP_LINK_M;
872 u32 savePIPEA_DP_LINK_N;
873 u32 savePIPEB_DP_LINK_N;
884 u32 savePCH_DREF_CONTROL;
885 u32 saveDISP_ARB_CTL;
886 u32 savePIPEA_DATA_M1;
887 u32 savePIPEA_DATA_N1;
888 u32 savePIPEA_LINK_M1;
889 u32 savePIPEA_LINK_N1;
890 u32 savePIPEB_DATA_M1;
891 u32 savePIPEB_DATA_N1;
892 u32 savePIPEB_LINK_M1;
893 u32 savePIPEB_LINK_N1;
894 u32 saveMCHBAR_RENDER_STANDBY;
895 u32 savePCH_PORT_HOTPLUG;
898 struct intel_gen6_power_mgmt {
899 /* work and pm_iir are protected by dev_priv->irq_lock */
900 struct work_struct work;
903 /* The below variables an all the rps hw state are protected by
904 * dev->struct mutext. */
914 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
917 struct delayed_work delayed_resume_work;
920 * Protects RPS/RC6 register access and PCU communication.
921 * Must be taken after struct_mutex if nested.
923 struct mutex hw_lock;
926 /* defined intel_pm.c */
927 extern spinlock_t mchdev_lock;
929 struct intel_ilk_power_mgmt {
937 unsigned long last_time1;
938 unsigned long chipset_power;
940 struct timespec last_time2;
941 unsigned long gfx_power;
947 struct drm_i915_gem_object *pwrctx;
948 struct drm_i915_gem_object *renderctx;
951 /* Power well structure for haswell */
952 struct i915_power_well {
953 /* power well enable/disable usage count */
957 #define I915_MAX_POWER_WELLS 1
959 struct i915_power_domains {
961 * Power wells needed for initialization at driver init and suspend
962 * time are on. They are kept on until after the first modeset.
967 struct i915_power_well power_wells[I915_MAX_POWER_WELLS];
970 struct i915_dri1_state {
971 unsigned allow_batchbuffer : 1;
972 u32 __iomem *gfx_hws_cpu_addr;
983 struct i915_ums_state {
985 * Flag if the X Server, and thus DRM, is not currently in
986 * control of the device.
988 * This is set between LeaveVT and EnterVT. It needs to be
989 * replaced with a semaphore. It also needs to be
990 * transitioned away from for kernel modesetting.
995 #define MAX_L3_SLICES 2
996 struct intel_l3_parity {
997 u32 *remap_info[MAX_L3_SLICES];
998 struct work_struct error_work;
1002 struct i915_gem_mm {
1003 /** Memory allocator for GTT stolen memory */
1004 struct drm_mm stolen;
1005 /** List of all objects in gtt_space. Used to restore gtt
1006 * mappings on resume */
1007 struct list_head bound_list;
1009 * List of objects which are not bound to the GTT (thus
1010 * are idle and not used by the GPU) but still have
1011 * (presumably uncached) pages still attached.
1013 struct list_head unbound_list;
1015 /** Usable portion of the GTT for GEM */
1016 unsigned long stolen_base; /* limited to low memory (32-bit) */
1018 /** PPGTT used for aliasing the PPGTT with the GTT */
1019 struct i915_hw_ppgtt *aliasing_ppgtt;
1021 struct shrinker inactive_shrinker;
1022 bool shrinker_no_lock_stealing;
1024 /** LRU list of objects with fence regs on them. */
1025 struct list_head fence_list;
1028 * We leave the user IRQ off as much as possible,
1029 * but this means that requests will finish and never
1030 * be retired once the system goes idle. Set a timer to
1031 * fire periodically while the ring is running. When it
1032 * fires, go retire requests.
1034 struct delayed_work retire_work;
1037 * When we detect an idle GPU, we want to turn on
1038 * powersaving features. So once we see that there
1039 * are no more requests outstanding and no more
1040 * arrive within a small period of time, we fire
1041 * off the idle_work.
1043 struct delayed_work idle_work;
1046 * Are we in a non-interruptible section of code like
1051 /** Bit 6 swizzling required for X tiling */
1052 uint32_t bit_6_swizzle_x;
1053 /** Bit 6 swizzling required for Y tiling */
1054 uint32_t bit_6_swizzle_y;
1056 /* storage for physical objects */
1057 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1059 /* accounting, useful for userland debugging */
1060 spinlock_t object_stat_lock;
1061 size_t object_memory;
1065 struct drm_i915_error_state_buf {
1074 struct i915_error_state_file_priv {
1075 struct drm_device *dev;
1076 struct drm_i915_error_state *error;
1079 struct i915_gpu_error {
1080 /* For hangcheck timer */
1081 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1082 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1083 /* Hang gpu twice in this window and your context gets banned */
1084 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1086 struct timer_list hangcheck_timer;
1088 /* For reset and error_state handling. */
1090 /* Protected by the above dev->gpu_error.lock. */
1091 struct drm_i915_error_state *first_error;
1092 struct work_struct work;
1095 unsigned long missed_irq_rings;
1098 * State variable controlling the reset flow and count
1100 * This is a counter which gets incremented when reset is triggered,
1101 * and again when reset has been handled. So odd values (lowest bit set)
1102 * means that reset is in progress and even values that
1103 * (reset_counter >> 1):th reset was successfully completed.
1105 * If reset is not completed succesfully, the I915_WEDGE bit is
1106 * set meaning that hardware is terminally sour and there is no
1107 * recovery. All waiters on the reset_queue will be woken when
1110 * This counter is used by the wait_seqno code to notice that reset
1111 * event happened and it needs to restart the entire ioctl (since most
1112 * likely the seqno it waited for won't ever signal anytime soon).
1114 * This is important for lock-free wait paths, where no contended lock
1115 * naturally enforces the correct ordering between the bail-out of the
1116 * waiter and the gpu reset work code.
1118 atomic_t reset_counter;
1120 #define I915_RESET_IN_PROGRESS_FLAG 1
1121 #define I915_WEDGED (1 << 31)
1124 * Waitqueue to signal when the reset has completed. Used by clients
1125 * that wait for dev_priv->mm.wedged to settle.
1127 wait_queue_head_t reset_queue;
1129 /* For gpu hang simulation. */
1130 unsigned int stop_rings;
1132 /* For missed irq/seqno simulation. */
1133 unsigned int test_irq_rings;
1136 enum modeset_restore {
1137 MODESET_ON_LID_OPEN,
1142 struct ddi_vbt_port_info {
1143 uint8_t hdmi_level_shift;
1145 uint8_t supports_dvi:1;
1146 uint8_t supports_hdmi:1;
1147 uint8_t supports_dp:1;
1150 struct intel_vbt_data {
1151 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1152 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1155 unsigned int int_tv_support:1;
1156 unsigned int lvds_dither:1;
1157 unsigned int lvds_vbt:1;
1158 unsigned int int_crt_support:1;
1159 unsigned int lvds_use_ssc:1;
1160 unsigned int display_clock_mode:1;
1161 unsigned int fdi_rx_polarity_inverted:1;
1163 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1168 int edp_preemphasis;
1170 bool edp_initialized;
1173 struct edp_power_seq edp_pps;
1183 union child_device_config *child_dev;
1185 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1188 enum intel_ddb_partitioning {
1190 INTEL_DDB_PART_5_6, /* IVB+ */
1193 struct intel_wm_level {
1201 struct hsw_wm_values {
1202 uint32_t wm_pipe[3];
1204 uint32_t wm_lp_spr[3];
1205 uint32_t wm_linetime[3];
1207 enum intel_ddb_partitioning partitioning;
1211 * This struct tracks the state needed for the Package C8+ feature.
1213 * Package states C8 and deeper are really deep PC states that can only be
1214 * reached when all the devices on the system allow it, so even if the graphics
1215 * device allows PC8+, it doesn't mean the system will actually get to these
1218 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1219 * is disabled and the GPU is idle. When these conditions are met, we manually
1220 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1223 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1224 * the state of some registers, so when we come back from PC8+ we need to
1225 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1226 * need to take care of the registers kept by RC6.
1228 * The interrupt disabling is part of the requirements. We can only leave the
1229 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1230 * can lock the machine.
1232 * Ideally every piece of our code that needs PC8+ disabled would call
1233 * hsw_disable_package_c8, which would increment disable_count and prevent the
1234 * system from reaching PC8+. But we don't have a symmetric way to do this for
1235 * everything, so we have the requirements_met and gpu_idle variables. When we
1236 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1237 * increase it in the opposite case. The requirements_met variable is true when
1238 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1239 * variable is true when the GPU is idle.
1241 * In addition to everything, we only actually enable PC8+ if disable_count
1242 * stays at zero for at least some seconds. This is implemented with the
1243 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1244 * consecutive times when all screens are disabled and some background app
1245 * queries the state of our connectors, or we have some application constantly
1246 * waking up to use the GPU. Only after the enable_work function actually
1247 * enables PC8+ the "enable" variable will become true, which means that it can
1248 * be false even if disable_count is 0.
1250 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1251 * goes back to false exactly before we reenable the IRQs. We use this variable
1252 * to check if someone is trying to enable/disable IRQs while they're supposed
1253 * to be disabled. This shouldn't happen and we'll print some error messages in
1254 * case it happens, but if it actually happens we'll also update the variables
1255 * inside struct regsave so when we restore the IRQs they will contain the
1256 * latest expected values.
1258 * For more, read "Display Sequences for Package C8" on our documentation.
1260 struct i915_package_c8 {
1261 bool requirements_met;
1264 /* Only true after the delayed work task actually enables it. */
1268 struct delayed_work enable_work;
1275 uint32_t gen6_pmimr;
1279 enum intel_pipe_crc_source {
1280 INTEL_PIPE_CRC_SOURCE_NONE,
1281 INTEL_PIPE_CRC_SOURCE_PLANE1,
1282 INTEL_PIPE_CRC_SOURCE_PLANE2,
1283 INTEL_PIPE_CRC_SOURCE_PF,
1284 INTEL_PIPE_CRC_SOURCE_PIPE,
1285 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1286 INTEL_PIPE_CRC_SOURCE_TV,
1287 INTEL_PIPE_CRC_SOURCE_DP_B,
1288 INTEL_PIPE_CRC_SOURCE_DP_C,
1289 INTEL_PIPE_CRC_SOURCE_DP_D,
1290 INTEL_PIPE_CRC_SOURCE_AUTO,
1291 INTEL_PIPE_CRC_SOURCE_MAX,
1294 struct intel_pipe_crc_entry {
1299 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1300 struct intel_pipe_crc {
1302 bool opened; /* exclusive access to the result file */
1303 struct intel_pipe_crc_entry *entries;
1304 enum intel_pipe_crc_source source;
1306 wait_queue_head_t wq;
1309 typedef struct drm_i915_private {
1310 struct drm_device *dev;
1311 struct kmem_cache *slab;
1313 const struct intel_device_info *info;
1315 int relative_constants_mode;
1319 struct intel_uncore uncore;
1321 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1324 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1325 * controller on different i2c buses. */
1326 struct mutex gmbus_mutex;
1329 * Base address of the gmbus and gpio block.
1331 uint32_t gpio_mmio_base;
1333 wait_queue_head_t gmbus_wait_queue;
1335 struct pci_dev *bridge_dev;
1336 struct intel_ring_buffer ring[I915_NUM_RINGS];
1337 uint32_t last_seqno, next_seqno;
1339 drm_dma_handle_t *status_page_dmah;
1340 struct resource mch_res;
1342 atomic_t irq_received;
1344 /* protects the irq masks */
1345 spinlock_t irq_lock;
1347 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1348 struct pm_qos_request pm_qos;
1350 /* DPIO indirect register protection */
1351 struct mutex dpio_lock;
1353 /** Cached value of IMR to avoid reads in updating the bitfield */
1356 u32 de_irq_mask[I915_MAX_PIPES];
1361 struct work_struct hotplug_work;
1362 bool enable_hotplug_processing;
1364 unsigned long hpd_last_jiffies;
1369 HPD_MARK_DISABLED = 2
1371 } hpd_stats[HPD_NUM_PINS];
1373 struct timer_list hotplug_reenable_timer;
1377 struct i915_fbc fbc;
1378 struct intel_opregion opregion;
1379 struct intel_vbt_data vbt;
1382 struct intel_overlay *overlay;
1383 unsigned int sprite_scaling_enabled;
1385 /* backlight registers and fields in struct intel_panel */
1386 spinlock_t backlight_lock;
1389 bool no_aux_handshake;
1391 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1392 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1393 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1395 unsigned int fsb_freq, mem_freq, is_ddr3;
1398 * wq - Driver workqueue for GEM.
1400 * NOTE: Work items scheduled here are not allowed to grab any modeset
1401 * locks, for otherwise the flushing done in the pageflip code will
1402 * result in deadlocks.
1404 struct workqueue_struct *wq;
1406 /* Display functions */
1407 struct drm_i915_display_funcs display;
1409 /* PCH chipset type */
1410 enum intel_pch pch_type;
1411 unsigned short pch_id;
1413 unsigned long quirks;
1415 enum modeset_restore modeset_restore;
1416 struct mutex modeset_restore_lock;
1418 struct list_head vm_list; /* Global list of all address spaces */
1419 struct i915_gtt gtt; /* VMA representing the global address space */
1421 struct i915_gem_mm mm;
1423 /* Kernel Modesetting */
1425 struct sdvo_device_mapping sdvo_mappings[2];
1427 struct drm_crtc *plane_to_crtc_mapping[3];
1428 struct drm_crtc *pipe_to_crtc_mapping[3];
1429 wait_queue_head_t pending_flip_queue;
1431 #ifdef CONFIG_DEBUG_FS
1432 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1435 int num_shared_dpll;
1436 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1437 struct intel_ddi_plls ddi_plls;
1438 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1440 /* Reclocking support */
1441 bool render_reclock_avail;
1442 bool lvds_downclock_avail;
1443 /* indicates the reduced downclock for LVDS*/
1447 bool mchbar_need_disable;
1449 struct intel_l3_parity l3_parity;
1451 /* Cannot be determined by PCIID. You must always read a register. */
1454 /* gen6+ rps state */
1455 struct intel_gen6_power_mgmt rps;
1457 /* ilk-only ips/rps state. Everything in here is protected by the global
1458 * mchdev_lock in intel_pm.c */
1459 struct intel_ilk_power_mgmt ips;
1461 struct i915_power_domains power_domains;
1463 struct i915_psr psr;
1465 struct i915_gpu_error gpu_error;
1467 struct drm_i915_gem_object *vlv_pctx;
1469 #ifdef CONFIG_DRM_I915_FBDEV
1470 /* list of fbdev register on this device */
1471 struct intel_fbdev *fbdev;
1475 * The console may be contended at resume, but we don't
1476 * want it to block on it.
1478 struct work_struct console_resume_work;
1480 struct drm_property *broadcast_rgb_property;
1481 struct drm_property *force_audio_property;
1483 uint32_t hw_context_size;
1484 struct list_head context_list;
1488 struct i915_suspend_saved_registers regfile;
1492 * Raw watermark latency values:
1493 * in 0.1us units for WM0,
1494 * in 0.5us units for WM1+.
1497 uint16_t pri_latency[5];
1499 uint16_t spr_latency[5];
1501 uint16_t cur_latency[5];
1503 /* current hardware state */
1504 struct hsw_wm_values hw;
1507 struct i915_package_c8 pc8;
1509 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1511 struct i915_dri1_state dri1;
1512 /* Old ums support infrastructure, same warning applies. */
1513 struct i915_ums_state ums;
1514 } drm_i915_private_t;
1516 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1518 return dev->dev_private;
1521 /* Iterate over initialised rings */
1522 #define for_each_ring(ring__, dev_priv__, i__) \
1523 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1524 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1526 enum hdmi_force_audio {
1527 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1528 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1529 HDMI_AUDIO_AUTO, /* trust EDID */
1530 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1533 #define I915_GTT_OFFSET_NONE ((u32)-1)
1535 struct drm_i915_gem_object_ops {
1536 /* Interface between the GEM object and its backing storage.
1537 * get_pages() is called once prior to the use of the associated set
1538 * of pages before to binding them into the GTT, and put_pages() is
1539 * called after we no longer need them. As we expect there to be
1540 * associated cost with migrating pages between the backing storage
1541 * and making them available for the GPU (e.g. clflush), we may hold
1542 * onto the pages after they are no longer referenced by the GPU
1543 * in case they may be used again shortly (for example migrating the
1544 * pages to a different memory domain within the GTT). put_pages()
1545 * will therefore most likely be called when the object itself is
1546 * being released or under memory pressure (where we attempt to
1547 * reap pages for the shrinker).
1549 int (*get_pages)(struct drm_i915_gem_object *);
1550 void (*put_pages)(struct drm_i915_gem_object *);
1553 struct drm_i915_gem_object {
1554 struct drm_gem_object base;
1556 const struct drm_i915_gem_object_ops *ops;
1558 /** List of VMAs backed by this object */
1559 struct list_head vma_list;
1561 /** Stolen memory for this object, instead of being backed by shmem. */
1562 struct drm_mm_node *stolen;
1563 struct list_head global_list;
1565 struct list_head ring_list;
1566 /** Used in execbuf to temporarily hold a ref */
1567 struct list_head obj_exec_link;
1570 * This is set if the object is on the active lists (has pending
1571 * rendering and so a non-zero seqno), and is not set if it i s on
1572 * inactive (ready to be unbound) list.
1574 unsigned int active:1;
1577 * This is set if the object has been written to since last bound
1580 unsigned int dirty:1;
1583 * Fence register bits (if any) for this object. Will be set
1584 * as needed when mapped into the GTT.
1585 * Protected by dev->struct_mutex.
1587 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1590 * Advice: are the backing pages purgeable?
1592 unsigned int madv:2;
1595 * Current tiling mode for the object.
1597 unsigned int tiling_mode:2;
1599 * Whether the tiling parameters for the currently associated fence
1600 * register have changed. Note that for the purposes of tracking
1601 * tiling changes we also treat the unfenced register, the register
1602 * slot that the object occupies whilst it executes a fenced
1603 * command (such as BLT on gen2/3), as a "fence".
1605 unsigned int fence_dirty:1;
1607 /** How many users have pinned this object in GTT space. The following
1608 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1609 * (via user_pin_count), execbuffer (objects are not allowed multiple
1610 * times for the same batchbuffer), and the framebuffer code. When
1611 * switching/pageflipping, the framebuffer code has at most two buffers
1614 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1615 * bits with absolutely no headroom. So use 4 bits. */
1616 unsigned int pin_count:4;
1617 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1620 * Is the object at the current location in the gtt mappable and
1621 * fenceable? Used to avoid costly recalculations.
1623 unsigned int map_and_fenceable:1;
1626 * Whether the current gtt mapping needs to be mappable (and isn't just
1627 * mappable by accident). Track pin and fault separate for a more
1628 * accurate mappable working set.
1630 unsigned int fault_mappable:1;
1631 unsigned int pin_mappable:1;
1632 unsigned int pin_display:1;
1635 * Is the GPU currently using a fence to access this buffer,
1637 unsigned int pending_fenced_gpu_access:1;
1638 unsigned int fenced_gpu_access:1;
1640 unsigned int cache_level:3;
1642 unsigned int has_aliasing_ppgtt_mapping:1;
1643 unsigned int has_global_gtt_mapping:1;
1644 unsigned int has_dma_mapping:1;
1646 struct sg_table *pages;
1647 int pages_pin_count;
1649 /* prime dma-buf support */
1650 void *dma_buf_vmapping;
1653 struct intel_ring_buffer *ring;
1655 /** Breadcrumb of last rendering to the buffer. */
1656 uint32_t last_read_seqno;
1657 uint32_t last_write_seqno;
1658 /** Breadcrumb of last fenced GPU access to the buffer. */
1659 uint32_t last_fenced_seqno;
1661 /** Current tiling stride for the object, if it's tiled. */
1664 /** References from framebuffers, locks out tiling changes. */
1665 unsigned long framebuffer_references;
1667 /** Record of address bit 17 of each page at last unbind. */
1668 unsigned long *bit_17;
1670 /** User space pin count and filp owning the pin */
1671 unsigned long user_pin_count;
1672 struct drm_file *pin_filp;
1674 /** for phy allocated objects */
1675 struct drm_i915_gem_phys_object *phys_obj;
1677 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1679 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1682 * Request queue structure.
1684 * The request queue allows us to note sequence numbers that have been emitted
1685 * and may be associated with active buffers to be retired.
1687 * By keeping this list, we can avoid having to do questionable
1688 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1689 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1691 struct drm_i915_gem_request {
1692 /** On Which ring this request was generated */
1693 struct intel_ring_buffer *ring;
1695 /** GEM sequence number associated with this request. */
1698 /** Position in the ringbuffer of the start of the request */
1701 /** Position in the ringbuffer of the end of the request */
1704 /** Context related to this request */
1705 struct i915_hw_context *ctx;
1707 /** Batch buffer related to this request if any */
1708 struct drm_i915_gem_object *batch_obj;
1710 /** Time at which this request was emitted, in jiffies. */
1711 unsigned long emitted_jiffies;
1713 /** global list entry for this request */
1714 struct list_head list;
1716 struct drm_i915_file_private *file_priv;
1717 /** file_priv list entry for this request */
1718 struct list_head client_list;
1721 struct drm_i915_file_private {
1722 struct drm_i915_private *dev_priv;
1726 struct list_head request_list;
1727 struct delayed_work idle_work;
1729 struct idr context_idr;
1731 struct i915_ctx_hang_stats hang_stats;
1732 atomic_t rps_wait_boost;
1735 #define INTEL_INFO(dev) (to_i915(dev)->info)
1737 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1738 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1739 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1740 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1741 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1742 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1743 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1744 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1745 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1746 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1747 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1748 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1749 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1750 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1751 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1752 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1753 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1754 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1755 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1756 (dev)->pdev->device == 0x0152 || \
1757 (dev)->pdev->device == 0x015a)
1758 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1759 (dev)->pdev->device == 0x0106 || \
1760 (dev)->pdev->device == 0x010A)
1761 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1762 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1763 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1764 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1765 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1766 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1767 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1768 (((dev)->pdev->device & 0xf) == 0x2 || \
1769 ((dev)->pdev->device & 0xf) == 0x6 || \
1770 ((dev)->pdev->device & 0xf) == 0xe))
1771 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1772 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1773 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1774 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1775 ((dev)->pdev->device & 0x00F0) == 0x0020)
1776 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1779 * The genX designation typically refers to the render engine, so render
1780 * capability related checks should use IS_GEN, while display and other checks
1781 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1784 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1785 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1786 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1787 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1788 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1789 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1790 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1792 #define RENDER_RING (1<<RCS)
1793 #define BSD_RING (1<<VCS)
1794 #define BLT_RING (1<<BCS)
1795 #define VEBOX_RING (1<<VECS)
1796 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1797 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1798 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1799 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1800 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1801 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1803 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1804 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1806 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1807 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1809 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1810 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1812 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1813 * rows, which changed the alignment requirements and fence programming.
1815 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1817 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1818 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1819 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1820 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1821 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1823 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1824 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1825 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1827 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1829 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1830 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1831 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1832 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1834 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1835 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1836 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1837 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1838 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1839 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1841 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1842 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1843 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1844 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1845 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1846 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1848 /* DPF == dynamic parity feature */
1849 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1850 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1852 #define GT_FREQUENCY_MULTIPLIER 50
1854 #include "i915_trace.h"
1856 extern const struct drm_ioctl_desc i915_ioctls[];
1857 extern int i915_max_ioctl;
1858 extern unsigned int i915_fbpercrtc __always_unused;
1859 extern int i915_panel_ignore_lid __read_mostly;
1860 extern unsigned int i915_powersave __read_mostly;
1861 extern int i915_semaphores __read_mostly;
1862 extern unsigned int i915_lvds_downclock __read_mostly;
1863 extern int i915_lvds_channel_mode __read_mostly;
1864 extern int i915_panel_use_ssc __read_mostly;
1865 extern int i915_vbt_sdvo_panel_type __read_mostly;
1866 extern int i915_enable_rc6 __read_mostly;
1867 extern int i915_enable_fbc __read_mostly;
1868 extern bool i915_enable_hangcheck __read_mostly;
1869 extern int i915_enable_ppgtt __read_mostly;
1870 extern int i915_enable_psr __read_mostly;
1871 extern unsigned int i915_preliminary_hw_support __read_mostly;
1872 extern int i915_disable_power_well __read_mostly;
1873 extern int i915_enable_ips __read_mostly;
1874 extern bool i915_fastboot __read_mostly;
1875 extern int i915_enable_pc8 __read_mostly;
1876 extern int i915_pc8_timeout __read_mostly;
1877 extern bool i915_prefault_disable __read_mostly;
1879 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1880 extern int i915_resume(struct drm_device *dev);
1881 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1882 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1885 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1886 extern void i915_kernel_lost_context(struct drm_device * dev);
1887 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1888 extern int i915_driver_unload(struct drm_device *);
1889 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1890 extern void i915_driver_lastclose(struct drm_device * dev);
1891 extern void i915_driver_preclose(struct drm_device *dev,
1892 struct drm_file *file_priv);
1893 extern void i915_driver_postclose(struct drm_device *dev,
1894 struct drm_file *file_priv);
1895 extern int i915_driver_device_is_agp(struct drm_device * dev);
1896 #ifdef CONFIG_COMPAT
1897 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1900 extern int i915_emit_box(struct drm_device *dev,
1901 struct drm_clip_rect *box,
1903 extern int intel_gpu_reset(struct drm_device *dev);
1904 extern int i915_reset(struct drm_device *dev);
1905 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1906 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1907 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1908 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1910 extern void intel_console_resume(struct work_struct *work);
1913 void i915_queue_hangcheck(struct drm_device *dev);
1914 void i915_handle_error(struct drm_device *dev, bool wedged);
1916 extern void intel_irq_init(struct drm_device *dev);
1917 extern void intel_pm_init(struct drm_device *dev);
1918 extern void intel_hpd_init(struct drm_device *dev);
1919 extern void intel_pm_init(struct drm_device *dev);
1921 extern void intel_uncore_sanitize(struct drm_device *dev);
1922 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1923 extern void intel_uncore_init(struct drm_device *dev);
1924 extern void intel_uncore_check_errors(struct drm_device *dev);
1925 extern void intel_uncore_fini(struct drm_device *dev);
1928 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1931 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1934 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1935 struct drm_file *file_priv);
1936 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1937 struct drm_file *file_priv);
1938 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1939 struct drm_file *file_priv);
1940 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1941 struct drm_file *file_priv);
1942 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *file_priv);
1944 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1945 struct drm_file *file_priv);
1946 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1947 struct drm_file *file_priv);
1948 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1949 struct drm_file *file_priv);
1950 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1951 struct drm_file *file_priv);
1952 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1953 struct drm_file *file_priv);
1954 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1955 struct drm_file *file_priv);
1956 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1957 struct drm_file *file_priv);
1958 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *file_priv);
1960 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1961 struct drm_file *file);
1962 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1963 struct drm_file *file);
1964 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *file_priv);
1966 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1967 struct drm_file *file_priv);
1968 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1969 struct drm_file *file_priv);
1970 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1971 struct drm_file *file_priv);
1972 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1973 struct drm_file *file_priv);
1974 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1975 struct drm_file *file_priv);
1976 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1977 struct drm_file *file_priv);
1978 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1979 struct drm_file *file_priv);
1980 void i915_gem_load(struct drm_device *dev);
1981 void *i915_gem_object_alloc(struct drm_device *dev);
1982 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1983 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1984 const struct drm_i915_gem_object_ops *ops);
1985 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1987 void i915_gem_free_object(struct drm_gem_object *obj);
1988 void i915_gem_vma_destroy(struct i915_vma *vma);
1990 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1991 struct i915_address_space *vm,
1993 bool map_and_fenceable,
1995 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1996 int __must_check i915_vma_unbind(struct i915_vma *vma);
1997 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
1998 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1999 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2000 void i915_gem_lastclose(struct drm_device *dev);
2002 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2003 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2005 struct sg_page_iter sg_iter;
2007 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2008 return sg_page_iter_page(&sg_iter);
2012 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2014 BUG_ON(obj->pages == NULL);
2015 obj->pages_pin_count++;
2017 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2019 BUG_ON(obj->pages_pin_count == 0);
2020 obj->pages_pin_count--;
2023 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2024 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2025 struct intel_ring_buffer *to);
2026 void i915_vma_move_to_active(struct i915_vma *vma,
2027 struct intel_ring_buffer *ring);
2028 int i915_gem_dumb_create(struct drm_file *file_priv,
2029 struct drm_device *dev,
2030 struct drm_mode_create_dumb *args);
2031 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2032 uint32_t handle, uint64_t *offset);
2034 * Returns true if seq1 is later than seq2.
2037 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2039 return (int32_t)(seq1 - seq2) >= 0;
2042 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2043 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2044 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2045 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2048 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2050 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2051 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2052 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2059 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2061 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2062 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2063 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2064 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2068 bool i915_gem_retire_requests(struct drm_device *dev);
2069 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2070 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2071 bool interruptible);
2072 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2074 return unlikely(atomic_read(&error->reset_counter)
2075 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2078 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2080 return atomic_read(&error->reset_counter) & I915_WEDGED;
2083 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2085 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2088 void i915_gem_reset(struct drm_device *dev);
2089 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2090 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2091 int __must_check i915_gem_init(struct drm_device *dev);
2092 int __must_check i915_gem_init_hw(struct drm_device *dev);
2093 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2094 void i915_gem_init_swizzling(struct drm_device *dev);
2095 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2096 int __must_check i915_gpu_idle(struct drm_device *dev);
2097 int __must_check i915_gem_suspend(struct drm_device *dev);
2098 int __i915_add_request(struct intel_ring_buffer *ring,
2099 struct drm_file *file,
2100 struct drm_i915_gem_object *batch_obj,
2102 #define i915_add_request(ring, seqno) \
2103 __i915_add_request(ring, NULL, NULL, seqno)
2104 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2106 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2108 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2111 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2113 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2115 struct intel_ring_buffer *pipelined);
2116 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2117 int i915_gem_attach_phys_object(struct drm_device *dev,
2118 struct drm_i915_gem_object *obj,
2121 void i915_gem_detach_phys_object(struct drm_device *dev,
2122 struct drm_i915_gem_object *obj);
2123 void i915_gem_free_all_phys_object(struct drm_device *dev);
2124 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2125 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2128 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2130 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2131 int tiling_mode, bool fenced);
2133 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2134 enum i915_cache_level cache_level);
2136 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2137 struct dma_buf *dma_buf);
2139 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2140 struct drm_gem_object *gem_obj, int flags);
2142 void i915_gem_restore_fences(struct drm_device *dev);
2144 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2145 struct i915_address_space *vm);
2146 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2147 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2148 struct i915_address_space *vm);
2149 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2150 struct i915_address_space *vm);
2151 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2152 struct i915_address_space *vm);
2154 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2155 struct i915_address_space *vm);
2157 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2159 /* Some GGTT VM helpers */
2160 #define obj_to_ggtt(obj) \
2161 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2162 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2164 struct i915_address_space *ggtt =
2165 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2169 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2171 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2174 static inline unsigned long
2175 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2177 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2180 static inline unsigned long
2181 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2183 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2186 static inline int __must_check
2187 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2189 bool map_and_fenceable,
2192 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2193 map_and_fenceable, nonblocking);
2196 /* i915_gem_context.c */
2197 int __must_check i915_gem_context_init(struct drm_device *dev);
2198 void i915_gem_context_fini(struct drm_device *dev);
2199 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2200 int i915_switch_context(struct intel_ring_buffer *ring,
2201 struct drm_file *file, int to_id);
2202 void i915_gem_context_free(struct kref *ctx_ref);
2203 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2205 kref_get(&ctx->ref);
2208 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2210 kref_put(&ctx->ref, i915_gem_context_free);
2213 struct i915_ctx_hang_stats * __must_check
2214 i915_gem_context_get_hang_stats(struct drm_device *dev,
2215 struct drm_file *file,
2217 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *file);
2219 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2220 struct drm_file *file);
2222 /* i915_gem_gtt.c */
2223 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
2224 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2225 struct drm_i915_gem_object *obj,
2226 enum i915_cache_level cache_level);
2227 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2228 struct drm_i915_gem_object *obj);
2230 void i915_check_and_clear_faults(struct drm_device *dev);
2231 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2232 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2233 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2234 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
2235 enum i915_cache_level cache_level);
2236 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
2237 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2238 void i915_gem_init_global_gtt(struct drm_device *dev);
2239 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2240 unsigned long mappable_end, unsigned long end);
2241 int i915_gem_gtt_init(struct drm_device *dev);
2242 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2244 if (INTEL_INFO(dev)->gen < 6)
2245 intel_gtt_chipset_flush();
2249 /* i915_gem_evict.c */
2250 int __must_check i915_gem_evict_something(struct drm_device *dev,
2251 struct i915_address_space *vm,
2254 unsigned cache_level,
2257 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2258 int i915_gem_evict_everything(struct drm_device *dev);
2260 /* i915_gem_stolen.c */
2261 int i915_gem_init_stolen(struct drm_device *dev);
2262 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2263 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2264 void i915_gem_cleanup_stolen(struct drm_device *dev);
2265 struct drm_i915_gem_object *
2266 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2267 struct drm_i915_gem_object *
2268 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2272 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2274 /* i915_gem_tiling.c */
2275 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2277 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2279 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2280 obj->tiling_mode != I915_TILING_NONE;
2283 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2284 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2285 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2287 /* i915_gem_debug.c */
2289 int i915_verify_lists(struct drm_device *dev);
2291 #define i915_verify_lists(dev) 0
2294 /* i915_debugfs.c */
2295 int i915_debugfs_init(struct drm_minor *minor);
2296 void i915_debugfs_cleanup(struct drm_minor *minor);
2297 #ifdef CONFIG_DEBUG_FS
2298 void intel_display_crc_init(struct drm_device *dev);
2300 static inline void intel_display_crc_init(struct drm_device *dev) {}
2303 /* i915_gpu_error.c */
2305 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2306 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2307 const struct i915_error_state_file_priv *error);
2308 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2309 size_t count, loff_t pos);
2310 static inline void i915_error_state_buf_release(
2311 struct drm_i915_error_state_buf *eb)
2315 void i915_capture_error_state(struct drm_device *dev);
2316 void i915_error_state_get(struct drm_device *dev,
2317 struct i915_error_state_file_priv *error_priv);
2318 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2319 void i915_destroy_error_state(struct drm_device *dev);
2321 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2322 const char *i915_cache_level_str(int type);
2324 /* i915_suspend.c */
2325 extern int i915_save_state(struct drm_device *dev);
2326 extern int i915_restore_state(struct drm_device *dev);
2329 void i915_save_display_reg(struct drm_device *dev);
2330 void i915_restore_display_reg(struct drm_device *dev);
2333 void i915_setup_sysfs(struct drm_device *dev_priv);
2334 void i915_teardown_sysfs(struct drm_device *dev_priv);
2337 extern int intel_setup_gmbus(struct drm_device *dev);
2338 extern void intel_teardown_gmbus(struct drm_device *dev);
2339 static inline bool intel_gmbus_is_port_valid(unsigned port)
2341 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2344 extern struct i2c_adapter *intel_gmbus_get_adapter(
2345 struct drm_i915_private *dev_priv, unsigned port);
2346 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2347 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2348 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2350 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2352 extern void intel_i2c_reset(struct drm_device *dev);
2354 /* intel_opregion.c */
2355 struct intel_encoder;
2356 extern int intel_opregion_setup(struct drm_device *dev);
2358 extern void intel_opregion_init(struct drm_device *dev);
2359 extern void intel_opregion_fini(struct drm_device *dev);
2360 extern void intel_opregion_asle_intr(struct drm_device *dev);
2361 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2363 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2366 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2367 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2368 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2370 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2375 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2383 extern void intel_register_dsm_handler(void);
2384 extern void intel_unregister_dsm_handler(void);
2386 static inline void intel_register_dsm_handler(void) { return; }
2387 static inline void intel_unregister_dsm_handler(void) { return; }
2388 #endif /* CONFIG_ACPI */
2391 extern void intel_modeset_init_hw(struct drm_device *dev);
2392 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2393 extern void intel_modeset_init(struct drm_device *dev);
2394 extern void intel_modeset_gem_init(struct drm_device *dev);
2395 extern void intel_modeset_cleanup(struct drm_device *dev);
2396 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2397 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2398 bool force_restore);
2399 extern void i915_redisable_vga(struct drm_device *dev);
2400 extern bool intel_fbc_enabled(struct drm_device *dev);
2401 extern void intel_disable_fbc(struct drm_device *dev);
2402 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2403 extern void intel_init_pch_refclk(struct drm_device *dev);
2404 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2405 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2406 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2407 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2408 extern void intel_detect_pch(struct drm_device *dev);
2409 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2410 extern int intel_enable_rc6(const struct drm_device *dev);
2412 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2413 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2414 struct drm_file *file);
2415 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2416 struct drm_file *file);
2419 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2420 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2421 struct intel_overlay_error_state *error);
2423 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2424 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2425 struct drm_device *dev,
2426 struct intel_display_error_state *error);
2428 /* On SNB platform, before reading ring registers forcewake bit
2429 * must be set to prevent GT core from power down and stale values being
2432 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2433 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2435 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2436 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2438 /* intel_sideband.c */
2439 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2440 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2441 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2442 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2443 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2444 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2445 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2446 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2447 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2448 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2449 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2450 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2451 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2452 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2453 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2454 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2455 enum intel_sbi_destination destination);
2456 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2457 enum intel_sbi_destination destination);
2459 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2460 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2462 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2463 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2465 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2466 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2467 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2468 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2470 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2471 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2472 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2473 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2475 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2476 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2478 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2479 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2481 /* "Broadcast RGB" property */
2482 #define INTEL_BROADCAST_RGB_AUTO 0
2483 #define INTEL_BROADCAST_RGB_FULL 1
2484 #define INTEL_BROADCAST_RGB_LIMITED 2
2486 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2488 if (HAS_PCH_SPLIT(dev))
2489 return CPU_VGACNTRL;
2490 else if (IS_VALLEYVIEW(dev))
2491 return VLV_VGACNTRL;
2496 static inline void __user *to_user_ptr(u64 address)
2498 return (void __user *)(uintptr_t)address;
2501 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2503 unsigned long j = msecs_to_jiffies(m);
2505 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2508 static inline unsigned long
2509 timespec_to_jiffies_timeout(const struct timespec *value)
2511 unsigned long j = timespec_to_jiffies(value);
2513 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);