1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
87 #define port_name(p) ((p) + 'A')
89 #define I915_GEM_GPU_DOMAINS \
90 (I915_GEM_DOMAIN_RENDER | \
91 I915_GEM_DOMAIN_SAMPLER | \
92 I915_GEM_DOMAIN_COMMAND | \
93 I915_GEM_DOMAIN_INSTRUCTION | \
94 I915_GEM_DOMAIN_VERTEX)
96 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
98 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
99 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
100 if ((intel_encoder)->base.crtc == (__crtc))
102 struct intel_pch_pll {
103 int refcount; /* count of number of CRTCs sharing this PLL */
104 int active; /* count of number of active CRTCs (i.e. DPMS on) */
105 bool on; /* is the PLL actually active? Disabled during modeset */
110 #define I915_NUM_PLLS 2
112 /* Used by dp and fdi links */
113 struct intel_link_m_n {
121 void intel_link_compute_m_n(int bpp, int nlanes,
122 int pixel_clock, int link_clock,
123 struct intel_link_m_n *m_n);
125 struct intel_ddi_plls {
131 /* Interface history:
134 * 1.2: Add Power Management
135 * 1.3: Add vblank support
136 * 1.4: Fix cmdbuffer path, add heap destroy
137 * 1.5: Add vblank pipe configuration
138 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
139 * - Support vertical blank on secondary display pipe
141 #define DRIVER_MAJOR 1
142 #define DRIVER_MINOR 6
143 #define DRIVER_PATCHLEVEL 0
145 #define WATCH_COHERENCY 0
146 #define WATCH_LISTS 0
149 #define I915_GEM_PHYS_CURSOR_0 1
150 #define I915_GEM_PHYS_CURSOR_1 2
151 #define I915_GEM_PHYS_OVERLAY_REGS 3
152 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
154 struct drm_i915_gem_phys_object {
156 struct page **page_list;
157 drm_dma_handle_t *handle;
158 struct drm_i915_gem_object *cur_obj;
161 struct opregion_header;
162 struct opregion_acpi;
163 struct opregion_swsci;
164 struct opregion_asle;
165 struct drm_i915_private;
167 struct intel_opregion {
168 struct opregion_header __iomem *header;
169 struct opregion_acpi __iomem *acpi;
170 struct opregion_swsci __iomem *swsci;
171 struct opregion_asle __iomem *asle;
173 u32 __iomem *lid_state;
175 #define OPREGION_SIZE (8*1024)
177 struct intel_overlay;
178 struct intel_overlay_error_state;
180 struct drm_i915_master_private {
181 drm_local_map_t *sarea;
182 struct _drm_i915_sarea *sarea_priv;
184 #define I915_FENCE_REG_NONE -1
185 #define I915_MAX_NUM_FENCES 16
186 /* 16 fences + sign bit for FENCE_REG_NONE */
187 #define I915_MAX_NUM_FENCE_BITS 5
189 struct drm_i915_fence_reg {
190 struct list_head lru_list;
191 struct drm_i915_gem_object *obj;
195 struct sdvo_device_mapping {
204 struct intel_display_error_state;
206 struct drm_i915_error_state {
212 bool waiting[I915_NUM_RINGS];
213 u32 pipestat[I915_MAX_PIPES];
214 u32 tail[I915_NUM_RINGS];
215 u32 head[I915_NUM_RINGS];
216 u32 ipeir[I915_NUM_RINGS];
217 u32 ipehr[I915_NUM_RINGS];
218 u32 instdone[I915_NUM_RINGS];
219 u32 acthd[I915_NUM_RINGS];
220 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
221 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
222 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
223 /* our own tracking of ring head and tail */
224 u32 cpu_ring_head[I915_NUM_RINGS];
225 u32 cpu_ring_tail[I915_NUM_RINGS];
226 u32 error; /* gen6+ */
227 u32 err_int; /* gen7 */
228 u32 instpm[I915_NUM_RINGS];
229 u32 instps[I915_NUM_RINGS];
230 u32 extra_instdone[I915_NUM_INSTDONE_REG];
231 u32 seqno[I915_NUM_RINGS];
233 u32 fault_reg[I915_NUM_RINGS];
235 u32 faddr[I915_NUM_RINGS];
236 u64 fence[I915_MAX_NUM_FENCES];
238 struct drm_i915_error_ring {
239 struct drm_i915_error_object {
243 } *ringbuffer, *batchbuffer;
244 struct drm_i915_error_request {
250 } ring[I915_NUM_RINGS];
251 struct drm_i915_error_buffer {
258 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
265 } *active_bo, *pinned_bo;
266 u32 active_bo_count, pinned_bo_count;
267 struct intel_overlay_error_state *overlay;
268 struct intel_display_error_state *display;
271 struct drm_i915_display_funcs {
272 bool (*fbc_enabled)(struct drm_device *dev);
273 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
274 void (*disable_fbc)(struct drm_device *dev);
275 int (*get_display_clock_speed)(struct drm_device *dev);
276 int (*get_fifo_size)(struct drm_device *dev, int plane);
277 void (*update_wm)(struct drm_device *dev);
278 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
279 uint32_t sprite_width, int pixel_size);
280 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
281 struct drm_display_mode *mode);
282 void (*modeset_global_resources)(struct drm_device *dev);
283 int (*crtc_mode_set)(struct drm_crtc *crtc,
284 struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode,
287 struct drm_framebuffer *old_fb);
288 void (*crtc_enable)(struct drm_crtc *crtc);
289 void (*crtc_disable)(struct drm_crtc *crtc);
290 void (*off)(struct drm_crtc *crtc);
291 void (*write_eld)(struct drm_connector *connector,
292 struct drm_crtc *crtc);
293 void (*fdi_link_train)(struct drm_crtc *crtc);
294 void (*init_clock_gating)(struct drm_device *dev);
295 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
296 struct drm_framebuffer *fb,
297 struct drm_i915_gem_object *obj);
298 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
300 void (*hpd_irq_setup)(struct drm_device *dev);
301 /* clock updates for mode set */
303 /* render clock increase/decrease */
304 /* display clock increase/decrease */
305 /* pll clock increase/decrease */
308 struct drm_i915_gt_funcs {
309 void (*force_wake_get)(struct drm_i915_private *dev_priv);
310 void (*force_wake_put)(struct drm_i915_private *dev_priv);
313 #define DEV_INFO_FLAGS \
314 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
315 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
316 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
317 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
318 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
319 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
320 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
321 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
322 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
323 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
324 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
325 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
326 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
327 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
328 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
329 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
330 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
331 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
332 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
333 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
334 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
335 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
336 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
337 DEV_INFO_FLAG(has_llc)
339 struct intel_device_info {
358 u8 cursor_needs_physical:1;
360 u8 overlay_needs_physical:1;
367 #define I915_PPGTT_PD_ENTRIES 512
368 #define I915_PPGTT_PT_ENTRIES 1024
369 struct i915_hw_ppgtt {
370 struct drm_device *dev;
371 unsigned num_pd_entries;
372 struct page **pt_pages;
374 dma_addr_t *pt_dma_addr;
375 dma_addr_t scratch_page_dma_addr;
379 /* This must match up with the value previously used for execbuf2.rsvd1. */
380 #define DEFAULT_CONTEXT_ID 0
381 struct i915_hw_context {
384 struct drm_i915_file_private *file_priv;
385 struct intel_ring_buffer *ring;
386 struct drm_i915_gem_object *obj;
390 FBC_NO_OUTPUT, /* no outputs enabled to compress */
391 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
392 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
393 FBC_MODE_TOO_LARGE, /* mode too large for compression */
394 FBC_BAD_PLANE, /* fbc not supported on plane */
395 FBC_NOT_TILED, /* buffer not tiled */
396 FBC_MULTIPLE_PIPES, /* more than one pipe active */
401 PCH_NONE = 0, /* No PCH present */
402 PCH_IBX, /* Ibexpeak PCH */
403 PCH_CPT, /* Cougarpoint PCH */
404 PCH_LPT, /* Lynxpoint PCH */
407 enum intel_sbi_destination {
412 #define QUIRK_PIPEA_FORCE (1<<0)
413 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
414 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
417 struct intel_fbc_work;
420 struct i2c_adapter adapter;
424 struct i2c_algo_bit_data bit_algo;
425 struct drm_i915_private *dev_priv;
428 struct i915_suspend_saved_registers {
449 u32 saveTRANS_HTOTAL_A;
450 u32 saveTRANS_HBLANK_A;
451 u32 saveTRANS_HSYNC_A;
452 u32 saveTRANS_VTOTAL_A;
453 u32 saveTRANS_VBLANK_A;
454 u32 saveTRANS_VSYNC_A;
462 u32 savePFIT_PGM_RATIOS;
463 u32 saveBLC_HIST_CTL;
465 u32 saveBLC_PWM_CTL2;
466 u32 saveBLC_CPU_PWM_CTL;
467 u32 saveBLC_CPU_PWM_CTL2;
480 u32 saveTRANS_HTOTAL_B;
481 u32 saveTRANS_HBLANK_B;
482 u32 saveTRANS_HSYNC_B;
483 u32 saveTRANS_VTOTAL_B;
484 u32 saveTRANS_VBLANK_B;
485 u32 saveTRANS_VSYNC_B;
499 u32 savePP_ON_DELAYS;
500 u32 savePP_OFF_DELAYS;
508 u32 savePFIT_CONTROL;
509 u32 save_palette_a[256];
510 u32 save_palette_b[256];
511 u32 saveDPFC_CB_BASE;
512 u32 saveFBC_CFB_BASE;
515 u32 saveFBC_CONTROL2;
525 u32 saveCACHE_MODE_0;
526 u32 saveMI_ARB_STATE;
537 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
548 u32 savePIPEA_GMCH_DATA_M;
549 u32 savePIPEB_GMCH_DATA_M;
550 u32 savePIPEA_GMCH_DATA_N;
551 u32 savePIPEB_GMCH_DATA_N;
552 u32 savePIPEA_DP_LINK_M;
553 u32 savePIPEB_DP_LINK_M;
554 u32 savePIPEA_DP_LINK_N;
555 u32 savePIPEB_DP_LINK_N;
566 u32 savePCH_DREF_CONTROL;
567 u32 saveDISP_ARB_CTL;
568 u32 savePIPEA_DATA_M1;
569 u32 savePIPEA_DATA_N1;
570 u32 savePIPEA_LINK_M1;
571 u32 savePIPEA_LINK_N1;
572 u32 savePIPEB_DATA_M1;
573 u32 savePIPEB_DATA_N1;
574 u32 savePIPEB_LINK_M1;
575 u32 savePIPEB_LINK_N1;
576 u32 saveMCHBAR_RENDER_STANDBY;
577 u32 savePCH_PORT_HOTPLUG;
580 struct intel_gen6_power_mgmt {
581 struct work_struct work;
583 /* lock - irqsave spinlock that protectects the work_struct and
587 /* The below variables an all the rps hw state are protected by
588 * dev->struct mutext. */
593 struct delayed_work delayed_resume_work;
596 * Protects RPS/RC6 register access and PCU communication.
597 * Must be taken after struct_mutex if nested.
599 struct mutex hw_lock;
602 /* defined intel_pm.c */
603 extern spinlock_t mchdev_lock;
605 struct intel_ilk_power_mgmt {
613 unsigned long last_time1;
614 unsigned long chipset_power;
616 struct timespec last_time2;
617 unsigned long gfx_power;
623 struct drm_i915_gem_object *pwrctx;
624 struct drm_i915_gem_object *renderctx;
627 struct i915_dri1_state {
628 unsigned allow_batchbuffer : 1;
629 u32 __iomem *gfx_hws_cpu_addr;
640 struct intel_l3_parity {
642 struct work_struct error_work;
645 typedef struct drm_i915_private {
646 struct drm_device *dev;
647 struct kmem_cache *slab;
649 const struct intel_device_info *info;
651 int relative_constants_mode;
655 struct drm_i915_gt_funcs gt;
656 /** gt_fifo_count and the subsequent register write are synchronized
657 * with dev->struct_mutex. */
658 unsigned gt_fifo_count;
659 /** forcewake_count is protected by gt_lock */
660 unsigned forcewake_count;
661 /** gt_lock is also taken in irq contexts. */
664 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
667 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
668 * controller on different i2c buses. */
669 struct mutex gmbus_mutex;
672 * Base address of the gmbus and gpio block.
674 uint32_t gpio_mmio_base;
676 wait_queue_head_t gmbus_wait_queue;
678 struct pci_dev *bridge_dev;
679 struct intel_ring_buffer ring[I915_NUM_RINGS];
680 uint32_t last_seqno, next_seqno;
682 drm_dma_handle_t *status_page_dmah;
683 struct resource mch_res;
685 atomic_t irq_received;
687 /* protects the irq masks */
690 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
691 struct pm_qos_request pm_qos;
693 /* DPIO indirect register protection */
694 struct mutex dpio_lock;
696 /** Cached value of IMR to avoid reads in updating the bitfield */
701 u32 hotplug_supported_mask;
702 struct work_struct hotplug_work;
703 bool enable_hotplug_processing;
708 /* For hangcheck timer */
709 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
710 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
711 struct timer_list hangcheck_timer;
713 uint32_t last_acthd[I915_NUM_RINGS];
714 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
716 unsigned int stop_rings;
718 unsigned long cfb_size;
720 enum plane cfb_plane;
722 struct intel_fbc_work *fbc_work;
724 struct intel_opregion opregion;
727 struct intel_overlay *overlay;
728 bool sprite_scaling_enabled;
731 int backlight_level; /* restore backlight to this value */
732 bool backlight_enabled;
733 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
734 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
736 /* Feature bits from the VBIOS */
737 unsigned int int_tv_support:1;
738 unsigned int lvds_dither:1;
739 unsigned int lvds_vbt:1;
740 unsigned int int_crt_support:1;
741 unsigned int lvds_use_ssc:1;
742 unsigned int display_clock_mode:1;
744 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
754 struct edp_power_seq pps;
756 bool no_aux_handshake;
759 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
760 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
761 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
763 unsigned int fsb_freq, mem_freq, is_ddr3;
765 spinlock_t error_lock;
766 /* Protected by dev->error_lock. */
767 struct drm_i915_error_state *first_error;
768 struct work_struct error_work;
769 struct completion error_completion;
770 struct workqueue_struct *wq;
772 /* Display functions */
773 struct drm_i915_display_funcs display;
775 /* PCH chipset type */
776 enum intel_pch pch_type;
777 unsigned short pch_id;
779 unsigned long quirks;
785 /** Bridge to intel-gtt-ko */
786 struct intel_gtt *gtt;
787 /** Memory allocator for GTT stolen memory */
788 struct drm_mm stolen;
789 /** Memory allocator for GTT */
790 struct drm_mm gtt_space;
791 /** List of all objects in gtt_space. Used to restore gtt
792 * mappings on resume */
793 struct list_head bound_list;
795 * List of objects which are not bound to the GTT (thus
796 * are idle and not used by the GPU) but still have
797 * (presumably uncached) pages still attached.
799 struct list_head unbound_list;
801 /** Usable portion of the GTT for GEM */
802 unsigned long gtt_start;
803 unsigned long gtt_mappable_end;
804 unsigned long gtt_end;
805 unsigned long stolen_base; /* limited to low memory (32-bit) */
807 /** "Graphics Stolen Memory" holds the global PTEs */
810 struct io_mapping *gtt_mapping;
811 phys_addr_t gtt_base_addr;
814 /** PPGTT used for aliasing the PPGTT with the GTT */
815 struct i915_hw_ppgtt *aliasing_ppgtt;
817 struct shrinker inactive_shrinker;
818 bool shrinker_no_lock_stealing;
821 * List of objects currently involved in rendering.
823 * Includes buffers having the contents of their GPU caches
824 * flushed, not necessarily primitives. last_rendering_seqno
825 * represents when the rendering involved will be completed.
827 * A reference is held on the buffer while on this list.
829 struct list_head active_list;
832 * LRU list of objects which are not in the ringbuffer and
833 * are ready to unbind, but are still in the GTT.
835 * last_rendering_seqno is 0 while an object is in this list.
837 * A reference is not held on the buffer while on this list,
838 * as merely being GTT-bound shouldn't prevent its being
839 * freed, and we'll pull it off the list in the free path.
841 struct list_head inactive_list;
843 /** LRU list of objects with fence regs on them. */
844 struct list_head fence_list;
847 * We leave the user IRQ off as much as possible,
848 * but this means that requests will finish and never
849 * be retired once the system goes idle. Set a timer to
850 * fire periodically while the ring is running. When it
851 * fires, go retire requests.
853 struct delayed_work retire_work;
856 * Are we in a non-interruptible section of code like
862 * Flag if the X Server, and thus DRM, is not currently in
863 * control of the device.
865 * This is set between LeaveVT and EnterVT. It needs to be
866 * replaced with a semaphore. It also needs to be
867 * transitioned away from for kernel modesetting.
872 * Flag if the hardware appears to be wedged.
874 * This is set when attempts to idle the device timeout.
875 * It prevents command submission from occurring and makes
876 * every pending request fail
880 /** Bit 6 swizzling required for X tiling */
881 uint32_t bit_6_swizzle_x;
882 /** Bit 6 swizzling required for Y tiling */
883 uint32_t bit_6_swizzle_y;
885 /* storage for physical objects */
886 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
888 /* accounting, useful for userland debugging */
890 size_t mappable_gtt_total;
891 size_t object_memory;
895 /* Kernel Modesetting */
897 struct sdvo_device_mapping sdvo_mappings[2];
898 /* indicate whether the LVDS_BORDER should be enabled or not */
899 unsigned int lvds_border_bits;
900 /* Panel fitter placement and size for Ironlake+ */
901 u32 pch_pf_pos, pch_pf_size;
903 struct drm_crtc *plane_to_crtc_mapping[3];
904 struct drm_crtc *pipe_to_crtc_mapping[3];
905 wait_queue_head_t pending_flip_queue;
907 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
908 struct intel_ddi_plls ddi_plls;
910 /* Reclocking support */
911 bool render_reclock_avail;
912 bool lvds_downclock_avail;
913 /* indicates the reduced downclock for LVDS*/
917 struct child_device_config *child_dev;
919 bool mchbar_need_disable;
921 struct intel_l3_parity l3_parity;
923 /* gen6+ rps state */
924 struct intel_gen6_power_mgmt rps;
926 /* ilk-only ips/rps state. Everything in here is protected by the global
927 * mchdev_lock in intel_pm.c */
928 struct intel_ilk_power_mgmt ips;
930 enum no_fbc_reason no_fbc_reason;
932 struct drm_mm_node *compressed_fb;
933 struct drm_mm_node *compressed_llb;
935 unsigned long last_gpu_reset;
937 /* list of fbdev register on this device */
938 struct intel_fbdev *fbdev;
941 * The console may be contended at resume, but we don't
942 * want it to block on it.
944 struct work_struct console_resume_work;
946 struct backlight_device *backlight;
948 struct drm_property *broadcast_rgb_property;
949 struct drm_property *force_audio_property;
951 bool hw_contexts_disabled;
952 uint32_t hw_context_size;
954 bool fdi_rx_polarity_reversed;
956 struct i915_suspend_saved_registers regfile;
958 /* Old dri1 support infrastructure, beware the dragons ya fools entering
960 struct i915_dri1_state dri1;
961 } drm_i915_private_t;
963 /* Iterate over initialised rings */
964 #define for_each_ring(ring__, dev_priv__, i__) \
965 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
966 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
968 enum hdmi_force_audio {
969 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
970 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
971 HDMI_AUDIO_AUTO, /* trust EDID */
972 HDMI_AUDIO_ON, /* force turn on HDMI audio */
975 enum i915_cache_level {
978 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
981 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
983 struct drm_i915_gem_object_ops {
984 /* Interface between the GEM object and its backing storage.
985 * get_pages() is called once prior to the use of the associated set
986 * of pages before to binding them into the GTT, and put_pages() is
987 * called after we no longer need them. As we expect there to be
988 * associated cost with migrating pages between the backing storage
989 * and making them available for the GPU (e.g. clflush), we may hold
990 * onto the pages after they are no longer referenced by the GPU
991 * in case they may be used again shortly (for example migrating the
992 * pages to a different memory domain within the GTT). put_pages()
993 * will therefore most likely be called when the object itself is
994 * being released or under memory pressure (where we attempt to
995 * reap pages for the shrinker).
997 int (*get_pages)(struct drm_i915_gem_object *);
998 void (*put_pages)(struct drm_i915_gem_object *);
1001 struct drm_i915_gem_object {
1002 struct drm_gem_object base;
1004 const struct drm_i915_gem_object_ops *ops;
1006 /** Current space allocated to this object in the GTT, if any. */
1007 struct drm_mm_node *gtt_space;
1008 /** Stolen memory for this object, instead of being backed by shmem. */
1009 struct drm_mm_node *stolen;
1010 struct list_head gtt_list;
1012 /** This object's place on the active/inactive lists */
1013 struct list_head ring_list;
1014 struct list_head mm_list;
1015 /** This object's place in the batchbuffer or on the eviction list */
1016 struct list_head exec_list;
1019 * This is set if the object is on the active lists (has pending
1020 * rendering and so a non-zero seqno), and is not set if it i s on
1021 * inactive (ready to be unbound) list.
1023 unsigned int active:1;
1026 * This is set if the object has been written to since last bound
1029 unsigned int dirty:1;
1032 * Fence register bits (if any) for this object. Will be set
1033 * as needed when mapped into the GTT.
1034 * Protected by dev->struct_mutex.
1036 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1039 * Advice: are the backing pages purgeable?
1041 unsigned int madv:2;
1044 * Current tiling mode for the object.
1046 unsigned int tiling_mode:2;
1048 * Whether the tiling parameters for the currently associated fence
1049 * register have changed. Note that for the purposes of tracking
1050 * tiling changes we also treat the unfenced register, the register
1051 * slot that the object occupies whilst it executes a fenced
1052 * command (such as BLT on gen2/3), as a "fence".
1054 unsigned int fence_dirty:1;
1056 /** How many users have pinned this object in GTT space. The following
1057 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1058 * (via user_pin_count), execbuffer (objects are not allowed multiple
1059 * times for the same batchbuffer), and the framebuffer code. When
1060 * switching/pageflipping, the framebuffer code has at most two buffers
1063 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1064 * bits with absolutely no headroom. So use 4 bits. */
1065 unsigned int pin_count:4;
1066 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1069 * Is the object at the current location in the gtt mappable and
1070 * fenceable? Used to avoid costly recalculations.
1072 unsigned int map_and_fenceable:1;
1075 * Whether the current gtt mapping needs to be mappable (and isn't just
1076 * mappable by accident). Track pin and fault separate for a more
1077 * accurate mappable working set.
1079 unsigned int fault_mappable:1;
1080 unsigned int pin_mappable:1;
1083 * Is the GPU currently using a fence to access this buffer,
1085 unsigned int pending_fenced_gpu_access:1;
1086 unsigned int fenced_gpu_access:1;
1088 unsigned int cache_level:2;
1090 unsigned int has_aliasing_ppgtt_mapping:1;
1091 unsigned int has_global_gtt_mapping:1;
1092 unsigned int has_dma_mapping:1;
1094 struct sg_table *pages;
1095 int pages_pin_count;
1097 /* prime dma-buf support */
1098 void *dma_buf_vmapping;
1102 * Used for performing relocations during execbuffer insertion.
1104 struct hlist_node exec_node;
1105 unsigned long exec_handle;
1106 struct drm_i915_gem_exec_object2 *exec_entry;
1109 * Current offset of the object in GTT space.
1111 * This is the same as gtt_space->start
1113 uint32_t gtt_offset;
1115 struct intel_ring_buffer *ring;
1117 /** Breadcrumb of last rendering to the buffer. */
1118 uint32_t last_read_seqno;
1119 uint32_t last_write_seqno;
1120 /** Breadcrumb of last fenced GPU access to the buffer. */
1121 uint32_t last_fenced_seqno;
1123 /** Current tiling stride for the object, if it's tiled. */
1126 /** Record of address bit 17 of each page at last unbind. */
1127 unsigned long *bit_17;
1129 /** User space pin count and filp owning the pin */
1130 uint32_t user_pin_count;
1131 struct drm_file *pin_filp;
1133 /** for phy allocated objects */
1134 struct drm_i915_gem_phys_object *phys_obj;
1137 * Number of crtcs where this object is currently the fb, but
1138 * will be page flipped away on the next vblank. When it
1139 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1141 atomic_t pending_flip;
1143 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1145 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1148 * Request queue structure.
1150 * The request queue allows us to note sequence numbers that have been emitted
1151 * and may be associated with active buffers to be retired.
1153 * By keeping this list, we can avoid having to do questionable
1154 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1155 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1157 struct drm_i915_gem_request {
1158 /** On Which ring this request was generated */
1159 struct intel_ring_buffer *ring;
1161 /** GEM sequence number associated with this request. */
1164 /** Postion in the ringbuffer of the end of the request */
1167 /** Time at which this request was emitted, in jiffies. */
1168 unsigned long emitted_jiffies;
1170 /** global list entry for this request */
1171 struct list_head list;
1173 struct drm_i915_file_private *file_priv;
1174 /** file_priv list entry for this request */
1175 struct list_head client_list;
1178 struct drm_i915_file_private {
1181 struct list_head request_list;
1183 struct idr context_idr;
1186 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1188 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1189 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1190 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1191 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1192 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1193 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1194 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1195 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1196 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1197 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1198 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1199 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1200 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1201 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1202 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1203 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1204 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1205 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1206 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1207 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1208 (dev)->pci_device == 0x0152 || \
1209 (dev)->pci_device == 0x015a)
1210 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1211 (dev)->pci_device == 0x0106 || \
1212 (dev)->pci_device == 0x010A)
1213 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1214 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1215 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1216 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1217 ((dev)->pci_device & 0xFF00) == 0x0A00)
1220 * The genX designation typically refers to the render engine, so render
1221 * capability related checks should use IS_GEN, while display and other checks
1222 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1225 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1226 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1227 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1228 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1229 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1230 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1232 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1233 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1234 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1235 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1237 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1238 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1240 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1241 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1243 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1244 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1246 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1247 * rows, which changed the alignment requirements and fence programming.
1249 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1251 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1252 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1253 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1254 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1255 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1256 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1257 /* dsparb controlled by hw only */
1258 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1260 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1261 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1262 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1264 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1266 #define HAS_DDI(dev) (IS_HASWELL(dev))
1268 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1269 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1270 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1271 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1272 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1273 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1275 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1276 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1277 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1278 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1279 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1281 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1283 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1285 #define GT_FREQUENCY_MULTIPLIER 50
1287 #include "i915_trace.h"
1290 * RC6 is a special power stage which allows the GPU to enter an very
1291 * low-voltage mode when idle, using down to 0V while at this stage. This
1292 * stage is entered automatically when the GPU is idle when RC6 support is
1293 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1295 * There are different RC6 modes available in Intel GPU, which differentiate
1296 * among each other with the latency required to enter and leave RC6 and
1297 * voltage consumed by the GPU in different states.
1299 * The combination of the following flags define which states GPU is allowed
1300 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1301 * RC6pp is deepest RC6. Their support by hardware varies according to the
1302 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1303 * which brings the most power savings; deeper states save more power, but
1304 * require higher latency to switch to and wake up.
1306 #define INTEL_RC6_ENABLE (1<<0)
1307 #define INTEL_RC6p_ENABLE (1<<1)
1308 #define INTEL_RC6pp_ENABLE (1<<2)
1310 extern struct drm_ioctl_desc i915_ioctls[];
1311 extern int i915_max_ioctl;
1312 extern unsigned int i915_fbpercrtc __always_unused;
1313 extern int i915_panel_ignore_lid __read_mostly;
1314 extern unsigned int i915_powersave __read_mostly;
1315 extern int i915_semaphores __read_mostly;
1316 extern unsigned int i915_lvds_downclock __read_mostly;
1317 extern int i915_lvds_channel_mode __read_mostly;
1318 extern int i915_panel_use_ssc __read_mostly;
1319 extern int i915_vbt_sdvo_panel_type __read_mostly;
1320 extern int i915_enable_rc6 __read_mostly;
1321 extern int i915_enable_fbc __read_mostly;
1322 extern bool i915_enable_hangcheck __read_mostly;
1323 extern int i915_enable_ppgtt __read_mostly;
1324 extern unsigned int i915_preliminary_hw_support __read_mostly;
1326 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1327 extern int i915_resume(struct drm_device *dev);
1328 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1329 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1332 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1333 extern void i915_kernel_lost_context(struct drm_device * dev);
1334 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1335 extern int i915_driver_unload(struct drm_device *);
1336 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1337 extern void i915_driver_lastclose(struct drm_device * dev);
1338 extern void i915_driver_preclose(struct drm_device *dev,
1339 struct drm_file *file_priv);
1340 extern void i915_driver_postclose(struct drm_device *dev,
1341 struct drm_file *file_priv);
1342 extern int i915_driver_device_is_agp(struct drm_device * dev);
1343 #ifdef CONFIG_COMPAT
1344 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1347 extern int i915_emit_box(struct drm_device *dev,
1348 struct drm_clip_rect *box,
1350 extern int intel_gpu_reset(struct drm_device *dev);
1351 extern int i915_reset(struct drm_device *dev);
1352 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1353 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1354 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1355 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1357 extern void intel_console_resume(struct work_struct *work);
1360 void i915_hangcheck_elapsed(unsigned long data);
1361 void i915_handle_error(struct drm_device *dev, bool wedged);
1363 extern void intel_irq_init(struct drm_device *dev);
1364 extern void intel_hpd_init(struct drm_device *dev);
1365 extern void intel_gt_init(struct drm_device *dev);
1366 extern void intel_gt_reset(struct drm_device *dev);
1368 void i915_error_state_free(struct kref *error_ref);
1371 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1374 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1376 void intel_enable_asle(struct drm_device *dev);
1378 #ifdef CONFIG_DEBUG_FS
1379 extern void i915_destroy_error_state(struct drm_device *dev);
1381 #define i915_destroy_error_state(x)
1386 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1387 struct drm_file *file_priv);
1388 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv);
1390 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file_priv);
1392 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv);
1394 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv);
1396 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1397 struct drm_file *file_priv);
1398 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1399 struct drm_file *file_priv);
1400 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1401 struct drm_file *file_priv);
1402 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1403 struct drm_file *file_priv);
1404 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1405 struct drm_file *file_priv);
1406 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1407 struct drm_file *file_priv);
1408 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1409 struct drm_file *file_priv);
1410 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1411 struct drm_file *file_priv);
1412 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1413 struct drm_file *file);
1414 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file);
1416 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1417 struct drm_file *file_priv);
1418 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1419 struct drm_file *file_priv);
1420 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1421 struct drm_file *file_priv);
1422 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1423 struct drm_file *file_priv);
1424 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1425 struct drm_file *file_priv);
1426 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1427 struct drm_file *file_priv);
1428 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *file_priv);
1430 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1431 struct drm_file *file_priv);
1432 void i915_gem_load(struct drm_device *dev);
1433 void *i915_gem_object_alloc(struct drm_device *dev);
1434 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1435 int i915_gem_init_object(struct drm_gem_object *obj);
1436 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1437 const struct drm_i915_gem_object_ops *ops);
1438 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1440 void i915_gem_free_object(struct drm_gem_object *obj);
1442 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1444 bool map_and_fenceable,
1446 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1447 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1448 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1449 void i915_gem_lastclose(struct drm_device *dev);
1451 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1452 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1454 struct scatterlist *sg = obj->pages->sgl;
1455 int nents = obj->pages->nents;
1456 while (nents > SG_MAX_SINGLE_ALLOC) {
1457 if (n < SG_MAX_SINGLE_ALLOC - 1)
1460 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1461 n -= SG_MAX_SINGLE_ALLOC - 1;
1462 nents -= SG_MAX_SINGLE_ALLOC - 1;
1464 return sg_page(sg+n);
1466 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1468 BUG_ON(obj->pages == NULL);
1469 obj->pages_pin_count++;
1471 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1473 BUG_ON(obj->pages_pin_count == 0);
1474 obj->pages_pin_count--;
1477 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1478 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1479 struct intel_ring_buffer *to);
1480 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1481 struct intel_ring_buffer *ring);
1483 int i915_gem_dumb_create(struct drm_file *file_priv,
1484 struct drm_device *dev,
1485 struct drm_mode_create_dumb *args);
1486 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1487 uint32_t handle, uint64_t *offset);
1488 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1491 * Returns true if seq1 is later than seq2.
1494 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1496 return (int32_t)(seq1 - seq2) >= 0;
1499 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1500 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1501 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1502 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1505 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1507 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1508 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1509 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1516 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1518 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1519 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1520 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1524 void i915_gem_retire_requests(struct drm_device *dev);
1525 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1526 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1527 bool interruptible);
1529 void i915_gem_reset(struct drm_device *dev);
1530 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1531 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1532 uint32_t read_domains,
1533 uint32_t write_domain);
1534 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1535 int __must_check i915_gem_init(struct drm_device *dev);
1536 int __must_check i915_gem_init_hw(struct drm_device *dev);
1537 void i915_gem_l3_remap(struct drm_device *dev);
1538 void i915_gem_init_swizzling(struct drm_device *dev);
1539 void i915_gem_init_ppgtt(struct drm_device *dev);
1540 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1541 int __must_check i915_gpu_idle(struct drm_device *dev);
1542 int __must_check i915_gem_idle(struct drm_device *dev);
1543 int i915_add_request(struct intel_ring_buffer *ring,
1544 struct drm_file *file,
1546 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1548 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1550 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1553 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1555 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1557 struct intel_ring_buffer *pipelined);
1558 int i915_gem_attach_phys_object(struct drm_device *dev,
1559 struct drm_i915_gem_object *obj,
1562 void i915_gem_detach_phys_object(struct drm_device *dev,
1563 struct drm_i915_gem_object *obj);
1564 void i915_gem_free_all_phys_object(struct drm_device *dev);
1565 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1568 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1570 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1571 int tiling_mode, bool fenced);
1573 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1574 enum i915_cache_level cache_level);
1576 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1577 struct dma_buf *dma_buf);
1579 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1580 struct drm_gem_object *gem_obj, int flags);
1582 /* i915_gem_context.c */
1583 void i915_gem_context_init(struct drm_device *dev);
1584 void i915_gem_context_fini(struct drm_device *dev);
1585 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1586 int i915_switch_context(struct intel_ring_buffer *ring,
1587 struct drm_file *file, int to_id);
1588 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1589 struct drm_file *file);
1590 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1591 struct drm_file *file);
1593 /* i915_gem_gtt.c */
1594 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1595 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1596 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1597 struct drm_i915_gem_object *obj,
1598 enum i915_cache_level cache_level);
1599 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1600 struct drm_i915_gem_object *obj);
1602 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1603 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1604 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1605 enum i915_cache_level cache_level);
1606 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1607 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1608 void i915_gem_init_global_gtt(struct drm_device *dev);
1609 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1610 unsigned long mappable_end, unsigned long end);
1611 int i915_gem_gtt_init(struct drm_device *dev);
1612 void i915_gem_gtt_fini(struct drm_device *dev);
1613 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1615 if (INTEL_INFO(dev)->gen < 6)
1616 intel_gtt_chipset_flush();
1620 /* i915_gem_evict.c */
1621 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1623 unsigned cache_level,
1626 int i915_gem_evict_everything(struct drm_device *dev);
1628 /* i915_gem_stolen.c */
1629 int i915_gem_init_stolen(struct drm_device *dev);
1630 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1631 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1632 void i915_gem_cleanup_stolen(struct drm_device *dev);
1633 struct drm_i915_gem_object *
1634 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1635 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1637 /* i915_gem_tiling.c */
1638 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1640 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1642 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1643 obj->tiling_mode != I915_TILING_NONE;
1646 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1647 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1648 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1650 /* i915_gem_debug.c */
1651 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1652 const char *where, uint32_t mark);
1654 int i915_verify_lists(struct drm_device *dev);
1656 #define i915_verify_lists(dev) 0
1658 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1660 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1661 const char *where, uint32_t mark);
1663 /* i915_debugfs.c */
1664 int i915_debugfs_init(struct drm_minor *minor);
1665 void i915_debugfs_cleanup(struct drm_minor *minor);
1667 /* i915_suspend.c */
1668 extern int i915_save_state(struct drm_device *dev);
1669 extern int i915_restore_state(struct drm_device *dev);
1671 /* i915_suspend.c */
1672 extern int i915_save_state(struct drm_device *dev);
1673 extern int i915_restore_state(struct drm_device *dev);
1676 void i915_setup_sysfs(struct drm_device *dev_priv);
1677 void i915_teardown_sysfs(struct drm_device *dev_priv);
1680 extern int intel_setup_gmbus(struct drm_device *dev);
1681 extern void intel_teardown_gmbus(struct drm_device *dev);
1682 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1684 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1687 extern struct i2c_adapter *intel_gmbus_get_adapter(
1688 struct drm_i915_private *dev_priv, unsigned port);
1689 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1690 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1691 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1693 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1695 extern void intel_i2c_reset(struct drm_device *dev);
1697 /* intel_opregion.c */
1698 extern int intel_opregion_setup(struct drm_device *dev);
1700 extern void intel_opregion_init(struct drm_device *dev);
1701 extern void intel_opregion_fini(struct drm_device *dev);
1702 extern void intel_opregion_asle_intr(struct drm_device *dev);
1703 extern void intel_opregion_gse_intr(struct drm_device *dev);
1704 extern void intel_opregion_enable_asle(struct drm_device *dev);
1706 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1707 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1708 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1709 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1710 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1715 extern void intel_register_dsm_handler(void);
1716 extern void intel_unregister_dsm_handler(void);
1718 static inline void intel_register_dsm_handler(void) { return; }
1719 static inline void intel_unregister_dsm_handler(void) { return; }
1720 #endif /* CONFIG_ACPI */
1723 extern void intel_modeset_init_hw(struct drm_device *dev);
1724 extern void intel_modeset_init(struct drm_device *dev);
1725 extern void intel_modeset_gem_init(struct drm_device *dev);
1726 extern void intel_modeset_cleanup(struct drm_device *dev);
1727 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1728 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1729 bool force_restore);
1730 extern bool intel_fbc_enabled(struct drm_device *dev);
1731 extern void intel_disable_fbc(struct drm_device *dev);
1732 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1733 extern void intel_init_pch_refclk(struct drm_device *dev);
1734 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1735 extern void intel_detect_pch(struct drm_device *dev);
1736 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1737 extern int intel_enable_rc6(const struct drm_device *dev);
1739 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1740 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1741 struct drm_file *file);
1744 #ifdef CONFIG_DEBUG_FS
1745 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1746 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1748 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1749 extern void intel_display_print_error_state(struct seq_file *m,
1750 struct drm_device *dev,
1751 struct intel_display_error_state *error);
1754 /* On SNB platform, before reading ring registers forcewake bit
1755 * must be set to prevent GT core from power down and stale values being
1758 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1759 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1760 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1762 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1763 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1765 #define __i915_read(x, y) \
1766 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1774 #define __i915_write(x, y) \
1775 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1783 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1784 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1786 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1787 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1788 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1789 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1791 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1792 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1793 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1794 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1796 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1797 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1799 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1800 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)