drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 i915_modparams.inject_load_failure = 0;
  71                 return true;
  72         }
  73
  74         return false;
  75 }
  76
  77 bool i915_error_injected(void)
  78 {
  79         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  80 }
  81
  82 #endif
  83
  84 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  85 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  86                     "providing the dmesg log by booting with drm.debug=0xf"
  87
  88 void
  89 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  90               const char *fmt, ...)
  91 {
  92         static bool shown_bug_once;
  93         struct device *kdev = dev_priv->drm.dev;
  94         bool is_error = level[1] <= KERN_ERR[1];
  95         bool is_debug = level[1] == KERN_DEBUG[1];
  96         struct va_format vaf;
  97         va_list args;
  98
  99         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 100                 return;
 101
 102         va_start(args, fmt);
 103
 104         vaf.fmt = fmt;
 105         vaf.va = &args;
 106
 107         if (is_error)
 108                 dev_printk(level, kdev, "%pV", &vaf);
 109         else
 110                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 111                            __builtin_return_address(0), &vaf);
 112
 113         va_end(args);
 114
 115         if (is_error && !shown_bug_once) {
 116                 /*
 117                  * Ask the user to file a bug report for the error, except
 118                  * if they may have caused the bug by fiddling with unsafe
 119                  * module parameters.
 120                  */
 121                 if (!test_taint(TAINT_USER))
 122                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 123                 shown_bug_once = true;
 124         }
 125 }
 126
 127 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 128 static enum intel_pch
 129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 130 {
 131         switch (id) {
 132         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 133                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 134                 WARN_ON(!IS_GEN5(dev_priv));
 135                 return PCH_IBX;
 136         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 137                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 138                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 139                 return PCH_CPT;
 140         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 141                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 142                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 143                 /* PantherPoint is CPT compatible */
 144                 return PCH_CPT;
 145         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 147                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 148                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 149                 return PCH_LPT;
 150         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 159                 /* WildcatPoint is LPT compatible */
 160                 return PCH_LPT;
 161         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 162                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 163                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 164                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 165                 /* WildcatPoint is LPT compatible */
 166                 return PCH_LPT;
 167         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 168                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 169                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 170                 return PCH_SPT;
 171         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 173                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 174                 return PCH_SPT;
 175         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 176                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 177                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 178                         !IS_COFFEELAKE(dev_priv));
 179                 return PCH_KBP;
 180         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 182                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 183                 return PCH_CNP;
 184         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 185                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 186                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 187                 return PCH_CNP;
 188         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 189                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 190                 WARN_ON(!IS_ICELAKE(dev_priv));
 191                 return PCH_ICP;
 192         default:
 193                 return PCH_NONE;
 194         }
 195 }
 196
 197 static bool intel_is_virt_pch(unsigned short id,
 198                               unsigned short svendor, unsigned short sdevice)
 199 {
 200         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 201                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 202                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 203                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 204                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 205 }
 206
 207 static unsigned short
 208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 209 {
 210         unsigned short id = 0;
 211
 212         /*
 213          * In a virtualized passthrough environment we can be in a
 214          * setup where the ISA bridge is not able to be passed through.
 215          * In this case, a south bridge can be emulated and we have to
 216          * make an educated guess as to which PCH is really there.
 217          */
 218
 219         if (IS_GEN5(dev_priv))
 220                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 221         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 222                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 223         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 224                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 225         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 226                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 227         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 228                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 229         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 231         else if (IS_ICELAKE(dev_priv))
 232                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 233
 234         if (id)
 235                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 236         else
 237                 DRM_DEBUG_KMS("Assuming no PCH\n");
 238
 239         return id;
 240 }
 241
 242 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 243 {
 244         struct pci_dev *pch = NULL;
 245
 246         /*
 247          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 248          * make graphics device passthrough work easy for VMM, that only
 249          * need to expose ISA bridge to let driver know the real hardware
 250          * underneath. This is a requirement from virtualization team.
 251          *
 252          * In some virtualized environments (e.g. XEN), there is irrelevant
 253          * ISA bridge in the system. To work reliably, we should scan trhough
 254          * all the ISA bridge devices and check for the first match, instead
 255          * of only checking the first one.
 256          */
 257         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 258                 unsigned short id;
 259                 enum intel_pch pch_type;
 260
 261                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 262                         continue;
 263
 264                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 265
 266                 pch_type = intel_pch_type(dev_priv, id);
 267                 if (pch_type != PCH_NONE) {
 268                         dev_priv->pch_type = pch_type;
 269                         dev_priv->pch_id = id;
 270                         break;
 271                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 272                                          pch->subsystem_device)) {
 273                         id = intel_virt_detect_pch(dev_priv);
 274                         pch_type = intel_pch_type(dev_priv, id);
 275
 276                         /* Sanity check virtual PCH id */
 277                         if (WARN_ON(id && pch_type == PCH_NONE))
 278                                 id = 0;
 279
 280                         dev_priv->pch_type = pch_type;
 281                         dev_priv->pch_id = id;
 282                         break;
 283                 }
 284         }
 285
 286         /*
 287          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 288          * display.
 289          */
 290         if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
 291                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 292                 dev_priv->pch_type = PCH_NOP;
 293                 dev_priv->pch_id = 0;
 294         }
 295
 296         if (!pch)
 297                 DRM_DEBUG_KMS("No PCH found.\n");
 298
 299         pci_dev_put(pch);
 300 }
 301
 302 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 303                                struct drm_file *file_priv)
 304 {
 305         struct drm_i915_private *dev_priv = to_i915(dev);
 306         struct pci_dev *pdev = dev_priv->drm.pdev;
 307         drm_i915_getparam_t *param = data;
 308         int value;
 309
 310         switch (param->param) {
 311         case I915_PARAM_IRQ_ACTIVE:
 312         case I915_PARAM_ALLOW_BATCHBUFFER:
 313         case I915_PARAM_LAST_DISPATCH:
 314         case I915_PARAM_HAS_EXEC_CONSTANTS:
 315                 /* Reject all old ums/dri params. */
 316                 return -ENODEV;
 317         case I915_PARAM_CHIPSET_ID:
 318                 value = pdev->device;
 319                 break;
 320         case I915_PARAM_REVISION:
 321                 value = pdev->revision;
 322                 break;
 323         case I915_PARAM_NUM_FENCES_AVAIL:
 324                 value = dev_priv->num_fence_regs;
 325                 break;
 326         case I915_PARAM_HAS_OVERLAY:
 327                 value = dev_priv->overlay ? 1 : 0;
 328                 break;
 329         case I915_PARAM_HAS_BSD:
 330                 value = !!dev_priv->engine[VCS];
 331                 break;
 332         case I915_PARAM_HAS_BLT:
 333                 value = !!dev_priv->engine[BCS];
 334                 break;
 335         case I915_PARAM_HAS_VEBOX:
 336                 value = !!dev_priv->engine[VECS];
 337                 break;
 338         case I915_PARAM_HAS_BSD2:
 339                 value = !!dev_priv->engine[VCS2];
 340                 break;
 341         case I915_PARAM_HAS_LLC:
 342                 value = HAS_LLC(dev_priv);
 343                 break;
 344         case I915_PARAM_HAS_WT:
 345                 value = HAS_WT(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_ALIASING_PPGTT:
 348                 value = USES_PPGTT(dev_priv);
 349                 break;
 350         case I915_PARAM_HAS_SEMAPHORES:
 351                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 352                 break;
 353         case I915_PARAM_HAS_SECURE_BATCHES:
 354                 value = capable(CAP_SYS_ADMIN);
 355                 break;
 356         case I915_PARAM_CMD_PARSER_VERSION:
 357                 value = i915_cmd_parser_get_version(dev_priv);
 358                 break;
 359         case I915_PARAM_SUBSLICE_TOTAL:
 360                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_EU_TOTAL:
 365                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 366                 if (!value)
 367                         return -ENODEV;
 368                 break;
 369         case I915_PARAM_HAS_GPU_RESET:
 370                 value = i915_modparams.enable_hangcheck &&
 371                         intel_has_gpu_reset(dev_priv);
 372                 if (value && intel_has_reset_engine(dev_priv))
 373                         value = 2;
 374                 break;
 375         case I915_PARAM_HAS_RESOURCE_STREAMER:
 376                 value = HAS_RESOURCE_STREAMER(dev_priv);
 377                 break;
 378         case I915_PARAM_HAS_POOLED_EU:
 379                 value = HAS_POOLED_EU(dev_priv);
 380                 break;
 381         case I915_PARAM_MIN_EU_IN_POOL:
 382                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 383                 break;
 384         case I915_PARAM_HUC_STATUS:
 385                 value = intel_huc_check_status(&dev_priv->huc);
 386                 if (value < 0)
 387                         return value;
 388                 break;
 389         case I915_PARAM_MMAP_GTT_VERSION:
 390                 /* Though we've started our numbering from 1, and so class all
 391                  * earlier versions as 0, in effect their value is undefined as
 392                  * the ioctl will report EINVAL for the unknown param!
 393                  */
 394                 value = i915_gem_mmap_gtt_version();
 395                 break;
 396         case I915_PARAM_HAS_SCHEDULER:
 397                 value = dev_priv->caps.scheduler;
 398                 break;
 399
 400         case I915_PARAM_MMAP_VERSION:
 401                 /* Remember to bump this if the version changes! */
 402         case I915_PARAM_HAS_GEM:
 403         case I915_PARAM_HAS_PAGEFLIPPING:
 404         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 405         case I915_PARAM_HAS_RELAXED_FENCING:
 406         case I915_PARAM_HAS_COHERENT_RINGS:
 407         case I915_PARAM_HAS_RELAXED_DELTA:
 408         case I915_PARAM_HAS_GEN7_SOL_RESET:
 409         case I915_PARAM_HAS_WAIT_TIMEOUT:
 410         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 411         case I915_PARAM_HAS_PINNED_BATCHES:
 412         case I915_PARAM_HAS_EXEC_NO_RELOC:
 413         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 414         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 415         case I915_PARAM_HAS_EXEC_SOFTPIN:
 416         case I915_PARAM_HAS_EXEC_ASYNC:
 417         case I915_PARAM_HAS_EXEC_FENCE:
 418         case I915_PARAM_HAS_EXEC_CAPTURE:
 419         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 420         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 421                 /* For the time being all of these are always true;
 422                  * if some supported hardware does not have one of these
 423                  * features this value needs to be provided from
 424                  * INTEL_INFO(), a feature macro, or similar.
 425                  */
 426                 value = 1;
 427                 break;
 428         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 429                 value = intel_engines_has_context_isolation(dev_priv);
 430                 break;
 431         case I915_PARAM_SLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_SUBSLICE_MASK:
 437                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 438                 if (!value)
 439                         return -ENODEV;
 440                 break;
 441         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 442                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 443                 break;
 444         default:
 445                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 446                 return -EINVAL;
 447         }
 448
 449         if (put_user(value, param->value))
 450                 return -EFAULT;
 451
 452         return 0;
 453 }
 454
 455 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 456 {
 457         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 458
 459         dev_priv->bridge_dev =
 460                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 461         if (!dev_priv->bridge_dev) {
 462                 DRM_ERROR("bridge device not found\n");
 463                 return -1;
 464         }
 465         return 0;
 466 }
 467
 468 /* Allocate space for the MCH regs if needed, return nonzero on error */
 469 static int
 470 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 471 {
 472         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 473         u32 temp_lo, temp_hi = 0;
 474         u64 mchbar_addr;
 475         int ret;
 476
 477         if (INTEL_GEN(dev_priv) >= 4)
 478                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 479         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 480         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 481
 482         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 483 #ifdef CONFIG_PNP
 484         if (mchbar_addr &&
 485             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 486                 return 0;
 487 #endif
 488
 489         /* Get some space for it */
 490         dev_priv->mch_res.name = "i915 MCHBAR";
 491         dev_priv->mch_res.flags = IORESOURCE_MEM;
 492         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 493                                      &dev_priv->mch_res,
 494                                      MCHBAR_SIZE, MCHBAR_SIZE,
 495                                      PCIBIOS_MIN_MEM,
 496                                      0, pcibios_align_resource,
 497                                      dev_priv->bridge_dev);
 498         if (ret) {
 499                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 500                 dev_priv->mch_res.start = 0;
 501                 return ret;
 502         }
 503
 504         if (INTEL_GEN(dev_priv) >= 4)
 505                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 506                                        upper_32_bits(dev_priv->mch_res.start));
 507
 508         pci_write_config_dword(dev_priv->bridge_dev, reg,
 509                                lower_32_bits(dev_priv->mch_res.start));
 510         return 0;
 511 }
 512
 513 /* Setup MCHBAR if possible, return true if we should disable it again */
 514 static void
 515 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 516 {
 517         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 518         u32 temp;
 519         bool enabled;
 520
 521         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 522                 return;
 523
 524         dev_priv->mchbar_need_disable = false;
 525
 526         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 527                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 528                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 529         } else {
 530                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 531                 enabled = temp & 1;
 532         }
 533
 534         /* If it's already enabled, don't have to do anything */
 535         if (enabled)
 536                 return;
 537
 538         if (intel_alloc_mchbar_resource(dev_priv))
 539                 return;
 540
 541         dev_priv->mchbar_need_disable = true;
 542
 543         /* Space is allocated or reserved, so enable it. */
 544         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 545                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 546                                        temp | DEVEN_MCHBAR_EN);
 547         } else {
 548                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 549                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 550         }
 551 }
 552
 553 static void
 554 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 555 {
 556         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 557
 558         if (dev_priv->mchbar_need_disable) {
 559                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 560                         u32 deven_val;
 561
 562                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 563                                               &deven_val);
 564                         deven_val &= ~DEVEN_MCHBAR_EN;
 565                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 566                                                deven_val);
 567                 } else {
 568                         u32 mchbar_val;
 569
 570                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 571                                               &mchbar_val);
 572                         mchbar_val &= ~1;
 573                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 574                                                mchbar_val);
 575                 }
 576         }
 577
 578         if (dev_priv->mch_res.start)
 579                 release_resource(&dev_priv->mch_res);
 580 }
 581
 582 /* true = enable decode, false = disable decoder */
 583 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 584 {
 585         struct drm_i915_private *dev_priv = cookie;
 586
 587         intel_modeset_vga_set_state(dev_priv, state);
 588         if (state)
 589                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 590                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 591         else
 592                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 593 }
 594
 595 static int i915_resume_switcheroo(struct drm_device *dev);
 596 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 597
 598 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 599 {
 600         struct drm_device *dev = pci_get_drvdata(pdev);
 601         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 602
 603         if (state == VGA_SWITCHEROO_ON) {
 604                 pr_info("switched on\n");
 605                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 606                 /* i915 resume handler doesn't set to D0 */
 607                 pci_set_power_state(pdev, PCI_D0);
 608                 i915_resume_switcheroo(dev);
 609                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 610         } else {
 611                 pr_info("switched off\n");
 612                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 613                 i915_suspend_switcheroo(dev, pmm);
 614                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 615         }
 616 }
 617
 618 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 619 {
 620         struct drm_device *dev = pci_get_drvdata(pdev);
 621
 622         /*
 623          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 624          * locking inversion with the driver load path. And the access here is
 625          * completely racy anyway. So don't bother with locking for now.
 626          */
 627         return dev->open_count == 0;
 628 }
 629
 630 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 631         .set_gpu_state = i915_switcheroo_set_state,
 632         .reprobe = NULL,
 633         .can_switch = i915_switcheroo_can_switch,
 634 };
 635
 636 static int i915_load_modeset_init(struct drm_device *dev)
 637 {
 638         struct drm_i915_private *dev_priv = to_i915(dev);
 639         struct pci_dev *pdev = dev_priv->drm.pdev;
 640         int ret;
 641
 642         if (i915_inject_load_failure())
 643                 return -ENODEV;
 644
 645         intel_bios_init(dev_priv);
 646
 647         /* If we have > 1 VGA cards, then we need to arbitrate access
 648          * to the common VGA resources.
 649          *
 650          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 651          * then we do not take part in VGA arbitration and the
 652          * vga_client_register() fails with -ENODEV.
 653          */
 654         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 655         if (ret && ret != -ENODEV)
 656                 goto out;
 657
 658         intel_register_dsm_handler();
 659
 660         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 661         if (ret)
 662                 goto cleanup_vga_client;
 663
 664         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 665         intel_update_rawclk(dev_priv);
 666
 667         intel_power_domains_init_hw(dev_priv, false);
 668
 669         intel_csr_ucode_init(dev_priv);
 670
 671         ret = intel_irq_install(dev_priv);
 672         if (ret)
 673                 goto cleanup_csr;
 674
 675         intel_setup_gmbus(dev_priv);
 676
 677         /* Important: The output setup functions called by modeset_init need
 678          * working irqs for e.g. gmbus and dp aux transfers. */
 679         ret = intel_modeset_init(dev);
 680         if (ret)
 681                 goto cleanup_irq;
 682
 683         ret = i915_gem_init(dev_priv);
 684         if (ret)
 685                 goto cleanup_modeset;
 686
 687         intel_setup_overlay(dev_priv);
 688
 689         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 690                 return 0;
 691
 692         ret = intel_fbdev_init(dev);
 693         if (ret)
 694                 goto cleanup_gem;
 695
 696         /* Only enable hotplug handling once the fbdev is fully set up. */
 697         intel_hpd_init(dev_priv);
 698
 699         return 0;
 700
 701 cleanup_gem:
 702         if (i915_gem_suspend(dev_priv))
 703                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 704         i915_gem_fini(dev_priv);
 705 cleanup_modeset:
 706         intel_modeset_cleanup(dev);
 707 cleanup_irq:
 708         drm_irq_uninstall(dev);
 709         intel_teardown_gmbus(dev_priv);
 710 cleanup_csr:
 711         intel_csr_ucode_fini(dev_priv);
 712         intel_power_domains_fini(dev_priv);
 713         vga_switcheroo_unregister_client(pdev);
 714 cleanup_vga_client:
 715         vga_client_register(pdev, NULL, NULL, NULL);
 716 out:
 717         return ret;
 718 }
 719
 720 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 721 {
 722         struct apertures_struct *ap;
 723         struct pci_dev *pdev = dev_priv->drm.pdev;
 724         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 725         bool primary;
 726         int ret;
 727
 728         ap = alloc_apertures(1);
 729         if (!ap)
 730                 return -ENOMEM;
 731
 732         ap->ranges[0].base = ggtt->gmadr.start;
 733         ap->ranges[0].size = ggtt->mappable_end;
 734
 735         primary =
 736                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 737
 738         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 739
 740         kfree(ap);
 741
 742         return ret;
 743 }
 744
 745 #if !defined(CONFIG_VGA_CONSOLE)
 746 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 747 {
 748         return 0;
 749 }
 750 #elif !defined(CONFIG_DUMMY_CONSOLE)
 751 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 752 {
 753         return -ENODEV;
 754 }
 755 #else
 756 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 757 {
 758         int ret = 0;
 759
 760         DRM_INFO("Replacing VGA console driver\n");
 761
 762         console_lock();
 763         if (con_is_bound(&vga_con))
 764                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 765         if (ret == 0) {
 766                 ret = do_unregister_con_driver(&vga_con);
 767
 768                 /* Ignore "already unregistered". */
 769                 if (ret == -ENODEV)
 770                         ret = 0;
 771         }
 772         console_unlock();
 773
 774         return ret;
 775 }
 776 #endif
 777
 778 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 779 {
 780         /*
 781          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 782          * CHV x1 PHY (DP/HDMI D)
 783          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 784          */
 785         if (IS_CHERRYVIEW(dev_priv)) {
 786                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 787                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 788         } else if (IS_VALLEYVIEW(dev_priv)) {
 789                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 790         }
 791 }
 792
 793 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 794 {
 795         /*
 796          * The i915 workqueue is primarily used for batched retirement of
 797          * requests (and thus managing bo) once the task has been completed
 798          * by the GPU. i915_retire_requests() is called directly when we
 799          * need high-priority retirement, such as waiting for an explicit
 800          * bo.
 801          *
 802          * It is also used for periodic low-priority events, such as
 803          * idle-timers and recording error state.
 804          *
 805          * All tasks on the workqueue are expected to acquire the dev mutex
 806          * so there is no point in running more than one instance of the
 807          * workqueue at any time.  Use an ordered one.
 808          */
 809         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 810         if (dev_priv->wq == NULL)
 811                 goto out_err;
 812
 813         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 814         if (dev_priv->hotplug.dp_wq == NULL)
 815                 goto out_free_wq;
 816
 817         return 0;
 818
 819 out_free_wq:
 820         destroy_workqueue(dev_priv->wq);
 821 out_err:
 822         DRM_ERROR("Failed to allocate workqueues.\n");
 823
 824         return -ENOMEM;
 825 }
 826
 827 static void i915_engines_cleanup(struct drm_i915_private *i915)
 828 {
 829         struct intel_engine_cs *engine;
 830         enum intel_engine_id id;
 831
 832         for_each_engine(engine, i915, id)
 833                 kfree(engine);
 834 }
 835
 836 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 837 {
 838         destroy_workqueue(dev_priv->hotplug.dp_wq);
 839         destroy_workqueue(dev_priv->wq);
 840 }
 841
 842 /*
 843  * We don't keep the workarounds for pre-production hardware, so we expect our
 844  * driver to fail on these machines in one way or another. A little warning on
 845  * dmesg may help both the user and the bug triagers.
 846  *
 847  * Our policy for removing pre-production workarounds is to keep the
 848  * current gen workarounds as a guide to the bring-up of the next gen
 849  * (workarounds have a habit of persisting!). Anything older than that
 850  * should be removed along with the complications they introduce.
 851  */
 852 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 853 {
 854         bool pre = false;
 855
 856         pre |= IS_HSW_EARLY_SDV(dev_priv);
 857         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 858         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 859
 860         if (pre) {
 861                 DRM_ERROR("This is a pre-production stepping. "
 862                           "It may not be fully functional.\n");
 863                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 864         }
 865 }
 866
 867 /**
 868  * i915_driver_init_early - setup state not requiring device access
 869  * @dev_priv: device private
 870  * @ent: the matching pci_device_id
 871  *
 872  * Initialize everything that is a "SW-only" state, that is state not
 873  * requiring accessing the device or exposing the driver via kernel internal
 874  * or userspace interfaces. Example steps belonging here: lock initialization,
 875  * system memory allocation, setting up device specific attributes and
 876  * function hooks not requiring accessing the device.
 877  */
 878 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 879                                   const struct pci_device_id *ent)
 880 {
 881         const struct intel_device_info *match_info =
 882                 (struct intel_device_info *)ent->driver_data;
 883         struct intel_device_info *device_info;
 884         int ret = 0;
 885
 886         if (i915_inject_load_failure())
 887                 return -ENODEV;
 888
 889         /* Setup the write-once "constant" device info */
 890         device_info = mkwrite_device_info(dev_priv);
 891         memcpy(device_info, match_info, sizeof(*device_info));
 892         device_info->device_id = dev_priv->drm.pdev->device;
 893
 894         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 895                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 896         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 897         spin_lock_init(&dev_priv->irq_lock);
 898         spin_lock_init(&dev_priv->gpu_error.lock);
 899         mutex_init(&dev_priv->backlight_lock);
 900         spin_lock_init(&dev_priv->uncore.lock);
 901
 902         mutex_init(&dev_priv->sb_lock);
 903         mutex_init(&dev_priv->modeset_restore_lock);
 904         mutex_init(&dev_priv->av_mutex);
 905         mutex_init(&dev_priv->wm.wm_mutex);
 906         mutex_init(&dev_priv->pps_mutex);
 907
 908         i915_memcpy_init_early(dev_priv);
 909
 910         ret = i915_workqueues_init(dev_priv);
 911         if (ret < 0)
 912                 goto err_engines;
 913
 914         ret = i915_gem_init_early(dev_priv);
 915         if (ret < 0)
 916                 goto err_workqueues;
 917
 918         /* This must be called before any calls to HAS_PCH_* */
 919         intel_detect_pch(dev_priv);
 920
 921         intel_wopcm_init_early(&dev_priv->wopcm);
 922         intel_uc_init_early(dev_priv);
 923         intel_pm_setup(dev_priv);
 924         intel_init_dpio(dev_priv);
 925         intel_power_domains_init(dev_priv);
 926         intel_irq_init(dev_priv);
 927         intel_hangcheck_init(dev_priv);
 928         intel_init_display_hooks(dev_priv);
 929         intel_init_clock_gating_hooks(dev_priv);
 930         intel_init_audio_hooks(dev_priv);
 931         intel_display_crc_init(dev_priv);
 932
 933         intel_detect_preproduction_hw(dev_priv);
 934
 935         return 0;
 936
 937 err_workqueues:
 938         i915_workqueues_cleanup(dev_priv);
 939 err_engines:
 940         i915_engines_cleanup(dev_priv);
 941         return ret;
 942 }
 943
 944 /**
 945  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 946  * @dev_priv: device private
 947  */
 948 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 949 {
 950         intel_irq_fini(dev_priv);
 951         intel_uc_cleanup_early(dev_priv);
 952         i915_gem_cleanup_early(dev_priv);
 953         i915_workqueues_cleanup(dev_priv);
 954         i915_engines_cleanup(dev_priv);
 955 }
 956
 957 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 958 {
 959         struct pci_dev *pdev = dev_priv->drm.pdev;
 960         int mmio_bar;
 961         int mmio_size;
 962
 963         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 964         /*
 965          * Before gen4, the registers and the GTT are behind different BARs.
 966          * However, from gen4 onwards, the registers and the GTT are shared
 967          * in the same BAR, so we want to restrict this ioremap from
 968          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 969          * the register BAR remains the same size for all the earlier
 970          * generations up to Ironlake.
 971          */
 972         if (INTEL_GEN(dev_priv) < 5)
 973                 mmio_size = 512 * 1024;
 974         else
 975                 mmio_size = 2 * 1024 * 1024;
 976         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 977         if (dev_priv->regs == NULL) {
 978                 DRM_ERROR("failed to map registers\n");
 979
 980                 return -EIO;
 981         }
 982
 983         /* Try to make sure MCHBAR is enabled before poking at it */
 984         intel_setup_mchbar(dev_priv);
 985
 986         return 0;
 987 }
 988
 989 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 990 {
 991         struct pci_dev *pdev = dev_priv->drm.pdev;
 992
 993         intel_teardown_mchbar(dev_priv);
 994         pci_iounmap(pdev, dev_priv->regs);
 995 }
 996
 997 /**
 998  * i915_driver_init_mmio - setup device MMIO
 999  * @dev_priv: device private
1000  *
1001  * Setup minimal device state necessary for MMIO accesses later in the
1002  * initialization sequence. The setup here should avoid any other device-wide
1003  * side effects or exposing the driver via kernel internal or user space
1004  * interfaces.
1005  */
1006 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1007 {
1008         int ret;
1009
1010         if (i915_inject_load_failure())
1011                 return -ENODEV;
1012
1013         if (i915_get_bridge_dev(dev_priv))
1014                 return -EIO;
1015
1016         ret = i915_mmio_setup(dev_priv);
1017         if (ret < 0)
1018                 goto err_bridge;
1019
1020         intel_uncore_init(dev_priv);
1021
1022         intel_device_info_init_mmio(dev_priv);
1023
1024         intel_uncore_prune(dev_priv);
1025
1026         intel_uc_init_mmio(dev_priv);
1027
1028         ret = intel_engines_init_mmio(dev_priv);
1029         if (ret)
1030                 goto err_uncore;
1031
1032         i915_gem_init_mmio(dev_priv);
1033
1034         return 0;
1035
1036 err_uncore:
1037         intel_uncore_fini(dev_priv);
1038 err_bridge:
1039         pci_dev_put(dev_priv->bridge_dev);
1040
1041         return ret;
1042 }
1043
1044 /**
1045  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1046  * @dev_priv: device private
1047  */
1048 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1049 {
1050         intel_uncore_fini(dev_priv);
1051         i915_mmio_cleanup(dev_priv);
1052         pci_dev_put(dev_priv->bridge_dev);
1053 }
1054
1055 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1056 {
1057         /*
1058          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1059          * user's requested state against the hardware/driver capabilities.  We
1060          * do this now so that we can print out any log messages once rather
1061          * than every time we check intel_enable_ppgtt().
1062          */
1063         i915_modparams.enable_ppgtt =
1064                 intel_sanitize_enable_ppgtt(dev_priv,
1065                                             i915_modparams.enable_ppgtt);
1066         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1067
1068         intel_gvt_sanitize_options(dev_priv);
1069 }
1070
1071 /**
1072  * i915_driver_init_hw - setup state requiring device access
1073  * @dev_priv: device private
1074  *
1075  * Setup state that requires accessing the device, but doesn't require
1076  * exposing the driver via kernel internal or userspace interfaces.
1077  */
1078 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1079 {
1080         struct pci_dev *pdev = dev_priv->drm.pdev;
1081         int ret;
1082
1083         if (i915_inject_load_failure())
1084                 return -ENODEV;
1085
1086         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1087
1088         intel_sanitize_options(dev_priv);
1089
1090         i915_perf_init(dev_priv);
1091
1092         ret = i915_ggtt_probe_hw(dev_priv);
1093         if (ret)
1094                 goto err_perf;
1095
1096         /*
1097          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1098          * otherwise the vga fbdev driver falls over.
1099          */
1100         ret = i915_kick_out_firmware_fb(dev_priv);
1101         if (ret) {
1102                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1103                 goto err_ggtt;
1104         }
1105
1106         ret = i915_kick_out_vgacon(dev_priv);
1107         if (ret) {
1108                 DRM_ERROR("failed to remove conflicting VGA console\n");
1109                 goto err_ggtt;
1110         }
1111
1112         ret = i915_ggtt_init_hw(dev_priv);
1113         if (ret)
1114                 goto err_ggtt;
1115
1116         ret = i915_ggtt_enable_hw(dev_priv);
1117         if (ret) {
1118                 DRM_ERROR("failed to enable GGTT\n");
1119                 goto err_ggtt;
1120         }
1121
1122         pci_set_master(pdev);
1123
1124         /* overlay on gen2 is broken and can't address above 1G */
1125         if (IS_GEN2(dev_priv)) {
1126                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1127                 if (ret) {
1128                         DRM_ERROR("failed to set DMA mask\n");
1129
1130                         goto err_ggtt;
1131                 }
1132         }
1133
1134         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1135          * using 32bit addressing, overwriting memory if HWS is located
1136          * above 4GB.
1137          *
1138          * The documentation also mentions an issue with undefined
1139          * behaviour if any general state is accessed within a page above 4GB,
1140          * which also needs to be handled carefully.
1141          */
1142         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1143                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1144
1145                 if (ret) {
1146                         DRM_ERROR("failed to set DMA mask\n");
1147
1148                         goto err_ggtt;
1149                 }
1150         }
1151
1152         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1153                            PM_QOS_DEFAULT_VALUE);
1154
1155         intel_uncore_sanitize(dev_priv);
1156
1157         intel_opregion_setup(dev_priv);
1158
1159         i915_gem_load_init_fences(dev_priv);
1160
1161         /* On the 945G/GM, the chipset reports the MSI capability on the
1162          * integrated graphics even though the support isn't actually there
1163          * according to the published specs.  It doesn't appear to function
1164          * correctly in testing on 945G.
1165          * This may be a side effect of MSI having been made available for PEG
1166          * and the registers being closely associated.
1167          *
1168          * According to chipset errata, on the 965GM, MSI interrupts may
1169          * be lost or delayed, and was defeatured. MSI interrupts seem to
1170          * get lost on g4x as well, and interrupt delivery seems to stay
1171          * properly dead afterwards. So we'll just disable them for all
1172          * pre-gen5 chipsets.
1173          *
1174          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1175          * interrupts even when in MSI mode. This results in spurious
1176          * interrupt warnings if the legacy irq no. is shared with another
1177          * device. The kernel then disables that interrupt source and so
1178          * prevents the other device from working properly.
1179          */
1180         if (INTEL_GEN(dev_priv) >= 5) {
1181                 if (pci_enable_msi(pdev) < 0)
1182                         DRM_DEBUG_DRIVER("can't enable MSI");
1183         }
1184
1185         ret = intel_gvt_init(dev_priv);
1186         if (ret)
1187                 goto err_ggtt;
1188
1189         return 0;
1190
1191 err_ggtt:
1192         i915_ggtt_cleanup_hw(dev_priv);
1193 err_perf:
1194         i915_perf_fini(dev_priv);
1195         return ret;
1196 }
1197
1198 /**
1199  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1200  * @dev_priv: device private
1201  */
1202 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1203 {
1204         struct pci_dev *pdev = dev_priv->drm.pdev;
1205
1206         i915_perf_fini(dev_priv);
1207
1208         if (pdev->msi_enabled)
1209                 pci_disable_msi(pdev);
1210
1211         pm_qos_remove_request(&dev_priv->pm_qos);
1212         i915_ggtt_cleanup_hw(dev_priv);
1213 }
1214
1215 /**
1216  * i915_driver_register - register the driver with the rest of the system
1217  * @dev_priv: device private
1218  *
1219  * Perform any steps necessary to make the driver available via kernel
1220  * internal or userspace interfaces.
1221  */
1222 static void i915_driver_register(struct drm_i915_private *dev_priv)
1223 {
1224         struct drm_device *dev = &dev_priv->drm;
1225
1226         i915_gem_shrinker_register(dev_priv);
1227         i915_pmu_register(dev_priv);
1228
1229         /*
1230          * Notify a valid surface after modesetting,
1231          * when running inside a VM.
1232          */
1233         if (intel_vgpu_active(dev_priv))
1234                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1235
1236         /* Reveal our presence to userspace */
1237         if (drm_dev_register(dev, 0) == 0) {
1238                 i915_debugfs_register(dev_priv);
1239                 i915_setup_sysfs(dev_priv);
1240
1241                 /* Depends on sysfs having been initialized */
1242                 i915_perf_register(dev_priv);
1243         } else
1244                 DRM_ERROR("Failed to register driver for userspace access!\n");
1245
1246         if (INTEL_INFO(dev_priv)->num_pipes) {
1247                 /* Must be done after probing outputs */
1248                 intel_opregion_register(dev_priv);
1249                 acpi_video_register();
1250         }
1251
1252         if (IS_GEN5(dev_priv))
1253                 intel_gpu_ips_init(dev_priv);
1254
1255         intel_audio_init(dev_priv);
1256
1257         /*
1258          * Some ports require correctly set-up hpd registers for detection to
1259          * work properly (leading to ghost connected connector status), e.g. VGA
1260          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1261          * irqs are fully enabled. We do it last so that the async config
1262          * cannot run before the connectors are registered.
1263          */
1264         intel_fbdev_initial_config_async(dev);
1265
1266         /*
1267          * We need to coordinate the hotplugs with the asynchronous fbdev
1268          * configuration, for which we use the fbdev->async_cookie.
1269          */
1270         if (INTEL_INFO(dev_priv)->num_pipes)
1271                 drm_kms_helper_poll_init(dev);
1272 }
1273
1274 /**
1275  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1276  * @dev_priv: device private
1277  */
1278 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1279 {
1280         intel_fbdev_unregister(dev_priv);
1281         intel_audio_deinit(dev_priv);
1282
1283         /*
1284          * After flushing the fbdev (incl. a late async config which will
1285          * have delayed queuing of a hotplug event), then flush the hotplug
1286          * events.
1287          */
1288         drm_kms_helper_poll_fini(&dev_priv->drm);
1289
1290         intel_gpu_ips_teardown();
1291         acpi_video_unregister();
1292         intel_opregion_unregister(dev_priv);
1293
1294         i915_perf_unregister(dev_priv);
1295         i915_pmu_unregister(dev_priv);
1296
1297         i915_teardown_sysfs(dev_priv);
1298         drm_dev_unregister(&dev_priv->drm);
1299
1300         i915_gem_shrinker_unregister(dev_priv);
1301 }
1302
1303 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1304 {
1305         if (drm_debug & DRM_UT_DRIVER) {
1306                 struct drm_printer p = drm_debug_printer("i915 device info:");
1307
1308                 intel_device_info_dump(&dev_priv->info, &p);
1309                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1310         }
1311
1312         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1313                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1314         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1315                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1316 }
1317
1318 /**
1319  * i915_driver_load - setup chip and create an initial config
1320  * @pdev: PCI device
1321  * @ent: matching PCI ID entry
1322  *
1323  * The driver load routine has to do several things:
1324  *   - drive output discovery via intel_modeset_init()
1325  *   - initialize the memory manager
1326  *   - allocate initial config memory
1327  *   - setup the DRM framebuffer with the allocated memory
1328  */
1329 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1330 {
1331         const struct intel_device_info *match_info =
1332                 (struct intel_device_info *)ent->driver_data;
1333         struct drm_i915_private *dev_priv;
1334         int ret;
1335
1336         /* Enable nuclear pageflip on ILK+ */
1337         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1338                 driver.driver_features &= ~DRIVER_ATOMIC;
1339
1340         ret = -ENOMEM;
1341         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1342         if (dev_priv)
1343                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1344         if (ret) {
1345                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1346                 goto out_free;
1347         }
1348
1349         dev_priv->drm.pdev = pdev;
1350         dev_priv->drm.dev_private = dev_priv;
1351
1352         ret = pci_enable_device(pdev);
1353         if (ret)
1354                 goto out_fini;
1355
1356         pci_set_drvdata(pdev, &dev_priv->drm);
1357         /*
1358          * Disable the system suspend direct complete optimization, which can
1359          * leave the device suspended skipping the driver's suspend handlers
1360          * if the device was already runtime suspended. This is needed due to
1361          * the difference in our runtime and system suspend sequence and
1362          * becaue the HDA driver may require us to enable the audio power
1363          * domain during system suspend.
1364          */
1365         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1366
1367         ret = i915_driver_init_early(dev_priv, ent);
1368         if (ret < 0)
1369                 goto out_pci_disable;
1370
1371         intel_runtime_pm_get(dev_priv);
1372
1373         ret = i915_driver_init_mmio(dev_priv);
1374         if (ret < 0)
1375                 goto out_runtime_pm_put;
1376
1377         ret = i915_driver_init_hw(dev_priv);
1378         if (ret < 0)
1379                 goto out_cleanup_mmio;
1380
1381         /*
1382          * TODO: move the vblank init and parts of modeset init steps into one
1383          * of the i915_driver_init_/i915_driver_register functions according
1384          * to the role/effect of the given init step.
1385          */
1386         if (INTEL_INFO(dev_priv)->num_pipes) {
1387                 ret = drm_vblank_init(&dev_priv->drm,
1388                                       INTEL_INFO(dev_priv)->num_pipes);
1389                 if (ret)
1390                         goto out_cleanup_hw;
1391         }
1392
1393         ret = i915_load_modeset_init(&dev_priv->drm);
1394         if (ret < 0)
1395                 goto out_cleanup_hw;
1396
1397         i915_driver_register(dev_priv);
1398
1399         intel_runtime_pm_enable(dev_priv);
1400
1401         intel_init_ipc(dev_priv);
1402
1403         intel_runtime_pm_put(dev_priv);
1404
1405         i915_welcome_messages(dev_priv);
1406
1407         return 0;
1408
1409 out_cleanup_hw:
1410         i915_driver_cleanup_hw(dev_priv);
1411 out_cleanup_mmio:
1412         i915_driver_cleanup_mmio(dev_priv);
1413 out_runtime_pm_put:
1414         intel_runtime_pm_put(dev_priv);
1415         i915_driver_cleanup_early(dev_priv);
1416 out_pci_disable:
1417         pci_disable_device(pdev);
1418 out_fini:
1419         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1420         drm_dev_fini(&dev_priv->drm);
1421 out_free:
1422         kfree(dev_priv);
1423         return ret;
1424 }
1425
1426 void i915_driver_unload(struct drm_device *dev)
1427 {
1428         struct drm_i915_private *dev_priv = to_i915(dev);
1429         struct pci_dev *pdev = dev_priv->drm.pdev;
1430
1431         i915_driver_unregister(dev_priv);
1432
1433         if (i915_gem_suspend(dev_priv))
1434                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1435
1436         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1437
1438         drm_atomic_helper_shutdown(dev);
1439
1440         intel_gvt_cleanup(dev_priv);
1441
1442         intel_modeset_cleanup(dev);
1443
1444         intel_bios_cleanup(dev_priv);
1445
1446         vga_switcheroo_unregister_client(pdev);
1447         vga_client_register(pdev, NULL, NULL, NULL);
1448
1449         intel_csr_ucode_fini(dev_priv);
1450
1451         /* Free error state after interrupts are fully disabled. */
1452         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1453         i915_reset_error_state(dev_priv);
1454
1455         i915_gem_fini(dev_priv);
1456         intel_fbc_cleanup_cfb(dev_priv);
1457
1458         intel_power_domains_fini(dev_priv);
1459
1460         i915_driver_cleanup_hw(dev_priv);
1461         i915_driver_cleanup_mmio(dev_priv);
1462
1463         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1464 }
1465
1466 static void i915_driver_release(struct drm_device *dev)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(dev);
1469
1470         i915_driver_cleanup_early(dev_priv);
1471         drm_dev_fini(&dev_priv->drm);
1472
1473         kfree(dev_priv);
1474 }
1475
1476 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1477 {
1478         struct drm_i915_private *i915 = to_i915(dev);
1479         int ret;
1480
1481         ret = i915_gem_open(i915, file);
1482         if (ret)
1483                 return ret;
1484
1485         return 0;
1486 }
1487
1488 /**
1489  * i915_driver_lastclose - clean up after all DRM clients have exited
1490  * @dev: DRM device
1491  *
1492  * Take care of cleaning up after all DRM clients have exited.  In the
1493  * mode setting case, we want to restore the kernel's initial mode (just
1494  * in case the last client left us in a bad state).
1495  *
1496  * Additionally, in the non-mode setting case, we'll tear down the GTT
1497  * and DMA structures, since the kernel won't be using them, and clea
1498  * up any GEM state.
1499  */
1500 static void i915_driver_lastclose(struct drm_device *dev)
1501 {
1502         intel_fbdev_restore_mode(dev);
1503         vga_switcheroo_process_delayed_switch();
1504 }
1505
1506 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1507 {
1508         struct drm_i915_file_private *file_priv = file->driver_priv;
1509
1510         mutex_lock(&dev->struct_mutex);
1511         i915_gem_context_close(file);
1512         i915_gem_release(dev, file);
1513         mutex_unlock(&dev->struct_mutex);
1514
1515         kfree(file_priv);
1516 }
1517
1518 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1519 {
1520         struct drm_device *dev = &dev_priv->drm;
1521         struct intel_encoder *encoder;
1522
1523         drm_modeset_lock_all(dev);
1524         for_each_intel_encoder(dev, encoder)
1525                 if (encoder->suspend)
1526                         encoder->suspend(encoder);
1527         drm_modeset_unlock_all(dev);
1528 }
1529
1530 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1531                               bool rpm_resume);
1532 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1533
1534 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1535 {
1536 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1537         if (acpi_target_system_state() < ACPI_STATE_S3)
1538                 return true;
1539 #endif
1540         return false;
1541 }
1542
1543 static int i915_drm_prepare(struct drm_device *dev)
1544 {
1545         struct drm_i915_private *i915 = to_i915(dev);
1546         int err;
1547
1548         /*
1549          * NB intel_display_suspend() may issue new requests after we've
1550          * ostensibly marked the GPU as ready-to-sleep here. We need to
1551          * split out that work and pull it forward so that after point,
1552          * the GPU is not woken again.
1553          */
1554         err = i915_gem_suspend(i915);
1555         if (err)
1556                 dev_err(&i915->drm.pdev->dev,
1557                         "GEM idle failed, suspend/resume might fail\n");
1558
1559         return err;
1560 }
1561
1562 static int i915_drm_suspend(struct drm_device *dev)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(dev);
1565         struct pci_dev *pdev = dev_priv->drm.pdev;
1566         pci_power_t opregion_target_state;
1567
1568         /* ignore lid events during suspend */
1569         mutex_lock(&dev_priv->modeset_restore_lock);
1570         dev_priv->modeset_restore = MODESET_SUSPENDED;
1571         mutex_unlock(&dev_priv->modeset_restore_lock);
1572
1573         disable_rpm_wakeref_asserts(dev_priv);
1574
1575         /* We do a lot of poking in a lot of registers, make sure they work
1576          * properly. */
1577         intel_display_set_init_power(dev_priv, true);
1578
1579         drm_kms_helper_poll_disable(dev);
1580
1581         pci_save_state(pdev);
1582
1583         intel_display_suspend(dev);
1584
1585         intel_dp_mst_suspend(dev);
1586
1587         intel_runtime_pm_disable_interrupts(dev_priv);
1588         intel_hpd_cancel_work(dev_priv);
1589
1590         intel_suspend_encoders(dev_priv);
1591
1592         intel_suspend_hw(dev_priv);
1593
1594         i915_gem_suspend_gtt_mappings(dev_priv);
1595
1596         i915_save_state(dev_priv);
1597
1598         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1599         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1600
1601         intel_opregion_unregister(dev_priv);
1602
1603         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1604
1605         dev_priv->suspend_count++;
1606
1607         intel_csr_ucode_suspend(dev_priv);
1608
1609         enable_rpm_wakeref_asserts(dev_priv);
1610
1611         return 0;
1612 }
1613
1614 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1615 {
1616         struct drm_i915_private *dev_priv = to_i915(dev);
1617         struct pci_dev *pdev = dev_priv->drm.pdev;
1618         int ret;
1619
1620         disable_rpm_wakeref_asserts(dev_priv);
1621
1622         i915_gem_suspend_late(dev_priv);
1623
1624         intel_display_set_init_power(dev_priv, false);
1625         intel_uncore_suspend(dev_priv);
1626
1627         /*
1628          * In case of firmware assisted context save/restore don't manually
1629          * deinit the power domains. This also means the CSR/DMC firmware will
1630          * stay active, it will power down any HW resources as required and
1631          * also enable deeper system power states that would be blocked if the
1632          * firmware was inactive.
1633          */
1634         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1635             dev_priv->csr.dmc_payload == NULL) {
1636                 intel_power_domains_suspend(dev_priv);
1637                 dev_priv->power_domains_suspended = true;
1638         }
1639
1640         ret = 0;
1641         if (IS_GEN9_LP(dev_priv))
1642                 bxt_enable_dc9(dev_priv);
1643         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1644                 hsw_enable_pc8(dev_priv);
1645         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1646                 ret = vlv_suspend_complete(dev_priv);
1647
1648         if (ret) {
1649                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1650                 if (dev_priv->power_domains_suspended) {
1651                         intel_power_domains_init_hw(dev_priv, true);
1652                         dev_priv->power_domains_suspended = false;
1653                 }
1654
1655                 goto out;
1656         }
1657
1658         pci_disable_device(pdev);
1659         /*
1660          * During hibernation on some platforms the BIOS may try to access
1661          * the device even though it's already in D3 and hang the machine. So
1662          * leave the device in D0 on those platforms and hope the BIOS will
1663          * power down the device properly. The issue was seen on multiple old
1664          * GENs with different BIOS vendors, so having an explicit blacklist
1665          * is inpractical; apply the workaround on everything pre GEN6. The
1666          * platforms where the issue was seen:
1667          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1668          * Fujitsu FSC S7110
1669          * Acer Aspire 1830T
1670          */
1671         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1672                 pci_set_power_state(pdev, PCI_D3hot);
1673
1674 out:
1675         enable_rpm_wakeref_asserts(dev_priv);
1676
1677         return ret;
1678 }
1679
1680 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1681 {
1682         int error;
1683
1684         if (!dev) {
1685                 DRM_ERROR("dev: %p\n", dev);
1686                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1687                 return -ENODEV;
1688         }
1689
1690         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1691                          state.event != PM_EVENT_FREEZE))
1692                 return -EINVAL;
1693
1694         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1695                 return 0;
1696
1697         error = i915_drm_suspend(dev);
1698         if (error)
1699                 return error;
1700
1701         return i915_drm_suspend_late(dev, false);
1702 }
1703
1704 static int i915_drm_resume(struct drm_device *dev)
1705 {
1706         struct drm_i915_private *dev_priv = to_i915(dev);
1707         int ret;
1708
1709         disable_rpm_wakeref_asserts(dev_priv);
1710         intel_sanitize_gt_powersave(dev_priv);
1711
1712         i915_gem_sanitize(dev_priv);
1713
1714         ret = i915_ggtt_enable_hw(dev_priv);
1715         if (ret)
1716                 DRM_ERROR("failed to re-enable GGTT\n");
1717
1718         intel_csr_ucode_resume(dev_priv);
1719
1720         i915_restore_state(dev_priv);
1721         intel_pps_unlock_regs_wa(dev_priv);
1722         intel_opregion_setup(dev_priv);
1723
1724         intel_init_pch_refclk(dev_priv);
1725
1726         /*
1727          * Interrupts have to be enabled before any batches are run. If not the
1728          * GPU will hang. i915_gem_init_hw() will initiate batches to
1729          * update/restore the context.
1730          *
1731          * drm_mode_config_reset() needs AUX interrupts.
1732          *
1733          * Modeset enabling in intel_modeset_init_hw() also needs working
1734          * interrupts.
1735          */
1736         intel_runtime_pm_enable_interrupts(dev_priv);
1737
1738         drm_mode_config_reset(dev);
1739
1740         i915_gem_resume(dev_priv);
1741
1742         intel_modeset_init_hw(dev);
1743         intel_init_clock_gating(dev_priv);
1744
1745         spin_lock_irq(&dev_priv->irq_lock);
1746         if (dev_priv->display.hpd_irq_setup)
1747                 dev_priv->display.hpd_irq_setup(dev_priv);
1748         spin_unlock_irq(&dev_priv->irq_lock);
1749
1750         intel_dp_mst_resume(dev);
1751
1752         intel_display_resume(dev);
1753
1754         drm_kms_helper_poll_enable(dev);
1755
1756         /*
1757          * ... but also need to make sure that hotplug processing
1758          * doesn't cause havoc. Like in the driver load code we don't
1759          * bother with the tiny race here where we might loose hotplug
1760          * notifications.
1761          * */
1762         intel_hpd_init(dev_priv);
1763
1764         intel_opregion_register(dev_priv);
1765
1766         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1767
1768         mutex_lock(&dev_priv->modeset_restore_lock);
1769         dev_priv->modeset_restore = MODESET_DONE;
1770         mutex_unlock(&dev_priv->modeset_restore_lock);
1771
1772         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1773
1774         enable_rpm_wakeref_asserts(dev_priv);
1775
1776         return 0;
1777 }
1778
1779 static int i915_drm_resume_early(struct drm_device *dev)
1780 {
1781         struct drm_i915_private *dev_priv = to_i915(dev);
1782         struct pci_dev *pdev = dev_priv->drm.pdev;
1783         int ret;
1784
1785         /*
1786          * We have a resume ordering issue with the snd-hda driver also
1787          * requiring our device to be power up. Due to the lack of a
1788          * parent/child relationship we currently solve this with an early
1789          * resume hook.
1790          *
1791          * FIXME: This should be solved with a special hdmi sink device or
1792          * similar so that power domains can be employed.
1793          */
1794
1795         /*
1796          * Note that we need to set the power state explicitly, since we
1797          * powered off the device during freeze and the PCI core won't power
1798          * it back up for us during thaw. Powering off the device during
1799          * freeze is not a hard requirement though, and during the
1800          * suspend/resume phases the PCI core makes sure we get here with the
1801          * device powered on. So in case we change our freeze logic and keep
1802          * the device powered we can also remove the following set power state
1803          * call.
1804          */
1805         ret = pci_set_power_state(pdev, PCI_D0);
1806         if (ret) {
1807                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1808                 goto out;
1809         }
1810
1811         /*
1812          * Note that pci_enable_device() first enables any parent bridge
1813          * device and only then sets the power state for this device. The
1814          * bridge enabling is a nop though, since bridge devices are resumed
1815          * first. The order of enabling power and enabling the device is
1816          * imposed by the PCI core as described above, so here we preserve the
1817          * same order for the freeze/thaw phases.
1818          *
1819          * TODO: eventually we should remove pci_disable_device() /
1820          * pci_enable_enable_device() from suspend/resume. Due to how they
1821          * depend on the device enable refcount we can't anyway depend on them
1822          * disabling/enabling the device.
1823          */
1824         if (pci_enable_device(pdev)) {
1825                 ret = -EIO;
1826                 goto out;
1827         }
1828
1829         pci_set_master(pdev);
1830
1831         disable_rpm_wakeref_asserts(dev_priv);
1832
1833         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1834                 ret = vlv_resume_prepare(dev_priv, false);
1835         if (ret)
1836                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1837                           ret);
1838
1839         intel_uncore_resume_early(dev_priv);
1840
1841         if (IS_GEN9_LP(dev_priv)) {
1842                 gen9_sanitize_dc_state(dev_priv);
1843                 bxt_disable_dc9(dev_priv);
1844         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1845                 hsw_disable_pc8(dev_priv);
1846         }
1847
1848         intel_uncore_sanitize(dev_priv);
1849
1850         if (dev_priv->power_domains_suspended)
1851                 intel_power_domains_init_hw(dev_priv, true);
1852         else
1853                 intel_display_set_init_power(dev_priv, true);
1854
1855         intel_engines_sanitize(dev_priv);
1856
1857         enable_rpm_wakeref_asserts(dev_priv);
1858
1859 out:
1860         dev_priv->power_domains_suspended = false;
1861
1862         return ret;
1863 }
1864
1865 static int i915_resume_switcheroo(struct drm_device *dev)
1866 {
1867         int ret;
1868
1869         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1870                 return 0;
1871
1872         ret = i915_drm_resume_early(dev);
1873         if (ret)
1874                 return ret;
1875
1876         return i915_drm_resume(dev);
1877 }
1878
1879 /**
1880  * i915_reset - reset chip after a hang
1881  * @i915: #drm_i915_private to reset
1882  * @stalled_mask: mask of the stalled engines with the guilty requests
1883  * @reason: user error message for why we are resetting
1884  *
1885  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1886  * on failure.
1887  *
1888  * Caller must hold the struct_mutex.
1889  *
1890  * Procedure is fairly simple:
1891  *   - reset the chip using the reset reg
1892  *   - re-init context state
1893  *   - re-init hardware status page
1894  *   - re-init ring buffer
1895  *   - re-init interrupt state
1896  *   - re-init display
1897  */
1898 void i915_reset(struct drm_i915_private *i915,
1899                 unsigned int stalled_mask,
1900                 const char *reason)
1901 {
1902         struct i915_gpu_error *error = &i915->gpu_error;
1903         int ret;
1904         int i;
1905
1906         GEM_TRACE("flags=%lx\n", error->flags);
1907
1908         might_sleep();
1909         lockdep_assert_held(&i915->drm.struct_mutex);
1910         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1911
1912         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1913                 return;
1914
1915         /* Clear any previous failed attempts at recovery. Time to try again. */
1916         if (!i915_gem_unset_wedged(i915))
1917                 goto wakeup;
1918
1919         if (reason)
1920                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1921         error->reset_count++;
1922
1923         disable_irq(i915->drm.irq);
1924         ret = i915_gem_reset_prepare(i915);
1925         if (ret) {
1926                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1927                 goto taint;
1928         }
1929
1930         if (!intel_has_gpu_reset(i915)) {
1931                 if (i915_modparams.reset)
1932                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1933                 else
1934                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1935                 goto error;
1936         }
1937
1938         for (i = 0; i < 3; i++) {
1939                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1940                 if (ret == 0)
1941                         break;
1942
1943                 msleep(100);
1944         }
1945         if (ret) {
1946                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1947                 goto taint;
1948         }
1949
1950         /* Ok, now get things going again... */
1951
1952         /*
1953          * Everything depends on having the GTT running, so we need to start
1954          * there.
1955          */
1956         ret = i915_ggtt_enable_hw(i915);
1957         if (ret) {
1958                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1959                           ret);
1960                 goto error;
1961         }
1962
1963         i915_gem_reset(i915, stalled_mask);
1964         intel_overlay_reset(i915);
1965
1966         /*
1967          * Next we need to restore the context, but we don't use those
1968          * yet either...
1969          *
1970          * Ring buffer needs to be re-initialized in the KMS case, or if X
1971          * was running at the time of the reset (i.e. we weren't VT
1972          * switched away).
1973          */
1974         ret = i915_gem_init_hw(i915);
1975         if (ret) {
1976                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1977                           ret);
1978                 goto error;
1979         }
1980
1981         i915_queue_hangcheck(i915);
1982
1983 finish:
1984         i915_gem_reset_finish(i915);
1985         enable_irq(i915->drm.irq);
1986
1987 wakeup:
1988         clear_bit(I915_RESET_HANDOFF, &error->flags);
1989         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1990         return;
1991
1992 taint:
1993         /*
1994          * History tells us that if we cannot reset the GPU now, we
1995          * never will. This then impacts everything that is run
1996          * subsequently. On failing the reset, we mark the driver
1997          * as wedged, preventing further execution on the GPU.
1998          * We also want to go one step further and add a taint to the
1999          * kernel so that any subsequent faults can be traced back to
2000          * this failure. This is important for CI, where if the
2001          * GPU/driver fails we would like to reboot and restart testing
2002          * rather than continue on into oblivion. For everyone else,
2003          * the system should still plod along, but they have been warned!
2004          */
2005         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2006 error:
2007         i915_gem_set_wedged(i915);
2008         i915_retire_requests(i915);
2009         goto finish;
2010 }
2011
2012 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2013                                         struct intel_engine_cs *engine)
2014 {
2015         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2016 }
2017
2018 /**
2019  * i915_reset_engine - reset GPU engine to recover from a hang
2020  * @engine: engine to reset
2021  * @msg: reason for GPU reset; or NULL for no dev_notice()
2022  *
2023  * Reset a specific GPU engine. Useful if a hang is detected.
2024  * Returns zero on successful reset or otherwise an error code.
2025  *
2026  * Procedure is:
2027  *  - identifies the request that caused the hang and it is dropped
2028  *  - reset engine (which will force the engine to idle)
2029  *  - re-init/configure engine
2030  */
2031 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2032 {
2033         struct i915_gpu_error *error = &engine->i915->gpu_error;
2034         struct i915_request *active_request;
2035         int ret;
2036
2037         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2038         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2039
2040         active_request = i915_gem_reset_prepare_engine(engine);
2041         if (IS_ERR_OR_NULL(active_request)) {
2042                 /* Either the previous reset failed, or we pardon the reset. */
2043                 ret = PTR_ERR(active_request);
2044                 goto out;
2045         }
2046
2047         if (msg)
2048                 dev_notice(engine->i915->drm.dev,
2049                            "Resetting %s for %s\n", engine->name, msg);
2050         error->reset_engine_count[engine->id]++;
2051
2052         if (!engine->i915->guc.execbuf_client)
2053                 ret = intel_gt_reset_engine(engine->i915, engine);
2054         else
2055                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2056         if (ret) {
2057                 /* If we fail here, we expect to fallback to a global reset */
2058                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2059                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2060                                  engine->name, ret);
2061                 goto out;
2062         }
2063
2064         /*
2065          * The request that caused the hang is stuck on elsp, we know the
2066          * active request and can drop it, adjust head to skip the offending
2067          * request to resume executing remaining requests in the queue.
2068          */
2069         i915_gem_reset_engine(engine, active_request, true);
2070
2071         /*
2072          * The engine and its registers (and workarounds in case of render)
2073          * have been reset to their default values. Follow the init_ring
2074          * process to program RING_MODE, HWSP and re-enable submission.
2075          */
2076         ret = engine->init_hw(engine);
2077         if (ret)
2078                 goto out;
2079
2080 out:
2081         i915_gem_reset_finish_engine(engine);
2082         return ret;
2083 }
2084
2085 static int i915_pm_prepare(struct device *kdev)
2086 {
2087         struct pci_dev *pdev = to_pci_dev(kdev);
2088         struct drm_device *dev = pci_get_drvdata(pdev);
2089
2090         if (!dev) {
2091                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2092                 return -ENODEV;
2093         }
2094
2095         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2096                 return 0;
2097
2098         return i915_drm_prepare(dev);
2099 }
2100
2101 static int i915_pm_suspend(struct device *kdev)
2102 {
2103         struct pci_dev *pdev = to_pci_dev(kdev);
2104         struct drm_device *dev = pci_get_drvdata(pdev);
2105
2106         if (!dev) {
2107                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2108                 return -ENODEV;
2109         }
2110
2111         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2112                 return 0;
2113
2114         return i915_drm_suspend(dev);
2115 }
2116
2117 static int i915_pm_suspend_late(struct device *kdev)
2118 {
2119         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2120
2121         /*
2122          * We have a suspend ordering issue with the snd-hda driver also
2123          * requiring our device to be power up. Due to the lack of a
2124          * parent/child relationship we currently solve this with an late
2125          * suspend hook.
2126          *
2127          * FIXME: This should be solved with a special hdmi sink device or
2128          * similar so that power domains can be employed.
2129          */
2130         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2131                 return 0;
2132
2133         return i915_drm_suspend_late(dev, false);
2134 }
2135
2136 static int i915_pm_poweroff_late(struct device *kdev)
2137 {
2138         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2139
2140         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2141                 return 0;
2142
2143         return i915_drm_suspend_late(dev, true);
2144 }
2145
2146 static int i915_pm_resume_early(struct device *kdev)
2147 {
2148         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2149
2150         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2151                 return 0;
2152
2153         return i915_drm_resume_early(dev);
2154 }
2155
2156 static int i915_pm_resume(struct device *kdev)
2157 {
2158         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2159
2160         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2161                 return 0;
2162
2163         return i915_drm_resume(dev);
2164 }
2165
2166 /* freeze: before creating the hibernation_image */
2167 static int i915_pm_freeze(struct device *kdev)
2168 {
2169         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2170         int ret;
2171
2172         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2173                 ret = i915_drm_suspend(dev);
2174                 if (ret)
2175                         return ret;
2176         }
2177
2178         ret = i915_gem_freeze(kdev_to_i915(kdev));
2179         if (ret)
2180                 return ret;
2181
2182         return 0;
2183 }
2184
2185 static int i915_pm_freeze_late(struct device *kdev)
2186 {
2187         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2188         int ret;
2189
2190         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2191                 ret = i915_drm_suspend_late(dev, true);
2192                 if (ret)
2193                         return ret;
2194         }
2195
2196         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2197         if (ret)
2198                 return ret;
2199
2200         return 0;
2201 }
2202
2203 /* thaw: called after creating the hibernation image, but before turning off. */
2204 static int i915_pm_thaw_early(struct device *kdev)
2205 {
2206         return i915_pm_resume_early(kdev);
2207 }
2208
2209 static int i915_pm_thaw(struct device *kdev)
2210 {
2211         return i915_pm_resume(kdev);
2212 }
2213
2214 /* restore: called after loading the hibernation image. */
2215 static int i915_pm_restore_early(struct device *kdev)
2216 {
2217         return i915_pm_resume_early(kdev);
2218 }
2219
2220 static int i915_pm_restore(struct device *kdev)
2221 {
2222         return i915_pm_resume(kdev);
2223 }
2224
2225 /*
2226  * Save all Gunit registers that may be lost after a D3 and a subsequent
2227  * S0i[R123] transition. The list of registers needing a save/restore is
2228  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2229  * registers in the following way:
2230  * - Driver: saved/restored by the driver
2231  * - Punit : saved/restored by the Punit firmware
2232  * - No, w/o marking: no need to save/restore, since the register is R/O or
2233  *                    used internally by the HW in a way that doesn't depend
2234  *                    keeping the content across a suspend/resume.
2235  * - Debug : used for debugging
2236  *
2237  * We save/restore all registers marked with 'Driver', with the following
2238  * exceptions:
2239  * - Registers out of use, including also registers marked with 'Debug'.
2240  *   These have no effect on the driver's operation, so we don't save/restore
2241  *   them to reduce the overhead.
2242  * - Registers that are fully setup by an initialization function called from
2243  *   the resume path. For example many clock gating and RPS/RC6 registers.
2244  * - Registers that provide the right functionality with their reset defaults.
2245  *
2246  * TODO: Except for registers that based on the above 3 criteria can be safely
2247  * ignored, we save/restore all others, practically treating the HW context as
2248  * a black-box for the driver. Further investigation is needed to reduce the
2249  * saved/restored registers even further, by following the same 3 criteria.
2250  */
2251 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2252 {
2253         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2254         int i;
2255
2256         /* GAM 0x4000-0x4770 */
2257         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2258         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2259         s->arb_mode             = I915_READ(ARB_MODE);
2260         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2261         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2262
2263         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2264                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2265
2266         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2267         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2268
2269         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2270         s->ecochk               = I915_READ(GAM_ECOCHK);
2271         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2272         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2273
2274         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2275
2276         /* MBC 0x9024-0x91D0, 0x8500 */
2277         s->g3dctl               = I915_READ(VLV_G3DCTL);
2278         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2279         s->mbctl                = I915_READ(GEN6_MBCTL);
2280
2281         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2282         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2283         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2284         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2285         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2286         s->rstctl               = I915_READ(GEN6_RSTCTL);
2287         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2288
2289         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2290         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2291         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2292         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2293         s->ecobus               = I915_READ(ECOBUS);
2294         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2295         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2296         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2297         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2298         s->rcedata              = I915_READ(VLV_RCEDATA);
2299         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2300
2301         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2302         s->gt_imr               = I915_READ(GTIMR);
2303         s->gt_ier               = I915_READ(GTIER);
2304         s->pm_imr               = I915_READ(GEN6_PMIMR);
2305         s->pm_ier               = I915_READ(GEN6_PMIER);
2306
2307         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2308                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2309
2310         /* GT SA CZ domain, 0x100000-0x138124 */
2311         s->tilectl              = I915_READ(TILECTL);
2312         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2313         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2314         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2315         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2316
2317         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2318         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2319         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2320         s->pcbr                 = I915_READ(VLV_PCBR);
2321         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2322
2323         /*
2324          * Not saving any of:
2325          * DFT,         0x9800-0x9EC0
2326          * SARB,        0xB000-0xB1FC
2327          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2328          * PCI CFG
2329          */
2330 }
2331
2332 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2333 {
2334         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2335         u32 val;
2336         int i;
2337
2338         /* GAM 0x4000-0x4770 */
2339         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2340         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2341         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2342         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2343         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2344
2345         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2346                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2347
2348         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2349         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2350
2351         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2352         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2353         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2354         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2355
2356         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2357
2358         /* MBC 0x9024-0x91D0, 0x8500 */
2359         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2360         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2361         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2362
2363         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2364         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2365         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2366         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2367         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2368         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2369         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2370
2371         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2372         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2373         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2374         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2375         I915_WRITE(ECOBUS,              s->ecobus);
2376         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2377         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2378         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2379         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2380         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2381         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2382
2383         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2384         I915_WRITE(GTIMR,               s->gt_imr);
2385         I915_WRITE(GTIER,               s->gt_ier);
2386         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2387         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2388
2389         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2390                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2391
2392         /* GT SA CZ domain, 0x100000-0x138124 */
2393         I915_WRITE(TILECTL,                     s->tilectl);
2394         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2395         /*
2396          * Preserve the GT allow wake and GFX force clock bit, they are not
2397          * be restored, as they are used to control the s0ix suspend/resume
2398          * sequence by the caller.
2399          */
2400         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2401         val &= VLV_GTLC_ALLOWWAKEREQ;
2402         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2403         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2404
2405         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2406         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2407         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2408         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2409
2410         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2411
2412         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2413         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2414         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2415         I915_WRITE(VLV_PCBR,                    s->pcbr);
2416         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2417 }
2418
2419 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2420                                   u32 mask, u32 val)
2421 {
2422         /* The HW does not like us polling for PW_STATUS frequently, so
2423          * use the sleeping loop rather than risk the busy spin within
2424          * intel_wait_for_register().
2425          *
2426          * Transitioning between RC6 states should be at most 2ms (see
2427          * valleyview_enable_rps) so use a 3ms timeout.
2428          */
2429         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2430                         3);
2431 }
2432
2433 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2434 {
2435         u32 val;
2436         int err;
2437
2438         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2439         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2440         if (force_on)
2441                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2442         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2443
2444         if (!force_on)
2445                 return 0;
2446
2447         err = intel_wait_for_register(dev_priv,
2448                                       VLV_GTLC_SURVIVABILITY_REG,
2449                                       VLV_GFX_CLK_STATUS_BIT,
2450                                       VLV_GFX_CLK_STATUS_BIT,
2451                                       20);
2452         if (err)
2453                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2454                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2455
2456         return err;
2457 }
2458
2459 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2460 {
2461         u32 mask;
2462         u32 val;
2463         int err;
2464
2465         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2466         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2467         if (allow)
2468                 val |= VLV_GTLC_ALLOWWAKEREQ;
2469         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2470         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2471
2472         mask = VLV_GTLC_ALLOWWAKEACK;
2473         val = allow ? mask : 0;
2474
2475         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2476         if (err)
2477                 DRM_ERROR("timeout disabling GT waking\n");
2478
2479         return err;
2480 }
2481
2482 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2483                                   bool wait_for_on)
2484 {
2485         u32 mask;
2486         u32 val;
2487
2488         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2489         val = wait_for_on ? mask : 0;
2490
2491         /*
2492          * RC6 transitioning can be delayed up to 2 msec (see
2493          * valleyview_enable_rps), use 3 msec for safety.
2494          *
2495          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2496          * reset and we are trying to force the machine to sleep.
2497          */
2498         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2499                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2500                                  onoff(wait_for_on));
2501 }
2502
2503 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2504 {
2505         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2506                 return;
2507
2508         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2509         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2510 }
2511
2512 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2513 {
2514         u32 mask;
2515         int err;
2516
2517         /*
2518          * Bspec defines the following GT well on flags as debug only, so
2519          * don't treat them as hard failures.
2520          */
2521         vlv_wait_for_gt_wells(dev_priv, false);
2522
2523         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2524         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2525
2526         vlv_check_no_gt_access(dev_priv);
2527
2528         err = vlv_force_gfx_clock(dev_priv, true);
2529         if (err)
2530                 goto err1;
2531
2532         err = vlv_allow_gt_wake(dev_priv, false);
2533         if (err)
2534                 goto err2;
2535
2536         if (!IS_CHERRYVIEW(dev_priv))
2537                 vlv_save_gunit_s0ix_state(dev_priv);
2538
2539         err = vlv_force_gfx_clock(dev_priv, false);
2540         if (err)
2541                 goto err2;
2542
2543         return 0;
2544
2545 err2:
2546         /* For safety always re-enable waking and disable gfx clock forcing */
2547         vlv_allow_gt_wake(dev_priv, true);
2548 err1:
2549         vlv_force_gfx_clock(dev_priv, false);
2550
2551         return err;
2552 }
2553
2554 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2555                                 bool rpm_resume)
2556 {
2557         int err;
2558         int ret;
2559
2560         /*
2561          * If any of the steps fail just try to continue, that's the best we
2562          * can do at this point. Return the first error code (which will also
2563          * leave RPM permanently disabled).
2564          */
2565         ret = vlv_force_gfx_clock(dev_priv, true);
2566
2567         if (!IS_CHERRYVIEW(dev_priv))
2568                 vlv_restore_gunit_s0ix_state(dev_priv);
2569
2570         err = vlv_allow_gt_wake(dev_priv, true);
2571         if (!ret)
2572                 ret = err;
2573
2574         err = vlv_force_gfx_clock(dev_priv, false);
2575         if (!ret)
2576                 ret = err;
2577
2578         vlv_check_no_gt_access(dev_priv);
2579
2580         if (rpm_resume)
2581                 intel_init_clock_gating(dev_priv);
2582
2583         return ret;
2584 }
2585
2586 static int intel_runtime_suspend(struct device *kdev)
2587 {
2588         struct pci_dev *pdev = to_pci_dev(kdev);
2589         struct drm_device *dev = pci_get_drvdata(pdev);
2590         struct drm_i915_private *dev_priv = to_i915(dev);
2591         int ret;
2592
2593         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2594                 return -ENODEV;
2595
2596         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2597                 return -ENODEV;
2598
2599         DRM_DEBUG_KMS("Suspending device\n");
2600
2601         disable_rpm_wakeref_asserts(dev_priv);
2602
2603         /*
2604          * We are safe here against re-faults, since the fault handler takes
2605          * an RPM reference.
2606          */
2607         i915_gem_runtime_suspend(dev_priv);
2608
2609         intel_uc_suspend(dev_priv);
2610
2611         intel_runtime_pm_disable_interrupts(dev_priv);
2612
2613         intel_uncore_suspend(dev_priv);
2614
2615         ret = 0;
2616         if (IS_GEN9_LP(dev_priv)) {
2617                 bxt_display_core_uninit(dev_priv);
2618                 bxt_enable_dc9(dev_priv);
2619         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2620                 hsw_enable_pc8(dev_priv);
2621         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2622                 ret = vlv_suspend_complete(dev_priv);
2623         }
2624
2625         if (ret) {
2626                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2627                 intel_uncore_runtime_resume(dev_priv);
2628
2629                 intel_runtime_pm_enable_interrupts(dev_priv);
2630
2631                 intel_uc_resume(dev_priv);
2632
2633                 i915_gem_init_swizzling(dev_priv);
2634                 i915_gem_restore_fences(dev_priv);
2635
2636                 enable_rpm_wakeref_asserts(dev_priv);
2637
2638                 return ret;
2639         }
2640
2641         enable_rpm_wakeref_asserts(dev_priv);
2642         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2643
2644         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2645                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2646
2647         dev_priv->runtime_pm.suspended = true;
2648
2649         /*
2650          * FIXME: We really should find a document that references the arguments
2651          * used below!
2652          */
2653         if (IS_BROADWELL(dev_priv)) {
2654                 /*
2655                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2656                  * being detected, and the call we do at intel_runtime_resume()
2657                  * won't be able to restore them. Since PCI_D3hot matches the
2658                  * actual specification and appears to be working, use it.
2659                  */
2660                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2661         } else {
2662                 /*
2663                  * current versions of firmware which depend on this opregion
2664                  * notification have repurposed the D1 definition to mean
2665                  * "runtime suspended" vs. what you would normally expect (D3)
2666                  * to distinguish it from notifications that might be sent via
2667                  * the suspend path.
2668                  */
2669                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2670         }
2671
2672         assert_forcewakes_inactive(dev_priv);
2673
2674         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2675                 intel_hpd_poll_init(dev_priv);
2676
2677         DRM_DEBUG_KMS("Device suspended\n");
2678         return 0;
2679 }
2680
2681 static int intel_runtime_resume(struct device *kdev)
2682 {
2683         struct pci_dev *pdev = to_pci_dev(kdev);
2684         struct drm_device *dev = pci_get_drvdata(pdev);
2685         struct drm_i915_private *dev_priv = to_i915(dev);
2686         int ret = 0;
2687
2688         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2689                 return -ENODEV;
2690
2691         DRM_DEBUG_KMS("Resuming device\n");
2692
2693         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2694         disable_rpm_wakeref_asserts(dev_priv);
2695
2696         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2697         dev_priv->runtime_pm.suspended = false;
2698         if (intel_uncore_unclaimed_mmio(dev_priv))
2699                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2700
2701         if (IS_GEN9_LP(dev_priv)) {
2702                 bxt_disable_dc9(dev_priv);
2703                 bxt_display_core_init(dev_priv, true);
2704                 if (dev_priv->csr.dmc_payload &&
2705                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2706                         gen9_enable_dc5(dev_priv);
2707         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2708                 hsw_disable_pc8(dev_priv);
2709         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2710                 ret = vlv_resume_prepare(dev_priv, true);
2711         }
2712
2713         intel_uncore_runtime_resume(dev_priv);
2714
2715         intel_runtime_pm_enable_interrupts(dev_priv);
2716
2717         intel_uc_resume(dev_priv);
2718
2719         /*
2720          * No point of rolling back things in case of an error, as the best
2721          * we can do is to hope that things will still work (and disable RPM).
2722          */
2723         i915_gem_init_swizzling(dev_priv);
2724         i915_gem_restore_fences(dev_priv);
2725
2726         /*
2727          * On VLV/CHV display interrupts are part of the display
2728          * power well, so hpd is reinitialized from there. For
2729          * everyone else do it here.
2730          */
2731         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2732                 intel_hpd_init(dev_priv);
2733
2734         intel_enable_ipc(dev_priv);
2735
2736         enable_rpm_wakeref_asserts(dev_priv);
2737
2738         if (ret)
2739                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2740         else
2741                 DRM_DEBUG_KMS("Device resumed\n");
2742
2743         return ret;
2744 }
2745
2746 const struct dev_pm_ops i915_pm_ops = {
2747         /*
2748          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2749          * PMSG_RESUME]
2750          */
2751         .prepare = i915_pm_prepare,
2752         .suspend = i915_pm_suspend,
2753         .suspend_late = i915_pm_suspend_late,
2754         .resume_early = i915_pm_resume_early,
2755         .resume = i915_pm_resume,
2756
2757         /*
2758          * S4 event handlers
2759          * @freeze, @freeze_late    : called (1) before creating the
2760          *                            hibernation image [PMSG_FREEZE] and
2761          *                            (2) after rebooting, before restoring
2762          *                            the image [PMSG_QUIESCE]
2763          * @thaw, @thaw_early       : called (1) after creating the hibernation
2764          *                            image, before writing it [PMSG_THAW]
2765          *                            and (2) after failing to create or
2766          *                            restore the image [PMSG_RECOVER]
2767          * @poweroff, @poweroff_late: called after writing the hibernation
2768          *                            image, before rebooting [PMSG_HIBERNATE]
2769          * @restore, @restore_early : called after rebooting and restoring the
2770          *                            hibernation image [PMSG_RESTORE]
2771          */
2772         .freeze = i915_pm_freeze,
2773         .freeze_late = i915_pm_freeze_late,
2774         .thaw_early = i915_pm_thaw_early,
2775         .thaw = i915_pm_thaw,
2776         .poweroff = i915_pm_suspend,
2777         .poweroff_late = i915_pm_poweroff_late,
2778         .restore_early = i915_pm_restore_early,
2779         .restore = i915_pm_restore,
2780
2781         /* S0ix (via runtime suspend) event handlers */
2782         .runtime_suspend = intel_runtime_suspend,
2783         .runtime_resume = intel_runtime_resume,
2784 };
2785
2786 static const struct vm_operations_struct i915_gem_vm_ops = {
2787         .fault = i915_gem_fault,
2788         .open = drm_gem_vm_open,
2789         .close = drm_gem_vm_close,
2790 };
2791
2792 static const struct file_operations i915_driver_fops = {
2793         .owner = THIS_MODULE,
2794         .open = drm_open,
2795         .release = drm_release,
2796         .unlocked_ioctl = drm_ioctl,
2797         .mmap = drm_gem_mmap,
2798         .poll = drm_poll,
2799         .read = drm_read,
2800         .compat_ioctl = i915_compat_ioctl,
2801         .llseek = noop_llseek,
2802 };
2803
2804 static int
2805 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2806                           struct drm_file *file)
2807 {
2808         return -ENODEV;
2809 }
2810
2811 static const struct drm_ioctl_desc i915_ioctls[] = {
2812         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2813         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2814         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2815         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2816         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2817         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2818         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2820         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2821         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2822         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2823         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2824         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2825         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2826         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2827         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2828         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2834         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2837         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2838         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2844         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2848         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2849         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2850         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2851         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2852         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2853         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2854         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2855         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2856         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2857         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2858         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2859         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2860         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2861         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2862         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2863         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2864         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2865         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2866         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2867         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2868 };
2869
2870 static struct drm_driver driver = {
2871         /* Don't use MTRRs here; the Xserver or userspace app should
2872          * deal with them for Intel hardware.
2873          */
2874         .driver_features =
2875             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2876             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2877         .release = i915_driver_release,
2878         .open = i915_driver_open,
2879         .lastclose = i915_driver_lastclose,
2880         .postclose = i915_driver_postclose,
2881
2882         .gem_close_object = i915_gem_close_object,
2883         .gem_free_object_unlocked = i915_gem_free_object,
2884         .gem_vm_ops = &i915_gem_vm_ops,
2885
2886         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2887         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2888         .gem_prime_export = i915_gem_prime_export,
2889         .gem_prime_import = i915_gem_prime_import,
2890
2891         .dumb_create = i915_gem_dumb_create,
2892         .dumb_map_offset = i915_gem_mmap_gtt,
2893         .ioctls = i915_ioctls,
2894         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2895         .fops = &i915_driver_fops,
2896         .name = DRIVER_NAME,
2897         .desc = DRIVER_DESC,
2898         .date = DRIVER_DATE,
2899         .major = DRIVER_MAJOR,
2900         .minor = DRIVER_MINOR,
2901         .patchlevel = DRIVER_PATCHLEVEL,
2902 };
2903
2904 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2905 #include "selftests/mock_drm.c"
2906 #endif