drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52 #include "intel_uc.h"
  53
  54 static struct drm_driver driver;
  55
  56 static unsigned int i915_load_fail_count;
  57
  58 bool __i915_inject_load_failure(const char *func, int line)
  59 {
  60         if (i915_load_fail_count >= i915.inject_load_failure)
  61                 return false;
  62
  63         if (++i915_load_fail_count == i915.inject_load_failure) {
  64                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  65                          i915.inject_load_failure, func, line);
  66                 return true;
  67         }
  68
  69         return false;
  70 }
  71
  72 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  73 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  74                     "providing the dmesg log by booting with drm.debug=0xf"
  75
  76 void
  77 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  78               const char *fmt, ...)
  79 {
  80         static bool shown_bug_once;
  81         struct device *kdev = dev_priv->drm.dev;
  82         bool is_error = level[1] <= KERN_ERR[1];
  83         bool is_debug = level[1] == KERN_DEBUG[1];
  84         struct va_format vaf;
  85         va_list args;
  86
  87         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  88                 return;
  89
  90         va_start(args, fmt);
  91
  92         vaf.fmt = fmt;
  93         vaf.va = &args;
  94
  95         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  96                    __builtin_return_address(0), &vaf);
  97
  98         if (is_error && !shown_bug_once) {
  99                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 100                 shown_bug_once = true;
 101         }
 102
 103         va_end(args);
 104 }
 105
 106 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 107 {
 108         return i915.inject_load_failure &&
 109                i915_load_fail_count == i915.inject_load_failure;
 110 }
 111
 112 #define i915_load_error(dev_priv, fmt, ...)                                  \
 113         __i915_printk(dev_priv,                                              \
 114                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 115                       fmt, ##__VA_ARGS__)
 116
 117
 118 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 119 {
 120         enum intel_pch ret = PCH_NOP;
 121
 122         /*
 123          * In a virtualized passthrough environment we can be in a
 124          * setup where the ISA bridge is not able to be passed through.
 125          * In this case, a south bridge can be emulated and we have to
 126          * make an educated guess as to which PCH is really there.
 127          */
 128
 129         if (IS_GEN5(dev_priv)) {
 130                 ret = PCH_IBX;
 131                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 132         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 133                 ret = PCH_CPT;
 134                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 135         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 136                 ret = PCH_LPT;
 137                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 138         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 139                 ret = PCH_SPT;
 140                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 141         }
 142
 143         return ret;
 144 }
 145
 146 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 147 {
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev_priv));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 182                                         IS_IVYBRIDGE(dev_priv)));
 183                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 184                                 /* PantherPoint is CPT compatible */
 185                                 dev_priv->pch_type = PCH_CPT;
 186                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 187                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 188                                         IS_IVYBRIDGE(dev_priv)));
 189                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 190                                 dev_priv->pch_type = PCH_LPT;
 191                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 192                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 193                                         !IS_BROADWELL(dev_priv));
 194                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 195                                         IS_BDW_ULT(dev_priv));
 196                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 202                                         !IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_SPT;
 205                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 206                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 207                                         !IS_KABYLAKE(dev_priv));
 208                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 209                                 dev_priv->pch_type = PCH_SPT;
 210                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 211                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 212                                         !IS_KABYLAKE(dev_priv));
 213                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 214                                 dev_priv->pch_type = PCH_KBP;
 215                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 216                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 217                                         !IS_KABYLAKE(dev_priv));
 218                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 219                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 220                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 221                                     pch->subsystem_vendor ==
 222                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 223                                     pch->subsystem_device ==
 224                                             PCI_SUBDEVICE_ID_QEMU)) {
 225                                 dev_priv->pch_type =
 226                                         intel_virt_detect_pch(dev_priv);
 227                         } else
 228                                 continue;
 229
 230                         break;
 231                 }
 232         }
 233         if (!pch)
 234                 DRM_DEBUG_KMS("No PCH found.\n");
 235
 236         pci_dev_put(pch);
 237 }
 238
 239 static int i915_getparam(struct drm_device *dev, void *data,
 240                          struct drm_file *file_priv)
 241 {
 242         struct drm_i915_private *dev_priv = to_i915(dev);
 243         struct pci_dev *pdev = dev_priv->drm.pdev;
 244         drm_i915_getparam_t *param = data;
 245         int value;
 246
 247         switch (param->param) {
 248         case I915_PARAM_IRQ_ACTIVE:
 249         case I915_PARAM_ALLOW_BATCHBUFFER:
 250         case I915_PARAM_LAST_DISPATCH:
 251                 /* Reject all old ums/dri params. */
 252                 return -ENODEV;
 253         case I915_PARAM_CHIPSET_ID:
 254                 value = pdev->device;
 255                 break;
 256         case I915_PARAM_REVISION:
 257                 value = pdev->revision;
 258                 break;
 259         case I915_PARAM_NUM_FENCES_AVAIL:
 260                 value = dev_priv->num_fence_regs;
 261                 break;
 262         case I915_PARAM_HAS_OVERLAY:
 263                 value = dev_priv->overlay ? 1 : 0;
 264                 break;
 265         case I915_PARAM_HAS_BSD:
 266                 value = !!dev_priv->engine[VCS];
 267                 break;
 268         case I915_PARAM_HAS_BLT:
 269                 value = !!dev_priv->engine[BCS];
 270                 break;
 271         case I915_PARAM_HAS_VEBOX:
 272                 value = !!dev_priv->engine[VECS];
 273                 break;
 274         case I915_PARAM_HAS_BSD2:
 275                 value = !!dev_priv->engine[VCS2];
 276                 break;
 277         case I915_PARAM_HAS_EXEC_CONSTANTS:
 278                 value = INTEL_GEN(dev_priv) >= 4;
 279                 break;
 280         case I915_PARAM_HAS_LLC:
 281                 value = HAS_LLC(dev_priv);
 282                 break;
 283         case I915_PARAM_HAS_WT:
 284                 value = HAS_WT(dev_priv);
 285                 break;
 286         case I915_PARAM_HAS_ALIASING_PPGTT:
 287                 value = USES_PPGTT(dev_priv);
 288                 break;
 289         case I915_PARAM_HAS_SEMAPHORES:
 290                 value = i915.semaphores;
 291                 break;
 292         case I915_PARAM_HAS_SECURE_BATCHES:
 293                 value = capable(CAP_SYS_ADMIN);
 294                 break;
 295         case I915_PARAM_CMD_PARSER_VERSION:
 296                 value = i915_cmd_parser_get_version(dev_priv);
 297                 break;
 298         case I915_PARAM_SUBSLICE_TOTAL:
 299                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 300                 if (!value)
 301                         return -ENODEV;
 302                 break;
 303         case I915_PARAM_EU_TOTAL:
 304                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 305                 if (!value)
 306                         return -ENODEV;
 307                 break;
 308         case I915_PARAM_HAS_GPU_RESET:
 309                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 310                 break;
 311         case I915_PARAM_HAS_RESOURCE_STREAMER:
 312                 value = HAS_RESOURCE_STREAMER(dev_priv);
 313                 break;
 314         case I915_PARAM_HAS_POOLED_EU:
 315                 value = HAS_POOLED_EU(dev_priv);
 316                 break;
 317         case I915_PARAM_MIN_EU_IN_POOL:
 318                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 319                 break;
 320         case I915_PARAM_HUC_STATUS:
 321                 /* The register is already force-woken. We dont need
 322                  * any rpm here
 323                  */
 324                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 325                 break;
 326         case I915_PARAM_MMAP_GTT_VERSION:
 327                 /* Though we've started our numbering from 1, and so class all
 328                  * earlier versions as 0, in effect their value is undefined as
 329                  * the ioctl will report EINVAL for the unknown param!
 330                  */
 331                 value = i915_gem_mmap_gtt_version();
 332                 break;
 333         case I915_PARAM_HAS_SCHEDULER:
 334                 value = dev_priv->engine[RCS] &&
 335                         dev_priv->engine[RCS]->schedule;
 336                 break;
 337         case I915_PARAM_MMAP_VERSION:
 338                 /* Remember to bump this if the version changes! */
 339         case I915_PARAM_HAS_GEM:
 340         case I915_PARAM_HAS_PAGEFLIPPING:
 341         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 342         case I915_PARAM_HAS_RELAXED_FENCING:
 343         case I915_PARAM_HAS_COHERENT_RINGS:
 344         case I915_PARAM_HAS_RELAXED_DELTA:
 345         case I915_PARAM_HAS_GEN7_SOL_RESET:
 346         case I915_PARAM_HAS_WAIT_TIMEOUT:
 347         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 348         case I915_PARAM_HAS_PINNED_BATCHES:
 349         case I915_PARAM_HAS_EXEC_NO_RELOC:
 350         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 351         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 352         case I915_PARAM_HAS_EXEC_SOFTPIN:
 353                 /* For the time being all of these are always true;
 354                  * if some supported hardware does not have one of these
 355                  * features this value needs to be provided from
 356                  * INTEL_INFO(), a feature macro, or similar.
 357                  */
 358                 value = 1;
 359                 break;
 360         default:
 361                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 362                 return -EINVAL;
 363         }
 364
 365         if (put_user(value, param->value))
 366                 return -EFAULT;
 367
 368         return 0;
 369 }
 370
 371 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 372 {
 373         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 374         if (!dev_priv->bridge_dev) {
 375                 DRM_ERROR("bridge device not found\n");
 376                 return -1;
 377         }
 378         return 0;
 379 }
 380
 381 /* Allocate space for the MCH regs if needed, return nonzero on error */
 382 static int
 383 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 384 {
 385         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 386         u32 temp_lo, temp_hi = 0;
 387         u64 mchbar_addr;
 388         int ret;
 389
 390         if (INTEL_GEN(dev_priv) >= 4)
 391                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 392         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 393         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 394
 395         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 396 #ifdef CONFIG_PNP
 397         if (mchbar_addr &&
 398             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 399                 return 0;
 400 #endif
 401
 402         /* Get some space for it */
 403         dev_priv->mch_res.name = "i915 MCHBAR";
 404         dev_priv->mch_res.flags = IORESOURCE_MEM;
 405         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 406                                      &dev_priv->mch_res,
 407                                      MCHBAR_SIZE, MCHBAR_SIZE,
 408                                      PCIBIOS_MIN_MEM,
 409                                      0, pcibios_align_resource,
 410                                      dev_priv->bridge_dev);
 411         if (ret) {
 412                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 413                 dev_priv->mch_res.start = 0;
 414                 return ret;
 415         }
 416
 417         if (INTEL_GEN(dev_priv) >= 4)
 418                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 419                                        upper_32_bits(dev_priv->mch_res.start));
 420
 421         pci_write_config_dword(dev_priv->bridge_dev, reg,
 422                                lower_32_bits(dev_priv->mch_res.start));
 423         return 0;
 424 }
 425
 426 /* Setup MCHBAR if possible, return true if we should disable it again */
 427 static void
 428 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 429 {
 430         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 431         u32 temp;
 432         bool enabled;
 433
 434         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 435                 return;
 436
 437         dev_priv->mchbar_need_disable = false;
 438
 439         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 440                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 441                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 442         } else {
 443                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 444                 enabled = temp & 1;
 445         }
 446
 447         /* If it's already enabled, don't have to do anything */
 448         if (enabled)
 449                 return;
 450
 451         if (intel_alloc_mchbar_resource(dev_priv))
 452                 return;
 453
 454         dev_priv->mchbar_need_disable = true;
 455
 456         /* Space is allocated or reserved, so enable it. */
 457         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 458                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 459                                        temp | DEVEN_MCHBAR_EN);
 460         } else {
 461                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 462                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 463         }
 464 }
 465
 466 static void
 467 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 468 {
 469         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 470
 471         if (dev_priv->mchbar_need_disable) {
 472                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 473                         u32 deven_val;
 474
 475                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 476                                               &deven_val);
 477                         deven_val &= ~DEVEN_MCHBAR_EN;
 478                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 479                                                deven_val);
 480                 } else {
 481                         u32 mchbar_val;
 482
 483                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 484                                               &mchbar_val);
 485                         mchbar_val &= ~1;
 486                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 487                                                mchbar_val);
 488                 }
 489         }
 490
 491         if (dev_priv->mch_res.start)
 492                 release_resource(&dev_priv->mch_res);
 493 }
 494
 495 /* true = enable decode, false = disable decoder */
 496 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 497 {
 498         struct drm_i915_private *dev_priv = cookie;
 499
 500         intel_modeset_vga_set_state(dev_priv, state);
 501         if (state)
 502                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 503                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 504         else
 505                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506 }
 507
 508 static int i915_resume_switcheroo(struct drm_device *dev);
 509 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 510
 511 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 512 {
 513         struct drm_device *dev = pci_get_drvdata(pdev);
 514         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 515
 516         if (state == VGA_SWITCHEROO_ON) {
 517                 pr_info("switched on\n");
 518                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 519                 /* i915 resume handler doesn't set to D0 */
 520                 pci_set_power_state(pdev, PCI_D0);
 521                 i915_resume_switcheroo(dev);
 522                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 523         } else {
 524                 pr_info("switched off\n");
 525                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 526                 i915_suspend_switcheroo(dev, pmm);
 527                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 528         }
 529 }
 530
 531 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 532 {
 533         struct drm_device *dev = pci_get_drvdata(pdev);
 534
 535         /*
 536          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 537          * locking inversion with the driver load path. And the access here is
 538          * completely racy anyway. So don't bother with locking for now.
 539          */
 540         return dev->open_count == 0;
 541 }
 542
 543 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 544         .set_gpu_state = i915_switcheroo_set_state,
 545         .reprobe = NULL,
 546         .can_switch = i915_switcheroo_can_switch,
 547 };
 548
 549 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 550 {
 551         mutex_lock(&dev_priv->drm.struct_mutex);
 552         i915_gem_cleanup_engines(dev_priv);
 553         i915_gem_context_fini(dev_priv);
 554         mutex_unlock(&dev_priv->drm.struct_mutex);
 555
 556         i915_gem_drain_freed_objects(dev_priv);
 557
 558         WARN_ON(!list_empty(&dev_priv->context_list));
 559 }
 560
 561 static int i915_load_modeset_init(struct drm_device *dev)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(dev);
 564         struct pci_dev *pdev = dev_priv->drm.pdev;
 565         int ret;
 566
 567         if (i915_inject_load_failure())
 568                 return -ENODEV;
 569
 570         ret = intel_bios_init(dev_priv);
 571         if (ret)
 572                 DRM_INFO("failed to find VBIOS tables\n");
 573
 574         /* If we have > 1 VGA cards, then we need to arbitrate access
 575          * to the common VGA resources.
 576          *
 577          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 578          * then we do not take part in VGA arbitration and the
 579          * vga_client_register() fails with -ENODEV.
 580          */
 581         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 582         if (ret && ret != -ENODEV)
 583                 goto out;
 584
 585         intel_register_dsm_handler();
 586
 587         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 588         if (ret)
 589                 goto cleanup_vga_client;
 590
 591         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 592         intel_update_rawclk(dev_priv);
 593
 594         intel_power_domains_init_hw(dev_priv, false);
 595
 596         intel_csr_ucode_init(dev_priv);
 597
 598         ret = intel_irq_install(dev_priv);
 599         if (ret)
 600                 goto cleanup_csr;
 601
 602         intel_setup_gmbus(dev_priv);
 603
 604         /* Important: The output setup functions called by modeset_init need
 605          * working irqs for e.g. gmbus and dp aux transfers. */
 606         ret = intel_modeset_init(dev);
 607         if (ret)
 608                 goto cleanup_irq;
 609
 610         intel_huc_init(dev_priv);
 611         intel_guc_init(dev_priv);
 612
 613         ret = i915_gem_init(dev_priv);
 614         if (ret)
 615                 goto cleanup_irq;
 616
 617         intel_modeset_gem_init(dev);
 618
 619         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 620                 return 0;
 621
 622         ret = intel_fbdev_init(dev);
 623         if (ret)
 624                 goto cleanup_gem;
 625
 626         /* Only enable hotplug handling once the fbdev is fully set up. */
 627         intel_hpd_init(dev_priv);
 628
 629         drm_kms_helper_poll_init(dev);
 630
 631         return 0;
 632
 633 cleanup_gem:
 634         if (i915_gem_suspend(dev_priv))
 635                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 636         i915_gem_fini(dev_priv);
 637 cleanup_irq:
 638         intel_guc_fini(dev_priv);
 639         intel_huc_fini(dev_priv);
 640         drm_irq_uninstall(dev);
 641         intel_teardown_gmbus(dev_priv);
 642 cleanup_csr:
 643         intel_csr_ucode_fini(dev_priv);
 644         intel_power_domains_fini(dev_priv);
 645         vga_switcheroo_unregister_client(pdev);
 646 cleanup_vga_client:
 647         vga_client_register(pdev, NULL, NULL, NULL);
 648 out:
 649         return ret;
 650 }
 651
 652 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 653 {
 654         struct apertures_struct *ap;
 655         struct pci_dev *pdev = dev_priv->drm.pdev;
 656         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 657         bool primary;
 658         int ret;
 659
 660         ap = alloc_apertures(1);
 661         if (!ap)
 662                 return -ENOMEM;
 663
 664         ap->ranges[0].base = ggtt->mappable_base;
 665         ap->ranges[0].size = ggtt->mappable_end;
 666
 667         primary =
 668                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 669
 670         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 671
 672         kfree(ap);
 673
 674         return ret;
 675 }
 676
 677 #if !defined(CONFIG_VGA_CONSOLE)
 678 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 679 {
 680         return 0;
 681 }
 682 #elif !defined(CONFIG_DUMMY_CONSOLE)
 683 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 684 {
 685         return -ENODEV;
 686 }
 687 #else
 688 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 689 {
 690         int ret = 0;
 691
 692         DRM_INFO("Replacing VGA console driver\n");
 693
 694         console_lock();
 695         if (con_is_bound(&vga_con))
 696                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 697         if (ret == 0) {
 698                 ret = do_unregister_con_driver(&vga_con);
 699
 700                 /* Ignore "already unregistered". */
 701                 if (ret == -ENODEV)
 702                         ret = 0;
 703         }
 704         console_unlock();
 705
 706         return ret;
 707 }
 708 #endif
 709
 710 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 711 {
 712         /*
 713          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 714          * CHV x1 PHY (DP/HDMI D)
 715          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 716          */
 717         if (IS_CHERRYVIEW(dev_priv)) {
 718                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 719                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 720         } else if (IS_VALLEYVIEW(dev_priv)) {
 721                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 722         }
 723 }
 724
 725 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 726 {
 727         /*
 728          * The i915 workqueue is primarily used for batched retirement of
 729          * requests (and thus managing bo) once the task has been completed
 730          * by the GPU. i915_gem_retire_requests() is called directly when we
 731          * need high-priority retirement, such as waiting for an explicit
 732          * bo.
 733          *
 734          * It is also used for periodic low-priority events, such as
 735          * idle-timers and recording error state.
 736          *
 737          * All tasks on the workqueue are expected to acquire the dev mutex
 738          * so there is no point in running more than one instance of the
 739          * workqueue at any time.  Use an ordered one.
 740          */
 741         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 742         if (dev_priv->wq == NULL)
 743                 goto out_err;
 744
 745         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 746         if (dev_priv->hotplug.dp_wq == NULL)
 747                 goto out_free_wq;
 748
 749         return 0;
 750
 751 out_free_wq:
 752         destroy_workqueue(dev_priv->wq);
 753 out_err:
 754         DRM_ERROR("Failed to allocate workqueues.\n");
 755
 756         return -ENOMEM;
 757 }
 758
 759 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 760 {
 761         destroy_workqueue(dev_priv->hotplug.dp_wq);
 762         destroy_workqueue(dev_priv->wq);
 763 }
 764
 765 /*
 766  * We don't keep the workarounds for pre-production hardware, so we expect our
 767  * driver to fail on these machines in one way or another. A little warning on
 768  * dmesg may help both the user and the bug triagers.
 769  */
 770 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 771 {
 772         if (IS_HSW_EARLY_SDV(dev_priv) ||
 773             IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
 774                 DRM_ERROR("This is a pre-production stepping. "
 775                           "It may not be fully functional.\n");
 776 }
 777
 778 /**
 779  * i915_driver_init_early - setup state not requiring device access
 780  * @dev_priv: device private
 781  *
 782  * Initialize everything that is a "SW-only" state, that is state not
 783  * requiring accessing the device or exposing the driver via kernel internal
 784  * or userspace interfaces. Example steps belonging here: lock initialization,
 785  * system memory allocation, setting up device specific attributes and
 786  * function hooks not requiring accessing the device.
 787  */
 788 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 789                                   const struct pci_device_id *ent)
 790 {
 791         const struct intel_device_info *match_info =
 792                 (struct intel_device_info *)ent->driver_data;
 793         struct intel_device_info *device_info;
 794         int ret = 0;
 795
 796         if (i915_inject_load_failure())
 797                 return -ENODEV;
 798
 799         /* Setup the write-once "constant" device info */
 800         device_info = mkwrite_device_info(dev_priv);
 801         memcpy(device_info, match_info, sizeof(*device_info));
 802         device_info->device_id = dev_priv->drm.pdev->device;
 803
 804         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 805         device_info->gen_mask = BIT(device_info->gen - 1);
 806
 807         spin_lock_init(&dev_priv->irq_lock);
 808         spin_lock_init(&dev_priv->gpu_error.lock);
 809         mutex_init(&dev_priv->backlight_lock);
 810         spin_lock_init(&dev_priv->uncore.lock);
 811         spin_lock_init(&dev_priv->mm.object_stat_lock);
 812         spin_lock_init(&dev_priv->mmio_flip_lock);
 813         spin_lock_init(&dev_priv->wm.dsparb_lock);
 814         mutex_init(&dev_priv->sb_lock);
 815         mutex_init(&dev_priv->modeset_restore_lock);
 816         mutex_init(&dev_priv->av_mutex);
 817         mutex_init(&dev_priv->wm.wm_mutex);
 818         mutex_init(&dev_priv->pps_mutex);
 819
 820         intel_uc_init_early(dev_priv);
 821
 822         i915_memcpy_init_early(dev_priv);
 823
 824         ret = i915_workqueues_init(dev_priv);
 825         if (ret < 0)
 826                 return ret;
 827
 828         /* This must be called before any calls to HAS_PCH_* */
 829         intel_detect_pch(dev_priv);
 830
 831         intel_pm_setup(dev_priv);
 832         intel_init_dpio(dev_priv);
 833         intel_power_domains_init(dev_priv);
 834         intel_irq_init(dev_priv);
 835         intel_hangcheck_init(dev_priv);
 836         intel_init_display_hooks(dev_priv);
 837         intel_init_clock_gating_hooks(dev_priv);
 838         intel_init_audio_hooks(dev_priv);
 839         ret = i915_gem_load_init(dev_priv);
 840         if (ret < 0)
 841                 goto err_workqueues;
 842
 843         intel_display_crc_init(dev_priv);
 844
 845         intel_device_info_dump(dev_priv);
 846
 847         intel_detect_preproduction_hw(dev_priv);
 848
 849         i915_perf_init(dev_priv);
 850
 851         return 0;
 852
 853 err_workqueues:
 854         i915_workqueues_cleanup(dev_priv);
 855         return ret;
 856 }
 857
 858 /**
 859  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 860  * @dev_priv: device private
 861  */
 862 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 863 {
 864         i915_perf_fini(dev_priv);
 865         i915_gem_load_cleanup(dev_priv);
 866         i915_workqueues_cleanup(dev_priv);
 867 }
 868
 869 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 870 {
 871         struct pci_dev *pdev = dev_priv->drm.pdev;
 872         int mmio_bar;
 873         int mmio_size;
 874
 875         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 876         /*
 877          * Before gen4, the registers and the GTT are behind different BARs.
 878          * However, from gen4 onwards, the registers and the GTT are shared
 879          * in the same BAR, so we want to restrict this ioremap from
 880          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 881          * the register BAR remains the same size for all the earlier
 882          * generations up to Ironlake.
 883          */
 884         if (INTEL_GEN(dev_priv) < 5)
 885                 mmio_size = 512 * 1024;
 886         else
 887                 mmio_size = 2 * 1024 * 1024;
 888         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 889         if (dev_priv->regs == NULL) {
 890                 DRM_ERROR("failed to map registers\n");
 891
 892                 return -EIO;
 893         }
 894
 895         /* Try to make sure MCHBAR is enabled before poking at it */
 896         intel_setup_mchbar(dev_priv);
 897
 898         return 0;
 899 }
 900
 901 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 902 {
 903         struct pci_dev *pdev = dev_priv->drm.pdev;
 904
 905         intel_teardown_mchbar(dev_priv);
 906         pci_iounmap(pdev, dev_priv->regs);
 907 }
 908
 909 /**
 910  * i915_driver_init_mmio - setup device MMIO
 911  * @dev_priv: device private
 912  *
 913  * Setup minimal device state necessary for MMIO accesses later in the
 914  * initialization sequence. The setup here should avoid any other device-wide
 915  * side effects or exposing the driver via kernel internal or user space
 916  * interfaces.
 917  */
 918 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 919 {
 920         int ret;
 921
 922         if (i915_inject_load_failure())
 923                 return -ENODEV;
 924
 925         if (i915_get_bridge_dev(dev_priv))
 926                 return -EIO;
 927
 928         ret = i915_mmio_setup(dev_priv);
 929         if (ret < 0)
 930                 goto put_bridge;
 931
 932         intel_uncore_init(dev_priv);
 933
 934         return 0;
 935
 936 put_bridge:
 937         pci_dev_put(dev_priv->bridge_dev);
 938
 939         return ret;
 940 }
 941
 942 /**
 943  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 944  * @dev_priv: device private
 945  */
 946 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 947 {
 948         intel_uncore_fini(dev_priv);
 949         i915_mmio_cleanup(dev_priv);
 950         pci_dev_put(dev_priv->bridge_dev);
 951 }
 952
 953 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 954 {
 955         i915.enable_execlists =
 956                 intel_sanitize_enable_execlists(dev_priv,
 957                                                 i915.enable_execlists);
 958
 959         /*
 960          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 961          * user's requested state against the hardware/driver capabilities.  We
 962          * do this now so that we can print out any log messages once rather
 963          * than every time we check intel_enable_ppgtt().
 964          */
 965         i915.enable_ppgtt =
 966                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 967         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 968
 969         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 970         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 971 }
 972
 973 /**
 974  * i915_driver_init_hw - setup state requiring device access
 975  * @dev_priv: device private
 976  *
 977  * Setup state that requires accessing the device, but doesn't require
 978  * exposing the driver via kernel internal or userspace interfaces.
 979  */
 980 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 981 {
 982         struct pci_dev *pdev = dev_priv->drm.pdev;
 983         int ret;
 984
 985         if (i915_inject_load_failure())
 986                 return -ENODEV;
 987
 988         intel_device_info_runtime_init(dev_priv);
 989
 990         intel_sanitize_options(dev_priv);
 991
 992         ret = i915_ggtt_probe_hw(dev_priv);
 993         if (ret)
 994                 return ret;
 995
 996         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 997          * otherwise the vga fbdev driver falls over. */
 998         ret = i915_kick_out_firmware_fb(dev_priv);
 999         if (ret) {
1000                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1001                 goto out_ggtt;
1002         }
1003
1004         ret = i915_kick_out_vgacon(dev_priv);
1005         if (ret) {
1006                 DRM_ERROR("failed to remove conflicting VGA console\n");
1007                 goto out_ggtt;
1008         }
1009
1010         ret = i915_ggtt_init_hw(dev_priv);
1011         if (ret)
1012                 return ret;
1013
1014         ret = i915_ggtt_enable_hw(dev_priv);
1015         if (ret) {
1016                 DRM_ERROR("failed to enable GGTT\n");
1017                 goto out_ggtt;
1018         }
1019
1020         pci_set_master(pdev);
1021
1022         /* overlay on gen2 is broken and can't address above 1G */
1023         if (IS_GEN2(dev_priv)) {
1024                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1025                 if (ret) {
1026                         DRM_ERROR("failed to set DMA mask\n");
1027
1028                         goto out_ggtt;
1029                 }
1030         }
1031
1032         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1033          * using 32bit addressing, overwriting memory if HWS is located
1034          * above 4GB.
1035          *
1036          * The documentation also mentions an issue with undefined
1037          * behaviour if any general state is accessed within a page above 4GB,
1038          * which also needs to be handled carefully.
1039          */
1040         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1041                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1042
1043                 if (ret) {
1044                         DRM_ERROR("failed to set DMA mask\n");
1045
1046                         goto out_ggtt;
1047                 }
1048         }
1049
1050         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1051                            PM_QOS_DEFAULT_VALUE);
1052
1053         intel_uncore_sanitize(dev_priv);
1054
1055         intel_opregion_setup(dev_priv);
1056
1057         i915_gem_load_init_fences(dev_priv);
1058
1059         /* On the 945G/GM, the chipset reports the MSI capability on the
1060          * integrated graphics even though the support isn't actually there
1061          * according to the published specs.  It doesn't appear to function
1062          * correctly in testing on 945G.
1063          * This may be a side effect of MSI having been made available for PEG
1064          * and the registers being closely associated.
1065          *
1066          * According to chipset errata, on the 965GM, MSI interrupts may
1067          * be lost or delayed, but we use them anyways to avoid
1068          * stuck interrupts on some machines.
1069          */
1070         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1071                 if (pci_enable_msi(pdev) < 0)
1072                         DRM_DEBUG_DRIVER("can't enable MSI");
1073         }
1074
1075         ret = intel_gvt_init(dev_priv);
1076         if (ret)
1077                 goto out_ggtt;
1078
1079         return 0;
1080
1081 out_ggtt:
1082         i915_ggtt_cleanup_hw(dev_priv);
1083
1084         return ret;
1085 }
1086
1087 /**
1088  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1089  * @dev_priv: device private
1090  */
1091 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1092 {
1093         struct pci_dev *pdev = dev_priv->drm.pdev;
1094
1095         if (pdev->msi_enabled)
1096                 pci_disable_msi(pdev);
1097
1098         pm_qos_remove_request(&dev_priv->pm_qos);
1099         i915_ggtt_cleanup_hw(dev_priv);
1100 }
1101
1102 /**
1103  * i915_driver_register - register the driver with the rest of the system
1104  * @dev_priv: device private
1105  *
1106  * Perform any steps necessary to make the driver available via kernel
1107  * internal or userspace interfaces.
1108  */
1109 static void i915_driver_register(struct drm_i915_private *dev_priv)
1110 {
1111         struct drm_device *dev = &dev_priv->drm;
1112
1113         i915_gem_shrinker_init(dev_priv);
1114
1115         /*
1116          * Notify a valid surface after modesetting,
1117          * when running inside a VM.
1118          */
1119         if (intel_vgpu_active(dev_priv))
1120                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1121
1122         /* Reveal our presence to userspace */
1123         if (drm_dev_register(dev, 0) == 0) {
1124                 i915_debugfs_register(dev_priv);
1125                 i915_guc_log_register(dev_priv);
1126                 i915_setup_sysfs(dev_priv);
1127
1128                 /* Depends on sysfs having been initialized */
1129                 i915_perf_register(dev_priv);
1130         } else
1131                 DRM_ERROR("Failed to register driver for userspace access!\n");
1132
1133         if (INTEL_INFO(dev_priv)->num_pipes) {
1134                 /* Must be done after probing outputs */
1135                 intel_opregion_register(dev_priv);
1136                 acpi_video_register();
1137         }
1138
1139         if (IS_GEN5(dev_priv))
1140                 intel_gpu_ips_init(dev_priv);
1141
1142         intel_audio_init(dev_priv);
1143
1144         /*
1145          * Some ports require correctly set-up hpd registers for detection to
1146          * work properly (leading to ghost connected connector status), e.g. VGA
1147          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1148          * irqs are fully enabled. We do it last so that the async config
1149          * cannot run before the connectors are registered.
1150          */
1151         intel_fbdev_initial_config_async(dev);
1152 }
1153
1154 /**
1155  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1156  * @dev_priv: device private
1157  */
1158 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1159 {
1160         intel_audio_deinit(dev_priv);
1161
1162         intel_gpu_ips_teardown();
1163         acpi_video_unregister();
1164         intel_opregion_unregister(dev_priv);
1165
1166         i915_perf_unregister(dev_priv);
1167
1168         i915_teardown_sysfs(dev_priv);
1169         i915_guc_log_unregister(dev_priv);
1170         i915_debugfs_unregister(dev_priv);
1171         drm_dev_unregister(&dev_priv->drm);
1172
1173         i915_gem_shrinker_cleanup(dev_priv);
1174 }
1175
1176 /**
1177  * i915_driver_load - setup chip and create an initial config
1178  * @pdev: PCI device
1179  * @ent: matching PCI ID entry
1180  *
1181  * The driver load routine has to do several things:
1182  *   - drive output discovery via intel_modeset_init()
1183  *   - initialize the memory manager
1184  *   - allocate initial config memory
1185  *   - setup the DRM framebuffer with the allocated memory
1186  */
1187 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1188 {
1189         struct drm_i915_private *dev_priv;
1190         int ret;
1191
1192         if (i915.nuclear_pageflip)
1193                 driver.driver_features |= DRIVER_ATOMIC;
1194
1195         ret = -ENOMEM;
1196         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1197         if (dev_priv)
1198                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1199         if (ret) {
1200                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1201                 kfree(dev_priv);
1202                 return ret;
1203         }
1204
1205         dev_priv->drm.pdev = pdev;
1206         dev_priv->drm.dev_private = dev_priv;
1207
1208         ret = pci_enable_device(pdev);
1209         if (ret)
1210                 goto out_free_priv;
1211
1212         pci_set_drvdata(pdev, &dev_priv->drm);
1213
1214         ret = i915_driver_init_early(dev_priv, ent);
1215         if (ret < 0)
1216                 goto out_pci_disable;
1217
1218         intel_runtime_pm_get(dev_priv);
1219
1220         ret = i915_driver_init_mmio(dev_priv);
1221         if (ret < 0)
1222                 goto out_runtime_pm_put;
1223
1224         ret = i915_driver_init_hw(dev_priv);
1225         if (ret < 0)
1226                 goto out_cleanup_mmio;
1227
1228         /*
1229          * TODO: move the vblank init and parts of modeset init steps into one
1230          * of the i915_driver_init_/i915_driver_register functions according
1231          * to the role/effect of the given init step.
1232          */
1233         if (INTEL_INFO(dev_priv)->num_pipes) {
1234                 ret = drm_vblank_init(&dev_priv->drm,
1235                                       INTEL_INFO(dev_priv)->num_pipes);
1236                 if (ret)
1237                         goto out_cleanup_hw;
1238         }
1239
1240         ret = i915_load_modeset_init(&dev_priv->drm);
1241         if (ret < 0)
1242                 goto out_cleanup_vblank;
1243
1244         i915_driver_register(dev_priv);
1245
1246         intel_runtime_pm_enable(dev_priv);
1247
1248         dev_priv->ipc_enabled = false;
1249
1250         /* Everything is in place, we can now relax! */
1251         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1252                  driver.name, driver.major, driver.minor, driver.patchlevel,
1253                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1254         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1255                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1256         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1257                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1258
1259         intel_runtime_pm_put(dev_priv);
1260
1261         return 0;
1262
1263 out_cleanup_vblank:
1264         drm_vblank_cleanup(&dev_priv->drm);
1265 out_cleanup_hw:
1266         i915_driver_cleanup_hw(dev_priv);
1267 out_cleanup_mmio:
1268         i915_driver_cleanup_mmio(dev_priv);
1269 out_runtime_pm_put:
1270         intel_runtime_pm_put(dev_priv);
1271         i915_driver_cleanup_early(dev_priv);
1272 out_pci_disable:
1273         pci_disable_device(pdev);
1274 out_free_priv:
1275         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1276         drm_dev_unref(&dev_priv->drm);
1277         return ret;
1278 }
1279
1280 void i915_driver_unload(struct drm_device *dev)
1281 {
1282         struct drm_i915_private *dev_priv = to_i915(dev);
1283         struct pci_dev *pdev = dev_priv->drm.pdev;
1284
1285         intel_fbdev_fini(dev);
1286
1287         if (i915_gem_suspend(dev_priv))
1288                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1289
1290         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1291
1292         intel_gvt_cleanup(dev_priv);
1293
1294         i915_driver_unregister(dev_priv);
1295
1296         drm_vblank_cleanup(dev);
1297
1298         intel_modeset_cleanup(dev);
1299
1300         /*
1301          * free the memory space allocated for the child device
1302          * config parsed from VBT
1303          */
1304         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1305                 kfree(dev_priv->vbt.child_dev);
1306                 dev_priv->vbt.child_dev = NULL;
1307                 dev_priv->vbt.child_dev_num = 0;
1308         }
1309         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1310         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1311         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1312         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1313
1314         vga_switcheroo_unregister_client(pdev);
1315         vga_client_register(pdev, NULL, NULL, NULL);
1316
1317         intel_csr_ucode_fini(dev_priv);
1318
1319         /* Free error state after interrupts are fully disabled. */
1320         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1321         i915_destroy_error_state(dev_priv);
1322
1323         /* Flush any outstanding unpin_work. */
1324         drain_workqueue(dev_priv->wq);
1325
1326         intel_guc_fini(dev_priv);
1327         intel_huc_fini(dev_priv);
1328         i915_gem_fini(dev_priv);
1329         intel_fbc_cleanup_cfb(dev_priv);
1330
1331         intel_power_domains_fini(dev_priv);
1332
1333         i915_driver_cleanup_hw(dev_priv);
1334         i915_driver_cleanup_mmio(dev_priv);
1335
1336         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1337
1338         i915_driver_cleanup_early(dev_priv);
1339 }
1340
1341 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1342 {
1343         int ret;
1344
1345         ret = i915_gem_open(dev, file);
1346         if (ret)
1347                 return ret;
1348
1349         return 0;
1350 }
1351
1352 /**
1353  * i915_driver_lastclose - clean up after all DRM clients have exited
1354  * @dev: DRM device
1355  *
1356  * Take care of cleaning up after all DRM clients have exited.  In the
1357  * mode setting case, we want to restore the kernel's initial mode (just
1358  * in case the last client left us in a bad state).
1359  *
1360  * Additionally, in the non-mode setting case, we'll tear down the GTT
1361  * and DMA structures, since the kernel won't be using them, and clea
1362  * up any GEM state.
1363  */
1364 static void i915_driver_lastclose(struct drm_device *dev)
1365 {
1366         intel_fbdev_restore_mode(dev);
1367         vga_switcheroo_process_delayed_switch();
1368 }
1369
1370 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1371 {
1372         mutex_lock(&dev->struct_mutex);
1373         i915_gem_context_close(dev, file);
1374         i915_gem_release(dev, file);
1375         mutex_unlock(&dev->struct_mutex);
1376 }
1377
1378 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1379 {
1380         struct drm_i915_file_private *file_priv = file->driver_priv;
1381
1382         kfree(file_priv);
1383 }
1384
1385 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1386 {
1387         struct drm_device *dev = &dev_priv->drm;
1388         struct intel_encoder *encoder;
1389
1390         drm_modeset_lock_all(dev);
1391         for_each_intel_encoder(dev, encoder)
1392                 if (encoder->suspend)
1393                         encoder->suspend(encoder);
1394         drm_modeset_unlock_all(dev);
1395 }
1396
1397 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1398                               bool rpm_resume);
1399 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1400
1401 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1402 {
1403 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1404         if (acpi_target_system_state() < ACPI_STATE_S3)
1405                 return true;
1406 #endif
1407         return false;
1408 }
1409
1410 static int i915_drm_suspend(struct drm_device *dev)
1411 {
1412         struct drm_i915_private *dev_priv = to_i915(dev);
1413         struct pci_dev *pdev = dev_priv->drm.pdev;
1414         pci_power_t opregion_target_state;
1415         int error;
1416
1417         /* ignore lid events during suspend */
1418         mutex_lock(&dev_priv->modeset_restore_lock);
1419         dev_priv->modeset_restore = MODESET_SUSPENDED;
1420         mutex_unlock(&dev_priv->modeset_restore_lock);
1421
1422         disable_rpm_wakeref_asserts(dev_priv);
1423
1424         /* We do a lot of poking in a lot of registers, make sure they work
1425          * properly. */
1426         intel_display_set_init_power(dev_priv, true);
1427
1428         drm_kms_helper_poll_disable(dev);
1429
1430         pci_save_state(pdev);
1431
1432         error = i915_gem_suspend(dev_priv);
1433         if (error) {
1434                 dev_err(&pdev->dev,
1435                         "GEM idle failed, resume might fail\n");
1436                 goto out;
1437         }
1438
1439         intel_guc_suspend(dev_priv);
1440
1441         intel_display_suspend(dev);
1442
1443         intel_dp_mst_suspend(dev);
1444
1445         intel_runtime_pm_disable_interrupts(dev_priv);
1446         intel_hpd_cancel_work(dev_priv);
1447
1448         intel_suspend_encoders(dev_priv);
1449
1450         intel_suspend_hw(dev_priv);
1451
1452         i915_gem_suspend_gtt_mappings(dev_priv);
1453
1454         i915_save_state(dev_priv);
1455
1456         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1457         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1458
1459         intel_uncore_suspend(dev_priv);
1460         intel_opregion_unregister(dev_priv);
1461
1462         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1463
1464         dev_priv->suspend_count++;
1465
1466         intel_csr_ucode_suspend(dev_priv);
1467
1468 out:
1469         enable_rpm_wakeref_asserts(dev_priv);
1470
1471         return error;
1472 }
1473
1474 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1475 {
1476         struct drm_i915_private *dev_priv = to_i915(dev);
1477         struct pci_dev *pdev = dev_priv->drm.pdev;
1478         bool fw_csr;
1479         int ret;
1480
1481         disable_rpm_wakeref_asserts(dev_priv);
1482
1483         intel_display_set_init_power(dev_priv, false);
1484
1485         fw_csr = !IS_GEN9_LP(dev_priv) &&
1486                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1487         /*
1488          * In case of firmware assisted context save/restore don't manually
1489          * deinit the power domains. This also means the CSR/DMC firmware will
1490          * stay active, it will power down any HW resources as required and
1491          * also enable deeper system power states that would be blocked if the
1492          * firmware was inactive.
1493          */
1494         if (!fw_csr)
1495                 intel_power_domains_suspend(dev_priv);
1496
1497         ret = 0;
1498         if (IS_GEN9_LP(dev_priv))
1499                 bxt_enable_dc9(dev_priv);
1500         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1501                 hsw_enable_pc8(dev_priv);
1502         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1503                 ret = vlv_suspend_complete(dev_priv);
1504
1505         if (ret) {
1506                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1507                 if (!fw_csr)
1508                         intel_power_domains_init_hw(dev_priv, true);
1509
1510                 goto out;
1511         }
1512
1513         pci_disable_device(pdev);
1514         /*
1515          * During hibernation on some platforms the BIOS may try to access
1516          * the device even though it's already in D3 and hang the machine. So
1517          * leave the device in D0 on those platforms and hope the BIOS will
1518          * power down the device properly. The issue was seen on multiple old
1519          * GENs with different BIOS vendors, so having an explicit blacklist
1520          * is inpractical; apply the workaround on everything pre GEN6. The
1521          * platforms where the issue was seen:
1522          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1523          * Fujitsu FSC S7110
1524          * Acer Aspire 1830T
1525          */
1526         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1527                 pci_set_power_state(pdev, PCI_D3hot);
1528
1529         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1530
1531 out:
1532         enable_rpm_wakeref_asserts(dev_priv);
1533
1534         return ret;
1535 }
1536
1537 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1538 {
1539         int error;
1540
1541         if (!dev) {
1542                 DRM_ERROR("dev: %p\n", dev);
1543                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1544                 return -ENODEV;
1545         }
1546
1547         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1548                          state.event != PM_EVENT_FREEZE))
1549                 return -EINVAL;
1550
1551         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1552                 return 0;
1553
1554         error = i915_drm_suspend(dev);
1555         if (error)
1556                 return error;
1557
1558         return i915_drm_suspend_late(dev, false);
1559 }
1560
1561 static int i915_drm_resume(struct drm_device *dev)
1562 {
1563         struct drm_i915_private *dev_priv = to_i915(dev);
1564         int ret;
1565
1566         disable_rpm_wakeref_asserts(dev_priv);
1567         intel_sanitize_gt_powersave(dev_priv);
1568
1569         ret = i915_ggtt_enable_hw(dev_priv);
1570         if (ret)
1571                 DRM_ERROR("failed to re-enable GGTT\n");
1572
1573         intel_csr_ucode_resume(dev_priv);
1574
1575         i915_gem_resume(dev_priv);
1576
1577         i915_restore_state(dev_priv);
1578         intel_pps_unlock_regs_wa(dev_priv);
1579         intel_opregion_setup(dev_priv);
1580
1581         intel_init_pch_refclk(dev_priv);
1582
1583         /*
1584          * Interrupts have to be enabled before any batches are run. If not the
1585          * GPU will hang. i915_gem_init_hw() will initiate batches to
1586          * update/restore the context.
1587          *
1588          * drm_mode_config_reset() needs AUX interrupts.
1589          *
1590          * Modeset enabling in intel_modeset_init_hw() also needs working
1591          * interrupts.
1592          */
1593         intel_runtime_pm_enable_interrupts(dev_priv);
1594
1595         drm_mode_config_reset(dev);
1596
1597         mutex_lock(&dev->struct_mutex);
1598         if (i915_gem_init_hw(dev_priv)) {
1599                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1600                 i915_gem_set_wedged(dev_priv);
1601         }
1602         mutex_unlock(&dev->struct_mutex);
1603
1604         intel_guc_resume(dev_priv);
1605
1606         intel_modeset_init_hw(dev);
1607
1608         spin_lock_irq(&dev_priv->irq_lock);
1609         if (dev_priv->display.hpd_irq_setup)
1610                 dev_priv->display.hpd_irq_setup(dev_priv);
1611         spin_unlock_irq(&dev_priv->irq_lock);
1612
1613         intel_dp_mst_resume(dev);
1614
1615         intel_display_resume(dev);
1616
1617         drm_kms_helper_poll_enable(dev);
1618
1619         /*
1620          * ... but also need to make sure that hotplug processing
1621          * doesn't cause havoc. Like in the driver load code we don't
1622          * bother with the tiny race here where we might loose hotplug
1623          * notifications.
1624          * */
1625         intel_hpd_init(dev_priv);
1626
1627         intel_opregion_register(dev_priv);
1628
1629         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1630
1631         mutex_lock(&dev_priv->modeset_restore_lock);
1632         dev_priv->modeset_restore = MODESET_DONE;
1633         mutex_unlock(&dev_priv->modeset_restore_lock);
1634
1635         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1636
1637         intel_autoenable_gt_powersave(dev_priv);
1638
1639         enable_rpm_wakeref_asserts(dev_priv);
1640
1641         return 0;
1642 }
1643
1644 static int i915_drm_resume_early(struct drm_device *dev)
1645 {
1646         struct drm_i915_private *dev_priv = to_i915(dev);
1647         struct pci_dev *pdev = dev_priv->drm.pdev;
1648         int ret;
1649
1650         /*
1651          * We have a resume ordering issue with the snd-hda driver also
1652          * requiring our device to be power up. Due to the lack of a
1653          * parent/child relationship we currently solve this with an early
1654          * resume hook.
1655          *
1656          * FIXME: This should be solved with a special hdmi sink device or
1657          * similar so that power domains can be employed.
1658          */
1659
1660         /*
1661          * Note that we need to set the power state explicitly, since we
1662          * powered off the device during freeze and the PCI core won't power
1663          * it back up for us during thaw. Powering off the device during
1664          * freeze is not a hard requirement though, and during the
1665          * suspend/resume phases the PCI core makes sure we get here with the
1666          * device powered on. So in case we change our freeze logic and keep
1667          * the device powered we can also remove the following set power state
1668          * call.
1669          */
1670         ret = pci_set_power_state(pdev, PCI_D0);
1671         if (ret) {
1672                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1673                 goto out;
1674         }
1675
1676         /*
1677          * Note that pci_enable_device() first enables any parent bridge
1678          * device and only then sets the power state for this device. The
1679          * bridge enabling is a nop though, since bridge devices are resumed
1680          * first. The order of enabling power and enabling the device is
1681          * imposed by the PCI core as described above, so here we preserve the
1682          * same order for the freeze/thaw phases.
1683          *
1684          * TODO: eventually we should remove pci_disable_device() /
1685          * pci_enable_enable_device() from suspend/resume. Due to how they
1686          * depend on the device enable refcount we can't anyway depend on them
1687          * disabling/enabling the device.
1688          */
1689         if (pci_enable_device(pdev)) {
1690                 ret = -EIO;
1691                 goto out;
1692         }
1693
1694         pci_set_master(pdev);
1695
1696         disable_rpm_wakeref_asserts(dev_priv);
1697
1698         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1699                 ret = vlv_resume_prepare(dev_priv, false);
1700         if (ret)
1701                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1702                           ret);
1703
1704         intel_uncore_resume_early(dev_priv);
1705
1706         if (IS_GEN9_LP(dev_priv)) {
1707                 if (!dev_priv->suspended_to_idle)
1708                         gen9_sanitize_dc_state(dev_priv);
1709                 bxt_disable_dc9(dev_priv);
1710         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1711                 hsw_disable_pc8(dev_priv);
1712         }
1713
1714         intel_uncore_sanitize(dev_priv);
1715
1716         if (IS_GEN9_LP(dev_priv) ||
1717             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1718                 intel_power_domains_init_hw(dev_priv, true);
1719
1720         enable_rpm_wakeref_asserts(dev_priv);
1721
1722 out:
1723         dev_priv->suspended_to_idle = false;
1724
1725         return ret;
1726 }
1727
1728 static int i915_resume_switcheroo(struct drm_device *dev)
1729 {
1730         int ret;
1731
1732         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1733                 return 0;
1734
1735         ret = i915_drm_resume_early(dev);
1736         if (ret)
1737                 return ret;
1738
1739         return i915_drm_resume(dev);
1740 }
1741
1742 /**
1743  * i915_reset - reset chip after a hang
1744  * @dev_priv: device private to reset
1745  *
1746  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1747  * on failure.
1748  *
1749  * Caller must hold the struct_mutex.
1750  *
1751  * Procedure is fairly simple:
1752  *   - reset the chip using the reset reg
1753  *   - re-init context state
1754  *   - re-init hardware status page
1755  *   - re-init ring buffer
1756  *   - re-init interrupt state
1757  *   - re-init display
1758  */
1759 void i915_reset(struct drm_i915_private *dev_priv)
1760 {
1761         struct i915_gpu_error *error = &dev_priv->gpu_error;
1762         int ret;
1763
1764         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1765
1766         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1767                 return;
1768
1769         /* Clear any previous failed attempts at recovery. Time to try again. */
1770         __clear_bit(I915_WEDGED, &error->flags);
1771         error->reset_count++;
1772
1773         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1774         disable_irq(dev_priv->drm.irq);
1775         ret = i915_gem_reset_prepare(dev_priv);
1776         if (ret) {
1777                 DRM_ERROR("GPU recovery failed\n");
1778                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1779                 goto error;
1780         }
1781
1782         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1783         if (ret) {
1784                 if (ret != -ENODEV)
1785                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1786                 else
1787                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1788                 goto error;
1789         }
1790
1791         i915_gem_reset_finish(dev_priv);
1792         intel_overlay_reset(dev_priv);
1793
1794         /* Ok, now get things going again... */
1795
1796         /*
1797          * Everything depends on having the GTT running, so we need to start
1798          * there.  Fortunately we don't need to do this unless we reset the
1799          * chip at a PCI level.
1800          *
1801          * Next we need to restore the context, but we don't use those
1802          * yet either...
1803          *
1804          * Ring buffer needs to be re-initialized in the KMS case, or if X
1805          * was running at the time of the reset (i.e. we weren't VT
1806          * switched away).
1807          */
1808         ret = i915_gem_init_hw(dev_priv);
1809         if (ret) {
1810                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1811                 goto error;
1812         }
1813
1814         i915_queue_hangcheck(dev_priv);
1815
1816 wakeup:
1817         enable_irq(dev_priv->drm.irq);
1818         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1819         return;
1820
1821 error:
1822         i915_gem_set_wedged(dev_priv);
1823         goto wakeup;
1824 }
1825
1826 static int i915_pm_suspend(struct device *kdev)
1827 {
1828         struct pci_dev *pdev = to_pci_dev(kdev);
1829         struct drm_device *dev = pci_get_drvdata(pdev);
1830
1831         if (!dev) {
1832                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1833                 return -ENODEV;
1834         }
1835
1836         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1837                 return 0;
1838
1839         return i915_drm_suspend(dev);
1840 }
1841
1842 static int i915_pm_suspend_late(struct device *kdev)
1843 {
1844         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1845
1846         /*
1847          * We have a suspend ordering issue with the snd-hda driver also
1848          * requiring our device to be power up. Due to the lack of a
1849          * parent/child relationship we currently solve this with an late
1850          * suspend hook.
1851          *
1852          * FIXME: This should be solved with a special hdmi sink device or
1853          * similar so that power domains can be employed.
1854          */
1855         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1856                 return 0;
1857
1858         return i915_drm_suspend_late(dev, false);
1859 }
1860
1861 static int i915_pm_poweroff_late(struct device *kdev)
1862 {
1863         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1864
1865         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1866                 return 0;
1867
1868         return i915_drm_suspend_late(dev, true);
1869 }
1870
1871 static int i915_pm_resume_early(struct device *kdev)
1872 {
1873         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1874
1875         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1876                 return 0;
1877
1878         return i915_drm_resume_early(dev);
1879 }
1880
1881 static int i915_pm_resume(struct device *kdev)
1882 {
1883         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1884
1885         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1886                 return 0;
1887
1888         return i915_drm_resume(dev);
1889 }
1890
1891 /* freeze: before creating the hibernation_image */
1892 static int i915_pm_freeze(struct device *kdev)
1893 {
1894         int ret;
1895
1896         ret = i915_pm_suspend(kdev);
1897         if (ret)
1898                 return ret;
1899
1900         ret = i915_gem_freeze(kdev_to_i915(kdev));
1901         if (ret)
1902                 return ret;
1903
1904         return 0;
1905 }
1906
1907 static int i915_pm_freeze_late(struct device *kdev)
1908 {
1909         int ret;
1910
1911         ret = i915_pm_suspend_late(kdev);
1912         if (ret)
1913                 return ret;
1914
1915         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1916         if (ret)
1917                 return ret;
1918
1919         return 0;
1920 }
1921
1922 /* thaw: called after creating the hibernation image, but before turning off. */
1923 static int i915_pm_thaw_early(struct device *kdev)
1924 {
1925         return i915_pm_resume_early(kdev);
1926 }
1927
1928 static int i915_pm_thaw(struct device *kdev)
1929 {
1930         return i915_pm_resume(kdev);
1931 }
1932
1933 /* restore: called after loading the hibernation image. */
1934 static int i915_pm_restore_early(struct device *kdev)
1935 {
1936         return i915_pm_resume_early(kdev);
1937 }
1938
1939 static int i915_pm_restore(struct device *kdev)
1940 {
1941         return i915_pm_resume(kdev);
1942 }
1943
1944 /*
1945  * Save all Gunit registers that may be lost after a D3 and a subsequent
1946  * S0i[R123] transition. The list of registers needing a save/restore is
1947  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1948  * registers in the following way:
1949  * - Driver: saved/restored by the driver
1950  * - Punit : saved/restored by the Punit firmware
1951  * - No, w/o marking: no need to save/restore, since the register is R/O or
1952  *                    used internally by the HW in a way that doesn't depend
1953  *                    keeping the content across a suspend/resume.
1954  * - Debug : used for debugging
1955  *
1956  * We save/restore all registers marked with 'Driver', with the following
1957  * exceptions:
1958  * - Registers out of use, including also registers marked with 'Debug'.
1959  *   These have no effect on the driver's operation, so we don't save/restore
1960  *   them to reduce the overhead.
1961  * - Registers that are fully setup by an initialization function called from
1962  *   the resume path. For example many clock gating and RPS/RC6 registers.
1963  * - Registers that provide the right functionality with their reset defaults.
1964  *
1965  * TODO: Except for registers that based on the above 3 criteria can be safely
1966  * ignored, we save/restore all others, practically treating the HW context as
1967  * a black-box for the driver. Further investigation is needed to reduce the
1968  * saved/restored registers even further, by following the same 3 criteria.
1969  */
1970 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1971 {
1972         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1973         int i;
1974
1975         /* GAM 0x4000-0x4770 */
1976         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1977         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1978         s->arb_mode             = I915_READ(ARB_MODE);
1979         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1980         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1981
1982         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1983                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1984
1985         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1986         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1987
1988         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1989         s->ecochk               = I915_READ(GAM_ECOCHK);
1990         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1991         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1992
1993         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1994
1995         /* MBC 0x9024-0x91D0, 0x8500 */
1996         s->g3dctl               = I915_READ(VLV_G3DCTL);
1997         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1998         s->mbctl                = I915_READ(GEN6_MBCTL);
1999
2000         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2001         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2002         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2003         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2004         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2005         s->rstctl               = I915_READ(GEN6_RSTCTL);
2006         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2007
2008         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2009         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2010         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2011         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2012         s->ecobus               = I915_READ(ECOBUS);
2013         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2014         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2015         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2016         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2017         s->rcedata              = I915_READ(VLV_RCEDATA);
2018         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2019
2020         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2021         s->gt_imr               = I915_READ(GTIMR);
2022         s->gt_ier               = I915_READ(GTIER);
2023         s->pm_imr               = I915_READ(GEN6_PMIMR);
2024         s->pm_ier               = I915_READ(GEN6_PMIER);
2025
2026         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2027                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2028
2029         /* GT SA CZ domain, 0x100000-0x138124 */
2030         s->tilectl              = I915_READ(TILECTL);
2031         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2032         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2033         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2034         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2035
2036         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2037         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2038         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2039         s->pcbr                 = I915_READ(VLV_PCBR);
2040         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2041
2042         /*
2043          * Not saving any of:
2044          * DFT,         0x9800-0x9EC0
2045          * SARB,        0xB000-0xB1FC
2046          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2047          * PCI CFG
2048          */
2049 }
2050
2051 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2052 {
2053         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2054         u32 val;
2055         int i;
2056
2057         /* GAM 0x4000-0x4770 */
2058         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2059         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2060         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2061         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2062         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2063
2064         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2065                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2066
2067         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2068         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2069
2070         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2071         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2072         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2073         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2074
2075         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2076
2077         /* MBC 0x9024-0x91D0, 0x8500 */
2078         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2079         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2080         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2081
2082         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2083         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2084         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2085         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2086         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2087         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2088         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2089
2090         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2091         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2092         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2093         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2094         I915_WRITE(ECOBUS,              s->ecobus);
2095         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2096         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2097         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2098         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2099         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2100         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2101
2102         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2103         I915_WRITE(GTIMR,               s->gt_imr);
2104         I915_WRITE(GTIER,               s->gt_ier);
2105         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2106         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2107
2108         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2109                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2110
2111         /* GT SA CZ domain, 0x100000-0x138124 */
2112         I915_WRITE(TILECTL,                     s->tilectl);
2113         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2114         /*
2115          * Preserve the GT allow wake and GFX force clock bit, they are not
2116          * be restored, as they are used to control the s0ix suspend/resume
2117          * sequence by the caller.
2118          */
2119         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2120         val &= VLV_GTLC_ALLOWWAKEREQ;
2121         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2122         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2123
2124         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2125         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2126         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2127         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2128
2129         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2130
2131         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2132         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2133         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2134         I915_WRITE(VLV_PCBR,                    s->pcbr);
2135         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2136 }
2137
2138 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2139 {
2140         u32 val;
2141         int err;
2142
2143         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2144         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2145         if (force_on)
2146                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2147         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2148
2149         if (!force_on)
2150                 return 0;
2151
2152         err = intel_wait_for_register(dev_priv,
2153                                       VLV_GTLC_SURVIVABILITY_REG,
2154                                       VLV_GFX_CLK_STATUS_BIT,
2155                                       VLV_GFX_CLK_STATUS_BIT,
2156                                       20);
2157         if (err)
2158                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2159                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2160
2161         return err;
2162 }
2163
2164 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2165 {
2166         u32 val;
2167         int err = 0;
2168
2169         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2170         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2171         if (allow)
2172                 val |= VLV_GTLC_ALLOWWAKEREQ;
2173         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2174         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2175
2176         err = intel_wait_for_register(dev_priv,
2177                                       VLV_GTLC_PW_STATUS,
2178                                       VLV_GTLC_ALLOWWAKEACK,
2179                                       allow,
2180                                       1);
2181         if (err)
2182                 DRM_ERROR("timeout disabling GT waking\n");
2183
2184         return err;
2185 }
2186
2187 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2188                                  bool wait_for_on)
2189 {
2190         u32 mask;
2191         u32 val;
2192         int err;
2193
2194         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2195         val = wait_for_on ? mask : 0;
2196         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2197                 return 0;
2198
2199         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2200                       onoff(wait_for_on),
2201                       I915_READ(VLV_GTLC_PW_STATUS));
2202
2203         /*
2204          * RC6 transitioning can be delayed up to 2 msec (see
2205          * valleyview_enable_rps), use 3 msec for safety.
2206          */
2207         err = intel_wait_for_register(dev_priv,
2208                                       VLV_GTLC_PW_STATUS, mask, val,
2209                                       3);
2210         if (err)
2211                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2212                           onoff(wait_for_on));
2213
2214         return err;
2215 }
2216
2217 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2218 {
2219         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2220                 return;
2221
2222         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2223         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2224 }
2225
2226 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2227 {
2228         u32 mask;
2229         int err;
2230
2231         /*
2232          * Bspec defines the following GT well on flags as debug only, so
2233          * don't treat them as hard failures.
2234          */
2235         (void)vlv_wait_for_gt_wells(dev_priv, false);
2236
2237         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2238         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2239
2240         vlv_check_no_gt_access(dev_priv);
2241
2242         err = vlv_force_gfx_clock(dev_priv, true);
2243         if (err)
2244                 goto err1;
2245
2246         err = vlv_allow_gt_wake(dev_priv, false);
2247         if (err)
2248                 goto err2;
2249
2250         if (!IS_CHERRYVIEW(dev_priv))
2251                 vlv_save_gunit_s0ix_state(dev_priv);
2252
2253         err = vlv_force_gfx_clock(dev_priv, false);
2254         if (err)
2255                 goto err2;
2256
2257         return 0;
2258
2259 err2:
2260         /* For safety always re-enable waking and disable gfx clock forcing */
2261         vlv_allow_gt_wake(dev_priv, true);
2262 err1:
2263         vlv_force_gfx_clock(dev_priv, false);
2264
2265         return err;
2266 }
2267
2268 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2269                                 bool rpm_resume)
2270 {
2271         int err;
2272         int ret;
2273
2274         /*
2275          * If any of the steps fail just try to continue, that's the best we
2276          * can do at this point. Return the first error code (which will also
2277          * leave RPM permanently disabled).
2278          */
2279         ret = vlv_force_gfx_clock(dev_priv, true);
2280
2281         if (!IS_CHERRYVIEW(dev_priv))
2282                 vlv_restore_gunit_s0ix_state(dev_priv);
2283
2284         err = vlv_allow_gt_wake(dev_priv, true);
2285         if (!ret)
2286                 ret = err;
2287
2288         err = vlv_force_gfx_clock(dev_priv, false);
2289         if (!ret)
2290                 ret = err;
2291
2292         vlv_check_no_gt_access(dev_priv);
2293
2294         if (rpm_resume)
2295                 intel_init_clock_gating(dev_priv);
2296
2297         return ret;
2298 }
2299
2300 static int intel_runtime_suspend(struct device *kdev)
2301 {
2302         struct pci_dev *pdev = to_pci_dev(kdev);
2303         struct drm_device *dev = pci_get_drvdata(pdev);
2304         struct drm_i915_private *dev_priv = to_i915(dev);
2305         int ret;
2306
2307         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2308                 return -ENODEV;
2309
2310         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2311                 return -ENODEV;
2312
2313         DRM_DEBUG_KMS("Suspending device\n");
2314
2315         disable_rpm_wakeref_asserts(dev_priv);
2316
2317         /*
2318          * We are safe here against re-faults, since the fault handler takes
2319          * an RPM reference.
2320          */
2321         i915_gem_runtime_suspend(dev_priv);
2322
2323         intel_guc_suspend(dev_priv);
2324
2325         intel_runtime_pm_disable_interrupts(dev_priv);
2326
2327         ret = 0;
2328         if (IS_GEN9_LP(dev_priv)) {
2329                 bxt_display_core_uninit(dev_priv);
2330                 bxt_enable_dc9(dev_priv);
2331         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2332                 hsw_enable_pc8(dev_priv);
2333         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2334                 ret = vlv_suspend_complete(dev_priv);
2335         }
2336
2337         if (ret) {
2338                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2339                 intel_runtime_pm_enable_interrupts(dev_priv);
2340
2341                 enable_rpm_wakeref_asserts(dev_priv);
2342
2343                 return ret;
2344         }
2345
2346         intel_uncore_suspend(dev_priv);
2347
2348         enable_rpm_wakeref_asserts(dev_priv);
2349         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2350
2351         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2352                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2353
2354         dev_priv->pm.suspended = true;
2355
2356         /*
2357          * FIXME: We really should find a document that references the arguments
2358          * used below!
2359          */
2360         if (IS_BROADWELL(dev_priv)) {
2361                 /*
2362                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2363                  * being detected, and the call we do at intel_runtime_resume()
2364                  * won't be able to restore them. Since PCI_D3hot matches the
2365                  * actual specification and appears to be working, use it.
2366                  */
2367                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2368         } else {
2369                 /*
2370                  * current versions of firmware which depend on this opregion
2371                  * notification have repurposed the D1 definition to mean
2372                  * "runtime suspended" vs. what you would normally expect (D3)
2373                  * to distinguish it from notifications that might be sent via
2374                  * the suspend path.
2375                  */
2376                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2377         }
2378
2379         assert_forcewakes_inactive(dev_priv);
2380
2381         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2382                 intel_hpd_poll_init(dev_priv);
2383
2384         DRM_DEBUG_KMS("Device suspended\n");
2385         return 0;
2386 }
2387
2388 static int intel_runtime_resume(struct device *kdev)
2389 {
2390         struct pci_dev *pdev = to_pci_dev(kdev);
2391         struct drm_device *dev = pci_get_drvdata(pdev);
2392         struct drm_i915_private *dev_priv = to_i915(dev);
2393         int ret = 0;
2394
2395         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2396                 return -ENODEV;
2397
2398         DRM_DEBUG_KMS("Resuming device\n");
2399
2400         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2401         disable_rpm_wakeref_asserts(dev_priv);
2402
2403         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2404         dev_priv->pm.suspended = false;
2405         if (intel_uncore_unclaimed_mmio(dev_priv))
2406                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2407
2408         intel_guc_resume(dev_priv);
2409
2410         if (IS_GEN6(dev_priv))
2411                 intel_init_pch_refclk(dev_priv);
2412
2413         if (IS_GEN9_LP(dev_priv)) {
2414                 bxt_disable_dc9(dev_priv);
2415                 bxt_display_core_init(dev_priv, true);
2416                 if (dev_priv->csr.dmc_payload &&
2417                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2418                         gen9_enable_dc5(dev_priv);
2419         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2420                 hsw_disable_pc8(dev_priv);
2421         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2422                 ret = vlv_resume_prepare(dev_priv, true);
2423         }
2424
2425         /*
2426          * No point of rolling back things in case of an error, as the best
2427          * we can do is to hope that things will still work (and disable RPM).
2428          */
2429         i915_gem_init_swizzling(dev_priv);
2430         i915_gem_restore_fences(dev_priv);
2431
2432         intel_runtime_pm_enable_interrupts(dev_priv);
2433
2434         /*
2435          * On VLV/CHV display interrupts are part of the display
2436          * power well, so hpd is reinitialized from there. For
2437          * everyone else do it here.
2438          */
2439         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2440                 intel_hpd_init(dev_priv);
2441
2442         enable_rpm_wakeref_asserts(dev_priv);
2443
2444         if (ret)
2445                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2446         else
2447                 DRM_DEBUG_KMS("Device resumed\n");
2448
2449         return ret;
2450 }
2451
2452 const struct dev_pm_ops i915_pm_ops = {
2453         /*
2454          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2455          * PMSG_RESUME]
2456          */
2457         .suspend = i915_pm_suspend,
2458         .suspend_late = i915_pm_suspend_late,
2459         .resume_early = i915_pm_resume_early,
2460         .resume = i915_pm_resume,
2461
2462         /*
2463          * S4 event handlers
2464          * @freeze, @freeze_late    : called (1) before creating the
2465          *                            hibernation image [PMSG_FREEZE] and
2466          *                            (2) after rebooting, before restoring
2467          *                            the image [PMSG_QUIESCE]
2468          * @thaw, @thaw_early       : called (1) after creating the hibernation
2469          *                            image, before writing it [PMSG_THAW]
2470          *                            and (2) after failing to create or
2471          *                            restore the image [PMSG_RECOVER]
2472          * @poweroff, @poweroff_late: called after writing the hibernation
2473          *                            image, before rebooting [PMSG_HIBERNATE]
2474          * @restore, @restore_early : called after rebooting and restoring the
2475          *                            hibernation image [PMSG_RESTORE]
2476          */
2477         .freeze = i915_pm_freeze,
2478         .freeze_late = i915_pm_freeze_late,
2479         .thaw_early = i915_pm_thaw_early,
2480         .thaw = i915_pm_thaw,
2481         .poweroff = i915_pm_suspend,
2482         .poweroff_late = i915_pm_poweroff_late,
2483         .restore_early = i915_pm_restore_early,
2484         .restore = i915_pm_restore,
2485
2486         /* S0ix (via runtime suspend) event handlers */
2487         .runtime_suspend = intel_runtime_suspend,
2488         .runtime_resume = intel_runtime_resume,
2489 };
2490
2491 static const struct vm_operations_struct i915_gem_vm_ops = {
2492         .fault = i915_gem_fault,
2493         .open = drm_gem_vm_open,
2494         .close = drm_gem_vm_close,
2495 };
2496
2497 static const struct file_operations i915_driver_fops = {
2498         .owner = THIS_MODULE,
2499         .open = drm_open,
2500         .release = drm_release,
2501         .unlocked_ioctl = drm_ioctl,
2502         .mmap = drm_gem_mmap,
2503         .poll = drm_poll,
2504         .read = drm_read,
2505         .compat_ioctl = i915_compat_ioctl,
2506         .llseek = noop_llseek,
2507 };
2508
2509 static int
2510 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2511                           struct drm_file *file)
2512 {
2513         return -ENODEV;
2514 }
2515
2516 static const struct drm_ioctl_desc i915_ioctls[] = {
2517         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2518         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2519         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2520         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2521         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2522         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2524         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2526         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2527         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2528         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2529         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2530         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2532         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2534         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2536         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2537         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2556         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2567         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2569         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2570 };
2571
2572 static struct drm_driver driver = {
2573         /* Don't use MTRRs here; the Xserver or userspace app should
2574          * deal with them for Intel hardware.
2575          */
2576         .driver_features =
2577             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2578             DRIVER_RENDER | DRIVER_MODESET,
2579         .open = i915_driver_open,
2580         .lastclose = i915_driver_lastclose,
2581         .preclose = i915_driver_preclose,
2582         .postclose = i915_driver_postclose,
2583         .set_busid = drm_pci_set_busid,
2584
2585         .gem_close_object = i915_gem_close_object,
2586         .gem_free_object_unlocked = i915_gem_free_object,
2587         .gem_vm_ops = &i915_gem_vm_ops,
2588
2589         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2590         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2591         .gem_prime_export = i915_gem_prime_export,
2592         .gem_prime_import = i915_gem_prime_import,
2593
2594         .dumb_create = i915_gem_dumb_create,
2595         .dumb_map_offset = i915_gem_mmap_gtt,
2596         .dumb_destroy = drm_gem_dumb_destroy,
2597         .ioctls = i915_ioctls,
2598         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2599         .fops = &i915_driver_fops,
2600         .name = DRIVER_NAME,
2601         .desc = DRIVER_DESC,
2602         .date = DRIVER_DATE,
2603         .major = DRIVER_MAJOR,
2604         .minor = DRIVER_MINOR,
2605         .patchlevel = DRIVER_PATCHLEVEL,
2606 };