drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include "drm_crtc_helper.h"
  41
  42 static int i915_modeset __read_mostly = -1;
  43 module_param_named(modeset, i915_modeset, int, 0400);
  44 MODULE_PARM_DESC(modeset,
  45                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  46                 "1=on, -1=force vga console preference [default])");
  47
  48 unsigned int i915_fbpercrtc __always_unused = 0;
  49 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  50
  51 int i915_panel_ignore_lid __read_mostly = 0;
  52 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  53 MODULE_PARM_DESC(panel_ignore_lid,
  54                 "Override lid status (0=autodetect [default], 1=lid open, "
  55                 "-1=lid closed)");
  56
  57 unsigned int i915_powersave __read_mostly = 1;
  58 module_param_named(powersave, i915_powersave, int, 0600);
  59 MODULE_PARM_DESC(powersave,
  60                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  61
  62 int i915_semaphores __read_mostly = -1;
  63 module_param_named(semaphores, i915_semaphores, int, 0600);
  64 MODULE_PARM_DESC(semaphores,
  65                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  66
  67 int i915_enable_rc6 __read_mostly = -1;
  68 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  69 MODULE_PARM_DESC(i915_enable_rc6,
  70                 "Enable power-saving render C-state 6. "
  71                 "Different stages can be selected via bitmask values "
  72                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  73                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  74                 "default: -1 (use per-chip default)");
  75
  76 int i915_enable_fbc __read_mostly = -1;
  77 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  78 MODULE_PARM_DESC(i915_enable_fbc,
  79                 "Enable frame buffer compression for power savings "
  80                 "(default: -1 (use per-chip default))");
  81
  82 unsigned int i915_lvds_downclock __read_mostly = 0;
  83 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  84 MODULE_PARM_DESC(lvds_downclock,
  85                 "Use panel (LVDS/eDP) downclocking for power savings "
  86                 "(default: false)");
  87
  88 int i915_lvds_channel_mode __read_mostly;
  89 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  90 MODULE_PARM_DESC(lvds_channel_mode,
  91                  "Specify LVDS channel mode "
  92                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  93
  94 int i915_panel_use_ssc __read_mostly = -1;
  95 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  96 MODULE_PARM_DESC(lvds_use_ssc,
  97                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  98                 "(default: auto from VBT)");
  99
 100 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 101 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 102 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 103                 "Override/Ignore selection of SDVO panel mode in the VBT "
 104                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 105
 106 static bool i915_try_reset __read_mostly = true;
 107 module_param_named(reset, i915_try_reset, bool, 0600);
 108 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 109
 110 bool i915_enable_hangcheck __read_mostly = true;
 111 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 112 MODULE_PARM_DESC(enable_hangcheck,
 113                 "Periodically check GPU activity for detecting hangs. "
 114                 "WARNING: Disabling this can cause system wide hangs. "
 115                 "(default: true)");
 116
 117 int i915_enable_ppgtt __read_mostly = -1;
 118 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 119 MODULE_PARM_DESC(i915_enable_ppgtt,
 120                 "Enable PPGTT (default: true)");
 121
 122 static struct drm_driver driver;
 123 extern int intel_agp_enabled;
 124
 125 #define INTEL_VGA_DEVICE(id, info) {            \
 126         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 127         .class_mask = 0xff0000,                 \
 128         .vendor = 0x8086,                       \
 129         .device = id,                           \
 130         .subvendor = PCI_ANY_ID,                \
 131         .subdevice = PCI_ANY_ID,                \
 132         .driver_data = (unsigned long) info }
 133
 134 static const struct intel_device_info intel_i830_info = {
 135         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_845g_info = {
 140         .gen = 2,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143
 144 static const struct intel_device_info intel_i85x_info = {
 145         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 146         .cursor_needs_physical = 1,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i865g_info = {
 151         .gen = 2,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153 };
 154
 155 static const struct intel_device_info intel_i915g_info = {
 156         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 157         .has_overlay = 1, .overlay_needs_physical = 1,
 158 };
 159 static const struct intel_device_info intel_i915gm_info = {
 160         .gen = 3, .is_mobile = 1,
 161         .cursor_needs_physical = 1,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163         .supports_tv = 1,
 164 };
 165 static const struct intel_device_info intel_i945g_info = {
 166         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168 };
 169 static const struct intel_device_info intel_i945gm_info = {
 170         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 171         .has_hotplug = 1, .cursor_needs_physical = 1,
 172         .has_overlay = 1, .overlay_needs_physical = 1,
 173         .supports_tv = 1,
 174 };
 175
 176 static const struct intel_device_info intel_i965g_info = {
 177         .gen = 4, .is_broadwater = 1,
 178         .has_hotplug = 1,
 179         .has_overlay = 1,
 180 };
 181
 182 static const struct intel_device_info intel_i965gm_info = {
 183         .gen = 4, .is_crestline = 1,
 184         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 185         .has_overlay = 1,
 186         .supports_tv = 1,
 187 };
 188
 189 static const struct intel_device_info intel_g33_info = {
 190         .gen = 3, .is_g33 = 1,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .has_overlay = 1,
 193 };
 194
 195 static const struct intel_device_info intel_g45_info = {
 196         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 197         .has_pipe_cxsr = 1, .has_hotplug = 1,
 198         .has_bsd_ring = 1,
 199 };
 200
 201 static const struct intel_device_info intel_gm45_info = {
 202         .gen = 4, .is_g4x = 1,
 203         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 204         .has_pipe_cxsr = 1, .has_hotplug = 1,
 205         .supports_tv = 1,
 206         .has_bsd_ring = 1,
 207 };
 208
 209 static const struct intel_device_info intel_pineview_info = {
 210         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 211         .need_gfx_hws = 1, .has_hotplug = 1,
 212         .has_overlay = 1,
 213 };
 214
 215 static const struct intel_device_info intel_ironlake_d_info = {
 216         .gen = 5,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_bsd_ring = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_m_info = {
 222         .gen = 5, .is_mobile = 1,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .has_bsd_ring = 1,
 226 };
 227
 228 static const struct intel_device_info intel_sandybridge_d_info = {
 229         .gen = 6,
 230         .need_gfx_hws = 1, .has_hotplug = 1,
 231         .has_bsd_ring = 1,
 232         .has_blt_ring = 1,
 233         .has_llc = 1,
 234         .has_force_wake = 1,
 235 };
 236
 237 static const struct intel_device_info intel_sandybridge_m_info = {
 238         .gen = 6, .is_mobile = 1,
 239         .need_gfx_hws = 1, .has_hotplug = 1,
 240         .has_fbc = 1,
 241         .has_bsd_ring = 1,
 242         .has_blt_ring = 1,
 243         .has_llc = 1,
 244         .has_force_wake = 1,
 245 };
 246
 247 static const struct intel_device_info intel_ivybridge_d_info = {
 248         .is_ivybridge = 1, .gen = 7,
 249         .need_gfx_hws = 1, .has_hotplug = 1,
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253         .has_force_wake = 1,
 254 };
 255
 256 static const struct intel_device_info intel_ivybridge_m_info = {
 257         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 258         .need_gfx_hws = 1, .has_hotplug = 1,
 259         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 260         .has_bsd_ring = 1,
 261         .has_blt_ring = 1,
 262         .has_llc = 1,
 263         .has_force_wake = 1,
 264 };
 265
 266 static const struct intel_device_info intel_valleyview_m_info = {
 267         .gen = 7, .is_mobile = 1,
 268         .need_gfx_hws = 1, .has_hotplug = 1,
 269         .has_fbc = 0,
 270         .has_bsd_ring = 1,
 271         .has_blt_ring = 1,
 272         .is_valleyview = 1,
 273 };
 274
 275 static const struct intel_device_info intel_valleyview_d_info = {
 276         .gen = 7,
 277         .need_gfx_hws = 1, .has_hotplug = 1,
 278         .has_fbc = 0,
 279         .has_bsd_ring = 1,
 280         .has_blt_ring = 1,
 281         .is_valleyview = 1,
 282 };
 283
 284 static const struct intel_device_info intel_haswell_d_info = {
 285         .is_haswell = 1, .gen = 7,
 286         .need_gfx_hws = 1, .has_hotplug = 1,
 287         .has_bsd_ring = 1,
 288         .has_blt_ring = 1,
 289         .has_llc = 1,
 290         .has_force_wake = 1,
 291 };
 292
 293 static const struct intel_device_info intel_haswell_m_info = {
 294         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 295         .need_gfx_hws = 1, .has_hotplug = 1,
 296         .has_bsd_ring = 1,
 297         .has_blt_ring = 1,
 298         .has_llc = 1,
 299         .has_force_wake = 1,
 300 };
 301
 302 static const struct pci_device_id pciidlist[] = {               /* aka */
 303         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 304         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 305         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 306         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 307         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 308         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 309         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 310         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 311         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 312         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 313         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 314         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 315         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 316         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 317         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 318         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 319         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 320         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 321         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 322         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 323         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 324         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 325         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 326         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 327         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 328         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 329         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 330         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 331         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 332         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 333         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 334         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 335         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 337         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 338         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 340         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 341         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 342         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 343         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 344         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 345         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 346         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 347         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 348         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 349         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 350         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 351         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 352         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 353         INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 354         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 355         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 356         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 357         {0, 0, 0}
 358 };
 359
 360 #if defined(CONFIG_DRM_I915_KMS)
 361 MODULE_DEVICE_TABLE(pci, pciidlist);
 362 #endif
 363
 364 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 365 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 366 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 367 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 368 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 369
 370 void intel_detect_pch(struct drm_device *dev)
 371 {
 372         struct drm_i915_private *dev_priv = dev->dev_private;
 373         struct pci_dev *pch;
 374
 375         /*
 376          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 377          * make graphics device passthrough work easy for VMM, that only
 378          * need to expose ISA bridge to let driver know the real hardware
 379          * underneath. This is a requirement from virtualization team.
 380          */
 381         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 382         if (pch) {
 383                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 384                         int id;
 385                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 386
 387                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 388                                 dev_priv->pch_type = PCH_IBX;
 389                                 dev_priv->num_pch_pll = 2;
 390                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 391                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 392                                 dev_priv->pch_type = PCH_CPT;
 393                                 dev_priv->num_pch_pll = 2;
 394                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 395                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 396                                 /* PantherPoint is CPT compatible */
 397                                 dev_priv->pch_type = PCH_CPT;
 398                                 dev_priv->num_pch_pll = 2;
 399                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 400                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 401                                 dev_priv->pch_type = PCH_LPT;
 402                                 dev_priv->num_pch_pll = 0;
 403                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 404                         }
 405                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 406                 }
 407                 pci_dev_put(pch);
 408         }
 409 }
 410
 411 bool i915_semaphore_is_enabled(struct drm_device *dev)
 412 {
 413         if (INTEL_INFO(dev)->gen < 6)
 414                 return 0;
 415
 416         if (i915_semaphores >= 0)
 417                 return i915_semaphores;
 418
 419 #ifdef CONFIG_INTEL_IOMMU
 420         /* Enable semaphores on SNB when IO remapping is off */
 421         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 422                 return false;
 423 #endif
 424
 425         return 1;
 426 }
 427
 428 static int i915_drm_freeze(struct drm_device *dev)
 429 {
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431
 432         drm_kms_helper_poll_disable(dev);
 433
 434         pci_save_state(dev->pdev);
 435
 436         /* If KMS is active, we do the leavevt stuff here */
 437         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 438                 int error = i915_gem_idle(dev);
 439                 if (error) {
 440                         dev_err(&dev->pdev->dev,
 441                                 "GEM idle failed, resume might fail\n");
 442                         return error;
 443                 }
 444                 drm_irq_uninstall(dev);
 445         }
 446
 447         i915_save_state(dev);
 448
 449         intel_opregion_fini(dev);
 450
 451         /* Modeset on resume, not lid events */
 452         dev_priv->modeset_on_lid = 0;
 453
 454         console_lock();
 455         intel_fbdev_set_suspend(dev, 1);
 456         console_unlock();
 457
 458         return 0;
 459 }
 460
 461 int i915_suspend(struct drm_device *dev, pm_message_t state)
 462 {
 463         int error;
 464
 465         if (!dev || !dev->dev_private) {
 466                 DRM_ERROR("dev: %p\n", dev);
 467                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 468                 return -ENODEV;
 469         }
 470
 471         if (state.event == PM_EVENT_PRETHAW)
 472                 return 0;
 473
 474
 475         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 476                 return 0;
 477
 478         error = i915_drm_freeze(dev);
 479         if (error)
 480                 return error;
 481
 482         if (state.event == PM_EVENT_SUSPEND) {
 483                 /* Shut down the device */
 484                 pci_disable_device(dev->pdev);
 485                 pci_set_power_state(dev->pdev, PCI_D3hot);
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int i915_drm_thaw(struct drm_device *dev)
 492 {
 493         struct drm_i915_private *dev_priv = dev->dev_private;
 494         int error = 0;
 495
 496         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 497                 mutex_lock(&dev->struct_mutex);
 498                 i915_gem_restore_gtt_mappings(dev);
 499                 mutex_unlock(&dev->struct_mutex);
 500         }
 501
 502         i915_restore_state(dev);
 503         intel_opregion_setup(dev);
 504
 505         /* KMS EnterVT equivalent */
 506         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 507                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 508                         ironlake_init_pch_refclk(dev);
 509
 510                 mutex_lock(&dev->struct_mutex);
 511                 dev_priv->mm.suspended = 0;
 512
 513                 error = i915_gem_init_hw(dev);
 514                 mutex_unlock(&dev->struct_mutex);
 515
 516                 intel_modeset_init_hw(dev);
 517                 drm_mode_config_reset(dev);
 518                 drm_irq_install(dev);
 519
 520                 /* Resume the modeset for every activated CRTC */
 521                 mutex_lock(&dev->mode_config.mutex);
 522                 drm_helper_resume_force_mode(dev);
 523                 mutex_unlock(&dev->mode_config.mutex);
 524         }
 525
 526         intel_opregion_init(dev);
 527
 528         dev_priv->modeset_on_lid = 0;
 529
 530         console_lock();
 531         intel_fbdev_set_suspend(dev, 0);
 532         console_unlock();
 533         return error;
 534 }
 535
 536 int i915_resume(struct drm_device *dev)
 537 {
 538         int ret;
 539
 540         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 541                 return 0;
 542
 543         if (pci_enable_device(dev->pdev))
 544                 return -EIO;
 545
 546         pci_set_master(dev->pdev);
 547
 548         ret = i915_drm_thaw(dev);
 549         if (ret)
 550                 return ret;
 551
 552         drm_kms_helper_poll_enable(dev);
 553         return 0;
 554 }
 555
 556 static int i8xx_do_reset(struct drm_device *dev)
 557 {
 558         struct drm_i915_private *dev_priv = dev->dev_private;
 559
 560         if (IS_I85X(dev))
 561                 return -ENODEV;
 562
 563         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 564         POSTING_READ(D_STATE);
 565
 566         if (IS_I830(dev) || IS_845G(dev)) {
 567                 I915_WRITE(DEBUG_RESET_I830,
 568                            DEBUG_RESET_DISPLAY |
 569                            DEBUG_RESET_RENDER |
 570                            DEBUG_RESET_FULL);
 571                 POSTING_READ(DEBUG_RESET_I830);
 572                 msleep(1);
 573
 574                 I915_WRITE(DEBUG_RESET_I830, 0);
 575                 POSTING_READ(DEBUG_RESET_I830);
 576         }
 577
 578         msleep(1);
 579
 580         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 581         POSTING_READ(D_STATE);
 582
 583         return 0;
 584 }
 585
 586 static int i965_reset_complete(struct drm_device *dev)
 587 {
 588         u8 gdrst;
 589         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 590         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 591 }
 592
 593 static int i965_do_reset(struct drm_device *dev)
 594 {
 595         int ret;
 596         u8 gdrst;
 597
 598         /*
 599          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 600          * well as the reset bit (GR/bit 0).  Setting the GR bit
 601          * triggers the reset; when done, the hardware will clear it.
 602          */
 603         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 604         pci_write_config_byte(dev->pdev, I965_GDRST,
 605                               gdrst | GRDOM_RENDER |
 606                               GRDOM_RESET_ENABLE);
 607         ret =  wait_for(i965_reset_complete(dev), 500);
 608         if (ret)
 609                 return ret;
 610
 611         /* We can't reset render&media without also resetting display ... */
 612         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 613         pci_write_config_byte(dev->pdev, I965_GDRST,
 614                               gdrst | GRDOM_MEDIA |
 615                               GRDOM_RESET_ENABLE);
 616
 617         return wait_for(i965_reset_complete(dev), 500);
 618 }
 619
 620 static int ironlake_do_reset(struct drm_device *dev)
 621 {
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623         u32 gdrst;
 624         int ret;
 625
 626         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 627         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 628                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 629         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 630         if (ret)
 631                 return ret;
 632
 633         /* We can't reset render&media without also resetting display ... */
 634         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 635         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 636                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 637         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 638 }
 639
 640 static int gen6_do_reset(struct drm_device *dev)
 641 {
 642         struct drm_i915_private *dev_priv = dev->dev_private;
 643         int     ret;
 644         unsigned long irqflags;
 645
 646         /* Hold gt_lock across reset to prevent any register access
 647          * with forcewake not set correctly
 648          */
 649         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 650
 651         /* Reset the chip */
 652
 653         /* GEN6_GDRST is not in the gt power well, no need to check
 654          * for fifo space for the write or forcewake the chip for
 655          * the read
 656          */
 657         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 658
 659         /* Spin waiting for the device to ack the reset request */
 660         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 661
 662         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 663         if (dev_priv->forcewake_count)
 664                 dev_priv->gt.force_wake_get(dev_priv);
 665         else
 666                 dev_priv->gt.force_wake_put(dev_priv);
 667
 668         /* Restore fifo count */
 669         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 670
 671         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 672         return ret;
 673 }
 674
 675 int intel_gpu_reset(struct drm_device *dev)
 676 {
 677         struct drm_i915_private *dev_priv = dev->dev_private;
 678         int ret = -ENODEV;
 679
 680         switch (INTEL_INFO(dev)->gen) {
 681         case 7:
 682         case 6:
 683                 ret = gen6_do_reset(dev);
 684                 break;
 685         case 5:
 686                 ret = ironlake_do_reset(dev);
 687                 break;
 688         case 4:
 689                 ret = i965_do_reset(dev);
 690                 break;
 691         case 2:
 692                 ret = i8xx_do_reset(dev);
 693                 break;
 694         }
 695
 696         /* Also reset the gpu hangman. */
 697         if (dev_priv->stop_rings) {
 698                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 699                 dev_priv->stop_rings = 0;
 700                 if (ret == -ENODEV) {
 701                         DRM_ERROR("Reset not implemented, but ignoring "
 702                                   "error for simulated gpu hangs\n");
 703                         ret = 0;
 704                 }
 705         }
 706
 707         return ret;
 708 }
 709
 710 /**
 711  * i915_reset - reset chip after a hang
 712  * @dev: drm device to reset
 713  *
 714  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 715  * reset or otherwise an error code.
 716  *
 717  * Procedure is fairly simple:
 718  *   - reset the chip using the reset reg
 719  *   - re-init context state
 720  *   - re-init hardware status page
 721  *   - re-init ring buffer
 722  *   - re-init interrupt state
 723  *   - re-init display
 724  */
 725 int i915_reset(struct drm_device *dev)
 726 {
 727         drm_i915_private_t *dev_priv = dev->dev_private;
 728         int ret;
 729
 730         if (!i915_try_reset)
 731                 return 0;
 732
 733         mutex_lock(&dev->struct_mutex);
 734
 735         i915_gem_reset(dev);
 736
 737         ret = -ENODEV;
 738         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 739                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 740         else
 741                 ret = intel_gpu_reset(dev);
 742
 743         dev_priv->last_gpu_reset = get_seconds();
 744         if (ret) {
 745                 DRM_ERROR("Failed to reset chip.\n");
 746                 mutex_unlock(&dev->struct_mutex);
 747                 return ret;
 748         }
 749
 750         /* Ok, now get things going again... */
 751
 752         /*
 753          * Everything depends on having the GTT running, so we need to start
 754          * there.  Fortunately we don't need to do this unless we reset the
 755          * chip at a PCI level.
 756          *
 757          * Next we need to restore the context, but we don't use those
 758          * yet either...
 759          *
 760          * Ring buffer needs to be re-initialized in the KMS case, or if X
 761          * was running at the time of the reset (i.e. we weren't VT
 762          * switched away).
 763          */
 764         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 765                         !dev_priv->mm.suspended) {
 766                 struct intel_ring_buffer *ring;
 767                 int i;
 768
 769                 dev_priv->mm.suspended = 0;
 770
 771                 i915_gem_init_swizzling(dev);
 772
 773                 for_each_ring(ring, dev_priv, i)
 774                         ring->init(ring);
 775
 776                 i915_gem_context_init(dev);
 777                 i915_gem_init_ppgtt(dev);
 778
 779                 /*
 780                  * It would make sense to re-init all the other hw state, at
 781                  * least the rps/rc6/emon init done within modeset_init_hw. For
 782                  * some unknown reason, this blows up my ilk, so don't.
 783                  */
 784
 785                 mutex_unlock(&dev->struct_mutex);
 786
 787                 drm_irq_uninstall(dev);
 788                 drm_irq_install(dev);
 789         } else {
 790                 mutex_unlock(&dev->struct_mutex);
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int __devinit
 797 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 798 {
 799         struct intel_device_info *intel_info =
 800                 (struct intel_device_info *) ent->driver_data;
 801
 802         /* Only bind to function 0 of the device. Early generations
 803          * used function 1 as a placeholder for multi-head. This causes
 804          * us confusion instead, especially on the systems where both
 805          * functions have the same PCI-ID!
 806          */
 807         if (PCI_FUNC(pdev->devfn))
 808                 return -ENODEV;
 809
 810         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 811          * implementation for gen3 (and only gen3) that used legacy drm maps
 812          * (gasp!) to share buffers between X and the client. Hence we need to
 813          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 814         if (intel_info->gen != 3) {
 815                 driver.driver_features &=
 816                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 817         } else if (!intel_agp_enabled) {
 818                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 819                 return -ENODEV;
 820         }
 821
 822         return drm_get_pci_dev(pdev, ent, &driver);
 823 }
 824
 825 static void
 826 i915_pci_remove(struct pci_dev *pdev)
 827 {
 828         struct drm_device *dev = pci_get_drvdata(pdev);
 829
 830         drm_put_dev(dev);
 831 }
 832
 833 static int i915_pm_suspend(struct device *dev)
 834 {
 835         struct pci_dev *pdev = to_pci_dev(dev);
 836         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 837         int error;
 838
 839         if (!drm_dev || !drm_dev->dev_private) {
 840                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 841                 return -ENODEV;
 842         }
 843
 844         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 845                 return 0;
 846
 847         error = i915_drm_freeze(drm_dev);
 848         if (error)
 849                 return error;
 850
 851         pci_disable_device(pdev);
 852         pci_set_power_state(pdev, PCI_D3hot);
 853
 854         return 0;
 855 }
 856
 857 static int i915_pm_resume(struct device *dev)
 858 {
 859         struct pci_dev *pdev = to_pci_dev(dev);
 860         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 861
 862         return i915_resume(drm_dev);
 863 }
 864
 865 static int i915_pm_freeze(struct device *dev)
 866 {
 867         struct pci_dev *pdev = to_pci_dev(dev);
 868         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 869
 870         if (!drm_dev || !drm_dev->dev_private) {
 871                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 872                 return -ENODEV;
 873         }
 874
 875         return i915_drm_freeze(drm_dev);
 876 }
 877
 878 static int i915_pm_thaw(struct device *dev)
 879 {
 880         struct pci_dev *pdev = to_pci_dev(dev);
 881         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 882
 883         return i915_drm_thaw(drm_dev);
 884 }
 885
 886 static int i915_pm_poweroff(struct device *dev)
 887 {
 888         struct pci_dev *pdev = to_pci_dev(dev);
 889         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 890
 891         return i915_drm_freeze(drm_dev);
 892 }
 893
 894 static const struct dev_pm_ops i915_pm_ops = {
 895         .suspend = i915_pm_suspend,
 896         .resume = i915_pm_resume,
 897         .freeze = i915_pm_freeze,
 898         .thaw = i915_pm_thaw,
 899         .poweroff = i915_pm_poweroff,
 900         .restore = i915_pm_resume,
 901 };
 902
 903 static const struct vm_operations_struct i915_gem_vm_ops = {
 904         .fault = i915_gem_fault,
 905         .open = drm_gem_vm_open,
 906         .close = drm_gem_vm_close,
 907 };
 908
 909 static const struct file_operations i915_driver_fops = {
 910         .owner = THIS_MODULE,
 911         .open = drm_open,
 912         .release = drm_release,
 913         .unlocked_ioctl = drm_ioctl,
 914         .mmap = drm_gem_mmap,
 915         .poll = drm_poll,
 916         .fasync = drm_fasync,
 917         .read = drm_read,
 918 #ifdef CONFIG_COMPAT
 919         .compat_ioctl = i915_compat_ioctl,
 920 #endif
 921         .llseek = noop_llseek,
 922 };
 923
 924 static struct drm_driver driver = {
 925         /* Don't use MTRRs here; the Xserver or userspace app should
 926          * deal with them for Intel hardware.
 927          */
 928         .driver_features =
 929             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 930             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
 931         .load = i915_driver_load,
 932         .unload = i915_driver_unload,
 933         .open = i915_driver_open,
 934         .lastclose = i915_driver_lastclose,
 935         .preclose = i915_driver_preclose,
 936         .postclose = i915_driver_postclose,
 937
 938         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 939         .suspend = i915_suspend,
 940         .resume = i915_resume,
 941
 942         .device_is_agp = i915_driver_device_is_agp,
 943         .master_create = i915_master_create,
 944         .master_destroy = i915_master_destroy,
 945 #if defined(CONFIG_DEBUG_FS)
 946         .debugfs_init = i915_debugfs_init,
 947         .debugfs_cleanup = i915_debugfs_cleanup,
 948 #endif
 949         .gem_init_object = i915_gem_init_object,
 950         .gem_free_object = i915_gem_free_object,
 951         .gem_vm_ops = &i915_gem_vm_ops,
 952
 953         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 954         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 955         .gem_prime_export = i915_gem_prime_export,
 956         .gem_prime_import = i915_gem_prime_import,
 957
 958         .dumb_create = i915_gem_dumb_create,
 959         .dumb_map_offset = i915_gem_mmap_gtt,
 960         .dumb_destroy = i915_gem_dumb_destroy,
 961         .ioctls = i915_ioctls,
 962         .fops = &i915_driver_fops,
 963         .name = DRIVER_NAME,
 964         .desc = DRIVER_DESC,
 965         .date = DRIVER_DATE,
 966         .major = DRIVER_MAJOR,
 967         .minor = DRIVER_MINOR,
 968         .patchlevel = DRIVER_PATCHLEVEL,
 969 };
 970
 971 static struct pci_driver i915_pci_driver = {
 972         .name = DRIVER_NAME,
 973         .id_table = pciidlist,
 974         .probe = i915_pci_probe,
 975         .remove = i915_pci_remove,
 976         .driver.pm = &i915_pm_ops,
 977 };
 978
 979 static int __init i915_init(void)
 980 {
 981         driver.num_ioctls = i915_max_ioctl;
 982
 983         /*
 984          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 985          * explicitly disabled with the module pararmeter.
 986          *
 987          * Otherwise, just follow the parameter (defaulting to off).
 988          *
 989          * Allow optional vga_text_mode_force boot option to override
 990          * the default behavior.
 991          */
 992 #if defined(CONFIG_DRM_I915_KMS)
 993         if (i915_modeset != 0)
 994                 driver.driver_features |= DRIVER_MODESET;
 995 #endif
 996         if (i915_modeset == 1)
 997                 driver.driver_features |= DRIVER_MODESET;
 998
 999 #ifdef CONFIG_VGA_CONSOLE
1000         if (vgacon_text_force() && i915_modeset == -1)
1001                 driver.driver_features &= ~DRIVER_MODESET;
1002 #endif
1003
1004         if (!(driver.driver_features & DRIVER_MODESET))
1005                 driver.get_vblank_timestamp = NULL;
1006
1007         return drm_pci_init(&driver, &i915_pci_driver);
1008 }
1009
1010 static void __exit i915_exit(void)
1011 {
1012         drm_pci_exit(&driver, &i915_pci_driver);
1013 }
1014
1015 module_init(i915_init);
1016 module_exit(i915_exit);
1017
1018 MODULE_AUTHOR(DRIVER_AUTHOR);
1019 MODULE_DESCRIPTION(DRIVER_DESC);
1020 MODULE_LICENSE("GPL and additional rights");
1021
1022 /* We give fast paths for the really cool registers */
1023 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1024         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1025          ((reg) < 0x40000) &&            \
1026          ((reg) != FORCEWAKE))
1027
1028 static bool IS_DISPLAYREG(u32 reg)
1029 {
1030         /*
1031          * This should make it easier to transition modules over to the
1032          * new register block scheme, since we can do it incrementally.
1033          */
1034         if (reg >= 0x180000)
1035                 return false;
1036
1037         if (reg >= RENDER_RING_BASE &&
1038             reg < RENDER_RING_BASE + 0xff)
1039                 return false;
1040         if (reg >= GEN6_BSD_RING_BASE &&
1041             reg < GEN6_BSD_RING_BASE + 0xff)
1042                 return false;
1043         if (reg >= BLT_RING_BASE &&
1044             reg < BLT_RING_BASE + 0xff)
1045                 return false;
1046
1047         if (reg == PGTBL_ER)
1048                 return false;
1049
1050         if (reg >= IPEIR_I965 &&
1051             reg < HWSTAM)
1052                 return false;
1053
1054         if (reg == MI_MODE)
1055                 return false;
1056
1057         if (reg == GFX_MODE_GEN7)
1058                 return false;
1059
1060         if (reg == RENDER_HWS_PGA_GEN7 ||
1061             reg == BSD_HWS_PGA_GEN7 ||
1062             reg == BLT_HWS_PGA_GEN7)
1063                 return false;
1064
1065         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1066             reg == GEN6_BSD_RNCID)
1067                 return false;
1068
1069         if (reg == GEN6_BLITTER_ECOSKPD)
1070                 return false;
1071
1072         if (reg >= 0x4000c &&
1073             reg <= 0x4002c)
1074                 return false;
1075
1076         if (reg >= 0x4f000 &&
1077             reg <= 0x4f08f)
1078                 return false;
1079
1080         if (reg >= 0x4f100 &&
1081             reg <= 0x4f11f)
1082                 return false;
1083
1084         if (reg >= VLV_MASTER_IER &&
1085             reg <= GEN6_PMIER)
1086                 return false;
1087
1088         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1089             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1090                 return false;
1091
1092         if (reg >= VLV_IIR_RW &&
1093             reg <= VLV_ISR)
1094                 return false;
1095
1096         if (reg == FORCEWAKE_VLV ||
1097             reg == FORCEWAKE_ACK_VLV)
1098                 return false;
1099
1100         if (reg == GEN6_GDRST)
1101                 return false;
1102
1103         return true;
1104 }
1105
1106 #define __i915_read(x, y) \
1107 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1108         u##x val = 0; \
1109         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1110                 unsigned long irqflags; \
1111                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1112                 if (dev_priv->forcewake_count == 0) \
1113                         dev_priv->gt.force_wake_get(dev_priv); \
1114                 val = read##y(dev_priv->regs + reg); \
1115                 if (dev_priv->forcewake_count == 0) \
1116                         dev_priv->gt.force_wake_put(dev_priv); \
1117                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1118         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1119                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1120         } else { \
1121                 val = read##y(dev_priv->regs + reg); \
1122         } \
1123         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1124         return val; \
1125 }
1126
1127 __i915_read(8, b)
1128 __i915_read(16, w)
1129 __i915_read(32, l)
1130 __i915_read(64, q)
1131 #undef __i915_read
1132
1133 #define __i915_write(x, y) \
1134 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1135         u32 __fifo_ret = 0; \
1136         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1137         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1138                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1139         } \
1140         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1141                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1142         } else {                                                        \
1143                 write##y(val, dev_priv->regs + reg);                    \
1144         }                                                               \
1145         if (unlikely(__fifo_ret)) { \
1146                 gen6_gt_check_fifodbg(dev_priv); \
1147         } \
1148 }
1149 __i915_write(8, b)
1150 __i915_write(16, w)
1151 __i915_write(32, l)
1152 __i915_write(64, q)
1153 #undef __i915_write