drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. (default: false)");
 125
 126 int i915_disable_power_well __read_mostly = 0;
 127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 128 MODULE_PARM_DESC(disable_power_well,
 129                  "Disable the power well when possible (default: false)");
 130
 131 static struct drm_driver driver;
 132 extern int intel_agp_enabled;
 133
 134 #define INTEL_VGA_DEVICE(id, info) {            \
 135         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 136         .class_mask = 0xff0000,                 \
 137         .vendor = 0x8086,                       \
 138         .device = id,                           \
 139         .subvendor = PCI_ANY_ID,                \
 140         .subdevice = PCI_ANY_ID,                \
 141         .driver_data = (unsigned long) info }
 142
 143 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
 144         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 145         .class_mask = 0xff0000,                 \
 146         .vendor = 0x8086,                       \
 147         .device = 0x16a,                        \
 148         .subvendor = 0x152d,                    \
 149         .subdevice = 0x8990,                    \
 150         .driver_data = (unsigned long) info }
 151
 152
 153 static const struct intel_device_info intel_i830_info = {
 154         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 155         .has_overlay = 1, .overlay_needs_physical = 1,
 156 };
 157
 158 static const struct intel_device_info intel_845g_info = {
 159         .gen = 2, .num_pipes = 1,
 160         .has_overlay = 1, .overlay_needs_physical = 1,
 161 };
 162
 163 static const struct intel_device_info intel_i85x_info = {
 164         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 165         .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i865g_info = {
 170         .gen = 2, .num_pipes = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172 };
 173
 174 static const struct intel_device_info intel_i915g_info = {
 175         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 176         .has_overlay = 1, .overlay_needs_physical = 1,
 177 };
 178 static const struct intel_device_info intel_i915gm_info = {
 179         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 180         .cursor_needs_physical = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .supports_tv = 1,
 183 };
 184 static const struct intel_device_info intel_i945g_info = {
 185         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 186         .has_overlay = 1, .overlay_needs_physical = 1,
 187 };
 188 static const struct intel_device_info intel_i945gm_info = {
 189         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 190         .has_hotplug = 1, .cursor_needs_physical = 1,
 191         .has_overlay = 1, .overlay_needs_physical = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_i965g_info = {
 196         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 197         .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_i965gm_info = {
 202         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 203         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 204         .has_overlay = 1,
 205         .supports_tv = 1,
 206 };
 207
 208 static const struct intel_device_info intel_g33_info = {
 209         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_g45_info = {
 215         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 216         .has_pipe_cxsr = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218 };
 219
 220 static const struct intel_device_info intel_gm45_info = {
 221         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 222         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 223         .has_pipe_cxsr = 1, .has_hotplug = 1,
 224         .supports_tv = 1,
 225         .has_bsd_ring = 1,
 226 };
 227
 228 static const struct intel_device_info intel_pineview_info = {
 229         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 230         .need_gfx_hws = 1, .has_hotplug = 1,
 231         .has_overlay = 1,
 232 };
 233
 234 static const struct intel_device_info intel_ironlake_d_info = {
 235         .gen = 5, .num_pipes = 2,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238 };
 239
 240 static const struct intel_device_info intel_ironlake_m_info = {
 241         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 242         .need_gfx_hws = 1, .has_hotplug = 1,
 243         .has_fbc = 1,
 244         .has_bsd_ring = 1,
 245 };
 246
 247 static const struct intel_device_info intel_sandybridge_d_info = {
 248         .gen = 6, .num_pipes = 2,
 249         .need_gfx_hws = 1, .has_hotplug = 1,
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253         .has_force_wake = 1,
 254 };
 255
 256 static const struct intel_device_info intel_sandybridge_m_info = {
 257         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 258         .need_gfx_hws = 1, .has_hotplug = 1,
 259         .has_fbc = 1,
 260         .has_bsd_ring = 1,
 261         .has_blt_ring = 1,
 262         .has_llc = 1,
 263         .has_force_wake = 1,
 264 };
 265
 266 #define GEN7_FEATURES  \
 267         .gen = 7, .num_pipes = 3, \
 268         .need_gfx_hws = 1, .has_hotplug = 1, \
 269         .has_bsd_ring = 1, \
 270         .has_blt_ring = 1, \
 271         .has_llc = 1, \
 272         .has_force_wake = 1
 273
 274 static const struct intel_device_info intel_ivybridge_d_info = {
 275         GEN7_FEATURES,
 276         .is_ivybridge = 1,
 277 };
 278
 279 static const struct intel_device_info intel_ivybridge_m_info = {
 280         GEN7_FEATURES,
 281         .is_ivybridge = 1,
 282         .is_mobile = 1,
 283 };
 284
 285 static const struct intel_device_info intel_ivybridge_q_info = {
 286         GEN7_FEATURES,
 287         .is_ivybridge = 1,
 288         .num_pipes = 0, /* legal, last one wins */
 289 };
 290
 291 static const struct intel_device_info intel_valleyview_m_info = {
 292         GEN7_FEATURES,
 293         .is_mobile = 1,
 294         .num_pipes = 2,
 295         .is_valleyview = 1,
 296         .display_mmio_offset = VLV_DISPLAY_BASE,
 297         .has_llc = 0, /* legal, last one wins */
 298 };
 299
 300 static const struct intel_device_info intel_valleyview_d_info = {
 301         GEN7_FEATURES,
 302         .num_pipes = 2,
 303         .is_valleyview = 1,
 304         .display_mmio_offset = VLV_DISPLAY_BASE,
 305         .has_llc = 0, /* legal, last one wins */
 306 };
 307
 308 static const struct intel_device_info intel_haswell_d_info = {
 309         GEN7_FEATURES,
 310         .is_haswell = 1,
 311 };
 312
 313 static const struct intel_device_info intel_haswell_m_info = {
 314         GEN7_FEATURES,
 315         .is_haswell = 1,
 316         .is_mobile = 1,
 317 };
 318
 319 static const struct pci_device_id pciidlist[] = {               /* aka */
 320         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 321         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 322         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 323         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 324         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 325         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 326         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 327         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 328         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 329         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 330         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 331         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 332         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 333         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 334         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 335         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 336         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 337         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 338         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 339         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 340         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 341         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 342         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 343         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 344         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 345         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 346         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 347         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 348         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 349         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 350         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 351         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 352         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 353         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 354         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 355         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 356         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 357         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 358         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 359         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 360         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 361         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 362         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 363         INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
 364         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 365         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 366         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 367         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
 368         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 369         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 370         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
 371         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 372         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 373         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 374         INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
 375         INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
 376         INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
 377         INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
 378         INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
 379         INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
 380         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 381         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 382         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
 383         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 384         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 385         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
 386         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 387         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 388         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
 389         INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
 390         INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
 391         INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
 392         INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
 393         INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
 394         INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
 395         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 396         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 397         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
 398         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 399         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 400         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
 401         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 402         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 403         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
 404         INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
 405         INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
 406         INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
 407         INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
 408         INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
 409         INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
 410         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 411         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 412         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
 413         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 414         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 415         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
 416         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 417         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 418         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
 419         INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
 420         INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
 421         INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
 422         INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
 423         INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
 424         INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
 425         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 426         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 427         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 428         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 429         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 430         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 431         {0, 0, 0}
 432 };
 433
 434 #if defined(CONFIG_DRM_I915_KMS)
 435 MODULE_DEVICE_TABLE(pci, pciidlist);
 436 #endif
 437
 438 void intel_detect_pch(struct drm_device *dev)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         struct pci_dev *pch;
 442
 443         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 444          * (which really amounts to a PCH but no South Display).
 445          */
 446         if (INTEL_INFO(dev)->num_pipes == 0) {
 447                 dev_priv->pch_type = PCH_NOP;
 448                 dev_priv->num_pch_pll = 0;
 449                 return;
 450         }
 451
 452         /*
 453          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 454          * make graphics device passthrough work easy for VMM, that only
 455          * need to expose ISA bridge to let driver know the real hardware
 456          * underneath. This is a requirement from virtualization team.
 457          */
 458         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 459         if (pch) {
 460                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 461                         unsigned short id;
 462                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 463                         dev_priv->pch_id = id;
 464
 465                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 466                                 dev_priv->pch_type = PCH_IBX;
 467                                 dev_priv->num_pch_pll = 2;
 468                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 469                                 WARN_ON(!IS_GEN5(dev));
 470                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 471                                 dev_priv->pch_type = PCH_CPT;
 472                                 dev_priv->num_pch_pll = 2;
 473                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 474                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 475                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 476                                 /* PantherPoint is CPT compatible */
 477                                 dev_priv->pch_type = PCH_CPT;
 478                                 dev_priv->num_pch_pll = 2;
 479                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 480                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 481                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 482                                 dev_priv->pch_type = PCH_LPT;
 483                                 dev_priv->num_pch_pll = 0;
 484                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 485                                 WARN_ON(!IS_HASWELL(dev));
 486                                 WARN_ON(IS_ULT(dev));
 487                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 488                                 dev_priv->pch_type = PCH_LPT;
 489                                 dev_priv->num_pch_pll = 0;
 490                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 491                                 WARN_ON(!IS_HASWELL(dev));
 492                                 WARN_ON(!IS_ULT(dev));
 493                         }
 494                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 495                 }
 496                 pci_dev_put(pch);
 497         }
 498 }
 499
 500 bool i915_semaphore_is_enabled(struct drm_device *dev)
 501 {
 502         if (INTEL_INFO(dev)->gen < 6)
 503                 return 0;
 504
 505         if (i915_semaphores >= 0)
 506                 return i915_semaphores;
 507
 508 #ifdef CONFIG_INTEL_IOMMU
 509         /* Enable semaphores on SNB when IO remapping is off */
 510         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 511                 return false;
 512 #endif
 513
 514         return 1;
 515 }
 516
 517 static int i915_drm_freeze(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         struct drm_crtc *crtc;
 521
 522         /* ignore lid events during suspend */
 523         mutex_lock(&dev_priv->modeset_restore_lock);
 524         dev_priv->modeset_restore = MODESET_SUSPENDED;
 525         mutex_unlock(&dev_priv->modeset_restore_lock);
 526
 527         intel_set_power_well(dev, true);
 528
 529         drm_kms_helper_poll_disable(dev);
 530
 531         pci_save_state(dev->pdev);
 532
 533         /* If KMS is active, we do the leavevt stuff here */
 534         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 535                 int error = i915_gem_idle(dev);
 536                 if (error) {
 537                         dev_err(&dev->pdev->dev,
 538                                 "GEM idle failed, resume might fail\n");
 539                         return error;
 540                 }
 541
 542                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 543
 544                 drm_irq_uninstall(dev);
 545                 dev_priv->enable_hotplug_processing = false;
 546                 /*
 547                  * Disable CRTCs directly since we want to preserve sw state
 548                  * for _thaw.
 549                  */
 550                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 551                         dev_priv->display.crtc_disable(crtc);
 552         }
 553
 554         i915_save_state(dev);
 555
 556         intel_opregion_fini(dev);
 557
 558         console_lock();
 559         intel_fbdev_set_suspend(dev, 1);
 560         console_unlock();
 561
 562         return 0;
 563 }
 564
 565 int i915_suspend(struct drm_device *dev, pm_message_t state)
 566 {
 567         int error;
 568
 569         if (!dev || !dev->dev_private) {
 570                 DRM_ERROR("dev: %p\n", dev);
 571                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 572                 return -ENODEV;
 573         }
 574
 575         if (state.event == PM_EVENT_PRETHAW)
 576                 return 0;
 577
 578
 579         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 580                 return 0;
 581
 582         error = i915_drm_freeze(dev);
 583         if (error)
 584                 return error;
 585
 586         if (state.event == PM_EVENT_SUSPEND) {
 587                 /* Shut down the device */
 588                 pci_disable_device(dev->pdev);
 589                 pci_set_power_state(dev->pdev, PCI_D3hot);
 590         }
 591
 592         return 0;
 593 }
 594
 595 void intel_console_resume(struct work_struct *work)
 596 {
 597         struct drm_i915_private *dev_priv =
 598                 container_of(work, struct drm_i915_private,
 599                              console_resume_work);
 600         struct drm_device *dev = dev_priv->dev;
 601
 602         console_lock();
 603         intel_fbdev_set_suspend(dev, 0);
 604         console_unlock();
 605 }
 606
 607 static void intel_resume_hotplug(struct drm_device *dev)
 608 {
 609         struct drm_mode_config *mode_config = &dev->mode_config;
 610         struct intel_encoder *encoder;
 611
 612         mutex_lock(&mode_config->mutex);
 613         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 614
 615         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 616                 if (encoder->hot_plug)
 617                         encoder->hot_plug(encoder);
 618
 619         mutex_unlock(&mode_config->mutex);
 620
 621         /* Just fire off a uevent and let userspace tell us what to do */
 622         drm_helper_hpd_irq_event(dev);
 623 }
 624
 625 static int __i915_drm_thaw(struct drm_device *dev)
 626 {
 627         struct drm_i915_private *dev_priv = dev->dev_private;
 628         int error = 0;
 629
 630         i915_restore_state(dev);
 631         intel_opregion_setup(dev);
 632
 633         /* KMS EnterVT equivalent */
 634         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 635                 intel_init_pch_refclk(dev);
 636
 637                 mutex_lock(&dev->struct_mutex);
 638                 dev_priv->mm.suspended = 0;
 639
 640                 error = i915_gem_init_hw(dev);
 641                 mutex_unlock(&dev->struct_mutex);
 642
 643                 /* We need working interrupts for modeset enabling ... */
 644                 drm_irq_install(dev);
 645
 646                 intel_modeset_init_hw(dev);
 647
 648                 drm_modeset_lock_all(dev);
 649                 intel_modeset_setup_hw_state(dev, true);
 650                 drm_modeset_unlock_all(dev);
 651
 652                 /*
 653                  * ... but also need to make sure that hotplug processing
 654                  * doesn't cause havoc. Like in the driver load code we don't
 655                  * bother with the tiny race here where we might loose hotplug
 656                  * notifications.
 657                  * */
 658                 intel_hpd_init(dev);
 659                 dev_priv->enable_hotplug_processing = true;
 660                 /* Config may have changed between suspend and resume */
 661                 intel_resume_hotplug(dev);
 662         }
 663
 664         intel_opregion_init(dev);
 665
 666         /*
 667          * The console lock can be pretty contented on resume due
 668          * to all the printk activity.  Try to keep it out of the hot
 669          * path of resume if possible.
 670          */
 671         if (console_trylock()) {
 672                 intel_fbdev_set_suspend(dev, 0);
 673                 console_unlock();
 674         } else {
 675                 schedule_work(&dev_priv->console_resume_work);
 676         }
 677
 678         mutex_lock(&dev_priv->modeset_restore_lock);
 679         dev_priv->modeset_restore = MODESET_DONE;
 680         mutex_unlock(&dev_priv->modeset_restore_lock);
 681         return error;
 682 }
 683
 684 static int i915_drm_thaw(struct drm_device *dev)
 685 {
 686         int error = 0;
 687
 688         intel_gt_sanitize(dev);
 689
 690         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 691                 mutex_lock(&dev->struct_mutex);
 692                 i915_gem_restore_gtt_mappings(dev);
 693                 mutex_unlock(&dev->struct_mutex);
 694         }
 695
 696         __i915_drm_thaw(dev);
 697
 698         return error;
 699 }
 700
 701 int i915_resume(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int ret;
 705
 706         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 707                 return 0;
 708
 709         if (pci_enable_device(dev->pdev))
 710                 return -EIO;
 711
 712         pci_set_master(dev->pdev);
 713
 714         intel_gt_sanitize(dev);
 715
 716         /*
 717          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 718          * earlier) need this since the BIOS might clear all our scratch PTEs.
 719          */
 720         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 721             !dev_priv->opregion.header) {
 722                 mutex_lock(&dev->struct_mutex);
 723                 i915_gem_restore_gtt_mappings(dev);
 724                 mutex_unlock(&dev->struct_mutex);
 725         }
 726
 727         ret = __i915_drm_thaw(dev);
 728         if (ret)
 729                 return ret;
 730
 731         drm_kms_helper_poll_enable(dev);
 732         return 0;
 733 }
 734
 735 static int i8xx_do_reset(struct drm_device *dev)
 736 {
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738
 739         if (IS_I85X(dev))
 740                 return -ENODEV;
 741
 742         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 743         POSTING_READ(D_STATE);
 744
 745         if (IS_I830(dev) || IS_845G(dev)) {
 746                 I915_WRITE(DEBUG_RESET_I830,
 747                            DEBUG_RESET_DISPLAY |
 748                            DEBUG_RESET_RENDER |
 749                            DEBUG_RESET_FULL);
 750                 POSTING_READ(DEBUG_RESET_I830);
 751                 msleep(1);
 752
 753                 I915_WRITE(DEBUG_RESET_I830, 0);
 754                 POSTING_READ(DEBUG_RESET_I830);
 755         }
 756
 757         msleep(1);
 758
 759         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 760         POSTING_READ(D_STATE);
 761
 762         return 0;
 763 }
 764
 765 static int i965_reset_complete(struct drm_device *dev)
 766 {
 767         u8 gdrst;
 768         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 769         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 770 }
 771
 772 static int i965_do_reset(struct drm_device *dev)
 773 {
 774         int ret;
 775         u8 gdrst;
 776
 777         /*
 778          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 779          * well as the reset bit (GR/bit 0).  Setting the GR bit
 780          * triggers the reset; when done, the hardware will clear it.
 781          */
 782         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 783         pci_write_config_byte(dev->pdev, I965_GDRST,
 784                               gdrst | GRDOM_RENDER |
 785                               GRDOM_RESET_ENABLE);
 786         ret =  wait_for(i965_reset_complete(dev), 500);
 787         if (ret)
 788                 return ret;
 789
 790         /* We can't reset render&media without also resetting display ... */
 791         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 792         pci_write_config_byte(dev->pdev, I965_GDRST,
 793                               gdrst | GRDOM_MEDIA |
 794                               GRDOM_RESET_ENABLE);
 795
 796         return wait_for(i965_reset_complete(dev), 500);
 797 }
 798
 799 static int ironlake_do_reset(struct drm_device *dev)
 800 {
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         u32 gdrst;
 803         int ret;
 804
 805         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 806         gdrst &= ~GRDOM_MASK;
 807         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 808                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 809         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 810         if (ret)
 811                 return ret;
 812
 813         /* We can't reset render&media without also resetting display ... */
 814         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 815         gdrst &= ~GRDOM_MASK;
 816         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 817                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 818         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 819 }
 820
 821 static int gen6_do_reset(struct drm_device *dev)
 822 {
 823         struct drm_i915_private *dev_priv = dev->dev_private;
 824         int     ret;
 825         unsigned long irqflags;
 826
 827         /* Hold gt_lock across reset to prevent any register access
 828          * with forcewake not set correctly
 829          */
 830         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 831
 832         /* Reset the chip */
 833
 834         /* GEN6_GDRST is not in the gt power well, no need to check
 835          * for fifo space for the write or forcewake the chip for
 836          * the read
 837          */
 838         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 839
 840         /* Spin waiting for the device to ack the reset request */
 841         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 842
 843         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 844         if (dev_priv->forcewake_count)
 845                 dev_priv->gt.force_wake_get(dev_priv);
 846         else
 847                 dev_priv->gt.force_wake_put(dev_priv);
 848
 849         /* Restore fifo count */
 850         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 851
 852         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 853         return ret;
 854 }
 855
 856 int intel_gpu_reset(struct drm_device *dev)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859         int ret = -ENODEV;
 860
 861         switch (INTEL_INFO(dev)->gen) {
 862         case 7:
 863         case 6:
 864                 ret = gen6_do_reset(dev);
 865                 break;
 866         case 5:
 867                 ret = ironlake_do_reset(dev);
 868                 break;
 869         case 4:
 870                 ret = i965_do_reset(dev);
 871                 break;
 872         case 2:
 873                 ret = i8xx_do_reset(dev);
 874                 break;
 875         }
 876
 877         /* Also reset the gpu hangman. */
 878         if (dev_priv->gpu_error.stop_rings) {
 879                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 880                 dev_priv->gpu_error.stop_rings = 0;
 881                 if (ret == -ENODEV) {
 882                         DRM_ERROR("Reset not implemented, but ignoring "
 883                                   "error for simulated gpu hangs\n");
 884                         ret = 0;
 885                 }
 886         }
 887
 888         return ret;
 889 }
 890
 891 /**
 892  * i915_reset - reset chip after a hang
 893  * @dev: drm device to reset
 894  *
 895  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 896  * reset or otherwise an error code.
 897  *
 898  * Procedure is fairly simple:
 899  *   - reset the chip using the reset reg
 900  *   - re-init context state
 901  *   - re-init hardware status page
 902  *   - re-init ring buffer
 903  *   - re-init interrupt state
 904  *   - re-init display
 905  */
 906 int i915_reset(struct drm_device *dev)
 907 {
 908         drm_i915_private_t *dev_priv = dev->dev_private;
 909         int ret;
 910
 911         if (!i915_try_reset)
 912                 return 0;
 913
 914         mutex_lock(&dev->struct_mutex);
 915
 916         i915_gem_reset(dev);
 917
 918         ret = -ENODEV;
 919         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 920                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 921         else
 922                 ret = intel_gpu_reset(dev);
 923
 924         dev_priv->gpu_error.last_reset = get_seconds();
 925         if (ret) {
 926                 DRM_ERROR("Failed to reset chip.\n");
 927                 mutex_unlock(&dev->struct_mutex);
 928                 return ret;
 929         }
 930
 931         /* Ok, now get things going again... */
 932
 933         /*
 934          * Everything depends on having the GTT running, so we need to start
 935          * there.  Fortunately we don't need to do this unless we reset the
 936          * chip at a PCI level.
 937          *
 938          * Next we need to restore the context, but we don't use those
 939          * yet either...
 940          *
 941          * Ring buffer needs to be re-initialized in the KMS case, or if X
 942          * was running at the time of the reset (i.e. we weren't VT
 943          * switched away).
 944          */
 945         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 946                         !dev_priv->mm.suspended) {
 947                 struct intel_ring_buffer *ring;
 948                 int i;
 949
 950                 dev_priv->mm.suspended = 0;
 951
 952                 i915_gem_init_swizzling(dev);
 953
 954                 for_each_ring(ring, dev_priv, i)
 955                         ring->init(ring);
 956
 957                 i915_gem_context_init(dev);
 958                 if (dev_priv->mm.aliasing_ppgtt) {
 959                         ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
 960                         if (ret)
 961                                 i915_gem_cleanup_aliasing_ppgtt(dev);
 962                 }
 963
 964                 /*
 965                  * It would make sense to re-init all the other hw state, at
 966                  * least the rps/rc6/emon init done within modeset_init_hw. For
 967                  * some unknown reason, this blows up my ilk, so don't.
 968                  */
 969
 970                 mutex_unlock(&dev->struct_mutex);
 971
 972                 drm_irq_uninstall(dev);
 973                 drm_irq_install(dev);
 974                 intel_hpd_init(dev);
 975         } else {
 976                 mutex_unlock(&dev->struct_mutex);
 977         }
 978
 979         return 0;
 980 }
 981
 982 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 983 {
 984         struct intel_device_info *intel_info =
 985                 (struct intel_device_info *) ent->driver_data;
 986
 987         if (intel_info->is_valleyview)
 988                 if(!i915_preliminary_hw_support) {
 989                         DRM_ERROR("Preliminary hardware support disabled\n");
 990                         return -ENODEV;
 991                 }
 992
 993         /* Only bind to function 0 of the device. Early generations
 994          * used function 1 as a placeholder for multi-head. This causes
 995          * us confusion instead, especially on the systems where both
 996          * functions have the same PCI-ID!
 997          */
 998         if (PCI_FUNC(pdev->devfn))
 999                 return -ENODEV;
1000
1001         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
1002          * implementation for gen3 (and only gen3) that used legacy drm maps
1003          * (gasp!) to share buffers between X and the client. Hence we need to
1004          * keep around the fake agp stuff for gen3, even when kms is enabled. */
1005         if (intel_info->gen != 3) {
1006                 driver.driver_features &=
1007                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
1008         } else if (!intel_agp_enabled) {
1009                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1010                 return -ENODEV;
1011         }
1012
1013         return drm_get_pci_dev(pdev, ent, &driver);
1014 }
1015
1016 static void
1017 i915_pci_remove(struct pci_dev *pdev)
1018 {
1019         struct drm_device *dev = pci_get_drvdata(pdev);
1020
1021         drm_put_dev(dev);
1022 }
1023
1024 static int i915_pm_suspend(struct device *dev)
1025 {
1026         struct pci_dev *pdev = to_pci_dev(dev);
1027         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1028         int error;
1029
1030         if (!drm_dev || !drm_dev->dev_private) {
1031                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1032                 return -ENODEV;
1033         }
1034
1035         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1036                 return 0;
1037
1038         error = i915_drm_freeze(drm_dev);
1039         if (error)
1040                 return error;
1041
1042         pci_disable_device(pdev);
1043         pci_set_power_state(pdev, PCI_D3hot);
1044
1045         return 0;
1046 }
1047
1048 static int i915_pm_resume(struct device *dev)
1049 {
1050         struct pci_dev *pdev = to_pci_dev(dev);
1051         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1052
1053         return i915_resume(drm_dev);
1054 }
1055
1056 static int i915_pm_freeze(struct device *dev)
1057 {
1058         struct pci_dev *pdev = to_pci_dev(dev);
1059         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1060
1061         if (!drm_dev || !drm_dev->dev_private) {
1062                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1063                 return -ENODEV;
1064         }
1065
1066         return i915_drm_freeze(drm_dev);
1067 }
1068
1069 static int i915_pm_thaw(struct device *dev)
1070 {
1071         struct pci_dev *pdev = to_pci_dev(dev);
1072         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1073
1074         return i915_drm_thaw(drm_dev);
1075 }
1076
1077 static int i915_pm_poweroff(struct device *dev)
1078 {
1079         struct pci_dev *pdev = to_pci_dev(dev);
1080         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1081
1082         return i915_drm_freeze(drm_dev);
1083 }
1084
1085 static const struct dev_pm_ops i915_pm_ops = {
1086         .suspend = i915_pm_suspend,
1087         .resume = i915_pm_resume,
1088         .freeze = i915_pm_freeze,
1089         .thaw = i915_pm_thaw,
1090         .poweroff = i915_pm_poweroff,
1091         .restore = i915_pm_resume,
1092 };
1093
1094 static const struct vm_operations_struct i915_gem_vm_ops = {
1095         .fault = i915_gem_fault,
1096         .open = drm_gem_vm_open,
1097         .close = drm_gem_vm_close,
1098 };
1099
1100 static const struct file_operations i915_driver_fops = {
1101         .owner = THIS_MODULE,
1102         .open = drm_open,
1103         .release = drm_release,
1104         .unlocked_ioctl = drm_ioctl,
1105         .mmap = drm_gem_mmap,
1106         .poll = drm_poll,
1107         .fasync = drm_fasync,
1108         .read = drm_read,
1109 #ifdef CONFIG_COMPAT
1110         .compat_ioctl = i915_compat_ioctl,
1111 #endif
1112         .llseek = noop_llseek,
1113 };
1114
1115 static struct drm_driver driver = {
1116         /* Don't use MTRRs here; the Xserver or userspace app should
1117          * deal with them for Intel hardware.
1118          */
1119         .driver_features =
1120             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1121             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1122         .load = i915_driver_load,
1123         .unload = i915_driver_unload,
1124         .open = i915_driver_open,
1125         .lastclose = i915_driver_lastclose,
1126         .preclose = i915_driver_preclose,
1127         .postclose = i915_driver_postclose,
1128
1129         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1130         .suspend = i915_suspend,
1131         .resume = i915_resume,
1132
1133         .device_is_agp = i915_driver_device_is_agp,
1134         .master_create = i915_master_create,
1135         .master_destroy = i915_master_destroy,
1136 #if defined(CONFIG_DEBUG_FS)
1137         .debugfs_init = i915_debugfs_init,
1138         .debugfs_cleanup = i915_debugfs_cleanup,
1139 #endif
1140         .gem_init_object = i915_gem_init_object,
1141         .gem_free_object = i915_gem_free_object,
1142         .gem_vm_ops = &i915_gem_vm_ops,
1143
1144         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1145         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1146         .gem_prime_export = i915_gem_prime_export,
1147         .gem_prime_import = i915_gem_prime_import,
1148
1149         .dumb_create = i915_gem_dumb_create,
1150         .dumb_map_offset = i915_gem_mmap_gtt,
1151         .dumb_destroy = i915_gem_dumb_destroy,
1152         .ioctls = i915_ioctls,
1153         .fops = &i915_driver_fops,
1154         .name = DRIVER_NAME,
1155         .desc = DRIVER_DESC,
1156         .date = DRIVER_DATE,
1157         .major = DRIVER_MAJOR,
1158         .minor = DRIVER_MINOR,
1159         .patchlevel = DRIVER_PATCHLEVEL,
1160 };
1161
1162 static struct pci_driver i915_pci_driver = {
1163         .name = DRIVER_NAME,
1164         .id_table = pciidlist,
1165         .probe = i915_pci_probe,
1166         .remove = i915_pci_remove,
1167         .driver.pm = &i915_pm_ops,
1168 };
1169
1170 static int __init i915_init(void)
1171 {
1172         driver.num_ioctls = i915_max_ioctl;
1173
1174         /*
1175          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1176          * explicitly disabled with the module pararmeter.
1177          *
1178          * Otherwise, just follow the parameter (defaulting to off).
1179          *
1180          * Allow optional vga_text_mode_force boot option to override
1181          * the default behavior.
1182          */
1183 #if defined(CONFIG_DRM_I915_KMS)
1184         if (i915_modeset != 0)
1185                 driver.driver_features |= DRIVER_MODESET;
1186 #endif
1187         if (i915_modeset == 1)
1188                 driver.driver_features |= DRIVER_MODESET;
1189
1190 #ifdef CONFIG_VGA_CONSOLE
1191         if (vgacon_text_force() && i915_modeset == -1)
1192                 driver.driver_features &= ~DRIVER_MODESET;
1193 #endif
1194
1195         if (!(driver.driver_features & DRIVER_MODESET))
1196                 driver.get_vblank_timestamp = NULL;
1197
1198         return drm_pci_init(&driver, &i915_pci_driver);
1199 }
1200
1201 static void __exit i915_exit(void)
1202 {
1203         drm_pci_exit(&driver, &i915_pci_driver);
1204 }
1205
1206 module_init(i915_init);
1207 module_exit(i915_exit);
1208
1209 MODULE_AUTHOR(DRIVER_AUTHOR);
1210 MODULE_DESCRIPTION(DRIVER_DESC);
1211 MODULE_LICENSE("GPL and additional rights");
1212
1213 /* We give fast paths for the really cool registers */
1214 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1215         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1216          ((reg) < 0x40000) &&            \
1217          ((reg) != FORCEWAKE))
1218 static void
1219 ilk_dummy_write(struct drm_i915_private *dev_priv)
1220 {
1221         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1222          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1223          * harmless to write 0 into. */
1224         I915_WRITE_NOTRACE(MI_MODE, 0);
1225 }
1226
1227 static void
1228 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1229 {
1230         if (IS_HASWELL(dev_priv->dev) &&
1231             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1232                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1233                           reg);
1234                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1235         }
1236 }
1237
1238 static void
1239 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1240 {
1241         if (IS_HASWELL(dev_priv->dev) &&
1242             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1243                 DRM_ERROR("Unclaimed write to %x\n", reg);
1244                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1245         }
1246 }
1247
1248 #define __i915_read(x, y) \
1249 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1250         unsigned long irqflags; \
1251         u##x val = 0; \
1252         spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1253         if (IS_GEN5(dev_priv->dev)) \
1254                 ilk_dummy_write(dev_priv); \
1255         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1256                 if (dev_priv->forcewake_count == 0) \
1257                         dev_priv->gt.force_wake_get(dev_priv); \
1258                 val = read##y(dev_priv->regs + reg); \
1259                 if (dev_priv->forcewake_count == 0) \
1260                         dev_priv->gt.force_wake_put(dev_priv); \
1261         } else { \
1262                 val = read##y(dev_priv->regs + reg); \
1263         } \
1264         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1265         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1266         return val; \
1267 }
1268
1269 __i915_read(8, b)
1270 __i915_read(16, w)
1271 __i915_read(32, l)
1272 __i915_read(64, q)
1273 #undef __i915_read
1274
1275 #define __i915_write(x, y) \
1276 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1277         unsigned long irqflags; \
1278         u32 __fifo_ret = 0; \
1279         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1280         spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1281         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1282                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1283         } \
1284         if (IS_GEN5(dev_priv->dev)) \
1285                 ilk_dummy_write(dev_priv); \
1286         hsw_unclaimed_reg_clear(dev_priv, reg); \
1287         write##y(val, dev_priv->regs + reg); \
1288         if (unlikely(__fifo_ret)) { \
1289                 gen6_gt_check_fifodbg(dev_priv); \
1290         } \
1291         hsw_unclaimed_reg_check(dev_priv, reg); \
1292         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1293 }
1294 __i915_write(8, b)
1295 __i915_write(16, w)
1296 __i915_write(32, l)
1297 __i915_write(64, q)
1298 #undef __i915_write
1299
1300 static const struct register_whitelist {
1301         uint64_t offset;
1302         uint32_t size;
1303         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1304 } whitelist[] = {
1305         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1306 };
1307
1308 int i915_reg_read_ioctl(struct drm_device *dev,
1309                         void *data, struct drm_file *file)
1310 {
1311         struct drm_i915_private *dev_priv = dev->dev_private;
1312         struct drm_i915_reg_read *reg = data;
1313         struct register_whitelist const *entry = whitelist;
1314         int i;
1315
1316         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1317                 if (entry->offset == reg->offset &&
1318                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1319                         break;
1320         }
1321
1322         if (i == ARRAY_SIZE(whitelist))
1323                 return -EINVAL;
1324
1325         switch (entry->size) {
1326         case 8:
1327                 reg->val = I915_READ64(reg->offset);
1328                 break;
1329         case 4:
1330                 reg->val = I915_READ(reg->offset);
1331                 break;
1332         case 2:
1333                 reg->val = I915_READ16(reg->offset);
1334                 break;
1335         case 1:
1336                 reg->val = I915_READ8(reg->offset);
1337                 break;
1338         default:
1339                 WARN_ON(1);
1340                 return -EINVAL;
1341         }
1342
1343         return 0;
1344 }