drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 static struct drm_driver driver;
 122 extern int intel_agp_enabled;
 123
 124 #define INTEL_VGA_DEVICE(id, info) {            \
 125         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 126         .class_mask = 0xff0000,                 \
 127         .vendor = 0x8086,                       \
 128         .device = id,                           \
 129         .subvendor = PCI_ANY_ID,                \
 130         .subdevice = PCI_ANY_ID,                \
 131         .driver_data = (unsigned long) info }
 132
 133 static const struct intel_device_info intel_i830_info = {
 134         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136 };
 137
 138 static const struct intel_device_info intel_845g_info = {
 139         .gen = 2,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i85x_info = {
 144         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147 };
 148
 149 static const struct intel_device_info intel_i865g_info = {
 150         .gen = 2,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153
 154 static const struct intel_device_info intel_i915g_info = {
 155         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158 static const struct intel_device_info intel_i915gm_info = {
 159         .gen = 3, .is_mobile = 1,
 160         .cursor_needs_physical = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .supports_tv = 1,
 163 };
 164 static const struct intel_device_info intel_i945g_info = {
 165         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168 static const struct intel_device_info intel_i945gm_info = {
 169         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 170         .has_hotplug = 1, .cursor_needs_physical = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172         .supports_tv = 1,
 173 };
 174
 175 static const struct intel_device_info intel_i965g_info = {
 176         .gen = 4, .is_broadwater = 1,
 177         .has_hotplug = 1,
 178         .has_overlay = 1,
 179 };
 180
 181 static const struct intel_device_info intel_i965gm_info = {
 182         .gen = 4, .is_crestline = 1,
 183         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         .supports_tv = 1,
 186 };
 187
 188 static const struct intel_device_info intel_g33_info = {
 189         .gen = 3, .is_g33 = 1,
 190         .need_gfx_hws = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192 };
 193
 194 static const struct intel_device_info intel_g45_info = {
 195         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 196         .has_pipe_cxsr = 1, .has_hotplug = 1,
 197         .has_bsd_ring = 1,
 198 };
 199
 200 static const struct intel_device_info intel_gm45_info = {
 201         .gen = 4, .is_g4x = 1,
 202         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .supports_tv = 1,
 205         .has_bsd_ring = 1,
 206 };
 207
 208 static const struct intel_device_info intel_pineview_info = {
 209         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_ironlake_d_info = {
 215         .gen = 5,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218 };
 219
 220 static const struct intel_device_info intel_ironlake_m_info = {
 221         .gen = 5, .is_mobile = 1,
 222         .need_gfx_hws = 1, .has_hotplug = 1,
 223         .has_fbc = 1,
 224         .has_bsd_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_sandybridge_d_info = {
 228         .gen = 6,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_bsd_ring = 1,
 231         .has_blt_ring = 1,
 232         .has_llc = 1,
 233         .has_force_wake = 1,
 234 };
 235
 236 static const struct intel_device_info intel_sandybridge_m_info = {
 237         .gen = 6, .is_mobile = 1,
 238         .need_gfx_hws = 1, .has_hotplug = 1,
 239         .has_fbc = 1,
 240         .has_bsd_ring = 1,
 241         .has_blt_ring = 1,
 242         .has_llc = 1,
 243         .has_force_wake = 1,
 244 };
 245
 246 static const struct intel_device_info intel_ivybridge_d_info = {
 247         .is_ivybridge = 1, .gen = 7,
 248         .need_gfx_hws = 1, .has_hotplug = 1,
 249         .has_bsd_ring = 1,
 250         .has_blt_ring = 1,
 251         .has_llc = 1,
 252         .has_force_wake = 1,
 253 };
 254
 255 static const struct intel_device_info intel_ivybridge_m_info = {
 256         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 257         .need_gfx_hws = 1, .has_hotplug = 1,
 258         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 259         .has_bsd_ring = 1,
 260         .has_blt_ring = 1,
 261         .has_llc = 1,
 262         .has_force_wake = 1,
 263 };
 264
 265 static const struct intel_device_info intel_valleyview_m_info = {
 266         .gen = 7, .is_mobile = 1,
 267         .need_gfx_hws = 1, .has_hotplug = 1,
 268         .has_fbc = 0,
 269         .has_bsd_ring = 1,
 270         .has_blt_ring = 1,
 271         .is_valleyview = 1,
 272 };
 273
 274 static const struct intel_device_info intel_valleyview_d_info = {
 275         .gen = 7,
 276         .need_gfx_hws = 1, .has_hotplug = 1,
 277         .has_fbc = 0,
 278         .has_bsd_ring = 1,
 279         .has_blt_ring = 1,
 280         .is_valleyview = 1,
 281 };
 282
 283 static const struct intel_device_info intel_haswell_d_info = {
 284         .is_haswell = 1, .gen = 7,
 285         .need_gfx_hws = 1, .has_hotplug = 1,
 286         .has_bsd_ring = 1,
 287         .has_blt_ring = 1,
 288         .has_llc = 1,
 289         .has_force_wake = 1,
 290 };
 291
 292 static const struct intel_device_info intel_haswell_m_info = {
 293         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 294         .need_gfx_hws = 1, .has_hotplug = 1,
 295         .has_bsd_ring = 1,
 296         .has_blt_ring = 1,
 297         .has_llc = 1,
 298         .has_force_wake = 1,
 299 };
 300
 301 static const struct pci_device_id pciidlist[] = {               /* aka */
 302         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 303         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 304         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 305         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 306         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 307         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 308         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 309         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 310         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 311         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 312         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 313         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 314         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 315         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 316         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 317         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 318         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 319         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 320         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 321         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 322         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 323         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 324         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 325         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 326         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 327         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 328         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 329         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 330         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 331         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 332         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 333         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 334         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 335         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 337         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 338         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 340         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 341         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 342         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 343         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 344         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 345         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 346         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 347         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 348         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 349         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 350         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 351         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 352         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 353         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 354         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 355         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 356         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 357         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 358         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 359         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 360         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 361         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 362         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 363         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 364         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 365         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 366         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 367         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 368         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 369         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 370         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 371         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 372         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 373         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
 374         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 375         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
 376         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
 377         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 378         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
 379         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
 380         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 381         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 382         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 383         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 384         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 385         {0, 0, 0}
 386 };
 387
 388 #if defined(CONFIG_DRM_I915_KMS)
 389 MODULE_DEVICE_TABLE(pci, pciidlist);
 390 #endif
 391
 392 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 393 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 394 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 395 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 396 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 397
 398 void intel_detect_pch(struct drm_device *dev)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         struct pci_dev *pch;
 402
 403         /*
 404          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 405          * make graphics device passthrough work easy for VMM, that only
 406          * need to expose ISA bridge to let driver know the real hardware
 407          * underneath. This is a requirement from virtualization team.
 408          */
 409         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 410         if (pch) {
 411                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 412                         int id;
 413                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 414
 415                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 416                                 dev_priv->pch_type = PCH_IBX;
 417                                 dev_priv->num_pch_pll = 2;
 418                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 419                                 WARN_ON(!IS_GEN5(dev));
 420                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 421                                 dev_priv->pch_type = PCH_CPT;
 422                                 dev_priv->num_pch_pll = 2;
 423                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 424                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 425                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 426                                 /* PantherPoint is CPT compatible */
 427                                 dev_priv->pch_type = PCH_CPT;
 428                                 dev_priv->num_pch_pll = 2;
 429                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 430                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 431                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 432                                 dev_priv->pch_type = PCH_LPT;
 433                                 dev_priv->num_pch_pll = 0;
 434                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 435                                 WARN_ON(!IS_HASWELL(dev));
 436                         }
 437                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 438                 }
 439                 pci_dev_put(pch);
 440         }
 441 }
 442
 443 bool i915_semaphore_is_enabled(struct drm_device *dev)
 444 {
 445         if (INTEL_INFO(dev)->gen < 6)
 446                 return 0;
 447
 448         if (i915_semaphores >= 0)
 449                 return i915_semaphores;
 450
 451 #ifdef CONFIG_INTEL_IOMMU
 452         /* Enable semaphores on SNB when IO remapping is off */
 453         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 454                 return false;
 455 #endif
 456
 457         return 1;
 458 }
 459
 460 static int i915_drm_freeze(struct drm_device *dev)
 461 {
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463
 464         drm_kms_helper_poll_disable(dev);
 465
 466         pci_save_state(dev->pdev);
 467
 468         /* If KMS is active, we do the leavevt stuff here */
 469         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 470                 int error = i915_gem_idle(dev);
 471                 if (error) {
 472                         dev_err(&dev->pdev->dev,
 473                                 "GEM idle failed, resume might fail\n");
 474                         return error;
 475                 }
 476
 477                 intel_modeset_disable(dev);
 478
 479                 drm_irq_uninstall(dev);
 480         }
 481
 482         i915_save_state(dev);
 483
 484         intel_opregion_fini(dev);
 485
 486         /* Modeset on resume, not lid events */
 487         dev_priv->modeset_on_lid = 0;
 488
 489         console_lock();
 490         intel_fbdev_set_suspend(dev, 1);
 491         console_unlock();
 492
 493         return 0;
 494 }
 495
 496 int i915_suspend(struct drm_device *dev, pm_message_t state)
 497 {
 498         int error;
 499
 500         if (!dev || !dev->dev_private) {
 501                 DRM_ERROR("dev: %p\n", dev);
 502                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 503                 return -ENODEV;
 504         }
 505
 506         if (state.event == PM_EVENT_PRETHAW)
 507                 return 0;
 508
 509
 510         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 511                 return 0;
 512
 513         error = i915_drm_freeze(dev);
 514         if (error)
 515                 return error;
 516
 517         if (state.event == PM_EVENT_SUSPEND) {
 518                 /* Shut down the device */
 519                 pci_disable_device(dev->pdev);
 520                 pci_set_power_state(dev->pdev, PCI_D3hot);
 521         }
 522
 523         return 0;
 524 }
 525
 526 static int i915_drm_thaw(struct drm_device *dev)
 527 {
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         int error = 0;
 530
 531         intel_gt_reset(dev);
 532
 533         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 534                 mutex_lock(&dev->struct_mutex);
 535                 i915_gem_restore_gtt_mappings(dev);
 536                 mutex_unlock(&dev->struct_mutex);
 537         }
 538
 539         i915_restore_state(dev);
 540         intel_opregion_setup(dev);
 541
 542         /* KMS EnterVT equivalent */
 543         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 544                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 545                         ironlake_init_pch_refclk(dev);
 546
 547                 mutex_lock(&dev->struct_mutex);
 548                 dev_priv->mm.suspended = 0;
 549
 550                 error = i915_gem_init_hw(dev);
 551                 mutex_unlock(&dev->struct_mutex);
 552
 553                 intel_modeset_init_hw(dev);
 554                 intel_modeset_setup_hw_state(dev);
 555                 drm_irq_install(dev);
 556         }
 557
 558         intel_opregion_init(dev);
 559
 560         dev_priv->modeset_on_lid = 0;
 561
 562         console_lock();
 563         intel_fbdev_set_suspend(dev, 0);
 564         console_unlock();
 565         return error;
 566 }
 567
 568 int i915_resume(struct drm_device *dev)
 569 {
 570         int ret;
 571
 572         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 573                 return 0;
 574
 575         if (pci_enable_device(dev->pdev))
 576                 return -EIO;
 577
 578         pci_set_master(dev->pdev);
 579
 580         ret = i915_drm_thaw(dev);
 581         if (ret)
 582                 return ret;
 583
 584         drm_kms_helper_poll_enable(dev);
 585         return 0;
 586 }
 587
 588 static int i8xx_do_reset(struct drm_device *dev)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591
 592         if (IS_I85X(dev))
 593                 return -ENODEV;
 594
 595         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 596         POSTING_READ(D_STATE);
 597
 598         if (IS_I830(dev) || IS_845G(dev)) {
 599                 I915_WRITE(DEBUG_RESET_I830,
 600                            DEBUG_RESET_DISPLAY |
 601                            DEBUG_RESET_RENDER |
 602                            DEBUG_RESET_FULL);
 603                 POSTING_READ(DEBUG_RESET_I830);
 604                 msleep(1);
 605
 606                 I915_WRITE(DEBUG_RESET_I830, 0);
 607                 POSTING_READ(DEBUG_RESET_I830);
 608         }
 609
 610         msleep(1);
 611
 612         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 613         POSTING_READ(D_STATE);
 614
 615         return 0;
 616 }
 617
 618 static int i965_reset_complete(struct drm_device *dev)
 619 {
 620         u8 gdrst;
 621         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 622         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 623 }
 624
 625 static int i965_do_reset(struct drm_device *dev)
 626 {
 627         int ret;
 628         u8 gdrst;
 629
 630         /*
 631          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 632          * well as the reset bit (GR/bit 0).  Setting the GR bit
 633          * triggers the reset; when done, the hardware will clear it.
 634          */
 635         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 636         pci_write_config_byte(dev->pdev, I965_GDRST,
 637                               gdrst | GRDOM_RENDER |
 638                               GRDOM_RESET_ENABLE);
 639         ret =  wait_for(i965_reset_complete(dev), 500);
 640         if (ret)
 641                 return ret;
 642
 643         /* We can't reset render&media without also resetting display ... */
 644         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 645         pci_write_config_byte(dev->pdev, I965_GDRST,
 646                               gdrst | GRDOM_MEDIA |
 647                               GRDOM_RESET_ENABLE);
 648
 649         return wait_for(i965_reset_complete(dev), 500);
 650 }
 651
 652 static int ironlake_do_reset(struct drm_device *dev)
 653 {
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         u32 gdrst;
 656         int ret;
 657
 658         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 659         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 660                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 661         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 662         if (ret)
 663                 return ret;
 664
 665         /* We can't reset render&media without also resetting display ... */
 666         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 667         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 668                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 669         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 670 }
 671
 672 static int gen6_do_reset(struct drm_device *dev)
 673 {
 674         struct drm_i915_private *dev_priv = dev->dev_private;
 675         int     ret;
 676         unsigned long irqflags;
 677
 678         /* Hold gt_lock across reset to prevent any register access
 679          * with forcewake not set correctly
 680          */
 681         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 682
 683         /* Reset the chip */
 684
 685         /* GEN6_GDRST is not in the gt power well, no need to check
 686          * for fifo space for the write or forcewake the chip for
 687          * the read
 688          */
 689         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 690
 691         /* Spin waiting for the device to ack the reset request */
 692         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 693
 694         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 695         if (dev_priv->forcewake_count)
 696                 dev_priv->gt.force_wake_get(dev_priv);
 697         else
 698                 dev_priv->gt.force_wake_put(dev_priv);
 699
 700         /* Restore fifo count */
 701         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 702
 703         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 704         return ret;
 705 }
 706
 707 int intel_gpu_reset(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         int ret = -ENODEV;
 711
 712         switch (INTEL_INFO(dev)->gen) {
 713         case 7:
 714         case 6:
 715                 ret = gen6_do_reset(dev);
 716                 break;
 717         case 5:
 718                 ret = ironlake_do_reset(dev);
 719                 break;
 720         case 4:
 721                 ret = i965_do_reset(dev);
 722                 break;
 723         case 2:
 724                 ret = i8xx_do_reset(dev);
 725                 break;
 726         }
 727
 728         /* Also reset the gpu hangman. */
 729         if (dev_priv->stop_rings) {
 730                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 731                 dev_priv->stop_rings = 0;
 732                 if (ret == -ENODEV) {
 733                         DRM_ERROR("Reset not implemented, but ignoring "
 734                                   "error for simulated gpu hangs\n");
 735                         ret = 0;
 736                 }
 737         }
 738
 739         return ret;
 740 }
 741
 742 /**
 743  * i915_reset - reset chip after a hang
 744  * @dev: drm device to reset
 745  *
 746  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 747  * reset or otherwise an error code.
 748  *
 749  * Procedure is fairly simple:
 750  *   - reset the chip using the reset reg
 751  *   - re-init context state
 752  *   - re-init hardware status page
 753  *   - re-init ring buffer
 754  *   - re-init interrupt state
 755  *   - re-init display
 756  */
 757 int i915_reset(struct drm_device *dev)
 758 {
 759         drm_i915_private_t *dev_priv = dev->dev_private;
 760         int ret;
 761
 762         if (!i915_try_reset)
 763                 return 0;
 764
 765         mutex_lock(&dev->struct_mutex);
 766
 767         i915_gem_reset(dev);
 768
 769         ret = -ENODEV;
 770         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 771                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 772         else
 773                 ret = intel_gpu_reset(dev);
 774
 775         dev_priv->last_gpu_reset = get_seconds();
 776         if (ret) {
 777                 DRM_ERROR("Failed to reset chip.\n");
 778                 mutex_unlock(&dev->struct_mutex);
 779                 return ret;
 780         }
 781
 782         /* Ok, now get things going again... */
 783
 784         /*
 785          * Everything depends on having the GTT running, so we need to start
 786          * there.  Fortunately we don't need to do this unless we reset the
 787          * chip at a PCI level.
 788          *
 789          * Next we need to restore the context, but we don't use those
 790          * yet either...
 791          *
 792          * Ring buffer needs to be re-initialized in the KMS case, or if X
 793          * was running at the time of the reset (i.e. we weren't VT
 794          * switched away).
 795          */
 796         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 797                         !dev_priv->mm.suspended) {
 798                 struct intel_ring_buffer *ring;
 799                 int i;
 800
 801                 dev_priv->mm.suspended = 0;
 802
 803                 i915_gem_init_swizzling(dev);
 804
 805                 for_each_ring(ring, dev_priv, i)
 806                         ring->init(ring);
 807
 808                 i915_gem_context_init(dev);
 809                 i915_gem_init_ppgtt(dev);
 810
 811                 /*
 812                  * It would make sense to re-init all the other hw state, at
 813                  * least the rps/rc6/emon init done within modeset_init_hw. For
 814                  * some unknown reason, this blows up my ilk, so don't.
 815                  */
 816
 817                 mutex_unlock(&dev->struct_mutex);
 818
 819                 drm_irq_uninstall(dev);
 820                 drm_irq_install(dev);
 821         } else {
 822                 mutex_unlock(&dev->struct_mutex);
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int __devinit
 829 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 830 {
 831         struct intel_device_info *intel_info =
 832                 (struct intel_device_info *) ent->driver_data;
 833
 834         /* Only bind to function 0 of the device. Early generations
 835          * used function 1 as a placeholder for multi-head. This causes
 836          * us confusion instead, especially on the systems where both
 837          * functions have the same PCI-ID!
 838          */
 839         if (PCI_FUNC(pdev->devfn))
 840                 return -ENODEV;
 841
 842         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 843          * implementation for gen3 (and only gen3) that used legacy drm maps
 844          * (gasp!) to share buffers between X and the client. Hence we need to
 845          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 846         if (intel_info->gen != 3) {
 847                 driver.driver_features &=
 848                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 849         } else if (!intel_agp_enabled) {
 850                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 851                 return -ENODEV;
 852         }
 853
 854         return drm_get_pci_dev(pdev, ent, &driver);
 855 }
 856
 857 static void
 858 i915_pci_remove(struct pci_dev *pdev)
 859 {
 860         struct drm_device *dev = pci_get_drvdata(pdev);
 861
 862         drm_put_dev(dev);
 863 }
 864
 865 static int i915_pm_suspend(struct device *dev)
 866 {
 867         struct pci_dev *pdev = to_pci_dev(dev);
 868         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 869         int error;
 870
 871         if (!drm_dev || !drm_dev->dev_private) {
 872                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 873                 return -ENODEV;
 874         }
 875
 876         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 877                 return 0;
 878
 879         error = i915_drm_freeze(drm_dev);
 880         if (error)
 881                 return error;
 882
 883         pci_disable_device(pdev);
 884         pci_set_power_state(pdev, PCI_D3hot);
 885
 886         return 0;
 887 }
 888
 889 static int i915_pm_resume(struct device *dev)
 890 {
 891         struct pci_dev *pdev = to_pci_dev(dev);
 892         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 893
 894         return i915_resume(drm_dev);
 895 }
 896
 897 static int i915_pm_freeze(struct device *dev)
 898 {
 899         struct pci_dev *pdev = to_pci_dev(dev);
 900         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 901
 902         if (!drm_dev || !drm_dev->dev_private) {
 903                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 904                 return -ENODEV;
 905         }
 906
 907         return i915_drm_freeze(drm_dev);
 908 }
 909
 910 static int i915_pm_thaw(struct device *dev)
 911 {
 912         struct pci_dev *pdev = to_pci_dev(dev);
 913         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 914
 915         return i915_drm_thaw(drm_dev);
 916 }
 917
 918 static int i915_pm_poweroff(struct device *dev)
 919 {
 920         struct pci_dev *pdev = to_pci_dev(dev);
 921         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 922
 923         return i915_drm_freeze(drm_dev);
 924 }
 925
 926 static const struct dev_pm_ops i915_pm_ops = {
 927         .suspend = i915_pm_suspend,
 928         .resume = i915_pm_resume,
 929         .freeze = i915_pm_freeze,
 930         .thaw = i915_pm_thaw,
 931         .poweroff = i915_pm_poweroff,
 932         .restore = i915_pm_resume,
 933 };
 934
 935 static const struct vm_operations_struct i915_gem_vm_ops = {
 936         .fault = i915_gem_fault,
 937         .open = drm_gem_vm_open,
 938         .close = drm_gem_vm_close,
 939 };
 940
 941 static const struct file_operations i915_driver_fops = {
 942         .owner = THIS_MODULE,
 943         .open = drm_open,
 944         .release = drm_release,
 945         .unlocked_ioctl = drm_ioctl,
 946         .mmap = drm_gem_mmap,
 947         .poll = drm_poll,
 948         .fasync = drm_fasync,
 949         .read = drm_read,
 950 #ifdef CONFIG_COMPAT
 951         .compat_ioctl = i915_compat_ioctl,
 952 #endif
 953         .llseek = noop_llseek,
 954 };
 955
 956 static struct drm_driver driver = {
 957         /* Don't use MTRRs here; the Xserver or userspace app should
 958          * deal with them for Intel hardware.
 959          */
 960         .driver_features =
 961             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 962             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
 963         .load = i915_driver_load,
 964         .unload = i915_driver_unload,
 965         .open = i915_driver_open,
 966         .lastclose = i915_driver_lastclose,
 967         .preclose = i915_driver_preclose,
 968         .postclose = i915_driver_postclose,
 969
 970         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 971         .suspend = i915_suspend,
 972         .resume = i915_resume,
 973
 974         .device_is_agp = i915_driver_device_is_agp,
 975         .master_create = i915_master_create,
 976         .master_destroy = i915_master_destroy,
 977 #if defined(CONFIG_DEBUG_FS)
 978         .debugfs_init = i915_debugfs_init,
 979         .debugfs_cleanup = i915_debugfs_cleanup,
 980 #endif
 981         .gem_init_object = i915_gem_init_object,
 982         .gem_free_object = i915_gem_free_object,
 983         .gem_vm_ops = &i915_gem_vm_ops,
 984
 985         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 986         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 987         .gem_prime_export = i915_gem_prime_export,
 988         .gem_prime_import = i915_gem_prime_import,
 989
 990         .dumb_create = i915_gem_dumb_create,
 991         .dumb_map_offset = i915_gem_mmap_gtt,
 992         .dumb_destroy = i915_gem_dumb_destroy,
 993         .ioctls = i915_ioctls,
 994         .fops = &i915_driver_fops,
 995         .name = DRIVER_NAME,
 996         .desc = DRIVER_DESC,
 997         .date = DRIVER_DATE,
 998         .major = DRIVER_MAJOR,
 999         .minor = DRIVER_MINOR,
1000         .patchlevel = DRIVER_PATCHLEVEL,
1001 };
1002
1003 static struct pci_driver i915_pci_driver = {
1004         .name = DRIVER_NAME,
1005         .id_table = pciidlist,
1006         .probe = i915_pci_probe,
1007         .remove = i915_pci_remove,
1008         .driver.pm = &i915_pm_ops,
1009 };
1010
1011 static int __init i915_init(void)
1012 {
1013         driver.num_ioctls = i915_max_ioctl;
1014
1015         /*
1016          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1017          * explicitly disabled with the module pararmeter.
1018          *
1019          * Otherwise, just follow the parameter (defaulting to off).
1020          *
1021          * Allow optional vga_text_mode_force boot option to override
1022          * the default behavior.
1023          */
1024 #if defined(CONFIG_DRM_I915_KMS)
1025         if (i915_modeset != 0)
1026                 driver.driver_features |= DRIVER_MODESET;
1027 #endif
1028         if (i915_modeset == 1)
1029                 driver.driver_features |= DRIVER_MODESET;
1030
1031 #ifdef CONFIG_VGA_CONSOLE
1032         if (vgacon_text_force() && i915_modeset == -1)
1033                 driver.driver_features &= ~DRIVER_MODESET;
1034 #endif
1035
1036         if (!(driver.driver_features & DRIVER_MODESET))
1037                 driver.get_vblank_timestamp = NULL;
1038
1039         return drm_pci_init(&driver, &i915_pci_driver);
1040 }
1041
1042 static void __exit i915_exit(void)
1043 {
1044         drm_pci_exit(&driver, &i915_pci_driver);
1045 }
1046
1047 module_init(i915_init);
1048 module_exit(i915_exit);
1049
1050 MODULE_AUTHOR(DRIVER_AUTHOR);
1051 MODULE_DESCRIPTION(DRIVER_DESC);
1052 MODULE_LICENSE("GPL and additional rights");
1053
1054 /* We give fast paths for the really cool registers */
1055 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1056         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1057          ((reg) < 0x40000) &&            \
1058          ((reg) != FORCEWAKE))
1059
1060 static bool IS_DISPLAYREG(u32 reg)
1061 {
1062         /*
1063          * This should make it easier to transition modules over to the
1064          * new register block scheme, since we can do it incrementally.
1065          */
1066         if (reg >= VLV_DISPLAY_BASE)
1067                 return false;
1068
1069         if (reg >= RENDER_RING_BASE &&
1070             reg < RENDER_RING_BASE + 0xff)
1071                 return false;
1072         if (reg >= GEN6_BSD_RING_BASE &&
1073             reg < GEN6_BSD_RING_BASE + 0xff)
1074                 return false;
1075         if (reg >= BLT_RING_BASE &&
1076             reg < BLT_RING_BASE + 0xff)
1077                 return false;
1078
1079         if (reg == PGTBL_ER)
1080                 return false;
1081
1082         if (reg >= IPEIR_I965 &&
1083             reg < HWSTAM)
1084                 return false;
1085
1086         if (reg == MI_MODE)
1087                 return false;
1088
1089         if (reg == GFX_MODE_GEN7)
1090                 return false;
1091
1092         if (reg == RENDER_HWS_PGA_GEN7 ||
1093             reg == BSD_HWS_PGA_GEN7 ||
1094             reg == BLT_HWS_PGA_GEN7)
1095                 return false;
1096
1097         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1098             reg == GEN6_BSD_RNCID)
1099                 return false;
1100
1101         if (reg == GEN6_BLITTER_ECOSKPD)
1102                 return false;
1103
1104         if (reg >= 0x4000c &&
1105             reg <= 0x4002c)
1106                 return false;
1107
1108         if (reg >= 0x4f000 &&
1109             reg <= 0x4f08f)
1110                 return false;
1111
1112         if (reg >= 0x4f100 &&
1113             reg <= 0x4f11f)
1114                 return false;
1115
1116         if (reg >= VLV_MASTER_IER &&
1117             reg <= GEN6_PMIER)
1118                 return false;
1119
1120         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1121             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1122                 return false;
1123
1124         if (reg >= VLV_IIR_RW &&
1125             reg <= VLV_ISR)
1126                 return false;
1127
1128         if (reg == FORCEWAKE_VLV ||
1129             reg == FORCEWAKE_ACK_VLV)
1130                 return false;
1131
1132         if (reg == GEN6_GDRST)
1133                 return false;
1134
1135         switch (reg) {
1136         case _3D_CHICKEN3:
1137         case IVB_CHICKEN3:
1138         case GEN7_COMMON_SLICE_CHICKEN1:
1139         case GEN7_L3CNTLREG1:
1140         case GEN7_L3_CHICKEN_MODE_REGISTER:
1141         case GEN7_ROW_CHICKEN2:
1142         case GEN7_L3SQCREG4:
1143         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
1144         case GEN7_HALF_SLICE_CHICKEN1:
1145         case GEN6_MBCTL:
1146         case GEN6_UCGCTL2:
1147                 return false;
1148         default:
1149                 break;
1150         }
1151
1152         return true;
1153 }
1154
1155 static void
1156 ilk_dummy_write(struct drm_i915_private *dev_priv)
1157 {
1158         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1159          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1160          * harmless to write 0 into. */
1161         I915_WRITE_NOTRACE(MI_MODE, 0);
1162 }
1163
1164 #define __i915_read(x, y) \
1165 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1166         u##x val = 0; \
1167         if (IS_GEN5(dev_priv->dev)) \
1168                 ilk_dummy_write(dev_priv); \
1169         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1170                 unsigned long irqflags; \
1171                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1172                 if (dev_priv->forcewake_count == 0) \
1173                         dev_priv->gt.force_wake_get(dev_priv); \
1174                 val = read##y(dev_priv->regs + reg); \
1175                 if (dev_priv->forcewake_count == 0) \
1176                         dev_priv->gt.force_wake_put(dev_priv); \
1177                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1178         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1179                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1180         } else { \
1181                 val = read##y(dev_priv->regs + reg); \
1182         } \
1183         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1184         return val; \
1185 }
1186
1187 __i915_read(8, b)
1188 __i915_read(16, w)
1189 __i915_read(32, l)
1190 __i915_read(64, q)
1191 #undef __i915_read
1192
1193 #define __i915_write(x, y) \
1194 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1195         u32 __fifo_ret = 0; \
1196         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1197         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1198                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1199         } \
1200         if (IS_GEN5(dev_priv->dev)) \
1201                 ilk_dummy_write(dev_priv); \
1202         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1203                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1204         } else {                                                        \
1205                 write##y(val, dev_priv->regs + reg);                    \
1206         }                                                               \
1207         if (unlikely(__fifo_ret)) { \
1208                 gen6_gt_check_fifodbg(dev_priv); \
1209         } \
1210         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1211                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1212                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
1213         } \
1214 }
1215 __i915_write(8, b)
1216 __i915_write(16, w)
1217 __i915_write(32, l)
1218 __i915_write(64, q)
1219 #undef __i915_write
1220
1221 static const struct register_whitelist {
1222         uint64_t offset;
1223         uint32_t size;
1224         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1225 } whitelist[] = {
1226         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1227 };
1228
1229 int i915_reg_read_ioctl(struct drm_device *dev,
1230                         void *data, struct drm_file *file)
1231 {
1232         struct drm_i915_private *dev_priv = dev->dev_private;
1233         struct drm_i915_reg_read *reg = data;
1234         struct register_whitelist const *entry = whitelist;
1235         int i;
1236
1237         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1238                 if (entry->offset == reg->offset &&
1239                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1240                         break;
1241         }
1242
1243         if (i == ARRAY_SIZE(whitelist))
1244                 return -EINVAL;
1245
1246         switch (entry->size) {
1247         case 8:
1248                 reg->val = I915_READ64(reg->offset);
1249                 break;
1250         case 4:
1251                 reg->val = I915_READ(reg->offset);
1252                 break;
1253         case 2:
1254                 reg->val = I915_READ16(reg->offset);
1255                 break;
1256         case 1:
1257                 reg->val = I915_READ8(reg->offset);
1258                 break;
1259         default:
1260                 WARN_ON(1);
1261                 return -EINVAL;
1262         }
1263
1264         return 0;
1265 }