drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158 extern int intel_agp_enabled;
 159
 160 static const struct intel_device_info intel_i830_info = {
 161         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163         .ring_mask = RENDER_RING,
 164 };
 165
 166 static const struct intel_device_info intel_845g_info = {
 167         .gen = 2, .num_pipes = 1,
 168         .has_overlay = 1, .overlay_needs_physical = 1,
 169         .ring_mask = RENDER_RING,
 170 };
 171
 172 static const struct intel_device_info intel_i85x_info = {
 173         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 174         .cursor_needs_physical = 1,
 175         .has_overlay = 1, .overlay_needs_physical = 1,
 176         .ring_mask = RENDER_RING,
 177 };
 178
 179 static const struct intel_device_info intel_i865g_info = {
 180         .gen = 2, .num_pipes = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .ring_mask = RENDER_RING,
 183 };
 184
 185 static const struct intel_device_info intel_i915g_info = {
 186         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 187         .has_overlay = 1, .overlay_needs_physical = 1,
 188         .ring_mask = RENDER_RING,
 189 };
 190 static const struct intel_device_info intel_i915gm_info = {
 191         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 192         .cursor_needs_physical = 1,
 193         .has_overlay = 1, .overlay_needs_physical = 1,
 194         .supports_tv = 1,
 195         .ring_mask = RENDER_RING,
 196 };
 197 static const struct intel_device_info intel_i945g_info = {
 198         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 199         .has_overlay = 1, .overlay_needs_physical = 1,
 200         .ring_mask = RENDER_RING,
 201 };
 202 static const struct intel_device_info intel_i945gm_info = {
 203         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 204         .has_hotplug = 1, .cursor_needs_physical = 1,
 205         .has_overlay = 1, .overlay_needs_physical = 1,
 206         .supports_tv = 1,
 207         .ring_mask = RENDER_RING,
 208 };
 209
 210 static const struct intel_device_info intel_i965g_info = {
 211         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 212         .has_hotplug = 1,
 213         .has_overlay = 1,
 214         .ring_mask = RENDER_RING,
 215 };
 216
 217 static const struct intel_device_info intel_i965gm_info = {
 218         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 219         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 220         .has_overlay = 1,
 221         .supports_tv = 1,
 222         .ring_mask = RENDER_RING,
 223 };
 224
 225 static const struct intel_device_info intel_g33_info = {
 226         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_overlay = 1,
 229         .ring_mask = RENDER_RING,
 230 };
 231
 232 static const struct intel_device_info intel_g45_info = {
 233         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 234         .has_pipe_cxsr = 1, .has_hotplug = 1,
 235         .ring_mask = RENDER_RING | BSD_RING,
 236 };
 237
 238 static const struct intel_device_info intel_gm45_info = {
 239         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 240         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 241         .has_pipe_cxsr = 1, .has_hotplug = 1,
 242         .supports_tv = 1,
 243         .ring_mask = RENDER_RING | BSD_RING,
 244 };
 245
 246 static const struct intel_device_info intel_pineview_info = {
 247         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 248         .need_gfx_hws = 1, .has_hotplug = 1,
 249         .has_overlay = 1,
 250 };
 251
 252 static const struct intel_device_info intel_ironlake_d_info = {
 253         .gen = 5, .num_pipes = 2,
 254         .need_gfx_hws = 1, .has_hotplug = 1,
 255         .ring_mask = RENDER_RING | BSD_RING,
 256 };
 257
 258 static const struct intel_device_info intel_ironlake_m_info = {
 259         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 260         .need_gfx_hws = 1, .has_hotplug = 1,
 261         .has_fbc = 1,
 262         .ring_mask = RENDER_RING | BSD_RING,
 263 };
 264
 265 static const struct intel_device_info intel_sandybridge_d_info = {
 266         .gen = 6, .num_pipes = 2,
 267         .need_gfx_hws = 1, .has_hotplug = 1,
 268         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 269         .has_llc = 1,
 270 };
 271
 272 static const struct intel_device_info intel_sandybridge_m_info = {
 273         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 1,
 276         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 277         .has_llc = 1,
 278 };
 279
 280 #define GEN7_FEATURES  \
 281         .gen = 7, .num_pipes = 3, \
 282         .need_gfx_hws = 1, .has_hotplug = 1, \
 283         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 284         .has_llc = 1
 285
 286 static const struct intel_device_info intel_ivybridge_d_info = {
 287         GEN7_FEATURES,
 288         .is_ivybridge = 1,
 289 };
 290
 291 static const struct intel_device_info intel_ivybridge_m_info = {
 292         GEN7_FEATURES,
 293         .is_ivybridge = 1,
 294         .is_mobile = 1,
 295         .has_fbc = 1,
 296 };
 297
 298 static const struct intel_device_info intel_ivybridge_q_info = {
 299         GEN7_FEATURES,
 300         .is_ivybridge = 1,
 301         .num_pipes = 0, /* legal, last one wins */
 302 };
 303
 304 static const struct intel_device_info intel_valleyview_m_info = {
 305         GEN7_FEATURES,
 306         .is_mobile = 1,
 307         .num_pipes = 2,
 308         .is_valleyview = 1,
 309         .display_mmio_offset = VLV_DISPLAY_BASE,
 310         .has_llc = 0, /* legal, last one wins */
 311 };
 312
 313 static const struct intel_device_info intel_valleyview_d_info = {
 314         GEN7_FEATURES,
 315         .num_pipes = 2,
 316         .is_valleyview = 1,
 317         .display_mmio_offset = VLV_DISPLAY_BASE,
 318         .has_llc = 0, /* legal, last one wins */
 319 };
 320
 321 static const struct intel_device_info intel_haswell_d_info = {
 322         GEN7_FEATURES,
 323         .is_haswell = 1,
 324         .has_ddi = 1,
 325         .has_fpga_dbg = 1,
 326         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 327 };
 328
 329 static const struct intel_device_info intel_haswell_m_info = {
 330         GEN7_FEATURES,
 331         .is_haswell = 1,
 332         .is_mobile = 1,
 333         .has_ddi = 1,
 334         .has_fpga_dbg = 1,
 335         .has_fbc = 1,
 336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 337 };
 338
 339 static const struct intel_device_info intel_broadwell_d_info = {
 340         .is_preliminary = 1,
 341         .gen = 8,
 342         .need_gfx_hws = 1, .has_hotplug = 1,
 343         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 344         .has_llc = 1,
 345         .has_ddi = 1,
 346 };
 347
 348 static const struct intel_device_info intel_broadwell_m_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .is_mobile = 1,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .has_llc = 1,
 354         .has_ddi = 1,
 355 };
 356
 357 /*
 358  * Make sure any device matches here are from most specific to most
 359  * general.  For example, since the Quanta match is based on the subsystem
 360  * and subvendor IDs, we need it to come before the more general IVB
 361  * PCI ID matches, otherwise we'll use the wrong info struct above.
 362  */
 363 #define INTEL_PCI_IDS \
 364         INTEL_I830_IDS(&intel_i830_info),       \
 365         INTEL_I845G_IDS(&intel_845g_info),      \
 366         INTEL_I85X_IDS(&intel_i85x_info),       \
 367         INTEL_I865G_IDS(&intel_i865g_info),     \
 368         INTEL_I915G_IDS(&intel_i915g_info),     \
 369         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 370         INTEL_I945G_IDS(&intel_i945g_info),     \
 371         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 372         INTEL_I965G_IDS(&intel_i965g_info),     \
 373         INTEL_G33_IDS(&intel_g33_info),         \
 374         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 375         INTEL_GM45_IDS(&intel_gm45_info),       \
 376         INTEL_G45_IDS(&intel_g45_info),         \
 377         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 378         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 379         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 380         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 381         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 382         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 383         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 384         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 385         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 386         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 387         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 388         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 389         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 390         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 391
 392 static const struct pci_device_id pciidlist[] = {               /* aka */
 393         INTEL_PCI_IDS,
 394         {0, 0, 0}
 395 };
 396
 397 #if defined(CONFIG_DRM_I915_KMS)
 398 MODULE_DEVICE_TABLE(pci, pciidlist);
 399 #endif
 400
 401 void intel_detect_pch(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct pci_dev *pch;
 405
 406         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 407          * (which really amounts to a PCH but no South Display).
 408          */
 409         if (INTEL_INFO(dev)->num_pipes == 0) {
 410                 dev_priv->pch_type = PCH_NOP;
 411                 return;
 412         }
 413
 414         /*
 415          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 416          * make graphics device passthrough work easy for VMM, that only
 417          * need to expose ISA bridge to let driver know the real hardware
 418          * underneath. This is a requirement from virtualization team.
 419          *
 420          * In some virtualized environments (e.g. XEN), there is irrelevant
 421          * ISA bridge in the system. To work reliably, we should scan trhough
 422          * all the ISA bridge devices and check for the first match, instead
 423          * of only checking the first one.
 424          */
 425         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 426         while (pch) {
 427                 struct pci_dev *curr = pch;
 428                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 429                         unsigned short id;
 430                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 431                         dev_priv->pch_id = id;
 432
 433                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 434                                 dev_priv->pch_type = PCH_IBX;
 435                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 436                                 WARN_ON(!IS_GEN5(dev));
 437                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 438                                 dev_priv->pch_type = PCH_CPT;
 439                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 440                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 441                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 442                                 /* PantherPoint is CPT compatible */
 443                                 dev_priv->pch_type = PCH_CPT;
 444                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 445                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 446                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 447                                 dev_priv->pch_type = PCH_LPT;
 448                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 449                                 WARN_ON(!IS_HASWELL(dev));
 450                                 WARN_ON(IS_ULT(dev));
 451                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 452                                 dev_priv->pch_type = PCH_LPT;
 453                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 454                                 WARN_ON(!IS_HASWELL(dev));
 455                                 WARN_ON(!IS_ULT(dev));
 456                         } else {
 457                                 goto check_next;
 458                         }
 459                         pci_dev_put(pch);
 460                         break;
 461                 }
 462 check_next:
 463                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 464                 pci_dev_put(curr);
 465         }
 466         if (!pch)
 467                 DRM_DEBUG_KMS("No PCH found?\n");
 468 }
 469
 470 bool i915_semaphore_is_enabled(struct drm_device *dev)
 471 {
 472         if (INTEL_INFO(dev)->gen < 6)
 473                 return 0;
 474
 475         if (i915_semaphores >= 0)
 476                 return i915_semaphores;
 477
 478 #ifdef CONFIG_INTEL_IOMMU
 479         /* Enable semaphores on SNB when IO remapping is off */
 480         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 481                 return false;
 482 #endif
 483
 484         return 1;
 485 }
 486
 487 static int i915_drm_freeze(struct drm_device *dev)
 488 {
 489         struct drm_i915_private *dev_priv = dev->dev_private;
 490         struct drm_crtc *crtc;
 491
 492         /* ignore lid events during suspend */
 493         mutex_lock(&dev_priv->modeset_restore_lock);
 494         dev_priv->modeset_restore = MODESET_SUSPENDED;
 495         mutex_unlock(&dev_priv->modeset_restore_lock);
 496
 497         /* We do a lot of poking in a lot of registers, make sure they work
 498          * properly. */
 499         hsw_disable_package_c8(dev_priv);
 500         intel_display_set_init_power(dev, true);
 501
 502         drm_kms_helper_poll_disable(dev);
 503
 504         pci_save_state(dev->pdev);
 505
 506         /* If KMS is active, we do the leavevt stuff here */
 507         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 508                 int error;
 509
 510                 error = i915_gem_suspend(dev);
 511                 if (error) {
 512                         dev_err(&dev->pdev->dev,
 513                                 "GEM idle failed, resume might fail\n");
 514                         return error;
 515                 }
 516
 517                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 518
 519                 drm_irq_uninstall(dev);
 520                 dev_priv->enable_hotplug_processing = false;
 521                 /*
 522                  * Disable CRTCs directly since we want to preserve sw state
 523                  * for _thaw.
 524                  */
 525                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 526                         dev_priv->display.crtc_disable(crtc);
 527
 528                 intel_modeset_suspend_hw(dev);
 529         }
 530
 531         i915_gem_suspend_gtt_mappings(dev);
 532
 533         i915_save_state(dev);
 534
 535         intel_opregion_fini(dev);
 536
 537         console_lock();
 538         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 539         console_unlock();
 540
 541         return 0;
 542 }
 543
 544 int i915_suspend(struct drm_device *dev, pm_message_t state)
 545 {
 546         int error;
 547
 548         if (!dev || !dev->dev_private) {
 549                 DRM_ERROR("dev: %p\n", dev);
 550                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 551                 return -ENODEV;
 552         }
 553
 554         if (state.event == PM_EVENT_PRETHAW)
 555                 return 0;
 556
 557
 558         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 559                 return 0;
 560
 561         error = i915_drm_freeze(dev);
 562         if (error)
 563                 return error;
 564
 565         if (state.event == PM_EVENT_SUSPEND) {
 566                 /* Shut down the device */
 567                 pci_disable_device(dev->pdev);
 568                 pci_set_power_state(dev->pdev, PCI_D3hot);
 569         }
 570
 571         return 0;
 572 }
 573
 574 void intel_console_resume(struct work_struct *work)
 575 {
 576         struct drm_i915_private *dev_priv =
 577                 container_of(work, struct drm_i915_private,
 578                              console_resume_work);
 579         struct drm_device *dev = dev_priv->dev;
 580
 581         console_lock();
 582         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 583         console_unlock();
 584 }
 585
 586 static void intel_resume_hotplug(struct drm_device *dev)
 587 {
 588         struct drm_mode_config *mode_config = &dev->mode_config;
 589         struct intel_encoder *encoder;
 590
 591         mutex_lock(&mode_config->mutex);
 592         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 593
 594         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 595                 if (encoder->hot_plug)
 596                         encoder->hot_plug(encoder);
 597
 598         mutex_unlock(&mode_config->mutex);
 599
 600         /* Just fire off a uevent and let userspace tell us what to do */
 601         drm_helper_hpd_irq_event(dev);
 602 }
 603
 604 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 605 {
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         int error = 0;
 608
 609         intel_uncore_early_sanitize(dev);
 610
 611         intel_uncore_sanitize(dev);
 612
 613         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 614             restore_gtt_mappings) {
 615                 mutex_lock(&dev->struct_mutex);
 616                 i915_gem_restore_gtt_mappings(dev);
 617                 mutex_unlock(&dev->struct_mutex);
 618         }
 619
 620         intel_power_domains_init_hw(dev);
 621
 622         i915_restore_state(dev);
 623         intel_opregion_setup(dev);
 624
 625         /* KMS EnterVT equivalent */
 626         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 627                 intel_init_pch_refclk(dev);
 628
 629                 mutex_lock(&dev->struct_mutex);
 630
 631                 error = i915_gem_init_hw(dev);
 632                 mutex_unlock(&dev->struct_mutex);
 633
 634                 /* We need working interrupts for modeset enabling ... */
 635                 drm_irq_install(dev);
 636
 637                 intel_modeset_init_hw(dev);
 638
 639                 drm_modeset_lock_all(dev);
 640                 intel_modeset_setup_hw_state(dev, true);
 641                 drm_modeset_unlock_all(dev);
 642
 643                 /*
 644                  * ... but also need to make sure that hotplug processing
 645                  * doesn't cause havoc. Like in the driver load code we don't
 646                  * bother with the tiny race here where we might loose hotplug
 647                  * notifications.
 648                  * */
 649                 intel_hpd_init(dev);
 650                 dev_priv->enable_hotplug_processing = true;
 651                 /* Config may have changed between suspend and resume */
 652                 intel_resume_hotplug(dev);
 653         }
 654
 655         intel_opregion_init(dev);
 656
 657         /*
 658          * The console lock can be pretty contented on resume due
 659          * to all the printk activity.  Try to keep it out of the hot
 660          * path of resume if possible.
 661          */
 662         if (console_trylock()) {
 663                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 664                 console_unlock();
 665         } else {
 666                 schedule_work(&dev_priv->console_resume_work);
 667         }
 668
 669         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 670          * expected level. */
 671         hsw_enable_package_c8(dev_priv);
 672
 673         mutex_lock(&dev_priv->modeset_restore_lock);
 674         dev_priv->modeset_restore = MODESET_DONE;
 675         mutex_unlock(&dev_priv->modeset_restore_lock);
 676         return error;
 677 }
 678
 679 static int i915_drm_thaw(struct drm_device *dev)
 680 {
 681         if (drm_core_check_feature(dev, DRIVER_MODESET))
 682                 i915_check_and_clear_faults(dev);
 683
 684         return __i915_drm_thaw(dev, true);
 685 }
 686
 687 int i915_resume(struct drm_device *dev)
 688 {
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         int ret;
 691
 692         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 693                 return 0;
 694
 695         if (pci_enable_device(dev->pdev))
 696                 return -EIO;
 697
 698         pci_set_master(dev->pdev);
 699
 700         /*
 701          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 702          * earlier) need to restore the GTT mappings since the BIOS might clear
 703          * all our scratch PTEs.
 704          */
 705         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 706         if (ret)
 707                 return ret;
 708
 709         drm_kms_helper_poll_enable(dev);
 710         return 0;
 711 }
 712
 713 /**
 714  * i915_reset - reset chip after a hang
 715  * @dev: drm device to reset
 716  *
 717  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 718  * reset or otherwise an error code.
 719  *
 720  * Procedure is fairly simple:
 721  *   - reset the chip using the reset reg
 722  *   - re-init context state
 723  *   - re-init hardware status page
 724  *   - re-init ring buffer
 725  *   - re-init interrupt state
 726  *   - re-init display
 727  */
 728 int i915_reset(struct drm_device *dev)
 729 {
 730         drm_i915_private_t *dev_priv = dev->dev_private;
 731         bool simulated;
 732         int ret;
 733
 734         if (!i915_try_reset)
 735                 return 0;
 736
 737         mutex_lock(&dev->struct_mutex);
 738
 739         i915_gem_reset(dev);
 740
 741         simulated = dev_priv->gpu_error.stop_rings != 0;
 742
 743         ret = intel_gpu_reset(dev);
 744
 745         /* Also reset the gpu hangman. */
 746         if (simulated) {
 747                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 748                 dev_priv->gpu_error.stop_rings = 0;
 749                 if (ret == -ENODEV) {
 750                         DRM_ERROR("Reset not implemented, but ignoring "
 751                                   "error for simulated gpu hangs\n");
 752                         ret = 0;
 753                 }
 754         }
 755
 756         if (ret) {
 757                 DRM_ERROR("Failed to reset chip.\n");
 758                 mutex_unlock(&dev->struct_mutex);
 759                 return ret;
 760         }
 761
 762         /* Ok, now get things going again... */
 763
 764         /*
 765          * Everything depends on having the GTT running, so we need to start
 766          * there.  Fortunately we don't need to do this unless we reset the
 767          * chip at a PCI level.
 768          *
 769          * Next we need to restore the context, but we don't use those
 770          * yet either...
 771          *
 772          * Ring buffer needs to be re-initialized in the KMS case, or if X
 773          * was running at the time of the reset (i.e. we weren't VT
 774          * switched away).
 775          */
 776         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 777                         !dev_priv->ums.mm_suspended) {
 778                 bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
 779                 dev_priv->ums.mm_suspended = 0;
 780
 781                 ret = i915_gem_init_hw(dev);
 782                 if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
 783                         DRM_ERROR("HW contexts didn't survive reset\n");
 784                 mutex_unlock(&dev->struct_mutex);
 785                 if (ret) {
 786                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 787                         return ret;
 788                 }
 789
 790                 drm_irq_uninstall(dev);
 791                 drm_irq_install(dev);
 792                 intel_hpd_init(dev);
 793         } else {
 794                 mutex_unlock(&dev->struct_mutex);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 801 {
 802         struct intel_device_info *intel_info =
 803                 (struct intel_device_info *) ent->driver_data;
 804
 805         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 806                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 807                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 808                 return -ENODEV;
 809         }
 810
 811         /* Only bind to function 0 of the device. Early generations
 812          * used function 1 as a placeholder for multi-head. This causes
 813          * us confusion instead, especially on the systems where both
 814          * functions have the same PCI-ID!
 815          */
 816         if (PCI_FUNC(pdev->devfn))
 817                 return -ENODEV;
 818
 819         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 820          * implementation for gen3 (and only gen3) that used legacy drm maps
 821          * (gasp!) to share buffers between X and the client. Hence we need to
 822          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 823         if (intel_info->gen != 3) {
 824                 driver.driver_features &=
 825                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 826         } else if (!intel_agp_enabled) {
 827                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 828                 return -ENODEV;
 829         }
 830
 831         return drm_get_pci_dev(pdev, ent, &driver);
 832 }
 833
 834 static void
 835 i915_pci_remove(struct pci_dev *pdev)
 836 {
 837         struct drm_device *dev = pci_get_drvdata(pdev);
 838
 839         drm_put_dev(dev);
 840 }
 841
 842 static int i915_pm_suspend(struct device *dev)
 843 {
 844         struct pci_dev *pdev = to_pci_dev(dev);
 845         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 846         int error;
 847
 848         if (!drm_dev || !drm_dev->dev_private) {
 849                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 850                 return -ENODEV;
 851         }
 852
 853         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 854                 return 0;
 855
 856         error = i915_drm_freeze(drm_dev);
 857         if (error)
 858                 return error;
 859
 860         pci_disable_device(pdev);
 861         pci_set_power_state(pdev, PCI_D3hot);
 862
 863         return 0;
 864 }
 865
 866 static int i915_pm_resume(struct device *dev)
 867 {
 868         struct pci_dev *pdev = to_pci_dev(dev);
 869         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 870
 871         return i915_resume(drm_dev);
 872 }
 873
 874 static int i915_pm_freeze(struct device *dev)
 875 {
 876         struct pci_dev *pdev = to_pci_dev(dev);
 877         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 878
 879         if (!drm_dev || !drm_dev->dev_private) {
 880                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 881                 return -ENODEV;
 882         }
 883
 884         return i915_drm_freeze(drm_dev);
 885 }
 886
 887 static int i915_pm_thaw(struct device *dev)
 888 {
 889         struct pci_dev *pdev = to_pci_dev(dev);
 890         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 891
 892         return i915_drm_thaw(drm_dev);
 893 }
 894
 895 static int i915_pm_poweroff(struct device *dev)
 896 {
 897         struct pci_dev *pdev = to_pci_dev(dev);
 898         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 899
 900         return i915_drm_freeze(drm_dev);
 901 }
 902
 903 static const struct dev_pm_ops i915_pm_ops = {
 904         .suspend = i915_pm_suspend,
 905         .resume = i915_pm_resume,
 906         .freeze = i915_pm_freeze,
 907         .thaw = i915_pm_thaw,
 908         .poweroff = i915_pm_poweroff,
 909         .restore = i915_pm_resume,
 910 };
 911
 912 static const struct vm_operations_struct i915_gem_vm_ops = {
 913         .fault = i915_gem_fault,
 914         .open = drm_gem_vm_open,
 915         .close = drm_gem_vm_close,
 916 };
 917
 918 static const struct file_operations i915_driver_fops = {
 919         .owner = THIS_MODULE,
 920         .open = drm_open,
 921         .release = drm_release,
 922         .unlocked_ioctl = drm_ioctl,
 923         .mmap = drm_gem_mmap,
 924         .poll = drm_poll,
 925         .read = drm_read,
 926 #ifdef CONFIG_COMPAT
 927         .compat_ioctl = i915_compat_ioctl,
 928 #endif
 929         .llseek = noop_llseek,
 930 };
 931
 932 static struct drm_driver driver = {
 933         /* Don't use MTRRs here; the Xserver or userspace app should
 934          * deal with them for Intel hardware.
 935          */
 936         .driver_features =
 937             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 938             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 939             DRIVER_RENDER,
 940         .load = i915_driver_load,
 941         .unload = i915_driver_unload,
 942         .open = i915_driver_open,
 943         .lastclose = i915_driver_lastclose,
 944         .preclose = i915_driver_preclose,
 945         .postclose = i915_driver_postclose,
 946
 947         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 948         .suspend = i915_suspend,
 949         .resume = i915_resume,
 950
 951         .device_is_agp = i915_driver_device_is_agp,
 952         .master_create = i915_master_create,
 953         .master_destroy = i915_master_destroy,
 954 #if defined(CONFIG_DEBUG_FS)
 955         .debugfs_init = i915_debugfs_init,
 956         .debugfs_cleanup = i915_debugfs_cleanup,
 957 #endif
 958         .gem_free_object = i915_gem_free_object,
 959         .gem_vm_ops = &i915_gem_vm_ops,
 960
 961         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 962         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 963         .gem_prime_export = i915_gem_prime_export,
 964         .gem_prime_import = i915_gem_prime_import,
 965
 966         .dumb_create = i915_gem_dumb_create,
 967         .dumb_map_offset = i915_gem_mmap_gtt,
 968         .dumb_destroy = drm_gem_dumb_destroy,
 969         .ioctls = i915_ioctls,
 970         .fops = &i915_driver_fops,
 971         .name = DRIVER_NAME,
 972         .desc = DRIVER_DESC,
 973         .date = DRIVER_DATE,
 974         .major = DRIVER_MAJOR,
 975         .minor = DRIVER_MINOR,
 976         .patchlevel = DRIVER_PATCHLEVEL,
 977 };
 978
 979 static struct pci_driver i915_pci_driver = {
 980         .name = DRIVER_NAME,
 981         .id_table = pciidlist,
 982         .probe = i915_pci_probe,
 983         .remove = i915_pci_remove,
 984         .driver.pm = &i915_pm_ops,
 985 };
 986
 987 static int __init i915_init(void)
 988 {
 989         driver.num_ioctls = i915_max_ioctl;
 990
 991         /*
 992          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 993          * explicitly disabled with the module pararmeter.
 994          *
 995          * Otherwise, just follow the parameter (defaulting to off).
 996          *
 997          * Allow optional vga_text_mode_force boot option to override
 998          * the default behavior.
 999          */
1000 #if defined(CONFIG_DRM_I915_KMS)
1001         if (i915_modeset != 0)
1002                 driver.driver_features |= DRIVER_MODESET;
1003 #endif
1004         if (i915_modeset == 1)
1005                 driver.driver_features |= DRIVER_MODESET;
1006
1007 #ifdef CONFIG_VGA_CONSOLE
1008         if (vgacon_text_force() && i915_modeset == -1)
1009                 driver.driver_features &= ~DRIVER_MODESET;
1010 #endif
1011
1012         if (!(driver.driver_features & DRIVER_MODESET))
1013                 driver.get_vblank_timestamp = NULL;
1014
1015         return drm_pci_init(&driver, &i915_pci_driver);
1016 }
1017
1018 static void __exit i915_exit(void)
1019 {
1020         drm_pci_exit(&driver, &i915_pci_driver);
1021 }
1022
1023 module_init(i915_init);
1024 module_exit(i915_exit);
1025
1026 MODULE_AUTHOR(DRIVER_AUTHOR);
1027 MODULE_DESCRIPTION(DRIVER_DESC);
1028 MODULE_LICENSE("GPL and additional rights");