drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         }
 143
 144         return ret;
 145 }
 146
 147 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 148 {
 149         struct pci_dev *pch = NULL;
 150
 151         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 152          * (which really amounts to a PCH but no South Display).
 153          */
 154         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 155                 dev_priv->pch_type = PCH_NOP;
 156                 return;
 157         }
 158
 159         /*
 160          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 161          * make graphics device passthrough work easy for VMM, that only
 162          * need to expose ISA bridge to let driver know the real hardware
 163          * underneath. This is a requirement from virtualization team.
 164          *
 165          * In some virtualized environments (e.g. XEN), there is irrelevant
 166          * ISA bridge in the system. To work reliably, we should scan trhough
 167          * all the ISA bridge devices and check for the first match, instead
 168          * of only checking the first one.
 169          */
 170         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 171                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 172                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 173                         dev_priv->pch_id = id;
 174
 175                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 176                                 dev_priv->pch_type = PCH_IBX;
 177                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 178                                 WARN_ON(!IS_GEN5(dev_priv));
 179                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 180                                 dev_priv->pch_type = PCH_CPT;
 181                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 182                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 183                                         IS_IVYBRIDGE(dev_priv)));
 184                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 185                                 /* PantherPoint is CPT compatible */
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 191                                 dev_priv->pch_type = PCH_LPT;
 192                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 193                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 194                                         !IS_BROADWELL(dev_priv));
 195                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 196                                         IS_BDW_ULT(dev_priv));
 197                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_LPT;
 199                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 200                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 201                                         !IS_BROADWELL(dev_priv));
 202                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 203                                         !IS_BDW_ULT(dev_priv));
 204                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 205                                 dev_priv->pch_type = PCH_SPT;
 206                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 207                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 208                                         !IS_KABYLAKE(dev_priv));
 209                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 210                                 dev_priv->pch_type = PCH_SPT;
 211                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 212                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 213                                         !IS_KABYLAKE(dev_priv));
 214                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 215                                 dev_priv->pch_type = PCH_KBP;
 216                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 217                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 218                                         !IS_KABYLAKE(dev_priv));
 219                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 220                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 221                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 222                                     pch->subsystem_vendor ==
 223                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 224                                     pch->subsystem_device ==
 225                                             PCI_SUBDEVICE_ID_QEMU)) {
 226                                 dev_priv->pch_type =
 227                                         intel_virt_detect_pch(dev_priv);
 228                         } else
 229                                 continue;
 230
 231                         break;
 232                 }
 233         }
 234         if (!pch)
 235                 DRM_DEBUG_KMS("No PCH found.\n");
 236
 237         pci_dev_put(pch);
 238 }
 239
 240 static int i915_getparam(struct drm_device *dev, void *data,
 241                          struct drm_file *file_priv)
 242 {
 243         struct drm_i915_private *dev_priv = to_i915(dev);
 244         struct pci_dev *pdev = dev_priv->drm.pdev;
 245         drm_i915_getparam_t *param = data;
 246         int value;
 247
 248         switch (param->param) {
 249         case I915_PARAM_IRQ_ACTIVE:
 250         case I915_PARAM_ALLOW_BATCHBUFFER:
 251         case I915_PARAM_LAST_DISPATCH:
 252         case I915_PARAM_HAS_EXEC_CONSTANTS:
 253                 /* Reject all old ums/dri params. */
 254                 return -ENODEV;
 255         case I915_PARAM_CHIPSET_ID:
 256                 value = pdev->device;
 257                 break;
 258         case I915_PARAM_REVISION:
 259                 value = pdev->revision;
 260                 break;
 261         case I915_PARAM_NUM_FENCES_AVAIL:
 262                 value = dev_priv->num_fence_regs;
 263                 break;
 264         case I915_PARAM_HAS_OVERLAY:
 265                 value = dev_priv->overlay ? 1 : 0;
 266                 break;
 267         case I915_PARAM_HAS_BSD:
 268                 value = !!dev_priv->engine[VCS];
 269                 break;
 270         case I915_PARAM_HAS_BLT:
 271                 value = !!dev_priv->engine[BCS];
 272                 break;
 273         case I915_PARAM_HAS_VEBOX:
 274                 value = !!dev_priv->engine[VECS];
 275                 break;
 276         case I915_PARAM_HAS_BSD2:
 277                 value = !!dev_priv->engine[VCS2];
 278                 break;
 279         case I915_PARAM_HAS_LLC:
 280                 value = HAS_LLC(dev_priv);
 281                 break;
 282         case I915_PARAM_HAS_WT:
 283                 value = HAS_WT(dev_priv);
 284                 break;
 285         case I915_PARAM_HAS_ALIASING_PPGTT:
 286                 value = USES_PPGTT(dev_priv);
 287                 break;
 288         case I915_PARAM_HAS_SEMAPHORES:
 289                 value = i915.semaphores;
 290                 break;
 291         case I915_PARAM_HAS_SECURE_BATCHES:
 292                 value = capable(CAP_SYS_ADMIN);
 293                 break;
 294         case I915_PARAM_CMD_PARSER_VERSION:
 295                 value = i915_cmd_parser_get_version(dev_priv);
 296                 break;
 297         case I915_PARAM_SUBSLICE_TOTAL:
 298                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 299                 if (!value)
 300                         return -ENODEV;
 301                 break;
 302         case I915_PARAM_EU_TOTAL:
 303                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 304                 if (!value)
 305                         return -ENODEV;
 306                 break;
 307         case I915_PARAM_HAS_GPU_RESET:
 308                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 309                 break;
 310         case I915_PARAM_HAS_RESOURCE_STREAMER:
 311                 value = HAS_RESOURCE_STREAMER(dev_priv);
 312                 break;
 313         case I915_PARAM_HAS_POOLED_EU:
 314                 value = HAS_POOLED_EU(dev_priv);
 315                 break;
 316         case I915_PARAM_MIN_EU_IN_POOL:
 317                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 318                 break;
 319         case I915_PARAM_HUC_STATUS:
 320                 intel_runtime_pm_get(dev_priv);
 321                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 322                 intel_runtime_pm_put(dev_priv);
 323                 break;
 324         case I915_PARAM_MMAP_GTT_VERSION:
 325                 /* Though we've started our numbering from 1, and so class all
 326                  * earlier versions as 0, in effect their value is undefined as
 327                  * the ioctl will report EINVAL for the unknown param!
 328                  */
 329                 value = i915_gem_mmap_gtt_version();
 330                 break;
 331         case I915_PARAM_HAS_SCHEDULER:
 332                 value = dev_priv->engine[RCS] &&
 333                         dev_priv->engine[RCS]->schedule;
 334                 break;
 335         case I915_PARAM_MMAP_VERSION:
 336                 /* Remember to bump this if the version changes! */
 337         case I915_PARAM_HAS_GEM:
 338         case I915_PARAM_HAS_PAGEFLIPPING:
 339         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 340         case I915_PARAM_HAS_RELAXED_FENCING:
 341         case I915_PARAM_HAS_COHERENT_RINGS:
 342         case I915_PARAM_HAS_RELAXED_DELTA:
 343         case I915_PARAM_HAS_GEN7_SOL_RESET:
 344         case I915_PARAM_HAS_WAIT_TIMEOUT:
 345         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 346         case I915_PARAM_HAS_PINNED_BATCHES:
 347         case I915_PARAM_HAS_EXEC_NO_RELOC:
 348         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 349         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 350         case I915_PARAM_HAS_EXEC_SOFTPIN:
 351         case I915_PARAM_HAS_EXEC_ASYNC:
 352         case I915_PARAM_HAS_EXEC_FENCE:
 353                 /* For the time being all of these are always true;
 354                  * if some supported hardware does not have one of these
 355                  * features this value needs to be provided from
 356                  * INTEL_INFO(), a feature macro, or similar.
 357                  */
 358                 value = 1;
 359                 break;
 360         default:
 361                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 362                 return -EINVAL;
 363         }
 364
 365         if (put_user(value, param->value))
 366                 return -EFAULT;
 367
 368         return 0;
 369 }
 370
 371 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 372 {
 373         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 374         if (!dev_priv->bridge_dev) {
 375                 DRM_ERROR("bridge device not found\n");
 376                 return -1;
 377         }
 378         return 0;
 379 }
 380
 381 /* Allocate space for the MCH regs if needed, return nonzero on error */
 382 static int
 383 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 384 {
 385         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 386         u32 temp_lo, temp_hi = 0;
 387         u64 mchbar_addr;
 388         int ret;
 389
 390         if (INTEL_GEN(dev_priv) >= 4)
 391                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 392         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 393         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 394
 395         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 396 #ifdef CONFIG_PNP
 397         if (mchbar_addr &&
 398             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 399                 return 0;
 400 #endif
 401
 402         /* Get some space for it */
 403         dev_priv->mch_res.name = "i915 MCHBAR";
 404         dev_priv->mch_res.flags = IORESOURCE_MEM;
 405         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 406                                      &dev_priv->mch_res,
 407                                      MCHBAR_SIZE, MCHBAR_SIZE,
 408                                      PCIBIOS_MIN_MEM,
 409                                      0, pcibios_align_resource,
 410                                      dev_priv->bridge_dev);
 411         if (ret) {
 412                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 413                 dev_priv->mch_res.start = 0;
 414                 return ret;
 415         }
 416
 417         if (INTEL_GEN(dev_priv) >= 4)
 418                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 419                                        upper_32_bits(dev_priv->mch_res.start));
 420
 421         pci_write_config_dword(dev_priv->bridge_dev, reg,
 422                                lower_32_bits(dev_priv->mch_res.start));
 423         return 0;
 424 }
 425
 426 /* Setup MCHBAR if possible, return true if we should disable it again */
 427 static void
 428 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 429 {
 430         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 431         u32 temp;
 432         bool enabled;
 433
 434         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 435                 return;
 436
 437         dev_priv->mchbar_need_disable = false;
 438
 439         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 440                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 441                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 442         } else {
 443                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 444                 enabled = temp & 1;
 445         }
 446
 447         /* If it's already enabled, don't have to do anything */
 448         if (enabled)
 449                 return;
 450
 451         if (intel_alloc_mchbar_resource(dev_priv))
 452                 return;
 453
 454         dev_priv->mchbar_need_disable = true;
 455
 456         /* Space is allocated or reserved, so enable it. */
 457         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 458                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 459                                        temp | DEVEN_MCHBAR_EN);
 460         } else {
 461                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 462                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 463         }
 464 }
 465
 466 static void
 467 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 468 {
 469         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 470
 471         if (dev_priv->mchbar_need_disable) {
 472                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 473                         u32 deven_val;
 474
 475                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 476                                               &deven_val);
 477                         deven_val &= ~DEVEN_MCHBAR_EN;
 478                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 479                                                deven_val);
 480                 } else {
 481                         u32 mchbar_val;
 482
 483                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 484                                               &mchbar_val);
 485                         mchbar_val &= ~1;
 486                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 487                                                mchbar_val);
 488                 }
 489         }
 490
 491         if (dev_priv->mch_res.start)
 492                 release_resource(&dev_priv->mch_res);
 493 }
 494
 495 /* true = enable decode, false = disable decoder */
 496 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 497 {
 498         struct drm_i915_private *dev_priv = cookie;
 499
 500         intel_modeset_vga_set_state(dev_priv, state);
 501         if (state)
 502                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 503                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 504         else
 505                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506 }
 507
 508 static int i915_resume_switcheroo(struct drm_device *dev);
 509 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 510
 511 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 512 {
 513         struct drm_device *dev = pci_get_drvdata(pdev);
 514         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 515
 516         if (state == VGA_SWITCHEROO_ON) {
 517                 pr_info("switched on\n");
 518                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 519                 /* i915 resume handler doesn't set to D0 */
 520                 pci_set_power_state(pdev, PCI_D0);
 521                 i915_resume_switcheroo(dev);
 522                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 523         } else {
 524                 pr_info("switched off\n");
 525                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 526                 i915_suspend_switcheroo(dev, pmm);
 527                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 528         }
 529 }
 530
 531 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 532 {
 533         struct drm_device *dev = pci_get_drvdata(pdev);
 534
 535         /*
 536          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 537          * locking inversion with the driver load path. And the access here is
 538          * completely racy anyway. So don't bother with locking for now.
 539          */
 540         return dev->open_count == 0;
 541 }
 542
 543 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 544         .set_gpu_state = i915_switcheroo_set_state,
 545         .reprobe = NULL,
 546         .can_switch = i915_switcheroo_can_switch,
 547 };
 548
 549 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 550 {
 551         mutex_lock(&dev_priv->drm.struct_mutex);
 552         i915_gem_cleanup_engines(dev_priv);
 553         i915_gem_context_fini(dev_priv);
 554         mutex_unlock(&dev_priv->drm.struct_mutex);
 555
 556         i915_gem_drain_freed_objects(dev_priv);
 557
 558         WARN_ON(!list_empty(&dev_priv->context_list));
 559 }
 560
 561 static int i915_load_modeset_init(struct drm_device *dev)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(dev);
 564         struct pci_dev *pdev = dev_priv->drm.pdev;
 565         int ret;
 566
 567         if (i915_inject_load_failure())
 568                 return -ENODEV;
 569
 570         ret = intel_bios_init(dev_priv);
 571         if (ret)
 572                 DRM_INFO("failed to find VBIOS tables\n");
 573
 574         /* If we have > 1 VGA cards, then we need to arbitrate access
 575          * to the common VGA resources.
 576          *
 577          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 578          * then we do not take part in VGA arbitration and the
 579          * vga_client_register() fails with -ENODEV.
 580          */
 581         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 582         if (ret && ret != -ENODEV)
 583                 goto out;
 584
 585         intel_register_dsm_handler();
 586
 587         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 588         if (ret)
 589                 goto cleanup_vga_client;
 590
 591         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 592         intel_update_rawclk(dev_priv);
 593
 594         intel_power_domains_init_hw(dev_priv, false);
 595
 596         intel_csr_ucode_init(dev_priv);
 597
 598         ret = intel_irq_install(dev_priv);
 599         if (ret)
 600                 goto cleanup_csr;
 601
 602         intel_setup_gmbus(dev_priv);
 603
 604         /* Important: The output setup functions called by modeset_init need
 605          * working irqs for e.g. gmbus and dp aux transfers. */
 606         ret = intel_modeset_init(dev);
 607         if (ret)
 608                 goto cleanup_irq;
 609
 610         intel_huc_init(dev_priv);
 611         intel_guc_init(dev_priv);
 612
 613         ret = i915_gem_init(dev_priv);
 614         if (ret)
 615                 goto cleanup_irq;
 616
 617         intel_modeset_gem_init(dev);
 618
 619         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 620                 return 0;
 621
 622         ret = intel_fbdev_init(dev);
 623         if (ret)
 624                 goto cleanup_gem;
 625
 626         /* Only enable hotplug handling once the fbdev is fully set up. */
 627         intel_hpd_init(dev_priv);
 628
 629         drm_kms_helper_poll_init(dev);
 630
 631         return 0;
 632
 633 cleanup_gem:
 634         if (i915_gem_suspend(dev_priv))
 635                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 636         i915_gem_fini(dev_priv);
 637 cleanup_irq:
 638         intel_guc_fini(dev_priv);
 639         intel_huc_fini(dev_priv);
 640         drm_irq_uninstall(dev);
 641         intel_teardown_gmbus(dev_priv);
 642 cleanup_csr:
 643         intel_csr_ucode_fini(dev_priv);
 644         intel_power_domains_fini(dev_priv);
 645         vga_switcheroo_unregister_client(pdev);
 646 cleanup_vga_client:
 647         vga_client_register(pdev, NULL, NULL, NULL);
 648 out:
 649         return ret;
 650 }
 651
 652 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 653 {
 654         struct apertures_struct *ap;
 655         struct pci_dev *pdev = dev_priv->drm.pdev;
 656         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 657         bool primary;
 658         int ret;
 659
 660         ap = alloc_apertures(1);
 661         if (!ap)
 662                 return -ENOMEM;
 663
 664         ap->ranges[0].base = ggtt->mappable_base;
 665         ap->ranges[0].size = ggtt->mappable_end;
 666
 667         primary =
 668                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 669
 670         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 671
 672         kfree(ap);
 673
 674         return ret;
 675 }
 676
 677 #if !defined(CONFIG_VGA_CONSOLE)
 678 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 679 {
 680         return 0;
 681 }
 682 #elif !defined(CONFIG_DUMMY_CONSOLE)
 683 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 684 {
 685         return -ENODEV;
 686 }
 687 #else
 688 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 689 {
 690         int ret = 0;
 691
 692         DRM_INFO("Replacing VGA console driver\n");
 693
 694         console_lock();
 695         if (con_is_bound(&vga_con))
 696                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 697         if (ret == 0) {
 698                 ret = do_unregister_con_driver(&vga_con);
 699
 700                 /* Ignore "already unregistered". */
 701                 if (ret == -ENODEV)
 702                         ret = 0;
 703         }
 704         console_unlock();
 705
 706         return ret;
 707 }
 708 #endif
 709
 710 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 711 {
 712         /*
 713          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 714          * CHV x1 PHY (DP/HDMI D)
 715          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 716          */
 717         if (IS_CHERRYVIEW(dev_priv)) {
 718                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 719                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 720         } else if (IS_VALLEYVIEW(dev_priv)) {
 721                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 722         }
 723 }
 724
 725 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 726 {
 727         /*
 728          * The i915 workqueue is primarily used for batched retirement of
 729          * requests (and thus managing bo) once the task has been completed
 730          * by the GPU. i915_gem_retire_requests() is called directly when we
 731          * need high-priority retirement, such as waiting for an explicit
 732          * bo.
 733          *
 734          * It is also used for periodic low-priority events, such as
 735          * idle-timers and recording error state.
 736          *
 737          * All tasks on the workqueue are expected to acquire the dev mutex
 738          * so there is no point in running more than one instance of the
 739          * workqueue at any time.  Use an ordered one.
 740          */
 741         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 742         if (dev_priv->wq == NULL)
 743                 goto out_err;
 744
 745         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 746         if (dev_priv->hotplug.dp_wq == NULL)
 747                 goto out_free_wq;
 748
 749         return 0;
 750
 751 out_free_wq:
 752         destroy_workqueue(dev_priv->wq);
 753 out_err:
 754         DRM_ERROR("Failed to allocate workqueues.\n");
 755
 756         return -ENOMEM;
 757 }
 758
 759 static void i915_engines_cleanup(struct drm_i915_private *i915)
 760 {
 761         struct intel_engine_cs *engine;
 762         enum intel_engine_id id;
 763
 764         for_each_engine(engine, i915, id)
 765                 kfree(engine);
 766 }
 767
 768 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 769 {
 770         destroy_workqueue(dev_priv->hotplug.dp_wq);
 771         destroy_workqueue(dev_priv->wq);
 772 }
 773
 774 /*
 775  * We don't keep the workarounds for pre-production hardware, so we expect our
 776  * driver to fail on these machines in one way or another. A little warning on
 777  * dmesg may help both the user and the bug triagers.
 778  */
 779 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 780 {
 781         bool pre = false;
 782
 783         pre |= IS_HSW_EARLY_SDV(dev_priv);
 784         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 785         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 786
 787         if (pre) {
 788                 DRM_ERROR("This is a pre-production stepping. "
 789                           "It may not be fully functional.\n");
 790                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 791         }
 792 }
 793
 794 /**
 795  * i915_driver_init_early - setup state not requiring device access
 796  * @dev_priv: device private
 797  *
 798  * Initialize everything that is a "SW-only" state, that is state not
 799  * requiring accessing the device or exposing the driver via kernel internal
 800  * or userspace interfaces. Example steps belonging here: lock initialization,
 801  * system memory allocation, setting up device specific attributes and
 802  * function hooks not requiring accessing the device.
 803  */
 804 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 805                                   const struct pci_device_id *ent)
 806 {
 807         const struct intel_device_info *match_info =
 808                 (struct intel_device_info *)ent->driver_data;
 809         struct intel_device_info *device_info;
 810         int ret = 0;
 811
 812         if (i915_inject_load_failure())
 813                 return -ENODEV;
 814
 815         /* Setup the write-once "constant" device info */
 816         device_info = mkwrite_device_info(dev_priv);
 817         memcpy(device_info, match_info, sizeof(*device_info));
 818         device_info->device_id = dev_priv->drm.pdev->device;
 819
 820         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 821         device_info->gen_mask = BIT(device_info->gen - 1);
 822
 823         spin_lock_init(&dev_priv->irq_lock);
 824         spin_lock_init(&dev_priv->gpu_error.lock);
 825         mutex_init(&dev_priv->backlight_lock);
 826         spin_lock_init(&dev_priv->uncore.lock);
 827
 828         spin_lock_init(&dev_priv->mm.object_stat_lock);
 829         spin_lock_init(&dev_priv->mmio_flip_lock);
 830         spin_lock_init(&dev_priv->wm.dsparb_lock);
 831         mutex_init(&dev_priv->sb_lock);
 832         mutex_init(&dev_priv->modeset_restore_lock);
 833         mutex_init(&dev_priv->av_mutex);
 834         mutex_init(&dev_priv->wm.wm_mutex);
 835         mutex_init(&dev_priv->pps_mutex);
 836
 837         intel_uc_init_early(dev_priv);
 838         i915_memcpy_init_early(dev_priv);
 839
 840         ret = intel_engines_init_early(dev_priv);
 841         if (ret)
 842                 return ret;
 843
 844         ret = i915_workqueues_init(dev_priv);
 845         if (ret < 0)
 846                 goto err_engines;
 847
 848         /* This must be called before any calls to HAS_PCH_* */
 849         intel_detect_pch(dev_priv);
 850
 851         intel_pm_setup(dev_priv);
 852         intel_init_dpio(dev_priv);
 853         intel_power_domains_init(dev_priv);
 854         intel_irq_init(dev_priv);
 855         intel_hangcheck_init(dev_priv);
 856         intel_init_display_hooks(dev_priv);
 857         intel_init_clock_gating_hooks(dev_priv);
 858         intel_init_audio_hooks(dev_priv);
 859         ret = i915_gem_load_init(dev_priv);
 860         if (ret < 0)
 861                 goto err_workqueues;
 862
 863         intel_display_crc_init(dev_priv);
 864
 865         intel_device_info_dump(dev_priv);
 866
 867         intel_detect_preproduction_hw(dev_priv);
 868
 869         i915_perf_init(dev_priv);
 870
 871         return 0;
 872
 873 err_workqueues:
 874         i915_workqueues_cleanup(dev_priv);
 875 err_engines:
 876         i915_engines_cleanup(dev_priv);
 877         return ret;
 878 }
 879
 880 /**
 881  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 882  * @dev_priv: device private
 883  */
 884 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 885 {
 886         i915_perf_fini(dev_priv);
 887         i915_gem_load_cleanup(dev_priv);
 888         i915_workqueues_cleanup(dev_priv);
 889         i915_engines_cleanup(dev_priv);
 890 }
 891
 892 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 893 {
 894         struct pci_dev *pdev = dev_priv->drm.pdev;
 895         int mmio_bar;
 896         int mmio_size;
 897
 898         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 899         /*
 900          * Before gen4, the registers and the GTT are behind different BARs.
 901          * However, from gen4 onwards, the registers and the GTT are shared
 902          * in the same BAR, so we want to restrict this ioremap from
 903          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 904          * the register BAR remains the same size for all the earlier
 905          * generations up to Ironlake.
 906          */
 907         if (INTEL_GEN(dev_priv) < 5)
 908                 mmio_size = 512 * 1024;
 909         else
 910                 mmio_size = 2 * 1024 * 1024;
 911         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 912         if (dev_priv->regs == NULL) {
 913                 DRM_ERROR("failed to map registers\n");
 914
 915                 return -EIO;
 916         }
 917
 918         /* Try to make sure MCHBAR is enabled before poking at it */
 919         intel_setup_mchbar(dev_priv);
 920
 921         return 0;
 922 }
 923
 924 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 925 {
 926         struct pci_dev *pdev = dev_priv->drm.pdev;
 927
 928         intel_teardown_mchbar(dev_priv);
 929         pci_iounmap(pdev, dev_priv->regs);
 930 }
 931
 932 /**
 933  * i915_driver_init_mmio - setup device MMIO
 934  * @dev_priv: device private
 935  *
 936  * Setup minimal device state necessary for MMIO accesses later in the
 937  * initialization sequence. The setup here should avoid any other device-wide
 938  * side effects or exposing the driver via kernel internal or user space
 939  * interfaces.
 940  */
 941 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 942 {
 943         int ret;
 944
 945         if (i915_inject_load_failure())
 946                 return -ENODEV;
 947
 948         if (i915_get_bridge_dev(dev_priv))
 949                 return -EIO;
 950
 951         ret = i915_mmio_setup(dev_priv);
 952         if (ret < 0)
 953                 goto put_bridge;
 954
 955         intel_uncore_init(dev_priv);
 956         i915_gem_init_mmio(dev_priv);
 957
 958         return 0;
 959
 960 put_bridge:
 961         pci_dev_put(dev_priv->bridge_dev);
 962
 963         return ret;
 964 }
 965
 966 /**
 967  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 968  * @dev_priv: device private
 969  */
 970 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 971 {
 972         intel_uncore_fini(dev_priv);
 973         i915_mmio_cleanup(dev_priv);
 974         pci_dev_put(dev_priv->bridge_dev);
 975 }
 976
 977 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 978 {
 979         i915.enable_execlists =
 980                 intel_sanitize_enable_execlists(dev_priv,
 981                                                 i915.enable_execlists);
 982
 983         /*
 984          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 985          * user's requested state against the hardware/driver capabilities.  We
 986          * do this now so that we can print out any log messages once rather
 987          * than every time we check intel_enable_ppgtt().
 988          */
 989         i915.enable_ppgtt =
 990                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 991         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 992
 993         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 994         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
 995 }
 996
 997 /**
 998  * i915_driver_init_hw - setup state requiring device access
 999  * @dev_priv: device private
1000  *
1001  * Setup state that requires accessing the device, but doesn't require
1002  * exposing the driver via kernel internal or userspace interfaces.
1003  */
1004 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1005 {
1006         struct pci_dev *pdev = dev_priv->drm.pdev;
1007         int ret;
1008
1009         if (i915_inject_load_failure())
1010                 return -ENODEV;
1011
1012         intel_device_info_runtime_init(dev_priv);
1013
1014         intel_sanitize_options(dev_priv);
1015
1016         ret = i915_ggtt_probe_hw(dev_priv);
1017         if (ret)
1018                 return ret;
1019
1020         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1021          * otherwise the vga fbdev driver falls over. */
1022         ret = i915_kick_out_firmware_fb(dev_priv);
1023         if (ret) {
1024                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1025                 goto out_ggtt;
1026         }
1027
1028         ret = i915_kick_out_vgacon(dev_priv);
1029         if (ret) {
1030                 DRM_ERROR("failed to remove conflicting VGA console\n");
1031                 goto out_ggtt;
1032         }
1033
1034         ret = i915_ggtt_init_hw(dev_priv);
1035         if (ret)
1036                 return ret;
1037
1038         ret = i915_ggtt_enable_hw(dev_priv);
1039         if (ret) {
1040                 DRM_ERROR("failed to enable GGTT\n");
1041                 goto out_ggtt;
1042         }
1043
1044         pci_set_master(pdev);
1045
1046         /* overlay on gen2 is broken and can't address above 1G */
1047         if (IS_GEN2(dev_priv)) {
1048                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1049                 if (ret) {
1050                         DRM_ERROR("failed to set DMA mask\n");
1051
1052                         goto out_ggtt;
1053                 }
1054         }
1055
1056         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1057          * using 32bit addressing, overwriting memory if HWS is located
1058          * above 4GB.
1059          *
1060          * The documentation also mentions an issue with undefined
1061          * behaviour if any general state is accessed within a page above 4GB,
1062          * which also needs to be handled carefully.
1063          */
1064         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1065                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1066
1067                 if (ret) {
1068                         DRM_ERROR("failed to set DMA mask\n");
1069
1070                         goto out_ggtt;
1071                 }
1072         }
1073
1074         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1075                            PM_QOS_DEFAULT_VALUE);
1076
1077         intel_uncore_sanitize(dev_priv);
1078
1079         intel_opregion_setup(dev_priv);
1080
1081         i915_gem_load_init_fences(dev_priv);
1082
1083         /* On the 945G/GM, the chipset reports the MSI capability on the
1084          * integrated graphics even though the support isn't actually there
1085          * according to the published specs.  It doesn't appear to function
1086          * correctly in testing on 945G.
1087          * This may be a side effect of MSI having been made available for PEG
1088          * and the registers being closely associated.
1089          *
1090          * According to chipset errata, on the 965GM, MSI interrupts may
1091          * be lost or delayed, but we use them anyways to avoid
1092          * stuck interrupts on some machines.
1093          */
1094         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1095                 if (pci_enable_msi(pdev) < 0)
1096                         DRM_DEBUG_DRIVER("can't enable MSI");
1097         }
1098
1099         ret = intel_gvt_init(dev_priv);
1100         if (ret)
1101                 goto out_ggtt;
1102
1103         return 0;
1104
1105 out_ggtt:
1106         i915_ggtt_cleanup_hw(dev_priv);
1107
1108         return ret;
1109 }
1110
1111 /**
1112  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1113  * @dev_priv: device private
1114  */
1115 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1116 {
1117         struct pci_dev *pdev = dev_priv->drm.pdev;
1118
1119         if (pdev->msi_enabled)
1120                 pci_disable_msi(pdev);
1121
1122         pm_qos_remove_request(&dev_priv->pm_qos);
1123         i915_ggtt_cleanup_hw(dev_priv);
1124 }
1125
1126 /**
1127  * i915_driver_register - register the driver with the rest of the system
1128  * @dev_priv: device private
1129  *
1130  * Perform any steps necessary to make the driver available via kernel
1131  * internal or userspace interfaces.
1132  */
1133 static void i915_driver_register(struct drm_i915_private *dev_priv)
1134 {
1135         struct drm_device *dev = &dev_priv->drm;
1136
1137         i915_gem_shrinker_init(dev_priv);
1138
1139         /*
1140          * Notify a valid surface after modesetting,
1141          * when running inside a VM.
1142          */
1143         if (intel_vgpu_active(dev_priv))
1144                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1145
1146         /* Reveal our presence to userspace */
1147         if (drm_dev_register(dev, 0) == 0) {
1148                 i915_debugfs_register(dev_priv);
1149                 i915_guc_log_register(dev_priv);
1150                 i915_setup_sysfs(dev_priv);
1151
1152                 /* Depends on sysfs having been initialized */
1153                 i915_perf_register(dev_priv);
1154         } else
1155                 DRM_ERROR("Failed to register driver for userspace access!\n");
1156
1157         if (INTEL_INFO(dev_priv)->num_pipes) {
1158                 /* Must be done after probing outputs */
1159                 intel_opregion_register(dev_priv);
1160                 acpi_video_register();
1161         }
1162
1163         if (IS_GEN5(dev_priv))
1164                 intel_gpu_ips_init(dev_priv);
1165
1166         intel_audio_init(dev_priv);
1167
1168         /*
1169          * Some ports require correctly set-up hpd registers for detection to
1170          * work properly (leading to ghost connected connector status), e.g. VGA
1171          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1172          * irqs are fully enabled. We do it last so that the async config
1173          * cannot run before the connectors are registered.
1174          */
1175         intel_fbdev_initial_config_async(dev);
1176 }
1177
1178 /**
1179  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1180  * @dev_priv: device private
1181  */
1182 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1183 {
1184         intel_audio_deinit(dev_priv);
1185
1186         intel_gpu_ips_teardown();
1187         acpi_video_unregister();
1188         intel_opregion_unregister(dev_priv);
1189
1190         i915_perf_unregister(dev_priv);
1191
1192         i915_teardown_sysfs(dev_priv);
1193         i915_guc_log_unregister(dev_priv);
1194         drm_dev_unregister(&dev_priv->drm);
1195
1196         i915_gem_shrinker_cleanup(dev_priv);
1197 }
1198
1199 /**
1200  * i915_driver_load - setup chip and create an initial config
1201  * @pdev: PCI device
1202  * @ent: matching PCI ID entry
1203  *
1204  * The driver load routine has to do several things:
1205  *   - drive output discovery via intel_modeset_init()
1206  *   - initialize the memory manager
1207  *   - allocate initial config memory
1208  *   - setup the DRM framebuffer with the allocated memory
1209  */
1210 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1211 {
1212         const struct intel_device_info *match_info =
1213                 (struct intel_device_info *)ent->driver_data;
1214         struct drm_i915_private *dev_priv;
1215         int ret;
1216
1217         /* Enable nuclear pageflip on ILK+, except vlv/chv */
1218         if (!i915.nuclear_pageflip &&
1219             (match_info->gen < 5 || match_info->has_gmch_display))
1220                 driver.driver_features &= ~DRIVER_ATOMIC;
1221
1222         ret = -ENOMEM;
1223         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1224         if (dev_priv)
1225                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1226         if (ret) {
1227                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1228                 goto out_free;
1229         }
1230
1231         dev_priv->drm.pdev = pdev;
1232         dev_priv->drm.dev_private = dev_priv;
1233
1234         ret = pci_enable_device(pdev);
1235         if (ret)
1236                 goto out_fini;
1237
1238         pci_set_drvdata(pdev, &dev_priv->drm);
1239
1240         ret = i915_driver_init_early(dev_priv, ent);
1241         if (ret < 0)
1242                 goto out_pci_disable;
1243
1244         intel_runtime_pm_get(dev_priv);
1245
1246         ret = i915_driver_init_mmio(dev_priv);
1247         if (ret < 0)
1248                 goto out_runtime_pm_put;
1249
1250         ret = i915_driver_init_hw(dev_priv);
1251         if (ret < 0)
1252                 goto out_cleanup_mmio;
1253
1254         /*
1255          * TODO: move the vblank init and parts of modeset init steps into one
1256          * of the i915_driver_init_/i915_driver_register functions according
1257          * to the role/effect of the given init step.
1258          */
1259         if (INTEL_INFO(dev_priv)->num_pipes) {
1260                 ret = drm_vblank_init(&dev_priv->drm,
1261                                       INTEL_INFO(dev_priv)->num_pipes);
1262                 if (ret)
1263                         goto out_cleanup_hw;
1264         }
1265
1266         ret = i915_load_modeset_init(&dev_priv->drm);
1267         if (ret < 0)
1268                 goto out_cleanup_vblank;
1269
1270         i915_driver_register(dev_priv);
1271
1272         intel_runtime_pm_enable(dev_priv);
1273
1274         dev_priv->ipc_enabled = false;
1275
1276         /* Everything is in place, we can now relax! */
1277         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1278                  driver.name, driver.major, driver.minor, driver.patchlevel,
1279                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1280         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1281                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1282         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1283                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1284
1285         intel_runtime_pm_put(dev_priv);
1286
1287         return 0;
1288
1289 out_cleanup_vblank:
1290         drm_vblank_cleanup(&dev_priv->drm);
1291 out_cleanup_hw:
1292         i915_driver_cleanup_hw(dev_priv);
1293 out_cleanup_mmio:
1294         i915_driver_cleanup_mmio(dev_priv);
1295 out_runtime_pm_put:
1296         intel_runtime_pm_put(dev_priv);
1297         i915_driver_cleanup_early(dev_priv);
1298 out_pci_disable:
1299         pci_disable_device(pdev);
1300 out_fini:
1301         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1302         drm_dev_fini(&dev_priv->drm);
1303 out_free:
1304         kfree(dev_priv);
1305         return ret;
1306 }
1307
1308 void i915_driver_unload(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = to_i915(dev);
1311         struct pci_dev *pdev = dev_priv->drm.pdev;
1312         struct drm_modeset_acquire_ctx ctx;
1313         int ret;
1314
1315         intel_fbdev_fini(dev);
1316
1317         if (i915_gem_suspend(dev_priv))
1318                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1319
1320         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1321
1322         drm_modeset_acquire_init(&ctx, 0);
1323         while (1) {
1324                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
1325                 if (!ret)
1326                         ret = drm_atomic_helper_disable_all(dev, &ctx);
1327
1328                 if (ret != -EDEADLK)
1329                         break;
1330
1331                 drm_modeset_backoff(&ctx);
1332         }
1333
1334         if (ret)
1335                 DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret);
1336
1337         drm_modeset_drop_locks(&ctx);
1338         drm_modeset_acquire_fini(&ctx);
1339
1340         intel_gvt_cleanup(dev_priv);
1341
1342         i915_driver_unregister(dev_priv);
1343
1344         drm_vblank_cleanup(dev);
1345
1346         intel_modeset_cleanup(dev);
1347
1348         /*
1349          * free the memory space allocated for the child device
1350          * config parsed from VBT
1351          */
1352         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1353                 kfree(dev_priv->vbt.child_dev);
1354                 dev_priv->vbt.child_dev = NULL;
1355                 dev_priv->vbt.child_dev_num = 0;
1356         }
1357         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1358         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1359         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1360         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1361
1362         vga_switcheroo_unregister_client(pdev);
1363         vga_client_register(pdev, NULL, NULL, NULL);
1364
1365         intel_csr_ucode_fini(dev_priv);
1366
1367         /* Free error state after interrupts are fully disabled. */
1368         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1369         i915_reset_error_state(dev_priv);
1370
1371         /* Flush any outstanding unpin_work. */
1372         drain_workqueue(dev_priv->wq);
1373
1374         intel_guc_fini(dev_priv);
1375         intel_huc_fini(dev_priv);
1376         i915_gem_fini(dev_priv);
1377         intel_fbc_cleanup_cfb(dev_priv);
1378
1379         intel_power_domains_fini(dev_priv);
1380
1381         i915_driver_cleanup_hw(dev_priv);
1382         i915_driver_cleanup_mmio(dev_priv);
1383
1384         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1385 }
1386
1387 static void i915_driver_release(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = to_i915(dev);
1390
1391         i915_driver_cleanup_early(dev_priv);
1392         drm_dev_fini(&dev_priv->drm);
1393
1394         kfree(dev_priv);
1395 }
1396
1397 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1398 {
1399         int ret;
1400
1401         ret = i915_gem_open(dev, file);
1402         if (ret)
1403                 return ret;
1404
1405         return 0;
1406 }
1407
1408 /**
1409  * i915_driver_lastclose - clean up after all DRM clients have exited
1410  * @dev: DRM device
1411  *
1412  * Take care of cleaning up after all DRM clients have exited.  In the
1413  * mode setting case, we want to restore the kernel's initial mode (just
1414  * in case the last client left us in a bad state).
1415  *
1416  * Additionally, in the non-mode setting case, we'll tear down the GTT
1417  * and DMA structures, since the kernel won't be using them, and clea
1418  * up any GEM state.
1419  */
1420 static void i915_driver_lastclose(struct drm_device *dev)
1421 {
1422         intel_fbdev_restore_mode(dev);
1423         vga_switcheroo_process_delayed_switch();
1424 }
1425
1426 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1427 {
1428         mutex_lock(&dev->struct_mutex);
1429         i915_gem_context_close(dev, file);
1430         i915_gem_release(dev, file);
1431         mutex_unlock(&dev->struct_mutex);
1432 }
1433
1434 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1435 {
1436         struct drm_i915_file_private *file_priv = file->driver_priv;
1437
1438         kfree(file_priv);
1439 }
1440
1441 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1442 {
1443         struct drm_device *dev = &dev_priv->drm;
1444         struct intel_encoder *encoder;
1445
1446         drm_modeset_lock_all(dev);
1447         for_each_intel_encoder(dev, encoder)
1448                 if (encoder->suspend)
1449                         encoder->suspend(encoder);
1450         drm_modeset_unlock_all(dev);
1451 }
1452
1453 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1454                               bool rpm_resume);
1455 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1456
1457 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1458 {
1459 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1460         if (acpi_target_system_state() < ACPI_STATE_S3)
1461                 return true;
1462 #endif
1463         return false;
1464 }
1465
1466 static int i915_drm_suspend(struct drm_device *dev)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(dev);
1469         struct pci_dev *pdev = dev_priv->drm.pdev;
1470         pci_power_t opregion_target_state;
1471         int error;
1472
1473         /* ignore lid events during suspend */
1474         mutex_lock(&dev_priv->modeset_restore_lock);
1475         dev_priv->modeset_restore = MODESET_SUSPENDED;
1476         mutex_unlock(&dev_priv->modeset_restore_lock);
1477
1478         disable_rpm_wakeref_asserts(dev_priv);
1479
1480         /* We do a lot of poking in a lot of registers, make sure they work
1481          * properly. */
1482         intel_display_set_init_power(dev_priv, true);
1483
1484         drm_kms_helper_poll_disable(dev);
1485
1486         pci_save_state(pdev);
1487
1488         error = i915_gem_suspend(dev_priv);
1489         if (error) {
1490                 dev_err(&pdev->dev,
1491                         "GEM idle failed, resume might fail\n");
1492                 goto out;
1493         }
1494
1495         intel_guc_suspend(dev_priv);
1496
1497         intel_display_suspend(dev);
1498
1499         intel_dp_mst_suspend(dev);
1500
1501         intel_runtime_pm_disable_interrupts(dev_priv);
1502         intel_hpd_cancel_work(dev_priv);
1503
1504         intel_suspend_encoders(dev_priv);
1505
1506         intel_suspend_hw(dev_priv);
1507
1508         i915_gem_suspend_gtt_mappings(dev_priv);
1509
1510         i915_save_state(dev_priv);
1511
1512         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1513         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1514
1515         intel_uncore_forcewake_reset(dev_priv, false);
1516         intel_opregion_unregister(dev_priv);
1517
1518         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1519
1520         dev_priv->suspend_count++;
1521
1522         intel_csr_ucode_suspend(dev_priv);
1523
1524 out:
1525         enable_rpm_wakeref_asserts(dev_priv);
1526
1527         return error;
1528 }
1529
1530 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(dev);
1533         struct pci_dev *pdev = dev_priv->drm.pdev;
1534         bool fw_csr;
1535         int ret;
1536
1537         disable_rpm_wakeref_asserts(dev_priv);
1538
1539         intel_display_set_init_power(dev_priv, false);
1540
1541         fw_csr = !IS_GEN9_LP(dev_priv) &&
1542                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1543         /*
1544          * In case of firmware assisted context save/restore don't manually
1545          * deinit the power domains. This also means the CSR/DMC firmware will
1546          * stay active, it will power down any HW resources as required and
1547          * also enable deeper system power states that would be blocked if the
1548          * firmware was inactive.
1549          */
1550         if (!fw_csr)
1551                 intel_power_domains_suspend(dev_priv);
1552
1553         ret = 0;
1554         if (IS_GEN9_LP(dev_priv))
1555                 bxt_enable_dc9(dev_priv);
1556         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1557                 hsw_enable_pc8(dev_priv);
1558         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1559                 ret = vlv_suspend_complete(dev_priv);
1560
1561         if (ret) {
1562                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1563                 if (!fw_csr)
1564                         intel_power_domains_init_hw(dev_priv, true);
1565
1566                 goto out;
1567         }
1568
1569         pci_disable_device(pdev);
1570         /*
1571          * During hibernation on some platforms the BIOS may try to access
1572          * the device even though it's already in D3 and hang the machine. So
1573          * leave the device in D0 on those platforms and hope the BIOS will
1574          * power down the device properly. The issue was seen on multiple old
1575          * GENs with different BIOS vendors, so having an explicit blacklist
1576          * is inpractical; apply the workaround on everything pre GEN6. The
1577          * platforms where the issue was seen:
1578          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1579          * Fujitsu FSC S7110
1580          * Acer Aspire 1830T
1581          */
1582         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1583                 pci_set_power_state(pdev, PCI_D3hot);
1584
1585         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1586
1587 out:
1588         enable_rpm_wakeref_asserts(dev_priv);
1589
1590         return ret;
1591 }
1592
1593 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1594 {
1595         int error;
1596
1597         if (!dev) {
1598                 DRM_ERROR("dev: %p\n", dev);
1599                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1600                 return -ENODEV;
1601         }
1602
1603         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1604                          state.event != PM_EVENT_FREEZE))
1605                 return -EINVAL;
1606
1607         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1608                 return 0;
1609
1610         error = i915_drm_suspend(dev);
1611         if (error)
1612                 return error;
1613
1614         return i915_drm_suspend_late(dev, false);
1615 }
1616
1617 static int i915_drm_resume(struct drm_device *dev)
1618 {
1619         struct drm_i915_private *dev_priv = to_i915(dev);
1620         int ret;
1621
1622         disable_rpm_wakeref_asserts(dev_priv);
1623         intel_sanitize_gt_powersave(dev_priv);
1624
1625         ret = i915_ggtt_enable_hw(dev_priv);
1626         if (ret)
1627                 DRM_ERROR("failed to re-enable GGTT\n");
1628
1629         intel_csr_ucode_resume(dev_priv);
1630
1631         i915_gem_resume(dev_priv);
1632
1633         i915_restore_state(dev_priv);
1634         intel_pps_unlock_regs_wa(dev_priv);
1635         intel_opregion_setup(dev_priv);
1636
1637         intel_init_pch_refclk(dev_priv);
1638
1639         /*
1640          * Interrupts have to be enabled before any batches are run. If not the
1641          * GPU will hang. i915_gem_init_hw() will initiate batches to
1642          * update/restore the context.
1643          *
1644          * drm_mode_config_reset() needs AUX interrupts.
1645          *
1646          * Modeset enabling in intel_modeset_init_hw() also needs working
1647          * interrupts.
1648          */
1649         intel_runtime_pm_enable_interrupts(dev_priv);
1650
1651         drm_mode_config_reset(dev);
1652
1653         mutex_lock(&dev->struct_mutex);
1654         if (i915_gem_init_hw(dev_priv)) {
1655                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1656                 i915_gem_set_wedged(dev_priv);
1657         }
1658         mutex_unlock(&dev->struct_mutex);
1659
1660         intel_guc_resume(dev_priv);
1661
1662         intel_modeset_init_hw(dev);
1663
1664         spin_lock_irq(&dev_priv->irq_lock);
1665         if (dev_priv->display.hpd_irq_setup)
1666                 dev_priv->display.hpd_irq_setup(dev_priv);
1667         spin_unlock_irq(&dev_priv->irq_lock);
1668
1669         intel_dp_mst_resume(dev);
1670
1671         intel_display_resume(dev);
1672
1673         drm_kms_helper_poll_enable(dev);
1674
1675         /*
1676          * ... but also need to make sure that hotplug processing
1677          * doesn't cause havoc. Like in the driver load code we don't
1678          * bother with the tiny race here where we might loose hotplug
1679          * notifications.
1680          * */
1681         intel_hpd_init(dev_priv);
1682
1683         intel_opregion_register(dev_priv);
1684
1685         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1686
1687         mutex_lock(&dev_priv->modeset_restore_lock);
1688         dev_priv->modeset_restore = MODESET_DONE;
1689         mutex_unlock(&dev_priv->modeset_restore_lock);
1690
1691         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1692
1693         intel_autoenable_gt_powersave(dev_priv);
1694
1695         enable_rpm_wakeref_asserts(dev_priv);
1696
1697         return 0;
1698 }
1699
1700 static int i915_drm_resume_early(struct drm_device *dev)
1701 {
1702         struct drm_i915_private *dev_priv = to_i915(dev);
1703         struct pci_dev *pdev = dev_priv->drm.pdev;
1704         int ret;
1705
1706         /*
1707          * We have a resume ordering issue with the snd-hda driver also
1708          * requiring our device to be power up. Due to the lack of a
1709          * parent/child relationship we currently solve this with an early
1710          * resume hook.
1711          *
1712          * FIXME: This should be solved with a special hdmi sink device or
1713          * similar so that power domains can be employed.
1714          */
1715
1716         /*
1717          * Note that we need to set the power state explicitly, since we
1718          * powered off the device during freeze and the PCI core won't power
1719          * it back up for us during thaw. Powering off the device during
1720          * freeze is not a hard requirement though, and during the
1721          * suspend/resume phases the PCI core makes sure we get here with the
1722          * device powered on. So in case we change our freeze logic and keep
1723          * the device powered we can also remove the following set power state
1724          * call.
1725          */
1726         ret = pci_set_power_state(pdev, PCI_D0);
1727         if (ret) {
1728                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1729                 goto out;
1730         }
1731
1732         /*
1733          * Note that pci_enable_device() first enables any parent bridge
1734          * device and only then sets the power state for this device. The
1735          * bridge enabling is a nop though, since bridge devices are resumed
1736          * first. The order of enabling power and enabling the device is
1737          * imposed by the PCI core as described above, so here we preserve the
1738          * same order for the freeze/thaw phases.
1739          *
1740          * TODO: eventually we should remove pci_disable_device() /
1741          * pci_enable_enable_device() from suspend/resume. Due to how they
1742          * depend on the device enable refcount we can't anyway depend on them
1743          * disabling/enabling the device.
1744          */
1745         if (pci_enable_device(pdev)) {
1746                 ret = -EIO;
1747                 goto out;
1748         }
1749
1750         pci_set_master(pdev);
1751
1752         disable_rpm_wakeref_asserts(dev_priv);
1753
1754         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1755                 ret = vlv_resume_prepare(dev_priv, false);
1756         if (ret)
1757                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1758                           ret);
1759
1760         intel_uncore_early_sanitize(dev_priv, true);
1761
1762         if (IS_GEN9_LP(dev_priv)) {
1763                 if (!dev_priv->suspended_to_idle)
1764                         gen9_sanitize_dc_state(dev_priv);
1765                 bxt_disable_dc9(dev_priv);
1766         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1767                 hsw_disable_pc8(dev_priv);
1768         }
1769
1770         intel_uncore_sanitize(dev_priv);
1771
1772         if (IS_GEN9_LP(dev_priv) ||
1773             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1774                 intel_power_domains_init_hw(dev_priv, true);
1775
1776         i915_gem_sanitize(dev_priv);
1777
1778         enable_rpm_wakeref_asserts(dev_priv);
1779
1780 out:
1781         dev_priv->suspended_to_idle = false;
1782
1783         return ret;
1784 }
1785
1786 static int i915_resume_switcheroo(struct drm_device *dev)
1787 {
1788         int ret;
1789
1790         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1791                 return 0;
1792
1793         ret = i915_drm_resume_early(dev);
1794         if (ret)
1795                 return ret;
1796
1797         return i915_drm_resume(dev);
1798 }
1799
1800 /**
1801  * i915_reset - reset chip after a hang
1802  * @dev_priv: device private to reset
1803  *
1804  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1805  * on failure.
1806  *
1807  * Caller must hold the struct_mutex.
1808  *
1809  * Procedure is fairly simple:
1810  *   - reset the chip using the reset reg
1811  *   - re-init context state
1812  *   - re-init hardware status page
1813  *   - re-init ring buffer
1814  *   - re-init interrupt state
1815  *   - re-init display
1816  */
1817 void i915_reset(struct drm_i915_private *dev_priv)
1818 {
1819         struct i915_gpu_error *error = &dev_priv->gpu_error;
1820         int ret;
1821
1822         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1823
1824         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1825                 return;
1826
1827         /* Clear any previous failed attempts at recovery. Time to try again. */
1828         __clear_bit(I915_WEDGED, &error->flags);
1829         error->reset_count++;
1830
1831         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1832         disable_irq(dev_priv->drm.irq);
1833         ret = i915_gem_reset_prepare(dev_priv);
1834         if (ret) {
1835                 DRM_ERROR("GPU recovery failed\n");
1836                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1837                 goto error;
1838         }
1839
1840         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1841         if (ret) {
1842                 if (ret != -ENODEV)
1843                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1844                 else
1845                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1846                 goto error;
1847         }
1848
1849         i915_gem_reset(dev_priv);
1850         intel_overlay_reset(dev_priv);
1851
1852         /* Ok, now get things going again... */
1853
1854         /*
1855          * Everything depends on having the GTT running, so we need to start
1856          * there.  Fortunately we don't need to do this unless we reset the
1857          * chip at a PCI level.
1858          *
1859          * Next we need to restore the context, but we don't use those
1860          * yet either...
1861          *
1862          * Ring buffer needs to be re-initialized in the KMS case, or if X
1863          * was running at the time of the reset (i.e. we weren't VT
1864          * switched away).
1865          */
1866         ret = i915_gem_init_hw(dev_priv);
1867         if (ret) {
1868                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1869                 goto error;
1870         }
1871
1872         i915_queue_hangcheck(dev_priv);
1873
1874 wakeup:
1875         i915_gem_reset_finish(dev_priv);
1876         enable_irq(dev_priv->drm.irq);
1877         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1878         return;
1879
1880 error:
1881         i915_gem_set_wedged(dev_priv);
1882         goto wakeup;
1883 }
1884
1885 static int i915_pm_suspend(struct device *kdev)
1886 {
1887         struct pci_dev *pdev = to_pci_dev(kdev);
1888         struct drm_device *dev = pci_get_drvdata(pdev);
1889
1890         if (!dev) {
1891                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1892                 return -ENODEV;
1893         }
1894
1895         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1896                 return 0;
1897
1898         return i915_drm_suspend(dev);
1899 }
1900
1901 static int i915_pm_suspend_late(struct device *kdev)
1902 {
1903         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1904
1905         /*
1906          * We have a suspend ordering issue with the snd-hda driver also
1907          * requiring our device to be power up. Due to the lack of a
1908          * parent/child relationship we currently solve this with an late
1909          * suspend hook.
1910          *
1911          * FIXME: This should be solved with a special hdmi sink device or
1912          * similar so that power domains can be employed.
1913          */
1914         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1915                 return 0;
1916
1917         return i915_drm_suspend_late(dev, false);
1918 }
1919
1920 static int i915_pm_poweroff_late(struct device *kdev)
1921 {
1922         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1923
1924         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1925                 return 0;
1926
1927         return i915_drm_suspend_late(dev, true);
1928 }
1929
1930 static int i915_pm_resume_early(struct device *kdev)
1931 {
1932         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1933
1934         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1935                 return 0;
1936
1937         return i915_drm_resume_early(dev);
1938 }
1939
1940 static int i915_pm_resume(struct device *kdev)
1941 {
1942         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1943
1944         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1945                 return 0;
1946
1947         return i915_drm_resume(dev);
1948 }
1949
1950 /* freeze: before creating the hibernation_image */
1951 static int i915_pm_freeze(struct device *kdev)
1952 {
1953         int ret;
1954
1955         ret = i915_pm_suspend(kdev);
1956         if (ret)
1957                 return ret;
1958
1959         ret = i915_gem_freeze(kdev_to_i915(kdev));
1960         if (ret)
1961                 return ret;
1962
1963         return 0;
1964 }
1965
1966 static int i915_pm_freeze_late(struct device *kdev)
1967 {
1968         int ret;
1969
1970         ret = i915_pm_suspend_late(kdev);
1971         if (ret)
1972                 return ret;
1973
1974         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1975         if (ret)
1976                 return ret;
1977
1978         return 0;
1979 }
1980
1981 /* thaw: called after creating the hibernation image, but before turning off. */
1982 static int i915_pm_thaw_early(struct device *kdev)
1983 {
1984         return i915_pm_resume_early(kdev);
1985 }
1986
1987 static int i915_pm_thaw(struct device *kdev)
1988 {
1989         return i915_pm_resume(kdev);
1990 }
1991
1992 /* restore: called after loading the hibernation image. */
1993 static int i915_pm_restore_early(struct device *kdev)
1994 {
1995         return i915_pm_resume_early(kdev);
1996 }
1997
1998 static int i915_pm_restore(struct device *kdev)
1999 {
2000         return i915_pm_resume(kdev);
2001 }
2002
2003 /*
2004  * Save all Gunit registers that may be lost after a D3 and a subsequent
2005  * S0i[R123] transition. The list of registers needing a save/restore is
2006  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2007  * registers in the following way:
2008  * - Driver: saved/restored by the driver
2009  * - Punit : saved/restored by the Punit firmware
2010  * - No, w/o marking: no need to save/restore, since the register is R/O or
2011  *                    used internally by the HW in a way that doesn't depend
2012  *                    keeping the content across a suspend/resume.
2013  * - Debug : used for debugging
2014  *
2015  * We save/restore all registers marked with 'Driver', with the following
2016  * exceptions:
2017  * - Registers out of use, including also registers marked with 'Debug'.
2018  *   These have no effect on the driver's operation, so we don't save/restore
2019  *   them to reduce the overhead.
2020  * - Registers that are fully setup by an initialization function called from
2021  *   the resume path. For example many clock gating and RPS/RC6 registers.
2022  * - Registers that provide the right functionality with their reset defaults.
2023  *
2024  * TODO: Except for registers that based on the above 3 criteria can be safely
2025  * ignored, we save/restore all others, practically treating the HW context as
2026  * a black-box for the driver. Further investigation is needed to reduce the
2027  * saved/restored registers even further, by following the same 3 criteria.
2028  */
2029 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2030 {
2031         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2032         int i;
2033
2034         /* GAM 0x4000-0x4770 */
2035         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2036         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2037         s->arb_mode             = I915_READ(ARB_MODE);
2038         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2039         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2040
2041         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2042                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2043
2044         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2045         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2046
2047         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2048         s->ecochk               = I915_READ(GAM_ECOCHK);
2049         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2050         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2051
2052         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2053
2054         /* MBC 0x9024-0x91D0, 0x8500 */
2055         s->g3dctl               = I915_READ(VLV_G3DCTL);
2056         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2057         s->mbctl                = I915_READ(GEN6_MBCTL);
2058
2059         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2060         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2061         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2062         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2063         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2064         s->rstctl               = I915_READ(GEN6_RSTCTL);
2065         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2066
2067         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2068         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2069         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2070         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2071         s->ecobus               = I915_READ(ECOBUS);
2072         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2073         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2074         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2075         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2076         s->rcedata              = I915_READ(VLV_RCEDATA);
2077         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2078
2079         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2080         s->gt_imr               = I915_READ(GTIMR);
2081         s->gt_ier               = I915_READ(GTIER);
2082         s->pm_imr               = I915_READ(GEN6_PMIMR);
2083         s->pm_ier               = I915_READ(GEN6_PMIER);
2084
2085         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2086                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2087
2088         /* GT SA CZ domain, 0x100000-0x138124 */
2089         s->tilectl              = I915_READ(TILECTL);
2090         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2091         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2092         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2093         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2094
2095         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2096         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2097         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2098         s->pcbr                 = I915_READ(VLV_PCBR);
2099         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2100
2101         /*
2102          * Not saving any of:
2103          * DFT,         0x9800-0x9EC0
2104          * SARB,        0xB000-0xB1FC
2105          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2106          * PCI CFG
2107          */
2108 }
2109
2110 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2111 {
2112         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2113         u32 val;
2114         int i;
2115
2116         /* GAM 0x4000-0x4770 */
2117         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2118         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2119         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2120         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2121         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2122
2123         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2124                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2125
2126         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2127         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2128
2129         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2130         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2131         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2132         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2133
2134         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2135
2136         /* MBC 0x9024-0x91D0, 0x8500 */
2137         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2138         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2139         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2140
2141         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2142         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2143         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2144         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2145         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2146         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2147         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2148
2149         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2150         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2151         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2152         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2153         I915_WRITE(ECOBUS,              s->ecobus);
2154         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2155         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2156         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2157         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2158         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2159         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2160
2161         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2162         I915_WRITE(GTIMR,               s->gt_imr);
2163         I915_WRITE(GTIER,               s->gt_ier);
2164         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2165         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2166
2167         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2168                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2169
2170         /* GT SA CZ domain, 0x100000-0x138124 */
2171         I915_WRITE(TILECTL,                     s->tilectl);
2172         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2173         /*
2174          * Preserve the GT allow wake and GFX force clock bit, they are not
2175          * be restored, as they are used to control the s0ix suspend/resume
2176          * sequence by the caller.
2177          */
2178         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2179         val &= VLV_GTLC_ALLOWWAKEREQ;
2180         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2181         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2182
2183         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2184         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2185         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2186         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2187
2188         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2189
2190         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2191         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2192         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2193         I915_WRITE(VLV_PCBR,                    s->pcbr);
2194         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2195 }
2196
2197 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2198 {
2199         u32 val;
2200         int err;
2201
2202         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2203         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2204         if (force_on)
2205                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2206         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2207
2208         if (!force_on)
2209                 return 0;
2210
2211         err = intel_wait_for_register(dev_priv,
2212                                       VLV_GTLC_SURVIVABILITY_REG,
2213                                       VLV_GFX_CLK_STATUS_BIT,
2214                                       VLV_GFX_CLK_STATUS_BIT,
2215                                       20);
2216         if (err)
2217                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2218                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2219
2220         return err;
2221 }
2222
2223 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2224 {
2225         u32 val;
2226         int err = 0;
2227
2228         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2229         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2230         if (allow)
2231                 val |= VLV_GTLC_ALLOWWAKEREQ;
2232         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2233         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2234
2235         err = intel_wait_for_register(dev_priv,
2236                                       VLV_GTLC_PW_STATUS,
2237                                       VLV_GTLC_ALLOWWAKEACK,
2238                                       allow,
2239                                       1);
2240         if (err)
2241                 DRM_ERROR("timeout disabling GT waking\n");
2242
2243         return err;
2244 }
2245
2246 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2247                                  bool wait_for_on)
2248 {
2249         u32 mask;
2250         u32 val;
2251         int err;
2252
2253         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2254         val = wait_for_on ? mask : 0;
2255         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2256                 return 0;
2257
2258         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2259                       onoff(wait_for_on),
2260                       I915_READ(VLV_GTLC_PW_STATUS));
2261
2262         /*
2263          * RC6 transitioning can be delayed up to 2 msec (see
2264          * valleyview_enable_rps), use 3 msec for safety.
2265          */
2266         err = intel_wait_for_register(dev_priv,
2267                                       VLV_GTLC_PW_STATUS, mask, val,
2268                                       3);
2269         if (err)
2270                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2271                           onoff(wait_for_on));
2272
2273         return err;
2274 }
2275
2276 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2277 {
2278         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2279                 return;
2280
2281         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2282         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2283 }
2284
2285 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2286 {
2287         u32 mask;
2288         int err;
2289
2290         /*
2291          * Bspec defines the following GT well on flags as debug only, so
2292          * don't treat them as hard failures.
2293          */
2294         (void)vlv_wait_for_gt_wells(dev_priv, false);
2295
2296         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2297         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2298
2299         vlv_check_no_gt_access(dev_priv);
2300
2301         err = vlv_force_gfx_clock(dev_priv, true);
2302         if (err)
2303                 goto err1;
2304
2305         err = vlv_allow_gt_wake(dev_priv, false);
2306         if (err)
2307                 goto err2;
2308
2309         if (!IS_CHERRYVIEW(dev_priv))
2310                 vlv_save_gunit_s0ix_state(dev_priv);
2311
2312         err = vlv_force_gfx_clock(dev_priv, false);
2313         if (err)
2314                 goto err2;
2315
2316         return 0;
2317
2318 err2:
2319         /* For safety always re-enable waking and disable gfx clock forcing */
2320         vlv_allow_gt_wake(dev_priv, true);
2321 err1:
2322         vlv_force_gfx_clock(dev_priv, false);
2323
2324         return err;
2325 }
2326
2327 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2328                                 bool rpm_resume)
2329 {
2330         int err;
2331         int ret;
2332
2333         /*
2334          * If any of the steps fail just try to continue, that's the best we
2335          * can do at this point. Return the first error code (which will also
2336          * leave RPM permanently disabled).
2337          */
2338         ret = vlv_force_gfx_clock(dev_priv, true);
2339
2340         if (!IS_CHERRYVIEW(dev_priv))
2341                 vlv_restore_gunit_s0ix_state(dev_priv);
2342
2343         err = vlv_allow_gt_wake(dev_priv, true);
2344         if (!ret)
2345                 ret = err;
2346
2347         err = vlv_force_gfx_clock(dev_priv, false);
2348         if (!ret)
2349                 ret = err;
2350
2351         vlv_check_no_gt_access(dev_priv);
2352
2353         if (rpm_resume)
2354                 intel_init_clock_gating(dev_priv);
2355
2356         return ret;
2357 }
2358
2359 static int intel_runtime_suspend(struct device *kdev)
2360 {
2361         struct pci_dev *pdev = to_pci_dev(kdev);
2362         struct drm_device *dev = pci_get_drvdata(pdev);
2363         struct drm_i915_private *dev_priv = to_i915(dev);
2364         int ret;
2365
2366         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2367                 return -ENODEV;
2368
2369         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2370                 return -ENODEV;
2371
2372         DRM_DEBUG_KMS("Suspending device\n");
2373
2374         disable_rpm_wakeref_asserts(dev_priv);
2375
2376         /*
2377          * We are safe here against re-faults, since the fault handler takes
2378          * an RPM reference.
2379          */
2380         i915_gem_runtime_suspend(dev_priv);
2381
2382         intel_guc_suspend(dev_priv);
2383
2384         intel_runtime_pm_disable_interrupts(dev_priv);
2385
2386         ret = 0;
2387         if (IS_GEN9_LP(dev_priv)) {
2388                 bxt_display_core_uninit(dev_priv);
2389                 bxt_enable_dc9(dev_priv);
2390         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2391                 hsw_enable_pc8(dev_priv);
2392         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2393                 ret = vlv_suspend_complete(dev_priv);
2394         }
2395
2396         if (ret) {
2397                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2398                 intel_runtime_pm_enable_interrupts(dev_priv);
2399
2400                 enable_rpm_wakeref_asserts(dev_priv);
2401
2402                 return ret;
2403         }
2404
2405         intel_uncore_forcewake_reset(dev_priv, false);
2406
2407         enable_rpm_wakeref_asserts(dev_priv);
2408         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2409
2410         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2411                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2412
2413         dev_priv->pm.suspended = true;
2414
2415         /*
2416          * FIXME: We really should find a document that references the arguments
2417          * used below!
2418          */
2419         if (IS_BROADWELL(dev_priv)) {
2420                 /*
2421                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2422                  * being detected, and the call we do at intel_runtime_resume()
2423                  * won't be able to restore them. Since PCI_D3hot matches the
2424                  * actual specification and appears to be working, use it.
2425                  */
2426                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2427         } else {
2428                 /*
2429                  * current versions of firmware which depend on this opregion
2430                  * notification have repurposed the D1 definition to mean
2431                  * "runtime suspended" vs. what you would normally expect (D3)
2432                  * to distinguish it from notifications that might be sent via
2433                  * the suspend path.
2434                  */
2435                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2436         }
2437
2438         assert_forcewakes_inactive(dev_priv);
2439
2440         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2441                 intel_hpd_poll_init(dev_priv);
2442
2443         DRM_DEBUG_KMS("Device suspended\n");
2444         return 0;
2445 }
2446
2447 static int intel_runtime_resume(struct device *kdev)
2448 {
2449         struct pci_dev *pdev = to_pci_dev(kdev);
2450         struct drm_device *dev = pci_get_drvdata(pdev);
2451         struct drm_i915_private *dev_priv = to_i915(dev);
2452         int ret = 0;
2453
2454         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2455                 return -ENODEV;
2456
2457         DRM_DEBUG_KMS("Resuming device\n");
2458
2459         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2460         disable_rpm_wakeref_asserts(dev_priv);
2461
2462         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2463         dev_priv->pm.suspended = false;
2464         if (intel_uncore_unclaimed_mmio(dev_priv))
2465                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2466
2467         intel_guc_resume(dev_priv);
2468
2469         if (IS_GEN6(dev_priv))
2470                 intel_init_pch_refclk(dev_priv);
2471
2472         if (IS_GEN9_LP(dev_priv)) {
2473                 bxt_disable_dc9(dev_priv);
2474                 bxt_display_core_init(dev_priv, true);
2475                 if (dev_priv->csr.dmc_payload &&
2476                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2477                         gen9_enable_dc5(dev_priv);
2478         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2479                 hsw_disable_pc8(dev_priv);
2480         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2481                 ret = vlv_resume_prepare(dev_priv, true);
2482         }
2483
2484         /*
2485          * No point of rolling back things in case of an error, as the best
2486          * we can do is to hope that things will still work (and disable RPM).
2487          */
2488         i915_gem_init_swizzling(dev_priv);
2489         i915_gem_restore_fences(dev_priv);
2490
2491         intel_runtime_pm_enable_interrupts(dev_priv);
2492
2493         /*
2494          * On VLV/CHV display interrupts are part of the display
2495          * power well, so hpd is reinitialized from there. For
2496          * everyone else do it here.
2497          */
2498         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2499                 intel_hpd_init(dev_priv);
2500
2501         enable_rpm_wakeref_asserts(dev_priv);
2502
2503         if (ret)
2504                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2505         else
2506                 DRM_DEBUG_KMS("Device resumed\n");
2507
2508         return ret;
2509 }
2510
2511 const struct dev_pm_ops i915_pm_ops = {
2512         /*
2513          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2514          * PMSG_RESUME]
2515          */
2516         .suspend = i915_pm_suspend,
2517         .suspend_late = i915_pm_suspend_late,
2518         .resume_early = i915_pm_resume_early,
2519         .resume = i915_pm_resume,
2520
2521         /*
2522          * S4 event handlers
2523          * @freeze, @freeze_late    : called (1) before creating the
2524          *                            hibernation image [PMSG_FREEZE] and
2525          *                            (2) after rebooting, before restoring
2526          *                            the image [PMSG_QUIESCE]
2527          * @thaw, @thaw_early       : called (1) after creating the hibernation
2528          *                            image, before writing it [PMSG_THAW]
2529          *                            and (2) after failing to create or
2530          *                            restore the image [PMSG_RECOVER]
2531          * @poweroff, @poweroff_late: called after writing the hibernation
2532          *                            image, before rebooting [PMSG_HIBERNATE]
2533          * @restore, @restore_early : called after rebooting and restoring the
2534          *                            hibernation image [PMSG_RESTORE]
2535          */
2536         .freeze = i915_pm_freeze,
2537         .freeze_late = i915_pm_freeze_late,
2538         .thaw_early = i915_pm_thaw_early,
2539         .thaw = i915_pm_thaw,
2540         .poweroff = i915_pm_suspend,
2541         .poweroff_late = i915_pm_poweroff_late,
2542         .restore_early = i915_pm_restore_early,
2543         .restore = i915_pm_restore,
2544
2545         /* S0ix (via runtime suspend) event handlers */
2546         .runtime_suspend = intel_runtime_suspend,
2547         .runtime_resume = intel_runtime_resume,
2548 };
2549
2550 static const struct vm_operations_struct i915_gem_vm_ops = {
2551         .fault = i915_gem_fault,
2552         .open = drm_gem_vm_open,
2553         .close = drm_gem_vm_close,
2554 };
2555
2556 static const struct file_operations i915_driver_fops = {
2557         .owner = THIS_MODULE,
2558         .open = drm_open,
2559         .release = drm_release,
2560         .unlocked_ioctl = drm_ioctl,
2561         .mmap = drm_gem_mmap,
2562         .poll = drm_poll,
2563         .read = drm_read,
2564         .compat_ioctl = i915_compat_ioctl,
2565         .llseek = noop_llseek,
2566 };
2567
2568 static int
2569 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2570                           struct drm_file *file)
2571 {
2572         return -ENODEV;
2573 }
2574
2575 static const struct drm_ioctl_desc i915_ioctls[] = {
2576         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2577         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2578         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2579         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2580         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2581         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2582         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2583         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2584         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2585         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2586         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2587         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2588         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2589         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2590         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2591         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2592         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2595         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2597         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2600         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2603         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2606         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2607         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2611         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2612         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2613         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2614         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2616         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2617         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2618         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2621         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2622         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2623         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2624         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2625         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2626         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2627         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2628         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2629 };
2630
2631 static struct drm_driver driver = {
2632         /* Don't use MTRRs here; the Xserver or userspace app should
2633          * deal with them for Intel hardware.
2634          */
2635         .driver_features =
2636             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2637             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2638         .release = i915_driver_release,
2639         .open = i915_driver_open,
2640         .lastclose = i915_driver_lastclose,
2641         .preclose = i915_driver_preclose,
2642         .postclose = i915_driver_postclose,
2643         .set_busid = drm_pci_set_busid,
2644
2645         .gem_close_object = i915_gem_close_object,
2646         .gem_free_object_unlocked = i915_gem_free_object,
2647         .gem_vm_ops = &i915_gem_vm_ops,
2648
2649         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2650         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2651         .gem_prime_export = i915_gem_prime_export,
2652         .gem_prime_import = i915_gem_prime_import,
2653
2654         .dumb_create = i915_gem_dumb_create,
2655         .dumb_map_offset = i915_gem_mmap_gtt,
2656         .dumb_destroy = drm_gem_dumb_destroy,
2657         .ioctls = i915_ioctls,
2658         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2659         .fops = &i915_driver_fops,
2660         .name = DRIVER_NAME,
2661         .desc = DRIVER_DESC,
2662         .date = DRIVER_DATE,
2663         .major = DRIVER_MAJOR,
2664         .minor = DRIVER_MINOR,
2665         .patchlevel = DRIVER_PATCHLEVEL,
2666 };
2667
2668 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2669 #include "selftests/mock_drm.c"
2670 #endif