1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
52 #include "i915_query.h"
53 #include "i915_vgpu.h"
54 #include "intel_drv.h"
57 static struct drm_driver driver;
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60 static unsigned int i915_load_fail_count;
62 bool __i915_inject_load_failure(const char *func, int line)
64 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
67 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
68 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
69 i915_modparams.inject_load_failure, func, line);
70 i915_modparams.inject_load_failure = 0;
77 bool i915_error_injected(void)
79 return i915_load_fail_count && !i915_modparams.inject_load_failure;
84 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
85 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
86 "providing the dmesg log by booting with drm.debug=0xf"
89 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
92 static bool shown_bug_once;
93 struct device *kdev = dev_priv->drm.dev;
94 bool is_error = level[1] <= KERN_ERR[1];
95 bool is_debug = level[1] == KERN_DEBUG[1];
99 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
108 dev_printk(level, kdev, "%pV", &vaf);
110 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
111 __builtin_return_address(0), &vaf);
115 if (is_error && !shown_bug_once) {
117 * Ask the user to file a bug report for the error, except
118 * if they may have caused the bug by fiddling with unsafe
121 if (!test_taint(TAINT_USER))
122 dev_notice(kdev, "%s", FDO_BUG_MSG);
123 shown_bug_once = true;
127 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
128 static enum intel_pch
129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
132 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
133 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
134 WARN_ON(!IS_GEN5(dev_priv));
136 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
137 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
138 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
140 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
141 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
142 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
143 /* PantherPoint is CPT compatible */
145 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
146 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
147 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
148 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
150 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
151 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
152 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
153 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
155 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
156 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
157 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
158 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
159 /* WildcatPoint is LPT compatible */
161 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
162 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
163 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
164 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
165 /* WildcatPoint is LPT compatible */
167 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
168 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
169 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
171 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
172 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
173 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
175 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
176 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
177 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
178 !IS_COFFEELAKE(dev_priv));
180 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
181 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
182 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
184 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
185 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
186 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
188 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
189 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
190 WARN_ON(!IS_ICELAKE(dev_priv));
197 static bool intel_is_virt_pch(unsigned short id,
198 unsigned short svendor, unsigned short sdevice)
200 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
201 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
202 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
203 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
204 sdevice == PCI_SUBDEVICE_ID_QEMU));
207 static unsigned short
208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
210 unsigned short id = 0;
213 * In a virtualized passthrough environment we can be in a
214 * setup where the ISA bridge is not able to be passed through.
215 * In this case, a south bridge can be emulated and we have to
216 * make an educated guess as to which PCH is really there.
219 if (IS_GEN5(dev_priv))
220 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
221 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
222 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
223 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
224 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
225 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
226 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
227 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
228 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
229 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
230 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
231 else if (IS_ICELAKE(dev_priv))
232 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
235 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
237 DRM_DEBUG_KMS("Assuming no PCH\n");
242 static void intel_detect_pch(struct drm_i915_private *dev_priv)
244 struct pci_dev *pch = NULL;
247 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
248 * make graphics device passthrough work easy for VMM, that only
249 * need to expose ISA bridge to let driver know the real hardware
250 * underneath. This is a requirement from virtualization team.
252 * In some virtualized environments (e.g. XEN), there is irrelevant
253 * ISA bridge in the system. To work reliably, we should scan trhough
254 * all the ISA bridge devices and check for the first match, instead
255 * of only checking the first one.
257 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
259 enum intel_pch pch_type;
261 if (pch->vendor != PCI_VENDOR_ID_INTEL)
264 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
266 pch_type = intel_pch_type(dev_priv, id);
267 if (pch_type != PCH_NONE) {
268 dev_priv->pch_type = pch_type;
269 dev_priv->pch_id = id;
271 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
272 pch->subsystem_device)) {
273 id = intel_virt_detect_pch(dev_priv);
274 pch_type = intel_pch_type(dev_priv, id);
276 /* Sanity check virtual PCH id */
277 if (WARN_ON(id && pch_type == PCH_NONE))
280 dev_priv->pch_type = pch_type;
281 dev_priv->pch_id = id;
287 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
290 if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
291 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
292 dev_priv->pch_type = PCH_NOP;
293 dev_priv->pch_id = 0;
297 DRM_DEBUG_KMS("No PCH found.\n");
302 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
303 struct drm_file *file_priv)
305 struct drm_i915_private *dev_priv = to_i915(dev);
306 struct pci_dev *pdev = dev_priv->drm.pdev;
307 drm_i915_getparam_t *param = data;
310 switch (param->param) {
311 case I915_PARAM_IRQ_ACTIVE:
312 case I915_PARAM_ALLOW_BATCHBUFFER:
313 case I915_PARAM_LAST_DISPATCH:
314 case I915_PARAM_HAS_EXEC_CONSTANTS:
315 /* Reject all old ums/dri params. */
317 case I915_PARAM_CHIPSET_ID:
318 value = pdev->device;
320 case I915_PARAM_REVISION:
321 value = pdev->revision;
323 case I915_PARAM_NUM_FENCES_AVAIL:
324 value = dev_priv->num_fence_regs;
326 case I915_PARAM_HAS_OVERLAY:
327 value = dev_priv->overlay ? 1 : 0;
329 case I915_PARAM_HAS_BSD:
330 value = !!dev_priv->engine[VCS];
332 case I915_PARAM_HAS_BLT:
333 value = !!dev_priv->engine[BCS];
335 case I915_PARAM_HAS_VEBOX:
336 value = !!dev_priv->engine[VECS];
338 case I915_PARAM_HAS_BSD2:
339 value = !!dev_priv->engine[VCS2];
341 case I915_PARAM_HAS_LLC:
342 value = HAS_LLC(dev_priv);
344 case I915_PARAM_HAS_WT:
345 value = HAS_WT(dev_priv);
347 case I915_PARAM_HAS_ALIASING_PPGTT:
348 value = USES_PPGTT(dev_priv);
350 case I915_PARAM_HAS_SEMAPHORES:
351 value = HAS_LEGACY_SEMAPHORES(dev_priv);
353 case I915_PARAM_HAS_SECURE_BATCHES:
354 value = capable(CAP_SYS_ADMIN);
356 case I915_PARAM_CMD_PARSER_VERSION:
357 value = i915_cmd_parser_get_version(dev_priv);
359 case I915_PARAM_SUBSLICE_TOTAL:
360 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
364 case I915_PARAM_EU_TOTAL:
365 value = INTEL_INFO(dev_priv)->sseu.eu_total;
369 case I915_PARAM_HAS_GPU_RESET:
370 value = i915_modparams.enable_hangcheck &&
371 intel_has_gpu_reset(dev_priv);
372 if (value && intel_has_reset_engine(dev_priv))
375 case I915_PARAM_HAS_RESOURCE_STREAMER:
378 case I915_PARAM_HAS_POOLED_EU:
379 value = HAS_POOLED_EU(dev_priv);
381 case I915_PARAM_MIN_EU_IN_POOL:
382 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
384 case I915_PARAM_HUC_STATUS:
385 value = intel_huc_check_status(&dev_priv->huc);
389 case I915_PARAM_MMAP_GTT_VERSION:
390 /* Though we've started our numbering from 1, and so class all
391 * earlier versions as 0, in effect their value is undefined as
392 * the ioctl will report EINVAL for the unknown param!
394 value = i915_gem_mmap_gtt_version();
396 case I915_PARAM_HAS_SCHEDULER:
397 value = dev_priv->caps.scheduler;
400 case I915_PARAM_MMAP_VERSION:
401 /* Remember to bump this if the version changes! */
402 case I915_PARAM_HAS_GEM:
403 case I915_PARAM_HAS_PAGEFLIPPING:
404 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
405 case I915_PARAM_HAS_RELAXED_FENCING:
406 case I915_PARAM_HAS_COHERENT_RINGS:
407 case I915_PARAM_HAS_RELAXED_DELTA:
408 case I915_PARAM_HAS_GEN7_SOL_RESET:
409 case I915_PARAM_HAS_WAIT_TIMEOUT:
410 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
411 case I915_PARAM_HAS_PINNED_BATCHES:
412 case I915_PARAM_HAS_EXEC_NO_RELOC:
413 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
414 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
415 case I915_PARAM_HAS_EXEC_SOFTPIN:
416 case I915_PARAM_HAS_EXEC_ASYNC:
417 case I915_PARAM_HAS_EXEC_FENCE:
418 case I915_PARAM_HAS_EXEC_CAPTURE:
419 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
420 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
421 /* For the time being all of these are always true;
422 * if some supported hardware does not have one of these
423 * features this value needs to be provided from
424 * INTEL_INFO(), a feature macro, or similar.
428 case I915_PARAM_HAS_CONTEXT_ISOLATION:
429 value = intel_engines_has_context_isolation(dev_priv);
431 case I915_PARAM_SLICE_MASK:
432 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
436 case I915_PARAM_SUBSLICE_MASK:
437 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
441 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
442 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
444 case I915_PARAM_MMAP_GTT_COHERENT:
445 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
448 DRM_DEBUG("Unknown parameter %d\n", param->param);
452 if (put_user(value, param->value))
458 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
460 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
462 dev_priv->bridge_dev =
463 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
464 if (!dev_priv->bridge_dev) {
465 DRM_ERROR("bridge device not found\n");
471 /* Allocate space for the MCH regs if needed, return nonzero on error */
473 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
475 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
476 u32 temp_lo, temp_hi = 0;
480 if (INTEL_GEN(dev_priv) >= 4)
481 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
482 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
483 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
485 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
488 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
492 /* Get some space for it */
493 dev_priv->mch_res.name = "i915 MCHBAR";
494 dev_priv->mch_res.flags = IORESOURCE_MEM;
495 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
497 MCHBAR_SIZE, MCHBAR_SIZE,
499 0, pcibios_align_resource,
500 dev_priv->bridge_dev);
502 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
503 dev_priv->mch_res.start = 0;
507 if (INTEL_GEN(dev_priv) >= 4)
508 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
509 upper_32_bits(dev_priv->mch_res.start));
511 pci_write_config_dword(dev_priv->bridge_dev, reg,
512 lower_32_bits(dev_priv->mch_res.start));
516 /* Setup MCHBAR if possible, return true if we should disable it again */
518 intel_setup_mchbar(struct drm_i915_private *dev_priv)
520 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
524 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
527 dev_priv->mchbar_need_disable = false;
529 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
530 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
531 enabled = !!(temp & DEVEN_MCHBAR_EN);
533 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
537 /* If it's already enabled, don't have to do anything */
541 if (intel_alloc_mchbar_resource(dev_priv))
544 dev_priv->mchbar_need_disable = true;
546 /* Space is allocated or reserved, so enable it. */
547 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
548 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
549 temp | DEVEN_MCHBAR_EN);
551 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
552 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
557 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
559 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
561 if (dev_priv->mchbar_need_disable) {
562 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
565 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
567 deven_val &= ~DEVEN_MCHBAR_EN;
568 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
573 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
576 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
581 if (dev_priv->mch_res.start)
582 release_resource(&dev_priv->mch_res);
585 /* true = enable decode, false = disable decoder */
586 static unsigned int i915_vga_set_decode(void *cookie, bool state)
588 struct drm_i915_private *dev_priv = cookie;
590 intel_modeset_vga_set_state(dev_priv, state);
592 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
593 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
595 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
598 static int i915_resume_switcheroo(struct drm_device *dev);
599 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
601 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
603 struct drm_device *dev = pci_get_drvdata(pdev);
604 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
606 if (state == VGA_SWITCHEROO_ON) {
607 pr_info("switched on\n");
608 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
609 /* i915 resume handler doesn't set to D0 */
610 pci_set_power_state(pdev, PCI_D0);
611 i915_resume_switcheroo(dev);
612 dev->switch_power_state = DRM_SWITCH_POWER_ON;
614 pr_info("switched off\n");
615 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
616 i915_suspend_switcheroo(dev, pmm);
617 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
621 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
623 struct drm_device *dev = pci_get_drvdata(pdev);
626 * FIXME: open_count is protected by drm_global_mutex but that would lead to
627 * locking inversion with the driver load path. And the access here is
628 * completely racy anyway. So don't bother with locking for now.
630 return dev->open_count == 0;
633 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
634 .set_gpu_state = i915_switcheroo_set_state,
636 .can_switch = i915_switcheroo_can_switch,
639 static int i915_load_modeset_init(struct drm_device *dev)
641 struct drm_i915_private *dev_priv = to_i915(dev);
642 struct pci_dev *pdev = dev_priv->drm.pdev;
645 if (i915_inject_load_failure())
648 intel_bios_init(dev_priv);
650 /* If we have > 1 VGA cards, then we need to arbitrate access
651 * to the common VGA resources.
653 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
654 * then we do not take part in VGA arbitration and the
655 * vga_client_register() fails with -ENODEV.
657 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
658 if (ret && ret != -ENODEV)
661 intel_register_dsm_handler();
663 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
665 goto cleanup_vga_client;
667 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
668 intel_update_rawclk(dev_priv);
670 intel_power_domains_init_hw(dev_priv, false);
672 intel_csr_ucode_init(dev_priv);
674 ret = intel_irq_install(dev_priv);
678 intel_setup_gmbus(dev_priv);
680 /* Important: The output setup functions called by modeset_init need
681 * working irqs for e.g. gmbus and dp aux transfers. */
682 ret = intel_modeset_init(dev);
686 ret = i915_gem_init(dev_priv);
688 goto cleanup_modeset;
690 intel_setup_overlay(dev_priv);
692 if (INTEL_INFO(dev_priv)->num_pipes == 0)
695 ret = intel_fbdev_init(dev);
699 /* Only enable hotplug handling once the fbdev is fully set up. */
700 intel_hpd_init(dev_priv);
705 if (i915_gem_suspend(dev_priv))
706 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
707 i915_gem_fini(dev_priv);
709 intel_modeset_cleanup(dev);
711 drm_irq_uninstall(dev);
712 intel_teardown_gmbus(dev_priv);
714 intel_csr_ucode_fini(dev_priv);
715 intel_power_domains_fini_hw(dev_priv);
716 vga_switcheroo_unregister_client(pdev);
718 vga_client_register(pdev, NULL, NULL, NULL);
723 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
725 struct apertures_struct *ap;
726 struct pci_dev *pdev = dev_priv->drm.pdev;
727 struct i915_ggtt *ggtt = &dev_priv->ggtt;
731 ap = alloc_apertures(1);
735 ap->ranges[0].base = ggtt->gmadr.start;
736 ap->ranges[0].size = ggtt->mappable_end;
739 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
741 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
748 #if !defined(CONFIG_VGA_CONSOLE)
749 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
753 #elif !defined(CONFIG_DUMMY_CONSOLE)
754 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
759 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
763 DRM_INFO("Replacing VGA console driver\n");
766 if (con_is_bound(&vga_con))
767 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
769 ret = do_unregister_con_driver(&vga_con);
771 /* Ignore "already unregistered". */
781 static void intel_init_dpio(struct drm_i915_private *dev_priv)
784 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
785 * CHV x1 PHY (DP/HDMI D)
786 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
788 if (IS_CHERRYVIEW(dev_priv)) {
789 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
790 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
791 } else if (IS_VALLEYVIEW(dev_priv)) {
792 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
796 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
799 * The i915 workqueue is primarily used for batched retirement of
800 * requests (and thus managing bo) once the task has been completed
801 * by the GPU. i915_retire_requests() is called directly when we
802 * need high-priority retirement, such as waiting for an explicit
805 * It is also used for periodic low-priority events, such as
806 * idle-timers and recording error state.
808 * All tasks on the workqueue are expected to acquire the dev mutex
809 * so there is no point in running more than one instance of the
810 * workqueue at any time. Use an ordered one.
812 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
813 if (dev_priv->wq == NULL)
816 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
817 if (dev_priv->hotplug.dp_wq == NULL)
823 destroy_workqueue(dev_priv->wq);
825 DRM_ERROR("Failed to allocate workqueues.\n");
830 static void i915_engines_cleanup(struct drm_i915_private *i915)
832 struct intel_engine_cs *engine;
833 enum intel_engine_id id;
835 for_each_engine(engine, i915, id)
839 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
841 destroy_workqueue(dev_priv->hotplug.dp_wq);
842 destroy_workqueue(dev_priv->wq);
846 * We don't keep the workarounds for pre-production hardware, so we expect our
847 * driver to fail on these machines in one way or another. A little warning on
848 * dmesg may help both the user and the bug triagers.
850 * Our policy for removing pre-production workarounds is to keep the
851 * current gen workarounds as a guide to the bring-up of the next gen
852 * (workarounds have a habit of persisting!). Anything older than that
853 * should be removed along with the complications they introduce.
855 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
859 pre |= IS_HSW_EARLY_SDV(dev_priv);
860 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
861 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
864 DRM_ERROR("This is a pre-production stepping. "
865 "It may not be fully functional.\n");
866 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
871 * i915_driver_init_early - setup state not requiring device access
872 * @dev_priv: device private
874 * Initialize everything that is a "SW-only" state, that is state not
875 * requiring accessing the device or exposing the driver via kernel internal
876 * or userspace interfaces. Example steps belonging here: lock initialization,
877 * system memory allocation, setting up device specific attributes and
878 * function hooks not requiring accessing the device.
880 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
884 if (i915_inject_load_failure())
887 spin_lock_init(&dev_priv->irq_lock);
888 spin_lock_init(&dev_priv->gpu_error.lock);
889 mutex_init(&dev_priv->backlight_lock);
890 spin_lock_init(&dev_priv->uncore.lock);
892 mutex_init(&dev_priv->sb_lock);
893 mutex_init(&dev_priv->av_mutex);
894 mutex_init(&dev_priv->wm.wm_mutex);
895 mutex_init(&dev_priv->pps_mutex);
897 i915_memcpy_init_early(dev_priv);
899 ret = i915_workqueues_init(dev_priv);
903 ret = i915_gem_init_early(dev_priv);
907 /* This must be called before any calls to HAS_PCH_* */
908 intel_detect_pch(dev_priv);
910 intel_wopcm_init_early(&dev_priv->wopcm);
911 intel_uc_init_early(dev_priv);
912 intel_pm_setup(dev_priv);
913 intel_init_dpio(dev_priv);
914 ret = intel_power_domains_init(dev_priv);
917 intel_irq_init(dev_priv);
918 intel_hangcheck_init(dev_priv);
919 intel_init_display_hooks(dev_priv);
920 intel_init_clock_gating_hooks(dev_priv);
921 intel_init_audio_hooks(dev_priv);
922 intel_display_crc_init(dev_priv);
924 intel_detect_preproduction_hw(dev_priv);
929 intel_uc_cleanup_early(dev_priv);
930 i915_gem_cleanup_early(dev_priv);
932 i915_workqueues_cleanup(dev_priv);
934 i915_engines_cleanup(dev_priv);
939 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
940 * @dev_priv: device private
942 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
944 intel_irq_fini(dev_priv);
945 intel_power_domains_cleanup(dev_priv);
946 intel_uc_cleanup_early(dev_priv);
947 i915_gem_cleanup_early(dev_priv);
948 i915_workqueues_cleanup(dev_priv);
949 i915_engines_cleanup(dev_priv);
952 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
954 struct pci_dev *pdev = dev_priv->drm.pdev;
958 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
960 * Before gen4, the registers and the GTT are behind different BARs.
961 * However, from gen4 onwards, the registers and the GTT are shared
962 * in the same BAR, so we want to restrict this ioremap from
963 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
964 * the register BAR remains the same size for all the earlier
965 * generations up to Ironlake.
967 if (INTEL_GEN(dev_priv) < 5)
968 mmio_size = 512 * 1024;
970 mmio_size = 2 * 1024 * 1024;
971 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
972 if (dev_priv->regs == NULL) {
973 DRM_ERROR("failed to map registers\n");
978 /* Try to make sure MCHBAR is enabled before poking at it */
979 intel_setup_mchbar(dev_priv);
984 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
986 struct pci_dev *pdev = dev_priv->drm.pdev;
988 intel_teardown_mchbar(dev_priv);
989 pci_iounmap(pdev, dev_priv->regs);
993 * i915_driver_init_mmio - setup device MMIO
994 * @dev_priv: device private
996 * Setup minimal device state necessary for MMIO accesses later in the
997 * initialization sequence. The setup here should avoid any other device-wide
998 * side effects or exposing the driver via kernel internal or user space
1001 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1005 if (i915_inject_load_failure())
1008 if (i915_get_bridge_dev(dev_priv))
1011 ret = i915_mmio_setup(dev_priv);
1015 intel_uncore_init(dev_priv);
1017 intel_device_info_init_mmio(dev_priv);
1019 intel_uncore_prune(dev_priv);
1021 intel_uc_init_mmio(dev_priv);
1023 ret = intel_engines_init_mmio(dev_priv);
1027 i915_gem_init_mmio(dev_priv);
1032 intel_uncore_fini(dev_priv);
1034 pci_dev_put(dev_priv->bridge_dev);
1040 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1041 * @dev_priv: device private
1043 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1045 intel_uncore_fini(dev_priv);
1046 i915_mmio_cleanup(dev_priv);
1047 pci_dev_put(dev_priv->bridge_dev);
1050 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1053 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1054 * user's requested state against the hardware/driver capabilities. We
1055 * do this now so that we can print out any log messages once rather
1056 * than every time we check intel_enable_ppgtt().
1058 i915_modparams.enable_ppgtt =
1059 intel_sanitize_enable_ppgtt(dev_priv,
1060 i915_modparams.enable_ppgtt);
1061 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1063 intel_gvt_sanitize_options(dev_priv);
1067 * i915_driver_init_hw - setup state requiring device access
1068 * @dev_priv: device private
1070 * Setup state that requires accessing the device, but doesn't require
1071 * exposing the driver via kernel internal or userspace interfaces.
1073 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1075 struct pci_dev *pdev = dev_priv->drm.pdev;
1078 if (i915_inject_load_failure())
1081 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1083 intel_sanitize_options(dev_priv);
1085 i915_perf_init(dev_priv);
1087 ret = i915_ggtt_probe_hw(dev_priv);
1092 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1093 * otherwise the vga fbdev driver falls over.
1095 ret = i915_kick_out_firmware_fb(dev_priv);
1097 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1101 ret = i915_kick_out_vgacon(dev_priv);
1103 DRM_ERROR("failed to remove conflicting VGA console\n");
1107 ret = i915_ggtt_init_hw(dev_priv);
1111 ret = i915_ggtt_enable_hw(dev_priv);
1113 DRM_ERROR("failed to enable GGTT\n");
1117 pci_set_master(pdev);
1119 /* overlay on gen2 is broken and can't address above 1G */
1120 if (IS_GEN2(dev_priv)) {
1121 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1123 DRM_ERROR("failed to set DMA mask\n");
1129 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1130 * using 32bit addressing, overwriting memory if HWS is located
1133 * The documentation also mentions an issue with undefined
1134 * behaviour if any general state is accessed within a page above 4GB,
1135 * which also needs to be handled carefully.
1137 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1138 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1141 DRM_ERROR("failed to set DMA mask\n");
1147 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1148 PM_QOS_DEFAULT_VALUE);
1150 intel_uncore_sanitize(dev_priv);
1152 i915_gem_load_init_fences(dev_priv);
1154 /* On the 945G/GM, the chipset reports the MSI capability on the
1155 * integrated graphics even though the support isn't actually there
1156 * according to the published specs. It doesn't appear to function
1157 * correctly in testing on 945G.
1158 * This may be a side effect of MSI having been made available for PEG
1159 * and the registers being closely associated.
1161 * According to chipset errata, on the 965GM, MSI interrupts may
1162 * be lost or delayed, and was defeatured. MSI interrupts seem to
1163 * get lost on g4x as well, and interrupt delivery seems to stay
1164 * properly dead afterwards. So we'll just disable them for all
1165 * pre-gen5 chipsets.
1167 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1168 * interrupts even when in MSI mode. This results in spurious
1169 * interrupt warnings if the legacy irq no. is shared with another
1170 * device. The kernel then disables that interrupt source and so
1171 * prevents the other device from working properly.
1173 if (INTEL_GEN(dev_priv) >= 5) {
1174 if (pci_enable_msi(pdev) < 0)
1175 DRM_DEBUG_DRIVER("can't enable MSI");
1178 ret = intel_gvt_init(dev_priv);
1182 intel_opregion_setup(dev_priv);
1187 if (pdev->msi_enabled)
1188 pci_disable_msi(pdev);
1189 pm_qos_remove_request(&dev_priv->pm_qos);
1191 i915_ggtt_cleanup_hw(dev_priv);
1193 i915_perf_fini(dev_priv);
1198 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1199 * @dev_priv: device private
1201 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1203 struct pci_dev *pdev = dev_priv->drm.pdev;
1205 i915_perf_fini(dev_priv);
1207 if (pdev->msi_enabled)
1208 pci_disable_msi(pdev);
1210 pm_qos_remove_request(&dev_priv->pm_qos);
1211 i915_ggtt_cleanup_hw(dev_priv);
1215 * i915_driver_register - register the driver with the rest of the system
1216 * @dev_priv: device private
1218 * Perform any steps necessary to make the driver available via kernel
1219 * internal or userspace interfaces.
1221 static void i915_driver_register(struct drm_i915_private *dev_priv)
1223 struct drm_device *dev = &dev_priv->drm;
1225 i915_gem_shrinker_register(dev_priv);
1226 i915_pmu_register(dev_priv);
1229 * Notify a valid surface after modesetting,
1230 * when running inside a VM.
1232 if (intel_vgpu_active(dev_priv))
1233 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1235 /* Reveal our presence to userspace */
1236 if (drm_dev_register(dev, 0) == 0) {
1237 i915_debugfs_register(dev_priv);
1238 i915_setup_sysfs(dev_priv);
1240 /* Depends on sysfs having been initialized */
1241 i915_perf_register(dev_priv);
1243 DRM_ERROR("Failed to register driver for userspace access!\n");
1245 if (INTEL_INFO(dev_priv)->num_pipes) {
1246 /* Must be done after probing outputs */
1247 intel_opregion_register(dev_priv);
1248 acpi_video_register();
1251 if (IS_GEN5(dev_priv))
1252 intel_gpu_ips_init(dev_priv);
1254 intel_audio_init(dev_priv);
1257 * Some ports require correctly set-up hpd registers for detection to
1258 * work properly (leading to ghost connected connector status), e.g. VGA
1259 * on gm45. Hence we can only set up the initial fbdev config after hpd
1260 * irqs are fully enabled. We do it last so that the async config
1261 * cannot run before the connectors are registered.
1263 intel_fbdev_initial_config_async(dev);
1266 * We need to coordinate the hotplugs with the asynchronous fbdev
1267 * configuration, for which we use the fbdev->async_cookie.
1269 if (INTEL_INFO(dev_priv)->num_pipes)
1270 drm_kms_helper_poll_init(dev);
1272 intel_power_domains_enable(dev_priv);
1273 intel_runtime_pm_enable(dev_priv);
1277 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1278 * @dev_priv: device private
1280 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1282 intel_runtime_pm_disable(dev_priv);
1283 intel_power_domains_disable(dev_priv);
1285 intel_fbdev_unregister(dev_priv);
1286 intel_audio_deinit(dev_priv);
1289 * After flushing the fbdev (incl. a late async config which will
1290 * have delayed queuing of a hotplug event), then flush the hotplug
1293 drm_kms_helper_poll_fini(&dev_priv->drm);
1295 intel_gpu_ips_teardown();
1296 acpi_video_unregister();
1297 intel_opregion_unregister(dev_priv);
1299 i915_perf_unregister(dev_priv);
1300 i915_pmu_unregister(dev_priv);
1302 i915_teardown_sysfs(dev_priv);
1303 drm_dev_unregister(&dev_priv->drm);
1305 i915_gem_shrinker_unregister(dev_priv);
1308 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1310 if (drm_debug & DRM_UT_DRIVER) {
1311 struct drm_printer p = drm_debug_printer("i915 device info:");
1313 intel_device_info_dump(&dev_priv->info, &p);
1314 intel_device_info_dump_runtime(&dev_priv->info, &p);
1317 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1318 DRM_INFO("DRM_I915_DEBUG enabled\n");
1319 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1320 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1321 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1322 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1325 static struct drm_i915_private *
1326 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1328 const struct intel_device_info *match_info =
1329 (struct intel_device_info *)ent->driver_data;
1330 struct intel_device_info *device_info;
1331 struct drm_i915_private *i915;
1333 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1337 if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
1342 i915->drm.pdev = pdev;
1343 i915->drm.dev_private = i915;
1344 pci_set_drvdata(pdev, &i915->drm);
1346 /* Setup the write-once "constant" device info */
1347 device_info = mkwrite_device_info(i915);
1348 memcpy(device_info, match_info, sizeof(*device_info));
1349 device_info->device_id = pdev->device;
1351 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1352 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
1353 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1358 static void i915_driver_destroy(struct drm_i915_private *i915)
1360 struct pci_dev *pdev = i915->drm.pdev;
1362 drm_dev_fini(&i915->drm);
1365 /* And make sure we never chase our dangling pointer from pci_dev */
1366 pci_set_drvdata(pdev, NULL);
1370 * i915_driver_load - setup chip and create an initial config
1372 * @ent: matching PCI ID entry
1374 * The driver load routine has to do several things:
1375 * - drive output discovery via intel_modeset_init()
1376 * - initialize the memory manager
1377 * - allocate initial config memory
1378 * - setup the DRM framebuffer with the allocated memory
1380 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1382 const struct intel_device_info *match_info =
1383 (struct intel_device_info *)ent->driver_data;
1384 struct drm_i915_private *dev_priv;
1387 /* Enable nuclear pageflip on ILK+ */
1388 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1389 driver.driver_features &= ~DRIVER_ATOMIC;
1391 dev_priv = i915_driver_create(pdev, ent);
1395 ret = pci_enable_device(pdev);
1399 ret = i915_driver_init_early(dev_priv);
1401 goto out_pci_disable;
1403 disable_rpm_wakeref_asserts(dev_priv);
1405 ret = i915_driver_init_mmio(dev_priv);
1407 goto out_runtime_pm_put;
1409 ret = i915_driver_init_hw(dev_priv);
1411 goto out_cleanup_mmio;
1414 * TODO: move the vblank init and parts of modeset init steps into one
1415 * of the i915_driver_init_/i915_driver_register functions according
1416 * to the role/effect of the given init step.
1418 if (INTEL_INFO(dev_priv)->num_pipes) {
1419 ret = drm_vblank_init(&dev_priv->drm,
1420 INTEL_INFO(dev_priv)->num_pipes);
1422 goto out_cleanup_hw;
1425 ret = i915_load_modeset_init(&dev_priv->drm);
1427 goto out_cleanup_hw;
1429 i915_driver_register(dev_priv);
1431 intel_init_ipc(dev_priv);
1433 enable_rpm_wakeref_asserts(dev_priv);
1435 i915_welcome_messages(dev_priv);
1440 i915_driver_cleanup_hw(dev_priv);
1442 i915_driver_cleanup_mmio(dev_priv);
1444 enable_rpm_wakeref_asserts(dev_priv);
1445 i915_driver_cleanup_early(dev_priv);
1447 pci_disable_device(pdev);
1449 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1450 i915_driver_destroy(dev_priv);
1454 void i915_driver_unload(struct drm_device *dev)
1456 struct drm_i915_private *dev_priv = to_i915(dev);
1457 struct pci_dev *pdev = dev_priv->drm.pdev;
1459 disable_rpm_wakeref_asserts(dev_priv);
1461 i915_driver_unregister(dev_priv);
1463 if (i915_gem_suspend(dev_priv))
1464 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1466 drm_atomic_helper_shutdown(dev);
1468 intel_gvt_cleanup(dev_priv);
1470 intel_modeset_cleanup(dev);
1472 intel_bios_cleanup(dev_priv);
1474 vga_switcheroo_unregister_client(pdev);
1475 vga_client_register(pdev, NULL, NULL, NULL);
1477 intel_csr_ucode_fini(dev_priv);
1479 /* Free error state after interrupts are fully disabled. */
1480 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1481 i915_reset_error_state(dev_priv);
1483 i915_gem_fini(dev_priv);
1484 intel_fbc_cleanup_cfb(dev_priv);
1486 intel_power_domains_fini_hw(dev_priv);
1488 i915_driver_cleanup_hw(dev_priv);
1489 i915_driver_cleanup_mmio(dev_priv);
1491 enable_rpm_wakeref_asserts(dev_priv);
1493 WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1496 static void i915_driver_release(struct drm_device *dev)
1498 struct drm_i915_private *dev_priv = to_i915(dev);
1500 i915_driver_cleanup_early(dev_priv);
1501 i915_driver_destroy(dev_priv);
1504 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1506 struct drm_i915_private *i915 = to_i915(dev);
1509 ret = i915_gem_open(i915, file);
1517 * i915_driver_lastclose - clean up after all DRM clients have exited
1520 * Take care of cleaning up after all DRM clients have exited. In the
1521 * mode setting case, we want to restore the kernel's initial mode (just
1522 * in case the last client left us in a bad state).
1524 * Additionally, in the non-mode setting case, we'll tear down the GTT
1525 * and DMA structures, since the kernel won't be using them, and clea
1528 static void i915_driver_lastclose(struct drm_device *dev)
1530 intel_fbdev_restore_mode(dev);
1531 vga_switcheroo_process_delayed_switch();
1534 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1536 struct drm_i915_file_private *file_priv = file->driver_priv;
1538 mutex_lock(&dev->struct_mutex);
1539 i915_gem_context_close(file);
1540 i915_gem_release(dev, file);
1541 mutex_unlock(&dev->struct_mutex);
1546 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1548 struct drm_device *dev = &dev_priv->drm;
1549 struct intel_encoder *encoder;
1551 drm_modeset_lock_all(dev);
1552 for_each_intel_encoder(dev, encoder)
1553 if (encoder->suspend)
1554 encoder->suspend(encoder);
1555 drm_modeset_unlock_all(dev);
1558 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1560 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1562 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1564 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1565 if (acpi_target_system_state() < ACPI_STATE_S3)
1571 static int i915_drm_prepare(struct drm_device *dev)
1573 struct drm_i915_private *i915 = to_i915(dev);
1577 * NB intel_display_suspend() may issue new requests after we've
1578 * ostensibly marked the GPU as ready-to-sleep here. We need to
1579 * split out that work and pull it forward so that after point,
1580 * the GPU is not woken again.
1582 err = i915_gem_suspend(i915);
1584 dev_err(&i915->drm.pdev->dev,
1585 "GEM idle failed, suspend/resume might fail\n");
1590 static int i915_drm_suspend(struct drm_device *dev)
1592 struct drm_i915_private *dev_priv = to_i915(dev);
1593 struct pci_dev *pdev = dev_priv->drm.pdev;
1594 pci_power_t opregion_target_state;
1596 disable_rpm_wakeref_asserts(dev_priv);
1598 /* We do a lot of poking in a lot of registers, make sure they work
1600 intel_power_domains_disable(dev_priv);
1602 drm_kms_helper_poll_disable(dev);
1604 pci_save_state(pdev);
1606 intel_display_suspend(dev);
1608 intel_dp_mst_suspend(dev_priv);
1610 intel_runtime_pm_disable_interrupts(dev_priv);
1611 intel_hpd_cancel_work(dev_priv);
1613 intel_suspend_encoders(dev_priv);
1615 intel_suspend_hw(dev_priv);
1617 i915_gem_suspend_gtt_mappings(dev_priv);
1619 i915_save_state(dev_priv);
1621 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1622 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1624 intel_opregion_unregister(dev_priv);
1626 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1628 dev_priv->suspend_count++;
1630 intel_csr_ucode_suspend(dev_priv);
1632 enable_rpm_wakeref_asserts(dev_priv);
1637 static enum i915_drm_suspend_mode
1638 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1641 return I915_DRM_SUSPEND_HIBERNATE;
1643 if (suspend_to_idle(dev_priv))
1644 return I915_DRM_SUSPEND_IDLE;
1646 return I915_DRM_SUSPEND_MEM;
1649 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1651 struct drm_i915_private *dev_priv = to_i915(dev);
1652 struct pci_dev *pdev = dev_priv->drm.pdev;
1655 disable_rpm_wakeref_asserts(dev_priv);
1657 i915_gem_suspend_late(dev_priv);
1659 intel_uncore_suspend(dev_priv);
1661 intel_power_domains_suspend(dev_priv,
1662 get_suspend_mode(dev_priv, hibernation));
1665 if (IS_GEN9_LP(dev_priv))
1666 bxt_enable_dc9(dev_priv);
1667 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1668 hsw_enable_pc8(dev_priv);
1669 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1670 ret = vlv_suspend_complete(dev_priv);
1673 DRM_ERROR("Suspend complete failed: %d\n", ret);
1674 intel_power_domains_resume(dev_priv);
1679 pci_disable_device(pdev);
1681 * During hibernation on some platforms the BIOS may try to access
1682 * the device even though it's already in D3 and hang the machine. So
1683 * leave the device in D0 on those platforms and hope the BIOS will
1684 * power down the device properly. The issue was seen on multiple old
1685 * GENs with different BIOS vendors, so having an explicit blacklist
1686 * is inpractical; apply the workaround on everything pre GEN6. The
1687 * platforms where the issue was seen:
1688 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1692 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1693 pci_set_power_state(pdev, PCI_D3hot);
1696 enable_rpm_wakeref_asserts(dev_priv);
1701 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1706 DRM_ERROR("dev: %p\n", dev);
1707 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1711 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1712 state.event != PM_EVENT_FREEZE))
1715 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1718 error = i915_drm_suspend(dev);
1722 return i915_drm_suspend_late(dev, false);
1725 static int i915_drm_resume(struct drm_device *dev)
1727 struct drm_i915_private *dev_priv = to_i915(dev);
1730 disable_rpm_wakeref_asserts(dev_priv);
1731 intel_sanitize_gt_powersave(dev_priv);
1733 i915_gem_sanitize(dev_priv);
1735 ret = i915_ggtt_enable_hw(dev_priv);
1737 DRM_ERROR("failed to re-enable GGTT\n");
1739 intel_csr_ucode_resume(dev_priv);
1741 i915_restore_state(dev_priv);
1742 intel_pps_unlock_regs_wa(dev_priv);
1743 intel_opregion_setup(dev_priv);
1745 intel_init_pch_refclk(dev_priv);
1748 * Interrupts have to be enabled before any batches are run. If not the
1749 * GPU will hang. i915_gem_init_hw() will initiate batches to
1750 * update/restore the context.
1752 * drm_mode_config_reset() needs AUX interrupts.
1754 * Modeset enabling in intel_modeset_init_hw() also needs working
1757 intel_runtime_pm_enable_interrupts(dev_priv);
1759 drm_mode_config_reset(dev);
1761 i915_gem_resume(dev_priv);
1763 intel_modeset_init_hw(dev);
1764 intel_init_clock_gating(dev_priv);
1766 spin_lock_irq(&dev_priv->irq_lock);
1767 if (dev_priv->display.hpd_irq_setup)
1768 dev_priv->display.hpd_irq_setup(dev_priv);
1769 spin_unlock_irq(&dev_priv->irq_lock);
1771 intel_dp_mst_resume(dev_priv);
1773 intel_display_resume(dev);
1775 drm_kms_helper_poll_enable(dev);
1778 * ... but also need to make sure that hotplug processing
1779 * doesn't cause havoc. Like in the driver load code we don't
1780 * bother with the tiny race here where we might lose hotplug
1783 intel_hpd_init(dev_priv);
1785 intel_opregion_register(dev_priv);
1787 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1789 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1791 intel_power_domains_enable(dev_priv);
1793 enable_rpm_wakeref_asserts(dev_priv);
1798 static int i915_drm_resume_early(struct drm_device *dev)
1800 struct drm_i915_private *dev_priv = to_i915(dev);
1801 struct pci_dev *pdev = dev_priv->drm.pdev;
1805 * We have a resume ordering issue with the snd-hda driver also
1806 * requiring our device to be power up. Due to the lack of a
1807 * parent/child relationship we currently solve this with an early
1810 * FIXME: This should be solved with a special hdmi sink device or
1811 * similar so that power domains can be employed.
1815 * Note that we need to set the power state explicitly, since we
1816 * powered off the device during freeze and the PCI core won't power
1817 * it back up for us during thaw. Powering off the device during
1818 * freeze is not a hard requirement though, and during the
1819 * suspend/resume phases the PCI core makes sure we get here with the
1820 * device powered on. So in case we change our freeze logic and keep
1821 * the device powered we can also remove the following set power state
1824 ret = pci_set_power_state(pdev, PCI_D0);
1826 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1831 * Note that pci_enable_device() first enables any parent bridge
1832 * device and only then sets the power state for this device. The
1833 * bridge enabling is a nop though, since bridge devices are resumed
1834 * first. The order of enabling power and enabling the device is
1835 * imposed by the PCI core as described above, so here we preserve the
1836 * same order for the freeze/thaw phases.
1838 * TODO: eventually we should remove pci_disable_device() /
1839 * pci_enable_enable_device() from suspend/resume. Due to how they
1840 * depend on the device enable refcount we can't anyway depend on them
1841 * disabling/enabling the device.
1843 if (pci_enable_device(pdev))
1846 pci_set_master(pdev);
1848 disable_rpm_wakeref_asserts(dev_priv);
1850 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1851 ret = vlv_resume_prepare(dev_priv, false);
1853 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1856 intel_uncore_resume_early(dev_priv);
1858 if (IS_GEN9_LP(dev_priv)) {
1859 gen9_sanitize_dc_state(dev_priv);
1860 bxt_disable_dc9(dev_priv);
1861 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1862 hsw_disable_pc8(dev_priv);
1865 intel_uncore_sanitize(dev_priv);
1867 intel_power_domains_resume(dev_priv);
1869 intel_engines_sanitize(dev_priv);
1871 enable_rpm_wakeref_asserts(dev_priv);
1876 static int i915_resume_switcheroo(struct drm_device *dev)
1880 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1883 ret = i915_drm_resume_early(dev);
1887 return i915_drm_resume(dev);
1891 * i915_reset - reset chip after a hang
1892 * @i915: #drm_i915_private to reset
1893 * @stalled_mask: mask of the stalled engines with the guilty requests
1894 * @reason: user error message for why we are resetting
1896 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1899 * Caller must hold the struct_mutex.
1901 * Procedure is fairly simple:
1902 * - reset the chip using the reset reg
1903 * - re-init context state
1904 * - re-init hardware status page
1905 * - re-init ring buffer
1906 * - re-init interrupt state
1909 void i915_reset(struct drm_i915_private *i915,
1910 unsigned int stalled_mask,
1913 struct i915_gpu_error *error = &i915->gpu_error;
1917 GEM_TRACE("flags=%lx\n", error->flags);
1920 lockdep_assert_held(&i915->drm.struct_mutex);
1921 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1923 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1926 /* Clear any previous failed attempts at recovery. Time to try again. */
1927 if (!i915_gem_unset_wedged(i915))
1931 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1932 error->reset_count++;
1934 ret = i915_gem_reset_prepare(i915);
1936 dev_err(i915->drm.dev, "GPU recovery failed\n");
1940 if (!intel_has_gpu_reset(i915)) {
1941 if (i915_modparams.reset)
1942 dev_err(i915->drm.dev, "GPU reset not supported\n");
1944 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1948 for (i = 0; i < 3; i++) {
1949 ret = intel_gpu_reset(i915, ALL_ENGINES);
1956 dev_err(i915->drm.dev, "Failed to reset chip\n");
1960 /* Ok, now get things going again... */
1963 * Everything depends on having the GTT running, so we need to start
1966 ret = i915_ggtt_enable_hw(i915);
1968 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1973 i915_gem_reset(i915, stalled_mask);
1974 intel_overlay_reset(i915);
1977 * Next we need to restore the context, but we don't use those
1980 * Ring buffer needs to be re-initialized in the KMS case, or if X
1981 * was running at the time of the reset (i.e. we weren't VT
1984 ret = i915_gem_init_hw(i915);
1986 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1991 i915_queue_hangcheck(i915);
1994 i915_gem_reset_finish(i915);
1996 clear_bit(I915_RESET_HANDOFF, &error->flags);
1997 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
2002 * History tells us that if we cannot reset the GPU now, we
2003 * never will. This then impacts everything that is run
2004 * subsequently. On failing the reset, we mark the driver
2005 * as wedged, preventing further execution on the GPU.
2006 * We also want to go one step further and add a taint to the
2007 * kernel so that any subsequent faults can be traced back to
2008 * this failure. This is important for CI, where if the
2009 * GPU/driver fails we would like to reboot and restart testing
2010 * rather than continue on into oblivion. For everyone else,
2011 * the system should still plod along, but they have been warned!
2013 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2015 i915_gem_set_wedged(i915);
2016 i915_retire_requests(i915);
2020 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2021 struct intel_engine_cs *engine)
2023 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2027 * i915_reset_engine - reset GPU engine to recover from a hang
2028 * @engine: engine to reset
2029 * @msg: reason for GPU reset; or NULL for no dev_notice()
2031 * Reset a specific GPU engine. Useful if a hang is detected.
2032 * Returns zero on successful reset or otherwise an error code.
2035 * - identifies the request that caused the hang and it is dropped
2036 * - reset engine (which will force the engine to idle)
2037 * - re-init/configure engine
2039 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2041 struct i915_gpu_error *error = &engine->i915->gpu_error;
2042 struct i915_request *active_request;
2045 GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2046 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2048 active_request = i915_gem_reset_prepare_engine(engine);
2049 if (IS_ERR_OR_NULL(active_request)) {
2050 /* Either the previous reset failed, or we pardon the reset. */
2051 ret = PTR_ERR(active_request);
2056 dev_notice(engine->i915->drm.dev,
2057 "Resetting %s for %s\n", engine->name, msg);
2058 error->reset_engine_count[engine->id]++;
2060 if (!engine->i915->guc.execbuf_client)
2061 ret = intel_gt_reset_engine(engine->i915, engine);
2063 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2065 /* If we fail here, we expect to fallback to a global reset */
2066 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2067 engine->i915->guc.execbuf_client ? "GuC " : "",
2073 * The request that caused the hang is stuck on elsp, we know the
2074 * active request and can drop it, adjust head to skip the offending
2075 * request to resume executing remaining requests in the queue.
2077 i915_gem_reset_engine(engine, active_request, true);
2080 * The engine and its registers (and workarounds in case of render)
2081 * have been reset to their default values. Follow the init_ring
2082 * process to program RING_MODE, HWSP and re-enable submission.
2084 ret = engine->init_hw(engine);
2089 intel_engine_cancel_stop_cs(engine);
2090 i915_gem_reset_finish_engine(engine);
2094 static int i915_pm_prepare(struct device *kdev)
2096 struct pci_dev *pdev = to_pci_dev(kdev);
2097 struct drm_device *dev = pci_get_drvdata(pdev);
2100 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2104 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2107 return i915_drm_prepare(dev);
2110 static int i915_pm_suspend(struct device *kdev)
2112 struct pci_dev *pdev = to_pci_dev(kdev);
2113 struct drm_device *dev = pci_get_drvdata(pdev);
2116 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2120 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2123 return i915_drm_suspend(dev);
2126 static int i915_pm_suspend_late(struct device *kdev)
2128 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2131 * We have a suspend ordering issue with the snd-hda driver also
2132 * requiring our device to be power up. Due to the lack of a
2133 * parent/child relationship we currently solve this with an late
2136 * FIXME: This should be solved with a special hdmi sink device or
2137 * similar so that power domains can be employed.
2139 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2142 return i915_drm_suspend_late(dev, false);
2145 static int i915_pm_poweroff_late(struct device *kdev)
2147 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2149 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2152 return i915_drm_suspend_late(dev, true);
2155 static int i915_pm_resume_early(struct device *kdev)
2157 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2159 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2162 return i915_drm_resume_early(dev);
2165 static int i915_pm_resume(struct device *kdev)
2167 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2169 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2172 return i915_drm_resume(dev);
2175 /* freeze: before creating the hibernation_image */
2176 static int i915_pm_freeze(struct device *kdev)
2178 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2181 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2182 ret = i915_drm_suspend(dev);
2187 ret = i915_gem_freeze(kdev_to_i915(kdev));
2194 static int i915_pm_freeze_late(struct device *kdev)
2196 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2199 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2200 ret = i915_drm_suspend_late(dev, true);
2205 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2212 /* thaw: called after creating the hibernation image, but before turning off. */
2213 static int i915_pm_thaw_early(struct device *kdev)
2215 return i915_pm_resume_early(kdev);
2218 static int i915_pm_thaw(struct device *kdev)
2220 return i915_pm_resume(kdev);
2223 /* restore: called after loading the hibernation image. */
2224 static int i915_pm_restore_early(struct device *kdev)
2226 return i915_pm_resume_early(kdev);
2229 static int i915_pm_restore(struct device *kdev)
2231 return i915_pm_resume(kdev);
2235 * Save all Gunit registers that may be lost after a D3 and a subsequent
2236 * S0i[R123] transition. The list of registers needing a save/restore is
2237 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2238 * registers in the following way:
2239 * - Driver: saved/restored by the driver
2240 * - Punit : saved/restored by the Punit firmware
2241 * - No, w/o marking: no need to save/restore, since the register is R/O or
2242 * used internally by the HW in a way that doesn't depend
2243 * keeping the content across a suspend/resume.
2244 * - Debug : used for debugging
2246 * We save/restore all registers marked with 'Driver', with the following
2248 * - Registers out of use, including also registers marked with 'Debug'.
2249 * These have no effect on the driver's operation, so we don't save/restore
2250 * them to reduce the overhead.
2251 * - Registers that are fully setup by an initialization function called from
2252 * the resume path. For example many clock gating and RPS/RC6 registers.
2253 * - Registers that provide the right functionality with their reset defaults.
2255 * TODO: Except for registers that based on the above 3 criteria can be safely
2256 * ignored, we save/restore all others, practically treating the HW context as
2257 * a black-box for the driver. Further investigation is needed to reduce the
2258 * saved/restored registers even further, by following the same 3 criteria.
2260 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2262 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2265 /* GAM 0x4000-0x4770 */
2266 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2267 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2268 s->arb_mode = I915_READ(ARB_MODE);
2269 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2270 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2272 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2273 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2275 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2276 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2278 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2279 s->ecochk = I915_READ(GAM_ECOCHK);
2280 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2281 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2283 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2285 /* MBC 0x9024-0x91D0, 0x8500 */
2286 s->g3dctl = I915_READ(VLV_G3DCTL);
2287 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2288 s->mbctl = I915_READ(GEN6_MBCTL);
2290 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2291 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2292 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2293 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2294 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2295 s->rstctl = I915_READ(GEN6_RSTCTL);
2296 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2298 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2299 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2300 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2301 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2302 s->ecobus = I915_READ(ECOBUS);
2303 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2304 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2305 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2306 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2307 s->rcedata = I915_READ(VLV_RCEDATA);
2308 s->spare2gh = I915_READ(VLV_SPAREG2H);
2310 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2311 s->gt_imr = I915_READ(GTIMR);
2312 s->gt_ier = I915_READ(GTIER);
2313 s->pm_imr = I915_READ(GEN6_PMIMR);
2314 s->pm_ier = I915_READ(GEN6_PMIER);
2316 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2317 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2319 /* GT SA CZ domain, 0x100000-0x138124 */
2320 s->tilectl = I915_READ(TILECTL);
2321 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2322 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2323 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2324 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2326 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2327 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2328 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2329 s->pcbr = I915_READ(VLV_PCBR);
2330 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2333 * Not saving any of:
2334 * DFT, 0x9800-0x9EC0
2335 * SARB, 0xB000-0xB1FC
2336 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2341 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2343 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2347 /* GAM 0x4000-0x4770 */
2348 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2349 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2350 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2351 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2352 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2354 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2355 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2357 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2358 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2360 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2361 I915_WRITE(GAM_ECOCHK, s->ecochk);
2362 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2363 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2365 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2367 /* MBC 0x9024-0x91D0, 0x8500 */
2368 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2369 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2370 I915_WRITE(GEN6_MBCTL, s->mbctl);
2372 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2373 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2374 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2375 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2376 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2377 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2378 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2380 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2381 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2382 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2383 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2384 I915_WRITE(ECOBUS, s->ecobus);
2385 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2386 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2387 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2388 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2389 I915_WRITE(VLV_RCEDATA, s->rcedata);
2390 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2392 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2393 I915_WRITE(GTIMR, s->gt_imr);
2394 I915_WRITE(GTIER, s->gt_ier);
2395 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2396 I915_WRITE(GEN6_PMIER, s->pm_ier);
2398 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2399 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2401 /* GT SA CZ domain, 0x100000-0x138124 */
2402 I915_WRITE(TILECTL, s->tilectl);
2403 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2405 * Preserve the GT allow wake and GFX force clock bit, they are not
2406 * be restored, as they are used to control the s0ix suspend/resume
2407 * sequence by the caller.
2409 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2410 val &= VLV_GTLC_ALLOWWAKEREQ;
2411 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2412 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2414 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2415 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2416 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2417 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2419 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2421 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2422 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2423 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2424 I915_WRITE(VLV_PCBR, s->pcbr);
2425 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2428 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2431 /* The HW does not like us polling for PW_STATUS frequently, so
2432 * use the sleeping loop rather than risk the busy spin within
2433 * intel_wait_for_register().
2435 * Transitioning between RC6 states should be at most 2ms (see
2436 * valleyview_enable_rps) so use a 3ms timeout.
2438 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2442 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2447 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2448 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2450 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2451 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2456 err = intel_wait_for_register(dev_priv,
2457 VLV_GTLC_SURVIVABILITY_REG,
2458 VLV_GFX_CLK_STATUS_BIT,
2459 VLV_GFX_CLK_STATUS_BIT,
2462 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2463 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2468 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2474 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2475 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2477 val |= VLV_GTLC_ALLOWWAKEREQ;
2478 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2479 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2481 mask = VLV_GTLC_ALLOWWAKEACK;
2482 val = allow ? mask : 0;
2484 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2486 DRM_ERROR("timeout disabling GT waking\n");
2491 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2497 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2498 val = wait_for_on ? mask : 0;
2501 * RC6 transitioning can be delayed up to 2 msec (see
2502 * valleyview_enable_rps), use 3 msec for safety.
2504 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2505 * reset and we are trying to force the machine to sleep.
2507 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2508 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2509 onoff(wait_for_on));
2512 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2514 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2517 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2518 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2521 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2527 * Bspec defines the following GT well on flags as debug only, so
2528 * don't treat them as hard failures.
2530 vlv_wait_for_gt_wells(dev_priv, false);
2532 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2533 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2535 vlv_check_no_gt_access(dev_priv);
2537 err = vlv_force_gfx_clock(dev_priv, true);
2541 err = vlv_allow_gt_wake(dev_priv, false);
2545 if (!IS_CHERRYVIEW(dev_priv))
2546 vlv_save_gunit_s0ix_state(dev_priv);
2548 err = vlv_force_gfx_clock(dev_priv, false);
2555 /* For safety always re-enable waking and disable gfx clock forcing */
2556 vlv_allow_gt_wake(dev_priv, true);
2558 vlv_force_gfx_clock(dev_priv, false);
2563 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2570 * If any of the steps fail just try to continue, that's the best we
2571 * can do at this point. Return the first error code (which will also
2572 * leave RPM permanently disabled).
2574 ret = vlv_force_gfx_clock(dev_priv, true);
2576 if (!IS_CHERRYVIEW(dev_priv))
2577 vlv_restore_gunit_s0ix_state(dev_priv);
2579 err = vlv_allow_gt_wake(dev_priv, true);
2583 err = vlv_force_gfx_clock(dev_priv, false);
2587 vlv_check_no_gt_access(dev_priv);
2590 intel_init_clock_gating(dev_priv);
2595 static int intel_runtime_suspend(struct device *kdev)
2597 struct pci_dev *pdev = to_pci_dev(kdev);
2598 struct drm_device *dev = pci_get_drvdata(pdev);
2599 struct drm_i915_private *dev_priv = to_i915(dev);
2602 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2605 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2608 DRM_DEBUG_KMS("Suspending device\n");
2610 disable_rpm_wakeref_asserts(dev_priv);
2613 * We are safe here against re-faults, since the fault handler takes
2616 i915_gem_runtime_suspend(dev_priv);
2618 intel_uc_suspend(dev_priv);
2620 intel_runtime_pm_disable_interrupts(dev_priv);
2622 intel_uncore_suspend(dev_priv);
2625 if (IS_GEN9_LP(dev_priv)) {
2626 bxt_display_core_uninit(dev_priv);
2627 bxt_enable_dc9(dev_priv);
2628 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2629 hsw_enable_pc8(dev_priv);
2630 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2631 ret = vlv_suspend_complete(dev_priv);
2635 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2636 intel_uncore_runtime_resume(dev_priv);
2638 intel_runtime_pm_enable_interrupts(dev_priv);
2640 intel_uc_resume(dev_priv);
2642 i915_gem_init_swizzling(dev_priv);
2643 i915_gem_restore_fences(dev_priv);
2645 enable_rpm_wakeref_asserts(dev_priv);
2650 enable_rpm_wakeref_asserts(dev_priv);
2651 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2653 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2654 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2656 dev_priv->runtime_pm.suspended = true;
2659 * FIXME: We really should find a document that references the arguments
2662 if (IS_BROADWELL(dev_priv)) {
2664 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2665 * being detected, and the call we do at intel_runtime_resume()
2666 * won't be able to restore them. Since PCI_D3hot matches the
2667 * actual specification and appears to be working, use it.
2669 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2672 * current versions of firmware which depend on this opregion
2673 * notification have repurposed the D1 definition to mean
2674 * "runtime suspended" vs. what you would normally expect (D3)
2675 * to distinguish it from notifications that might be sent via
2678 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2681 assert_forcewakes_inactive(dev_priv);
2683 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2684 intel_hpd_poll_init(dev_priv);
2686 DRM_DEBUG_KMS("Device suspended\n");
2690 static int intel_runtime_resume(struct device *kdev)
2692 struct pci_dev *pdev = to_pci_dev(kdev);
2693 struct drm_device *dev = pci_get_drvdata(pdev);
2694 struct drm_i915_private *dev_priv = to_i915(dev);
2697 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2700 DRM_DEBUG_KMS("Resuming device\n");
2702 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2703 disable_rpm_wakeref_asserts(dev_priv);
2705 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2706 dev_priv->runtime_pm.suspended = false;
2707 if (intel_uncore_unclaimed_mmio(dev_priv))
2708 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2710 if (IS_GEN9_LP(dev_priv)) {
2711 bxt_disable_dc9(dev_priv);
2712 bxt_display_core_init(dev_priv, true);
2713 if (dev_priv->csr.dmc_payload &&
2714 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2715 gen9_enable_dc5(dev_priv);
2716 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2717 hsw_disable_pc8(dev_priv);
2718 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2719 ret = vlv_resume_prepare(dev_priv, true);
2722 intel_uncore_runtime_resume(dev_priv);
2724 intel_runtime_pm_enable_interrupts(dev_priv);
2726 intel_uc_resume(dev_priv);
2729 * No point of rolling back things in case of an error, as the best
2730 * we can do is to hope that things will still work (and disable RPM).
2732 i915_gem_init_swizzling(dev_priv);
2733 i915_gem_restore_fences(dev_priv);
2736 * On VLV/CHV display interrupts are part of the display
2737 * power well, so hpd is reinitialized from there. For
2738 * everyone else do it here.
2740 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2741 intel_hpd_init(dev_priv);
2743 intel_enable_ipc(dev_priv);
2745 enable_rpm_wakeref_asserts(dev_priv);
2748 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2750 DRM_DEBUG_KMS("Device resumed\n");
2755 const struct dev_pm_ops i915_pm_ops = {
2757 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2760 .prepare = i915_pm_prepare,
2761 .suspend = i915_pm_suspend,
2762 .suspend_late = i915_pm_suspend_late,
2763 .resume_early = i915_pm_resume_early,
2764 .resume = i915_pm_resume,
2768 * @freeze, @freeze_late : called (1) before creating the
2769 * hibernation image [PMSG_FREEZE] and
2770 * (2) after rebooting, before restoring
2771 * the image [PMSG_QUIESCE]
2772 * @thaw, @thaw_early : called (1) after creating the hibernation
2773 * image, before writing it [PMSG_THAW]
2774 * and (2) after failing to create or
2775 * restore the image [PMSG_RECOVER]
2776 * @poweroff, @poweroff_late: called after writing the hibernation
2777 * image, before rebooting [PMSG_HIBERNATE]
2778 * @restore, @restore_early : called after rebooting and restoring the
2779 * hibernation image [PMSG_RESTORE]
2781 .freeze = i915_pm_freeze,
2782 .freeze_late = i915_pm_freeze_late,
2783 .thaw_early = i915_pm_thaw_early,
2784 .thaw = i915_pm_thaw,
2785 .poweroff = i915_pm_suspend,
2786 .poweroff_late = i915_pm_poweroff_late,
2787 .restore_early = i915_pm_restore_early,
2788 .restore = i915_pm_restore,
2790 /* S0ix (via runtime suspend) event handlers */
2791 .runtime_suspend = intel_runtime_suspend,
2792 .runtime_resume = intel_runtime_resume,
2795 static const struct vm_operations_struct i915_gem_vm_ops = {
2796 .fault = i915_gem_fault,
2797 .open = drm_gem_vm_open,
2798 .close = drm_gem_vm_close,
2801 static const struct file_operations i915_driver_fops = {
2802 .owner = THIS_MODULE,
2804 .release = drm_release,
2805 .unlocked_ioctl = drm_ioctl,
2806 .mmap = drm_gem_mmap,
2809 .compat_ioctl = i915_compat_ioctl,
2810 .llseek = noop_llseek,
2814 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2815 struct drm_file *file)
2820 static const struct drm_ioctl_desc i915_ioctls[] = {
2821 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2822 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2823 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2824 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2825 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2826 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2827 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2829 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2830 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2831 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2832 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2833 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2834 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2835 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2836 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2837 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2838 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2839 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2840 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2841 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2842 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2843 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2844 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2845 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2846 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2847 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2848 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2849 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2850 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2851 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2852 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2853 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2854 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2855 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2856 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2857 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2858 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2859 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2860 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2861 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2862 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2863 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2864 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2865 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2866 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2867 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2868 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2869 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2870 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2871 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2872 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2873 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2874 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2875 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2876 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2879 static struct drm_driver driver = {
2880 /* Don't use MTRRs here; the Xserver or userspace app should
2881 * deal with them for Intel hardware.
2884 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2885 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2886 .release = i915_driver_release,
2887 .open = i915_driver_open,
2888 .lastclose = i915_driver_lastclose,
2889 .postclose = i915_driver_postclose,
2891 .gem_close_object = i915_gem_close_object,
2892 .gem_free_object_unlocked = i915_gem_free_object,
2893 .gem_vm_ops = &i915_gem_vm_ops,
2895 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2896 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2897 .gem_prime_export = i915_gem_prime_export,
2898 .gem_prime_import = i915_gem_prime_import,
2900 .dumb_create = i915_gem_dumb_create,
2901 .dumb_map_offset = i915_gem_mmap_gtt,
2902 .ioctls = i915_ioctls,
2903 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2904 .fops = &i915_driver_fops,
2905 .name = DRIVER_NAME,
2906 .desc = DRIVER_DESC,
2907 .date = DRIVER_DATE,
2908 .major = DRIVER_MAJOR,
2909 .minor = DRIVER_MINOR,
2910 .patchlevel = DRIVER_PATCHLEVEL,
2913 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2914 #include "selftests/mock_drm.c"