drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_dmc.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_fbdev.h"
  55 #include "display/intel_hotplug.h"
  56 #include "display/intel_overlay.h"
  57 #include "display/intel_pipe_crc.h"
  58 #include "display/intel_pps.h"
  59 #include "display/intel_sprite.h"
  60 #include "display/intel_vga.h"
  61
  62 #include "gem/i915_gem_context.h"
  63 #include "gem/i915_gem_ioctls.h"
  64 #include "gem/i915_gem_mman.h"
  65 #include "gem/i915_gem_pm.h"
  66 #include "gt/intel_gt.h"
  67 #include "gt/intel_gt_pm.h"
  68 #include "gt/intel_rc6.h"
  69
  70 #include "i915_debugfs.h"
  71 #include "i915_drv.h"
  72 #include "i915_ioc32.h"
  73 #include "i915_irq.h"
  74 #include "i915_memcpy.h"
  75 #include "i915_perf.h"
  76 #include "i915_query.h"
  77 #include "i915_suspend.h"
  78 #include "i915_switcheroo.h"
  79 #include "i915_sysfs.h"
  80 #include "i915_trace.h"
  81 #include "i915_vgpu.h"
  82 #include "intel_dram.h"
  83 #include "intel_gvt.h"
  84 #include "intel_memory_region.h"
  85 #include "intel_pm.h"
  86 #include "intel_region_ttm.h"
  87 #include "intel_sideband.h"
  88 #include "vlv_suspend.h"
  89
  90 static const struct drm_driver driver;
  91
  92 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  93 {
  94         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
  95
  96         dev_priv->bridge_dev =
  97                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  98         if (!dev_priv->bridge_dev) {
  99                 drm_err(&dev_priv->drm, "bridge device not found\n");
 100                 return -1;
 101         }
 102         return 0;
 103 }
 104
 105 /* Allocate space for the MCH regs if needed, return nonzero on error */
 106 static int
 107 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 108 {
 109         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 110         u32 temp_lo, temp_hi = 0;
 111         u64 mchbar_addr;
 112         int ret;
 113
 114         if (GRAPHICS_VER(dev_priv) >= 4)
 115                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 116         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 117         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 118
 119         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 120 #ifdef CONFIG_PNP
 121         if (mchbar_addr &&
 122             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 123                 return 0;
 124 #endif
 125
 126         /* Get some space for it */
 127         dev_priv->mch_res.name = "i915 MCHBAR";
 128         dev_priv->mch_res.flags = IORESOURCE_MEM;
 129         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 130                                      &dev_priv->mch_res,
 131                                      MCHBAR_SIZE, MCHBAR_SIZE,
 132                                      PCIBIOS_MIN_MEM,
 133                                      0, pcibios_align_resource,
 134                                      dev_priv->bridge_dev);
 135         if (ret) {
 136                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 137                 dev_priv->mch_res.start = 0;
 138                 return ret;
 139         }
 140
 141         if (GRAPHICS_VER(dev_priv) >= 4)
 142                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 143                                        upper_32_bits(dev_priv->mch_res.start));
 144
 145         pci_write_config_dword(dev_priv->bridge_dev, reg,
 146                                lower_32_bits(dev_priv->mch_res.start));
 147         return 0;
 148 }
 149
 150 /* Setup MCHBAR if possible, return true if we should disable it again */
 151 static void
 152 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 153 {
 154         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 155         u32 temp;
 156         bool enabled;
 157
 158         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 159                 return;
 160
 161         dev_priv->mchbar_need_disable = false;
 162
 163         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 164                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 165                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 166         } else {
 167                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 168                 enabled = temp & 1;
 169         }
 170
 171         /* If it's already enabled, don't have to do anything */
 172         if (enabled)
 173                 return;
 174
 175         if (intel_alloc_mchbar_resource(dev_priv))
 176                 return;
 177
 178         dev_priv->mchbar_need_disable = true;
 179
 180         /* Space is allocated or reserved, so enable it. */
 181         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 182                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 183                                        temp | DEVEN_MCHBAR_EN);
 184         } else {
 185                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 186                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 187         }
 188 }
 189
 190 static void
 191 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 192 {
 193         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 194
 195         if (dev_priv->mchbar_need_disable) {
 196                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 197                         u32 deven_val;
 198
 199                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 200                                               &deven_val);
 201                         deven_val &= ~DEVEN_MCHBAR_EN;
 202                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 203                                                deven_val);
 204                 } else {
 205                         u32 mchbar_val;
 206
 207                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 208                                               &mchbar_val);
 209                         mchbar_val &= ~1;
 210                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 211                                                mchbar_val);
 212                 }
 213         }
 214
 215         if (dev_priv->mch_res.start)
 216                 release_resource(&dev_priv->mch_res);
 217 }
 218
 219 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 220 {
 221         /*
 222          * The i915 workqueue is primarily used for batched retirement of
 223          * requests (and thus managing bo) once the task has been completed
 224          * by the GPU. i915_retire_requests() is called directly when we
 225          * need high-priority retirement, such as waiting for an explicit
 226          * bo.
 227          *
 228          * It is also used for periodic low-priority events, such as
 229          * idle-timers and recording error state.
 230          *
 231          * All tasks on the workqueue are expected to acquire the dev mutex
 232          * so there is no point in running more than one instance of the
 233          * workqueue at any time.  Use an ordered one.
 234          */
 235         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 236         if (dev_priv->wq == NULL)
 237                 goto out_err;
 238
 239         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 240         if (dev_priv->hotplug.dp_wq == NULL)
 241                 goto out_free_wq;
 242
 243         return 0;
 244
 245 out_free_wq:
 246         destroy_workqueue(dev_priv->wq);
 247 out_err:
 248         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 249
 250         return -ENOMEM;
 251 }
 252
 253 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 254 {
 255         destroy_workqueue(dev_priv->hotplug.dp_wq);
 256         destroy_workqueue(dev_priv->wq);
 257 }
 258
 259 /*
 260  * We don't keep the workarounds for pre-production hardware, so we expect our
 261  * driver to fail on these machines in one way or another. A little warning on
 262  * dmesg may help both the user and the bug triagers.
 263  *
 264  * Our policy for removing pre-production workarounds is to keep the
 265  * current gen workarounds as a guide to the bring-up of the next gen
 266  * (workarounds have a habit of persisting!). Anything older than that
 267  * should be removed along with the complications they introduce.
 268  */
 269 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 270 {
 271         bool pre = false;
 272
 273         pre |= IS_HSW_EARLY_SDV(dev_priv);
 274         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 275         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 276         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 277         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 278         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 279
 280         if (pre) {
 281                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 282                           "It may not be fully functional.\n");
 283                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 284         }
 285 }
 286
 287 static void sanitize_gpu(struct drm_i915_private *i915)
 288 {
 289         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 290                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 291 }
 292
 293 /**
 294  * i915_driver_early_probe - setup state not requiring device access
 295  * @dev_priv: device private
 296  *
 297  * Initialize everything that is a "SW-only" state, that is state not
 298  * requiring accessing the device or exposing the driver via kernel internal
 299  * or userspace interfaces. Example steps belonging here: lock initialization,
 300  * system memory allocation, setting up device specific attributes and
 301  * function hooks not requiring accessing the device.
 302  */
 303 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 304 {
 305         int ret = 0;
 306
 307         if (i915_inject_probe_failure(dev_priv))
 308                 return -ENODEV;
 309
 310         intel_device_info_subplatform_init(dev_priv);
 311         intel_step_init(dev_priv);
 312
 313         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 314         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 315
 316         spin_lock_init(&dev_priv->irq_lock);
 317         spin_lock_init(&dev_priv->gpu_error.lock);
 318         mutex_init(&dev_priv->backlight_lock);
 319
 320         mutex_init(&dev_priv->sb_lock);
 321         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 322
 323         mutex_init(&dev_priv->av_mutex);
 324         mutex_init(&dev_priv->wm.wm_mutex);
 325         mutex_init(&dev_priv->pps_mutex);
 326         mutex_init(&dev_priv->hdcp_comp_mutex);
 327
 328         i915_memcpy_init_early(dev_priv);
 329         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 330
 331         ret = i915_workqueues_init(dev_priv);
 332         if (ret < 0)
 333                 return ret;
 334
 335         ret = vlv_suspend_init(dev_priv);
 336         if (ret < 0)
 337                 goto err_workqueues;
 338
 339         ret = intel_region_ttm_device_init(dev_priv);
 340         if (ret)
 341                 goto err_ttm;
 342
 343         intel_wopcm_init_early(&dev_priv->wopcm);
 344
 345         intel_gt_init_early(&dev_priv->gt, dev_priv);
 346
 347         i915_gem_init_early(dev_priv);
 348
 349         /* This must be called before any calls to HAS_PCH_* */
 350         intel_detect_pch(dev_priv);
 351
 352         intel_pm_setup(dev_priv);
 353         ret = intel_power_domains_init(dev_priv);
 354         if (ret < 0)
 355                 goto err_gem;
 356         intel_irq_init(dev_priv);
 357         intel_init_display_hooks(dev_priv);
 358         intel_init_clock_gating_hooks(dev_priv);
 359
 360         intel_detect_preproduction_hw(dev_priv);
 361
 362         return 0;
 363
 364 err_gem:
 365         i915_gem_cleanup_early(dev_priv);
 366         intel_gt_driver_late_release(&dev_priv->gt);
 367         intel_region_ttm_device_fini(dev_priv);
 368 err_ttm:
 369         vlv_suspend_cleanup(dev_priv);
 370 err_workqueues:
 371         i915_workqueues_cleanup(dev_priv);
 372         return ret;
 373 }
 374
 375 /**
 376  * i915_driver_late_release - cleanup the setup done in
 377  *                             i915_driver_early_probe()
 378  * @dev_priv: device private
 379  */
 380 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 381 {
 382         intel_irq_fini(dev_priv);
 383         intel_power_domains_cleanup(dev_priv);
 384         i915_gem_cleanup_early(dev_priv);
 385         intel_gt_driver_late_release(&dev_priv->gt);
 386         intel_region_ttm_device_fini(dev_priv);
 387         vlv_suspend_cleanup(dev_priv);
 388         i915_workqueues_cleanup(dev_priv);
 389
 390         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 391         mutex_destroy(&dev_priv->sb_lock);
 392
 393         i915_params_free(&dev_priv->params);
 394 }
 395
 396 /**
 397  * i915_driver_mmio_probe - setup device MMIO
 398  * @dev_priv: device private
 399  *
 400  * Setup minimal device state necessary for MMIO accesses later in the
 401  * initialization sequence. The setup here should avoid any other device-wide
 402  * side effects or exposing the driver via kernel internal or user space
 403  * interfaces.
 404  */
 405 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 406 {
 407         int ret;
 408
 409         if (i915_inject_probe_failure(dev_priv))
 410                 return -ENODEV;
 411
 412         if (i915_get_bridge_dev(dev_priv))
 413                 return -EIO;
 414
 415         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 416         if (ret < 0)
 417                 goto err_bridge;
 418
 419         /* Try to make sure MCHBAR is enabled before poking at it */
 420         intel_setup_mchbar(dev_priv);
 421         intel_device_info_runtime_init(dev_priv);
 422
 423         ret = intel_gt_init_mmio(&dev_priv->gt);
 424         if (ret)
 425                 goto err_uncore;
 426
 427         /* As early as possible, scrub existing GPU state before clobbering */
 428         sanitize_gpu(dev_priv);
 429
 430         return 0;
 431
 432 err_uncore:
 433         intel_teardown_mchbar(dev_priv);
 434         intel_uncore_fini_mmio(&dev_priv->uncore);
 435 err_bridge:
 436         pci_dev_put(dev_priv->bridge_dev);
 437
 438         return ret;
 439 }
 440
 441 /**
 442  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 443  * @dev_priv: device private
 444  */
 445 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 446 {
 447         intel_teardown_mchbar(dev_priv);
 448         intel_uncore_fini_mmio(&dev_priv->uncore);
 449         pci_dev_put(dev_priv->bridge_dev);
 450 }
 451
 452 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 453 {
 454         intel_gvt_sanitize_options(dev_priv);
 455 }
 456
 457 /**
 458  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 459  * platform
 460  * @i915: valid i915 instance
 461  *
 462  * Set the dma max segment size, device and coherent masks.  The dma mask set
 463  * needs to occur before i915_ggtt_probe_hw.
 464  *
 465  * A couple of platforms have special needs.  Address them as well.
 466  *
 467  */
 468 static int i915_set_dma_info(struct drm_i915_private *i915)
 469 {
 470         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 471         int ret;
 472
 473         GEM_BUG_ON(!mask_size);
 474
 475         /*
 476          * We don't have a max segment size, so set it to the max so sg's
 477          * debugging layer doesn't complain
 478          */
 479         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 480
 481         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 482         if (ret)
 483                 goto mask_err;
 484
 485         /* overlay on gen2 is broken and can't address above 1G */
 486         if (GRAPHICS_VER(i915) == 2)
 487                 mask_size = 30;
 488
 489         /*
 490          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 491          * using 32bit addressing, overwriting memory if HWS is located
 492          * above 4GB.
 493          *
 494          * The documentation also mentions an issue with undefined
 495          * behaviour if any general state is accessed within a page above 4GB,
 496          * which also needs to be handled carefully.
 497          */
 498         if (IS_I965G(i915) || IS_I965GM(i915))
 499                 mask_size = 32;
 500
 501         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 502         if (ret)
 503                 goto mask_err;
 504
 505         return 0;
 506
 507 mask_err:
 508         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 509         return ret;
 510 }
 511
 512 /**
 513  * i915_driver_hw_probe - setup state requiring device access
 514  * @dev_priv: device private
 515  *
 516  * Setup state that requires accessing the device, but doesn't require
 517  * exposing the driver via kernel internal or userspace interfaces.
 518  */
 519 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 520 {
 521         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 522         int ret;
 523
 524         if (i915_inject_probe_failure(dev_priv))
 525                 return -ENODEV;
 526
 527         if (HAS_PPGTT(dev_priv)) {
 528                 if (intel_vgpu_active(dev_priv) &&
 529                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 530                         i915_report_error(dev_priv,
 531                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 532                         return -ENXIO;
 533                 }
 534         }
 535
 536         if (HAS_EXECLISTS(dev_priv)) {
 537                 /*
 538                  * Older GVT emulation depends upon intercepting CSB mmio,
 539                  * which we no longer use, preferring to use the HWSP cache
 540                  * instead.
 541                  */
 542                 if (intel_vgpu_active(dev_priv) &&
 543                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 544                         i915_report_error(dev_priv,
 545                                           "old vGPU host found, support for HWSP emulation required\n");
 546                         return -ENXIO;
 547                 }
 548         }
 549
 550         intel_sanitize_options(dev_priv);
 551
 552         /* needs to be done before ggtt probe */
 553         intel_dram_edram_detect(dev_priv);
 554
 555         ret = i915_set_dma_info(dev_priv);
 556         if (ret)
 557                 return ret;
 558
 559         i915_perf_init(dev_priv);
 560
 561         ret = i915_ggtt_probe_hw(dev_priv);
 562         if (ret)
 563                 goto err_perf;
 564
 565         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 566         if (ret)
 567                 goto err_ggtt;
 568
 569         ret = i915_ggtt_init_hw(dev_priv);
 570         if (ret)
 571                 goto err_ggtt;
 572
 573         ret = intel_memory_regions_hw_probe(dev_priv);
 574         if (ret)
 575                 goto err_ggtt;
 576
 577         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 578
 579         ret = intel_gt_probe_lmem(&dev_priv->gt);
 580         if (ret)
 581                 goto err_mem_regions;
 582
 583         ret = i915_ggtt_enable_hw(dev_priv);
 584         if (ret) {
 585                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 586                 goto err_mem_regions;
 587         }
 588
 589         pci_set_master(pdev);
 590
 591         intel_gt_init_workarounds(dev_priv);
 592
 593         /* On the 945G/GM, the chipset reports the MSI capability on the
 594          * integrated graphics even though the support isn't actually there
 595          * according to the published specs.  It doesn't appear to function
 596          * correctly in testing on 945G.
 597          * This may be a side effect of MSI having been made available for PEG
 598          * and the registers being closely associated.
 599          *
 600          * According to chipset errata, on the 965GM, MSI interrupts may
 601          * be lost or delayed, and was defeatured. MSI interrupts seem to
 602          * get lost on g4x as well, and interrupt delivery seems to stay
 603          * properly dead afterwards. So we'll just disable them for all
 604          * pre-gen5 chipsets.
 605          *
 606          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 607          * interrupts even when in MSI mode. This results in spurious
 608          * interrupt warnings if the legacy irq no. is shared with another
 609          * device. The kernel then disables that interrupt source and so
 610          * prevents the other device from working properly.
 611          */
 612         if (GRAPHICS_VER(dev_priv) >= 5) {
 613                 if (pci_enable_msi(pdev) < 0)
 614                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 615         }
 616
 617         ret = intel_gvt_init(dev_priv);
 618         if (ret)
 619                 goto err_msi;
 620
 621         intel_opregion_setup(dev_priv);
 622
 623         ret = intel_pcode_init(dev_priv);
 624         if (ret)
 625                 goto err_msi;
 626
 627         /*
 628          * Fill the dram structure to get the system dram info. This will be
 629          * used for memory latency calculation.
 630          */
 631         intel_dram_detect(dev_priv);
 632
 633         intel_bw_init_hw(dev_priv);
 634
 635         return 0;
 636
 637 err_msi:
 638         if (pdev->msi_enabled)
 639                 pci_disable_msi(pdev);
 640 err_mem_regions:
 641         intel_memory_regions_driver_release(dev_priv);
 642 err_ggtt:
 643         i915_ggtt_driver_release(dev_priv);
 644         i915_gem_drain_freed_objects(dev_priv);
 645         i915_ggtt_driver_late_release(dev_priv);
 646 err_perf:
 647         i915_perf_fini(dev_priv);
 648         return ret;
 649 }
 650
 651 /**
 652  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 653  * @dev_priv: device private
 654  */
 655 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 656 {
 657         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 658
 659         i915_perf_fini(dev_priv);
 660
 661         if (pdev->msi_enabled)
 662                 pci_disable_msi(pdev);
 663 }
 664
 665 /**
 666  * i915_driver_register - register the driver with the rest of the system
 667  * @dev_priv: device private
 668  *
 669  * Perform any steps necessary to make the driver available via kernel
 670  * internal or userspace interfaces.
 671  */
 672 static void i915_driver_register(struct drm_i915_private *dev_priv)
 673 {
 674         struct drm_device *dev = &dev_priv->drm;
 675
 676         i915_gem_driver_register(dev_priv);
 677         i915_pmu_register(dev_priv);
 678
 679         intel_vgpu_register(dev_priv);
 680
 681         /* Reveal our presence to userspace */
 682         if (drm_dev_register(dev, 0)) {
 683                 drm_err(&dev_priv->drm,
 684                         "Failed to register driver for userspace access!\n");
 685                 return;
 686         }
 687
 688         i915_debugfs_register(dev_priv);
 689         i915_setup_sysfs(dev_priv);
 690
 691         /* Depends on sysfs having been initialized */
 692         i915_perf_register(dev_priv);
 693
 694         intel_gt_driver_register(&dev_priv->gt);
 695
 696         intel_display_driver_register(dev_priv);
 697
 698         intel_power_domains_enable(dev_priv);
 699         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 700
 701         intel_register_dsm_handler();
 702
 703         if (i915_switcheroo_register(dev_priv))
 704                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 705 }
 706
 707 /**
 708  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 709  * @dev_priv: device private
 710  */
 711 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 712 {
 713         i915_switcheroo_unregister(dev_priv);
 714
 715         intel_unregister_dsm_handler();
 716
 717         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 718         intel_power_domains_disable(dev_priv);
 719
 720         intel_display_driver_unregister(dev_priv);
 721
 722         intel_gt_driver_unregister(&dev_priv->gt);
 723
 724         i915_perf_unregister(dev_priv);
 725         i915_pmu_unregister(dev_priv);
 726
 727         i915_teardown_sysfs(dev_priv);
 728         drm_dev_unplug(&dev_priv->drm);
 729
 730         i915_gem_driver_unregister(dev_priv);
 731 }
 732
 733 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 734 {
 735         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 736                 struct drm_printer p = drm_debug_printer("i915 device info:");
 737
 738                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 739                            INTEL_DEVID(dev_priv),
 740                            INTEL_REVID(dev_priv),
 741                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 742                            intel_subplatform(RUNTIME_INFO(dev_priv),
 743                                              INTEL_INFO(dev_priv)->platform),
 744                            GRAPHICS_VER(dev_priv));
 745
 746                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 747                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 748                 intel_gt_info_print(&dev_priv->gt.info, &p);
 749         }
 750
 751         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 752                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 753         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 754                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 755         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 756                 drm_info(&dev_priv->drm,
 757                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 758 }
 759
 760 static struct drm_i915_private *
 761 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 762 {
 763         const struct intel_device_info *match_info =
 764                 (struct intel_device_info *)ent->driver_data;
 765         struct intel_device_info *device_info;
 766         struct drm_i915_private *i915;
 767
 768         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 769                                   struct drm_i915_private, drm);
 770         if (IS_ERR(i915))
 771                 return i915;
 772
 773         pci_set_drvdata(pdev, i915);
 774
 775         /* Device parameters start as a copy of module parameters. */
 776         i915_params_copy(&i915->params, &i915_modparams);
 777
 778         /* Setup the write-once "constant" device info */
 779         device_info = mkwrite_device_info(i915);
 780         memcpy(device_info, match_info, sizeof(*device_info));
 781         RUNTIME_INFO(i915)->device_id = pdev->device;
 782
 783         return i915;
 784 }
 785
 786 /**
 787  * i915_driver_probe - setup chip and create an initial config
 788  * @pdev: PCI device
 789  * @ent: matching PCI ID entry
 790  *
 791  * The driver probe routine has to do several things:
 792  *   - drive output discovery via intel_modeset_init()
 793  *   - initialize the memory manager
 794  *   - allocate initial config memory
 795  *   - setup the DRM framebuffer with the allocated memory
 796  */
 797 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 798 {
 799         const struct intel_device_info *match_info =
 800                 (struct intel_device_info *)ent->driver_data;
 801         struct drm_i915_private *i915;
 802         int ret;
 803
 804         i915 = i915_driver_create(pdev, ent);
 805         if (IS_ERR(i915))
 806                 return PTR_ERR(i915);
 807
 808         /* Disable nuclear pageflip by default on pre-ILK */
 809         if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
 810                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 811
 812         /*
 813          * Check if we support fake LMEM -- for now we only unleash this for
 814          * the live selftests(test-and-exit).
 815          */
 816 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 817         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 818                 if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&
 819                     i915->params.fake_lmem_start) {
 820                         mkwrite_device_info(i915)->memory_regions =
 821                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
 822                         GEM_BUG_ON(!HAS_LMEM(i915));
 823                 }
 824         }
 825 #endif
 826
 827         ret = pci_enable_device(pdev);
 828         if (ret)
 829                 goto out_fini;
 830
 831         ret = i915_driver_early_probe(i915);
 832         if (ret < 0)
 833                 goto out_pci_disable;
 834
 835         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 836
 837         intel_vgpu_detect(i915);
 838
 839         ret = i915_driver_mmio_probe(i915);
 840         if (ret < 0)
 841                 goto out_runtime_pm_put;
 842
 843         ret = i915_driver_hw_probe(i915);
 844         if (ret < 0)
 845                 goto out_cleanup_mmio;
 846
 847         ret = intel_modeset_init_noirq(i915);
 848         if (ret < 0)
 849                 goto out_cleanup_hw;
 850
 851         ret = intel_irq_install(i915);
 852         if (ret)
 853                 goto out_cleanup_modeset;
 854
 855         ret = intel_modeset_init_nogem(i915);
 856         if (ret)
 857                 goto out_cleanup_irq;
 858
 859         ret = i915_gem_init(i915);
 860         if (ret)
 861                 goto out_cleanup_modeset2;
 862
 863         ret = intel_modeset_init(i915);
 864         if (ret)
 865                 goto out_cleanup_gem;
 866
 867         i915_driver_register(i915);
 868
 869         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 870
 871         i915_welcome_messages(i915);
 872
 873         i915->do_release = true;
 874
 875         return 0;
 876
 877 out_cleanup_gem:
 878         i915_gem_suspend(i915);
 879         i915_gem_driver_remove(i915);
 880         i915_gem_driver_release(i915);
 881 out_cleanup_modeset2:
 882         /* FIXME clean up the error path */
 883         intel_modeset_driver_remove(i915);
 884         intel_irq_uninstall(i915);
 885         intel_modeset_driver_remove_noirq(i915);
 886         goto out_cleanup_modeset;
 887 out_cleanup_irq:
 888         intel_irq_uninstall(i915);
 889 out_cleanup_modeset:
 890         intel_modeset_driver_remove_nogem(i915);
 891 out_cleanup_hw:
 892         i915_driver_hw_remove(i915);
 893         intel_memory_regions_driver_release(i915);
 894         i915_ggtt_driver_release(i915);
 895         i915_gem_drain_freed_objects(i915);
 896         i915_ggtt_driver_late_release(i915);
 897 out_cleanup_mmio:
 898         i915_driver_mmio_release(i915);
 899 out_runtime_pm_put:
 900         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 901         i915_driver_late_release(i915);
 902 out_pci_disable:
 903         pci_disable_device(pdev);
 904 out_fini:
 905         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 906         return ret;
 907 }
 908
 909 void i915_driver_remove(struct drm_i915_private *i915)
 910 {
 911         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 912
 913         i915_driver_unregister(i915);
 914
 915         /* Flush any external code that still may be under the RCU lock */
 916         synchronize_rcu();
 917
 918         i915_gem_suspend(i915);
 919
 920         intel_gvt_driver_remove(i915);
 921
 922         intel_modeset_driver_remove(i915);
 923
 924         intel_irq_uninstall(i915);
 925
 926         intel_modeset_driver_remove_noirq(i915);
 927
 928         i915_reset_error_state(i915);
 929         i915_gem_driver_remove(i915);
 930
 931         intel_modeset_driver_remove_nogem(i915);
 932
 933         i915_driver_hw_remove(i915);
 934
 935         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 936 }
 937
 938 static void i915_driver_release(struct drm_device *dev)
 939 {
 940         struct drm_i915_private *dev_priv = to_i915(dev);
 941         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 942
 943         if (!dev_priv->do_release)
 944                 return;
 945
 946         disable_rpm_wakeref_asserts(rpm);
 947
 948         i915_gem_driver_release(dev_priv);
 949
 950         intel_memory_regions_driver_release(dev_priv);
 951         i915_ggtt_driver_release(dev_priv);
 952         i915_gem_drain_freed_objects(dev_priv);
 953         i915_ggtt_driver_late_release(dev_priv);
 954
 955         i915_driver_mmio_release(dev_priv);
 956
 957         enable_rpm_wakeref_asserts(rpm);
 958         intel_runtime_pm_driver_release(rpm);
 959
 960         i915_driver_late_release(dev_priv);
 961 }
 962
 963 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 964 {
 965         struct drm_i915_private *i915 = to_i915(dev);
 966         int ret;
 967
 968         ret = i915_gem_open(i915, file);
 969         if (ret)
 970                 return ret;
 971
 972         return 0;
 973 }
 974
 975 /**
 976  * i915_driver_lastclose - clean up after all DRM clients have exited
 977  * @dev: DRM device
 978  *
 979  * Take care of cleaning up after all DRM clients have exited.  In the
 980  * mode setting case, we want to restore the kernel's initial mode (just
 981  * in case the last client left us in a bad state).
 982  *
 983  * Additionally, in the non-mode setting case, we'll tear down the GTT
 984  * and DMA structures, since the kernel won't be using them, and clea
 985  * up any GEM state.
 986  */
 987 static void i915_driver_lastclose(struct drm_device *dev)
 988 {
 989         struct drm_i915_private *i915 = to_i915(dev);
 990
 991         intel_fbdev_restore_mode(dev);
 992
 993         if (HAS_DISPLAY(i915))
 994                 vga_switcheroo_process_delayed_switch();
 995 }
 996
 997 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 998 {
 999         struct drm_i915_file_private *file_priv = file->driver_priv;
1000
1001         i915_gem_context_close(file);
1002
1003         kfree_rcu(file_priv, rcu);
1004
1005         /* Catch up with all the deferred frees from "this" client */
1006         i915_gem_flush_free_objects(to_i915(dev));
1007 }
1008
1009 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1010 {
1011         struct drm_device *dev = &dev_priv->drm;
1012         struct intel_encoder *encoder;
1013
1014         if (!HAS_DISPLAY(dev_priv))
1015                 return;
1016
1017         drm_modeset_lock_all(dev);
1018         for_each_intel_encoder(dev, encoder)
1019                 if (encoder->suspend)
1020                         encoder->suspend(encoder);
1021         drm_modeset_unlock_all(dev);
1022 }
1023
1024 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1025 {
1026         struct drm_device *dev = &dev_priv->drm;
1027         struct intel_encoder *encoder;
1028
1029         if (!HAS_DISPLAY(dev_priv))
1030                 return;
1031
1032         drm_modeset_lock_all(dev);
1033         for_each_intel_encoder(dev, encoder)
1034                 if (encoder->shutdown)
1035                         encoder->shutdown(encoder);
1036         drm_modeset_unlock_all(dev);
1037 }
1038
1039 void i915_driver_shutdown(struct drm_i915_private *i915)
1040 {
1041         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1042         intel_runtime_pm_disable(&i915->runtime_pm);
1043         intel_power_domains_disable(i915);
1044
1045         i915_gem_suspend(i915);
1046
1047         if (HAS_DISPLAY(i915)) {
1048                 drm_kms_helper_poll_disable(&i915->drm);
1049
1050                 drm_atomic_helper_shutdown(&i915->drm);
1051         }
1052
1053         intel_dp_mst_suspend(i915);
1054
1055         intel_runtime_pm_disable_interrupts(i915);
1056         intel_hpd_cancel_work(i915);
1057
1058         intel_suspend_encoders(i915);
1059         intel_shutdown_encoders(i915);
1060
1061         intel_dmc_ucode_suspend(i915);
1062
1063         /*
1064          * The only requirement is to reboot with display DC states disabled,
1065          * for now leaving all display power wells in the INIT power domain
1066          * enabled.
1067          *
1068          * TODO:
1069          * - unify the pci_driver::shutdown sequence here with the
1070          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1071          * - unify the driver remove and system/runtime suspend sequences with
1072          *   the above unified shutdown/poweroff sequence.
1073          */
1074         intel_power_domains_driver_remove(i915);
1075         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1076
1077         intel_runtime_pm_driver_release(&i915->runtime_pm);
1078 }
1079
1080 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1081 {
1082 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1083         if (acpi_target_system_state() < ACPI_STATE_S3)
1084                 return true;
1085 #endif
1086         return false;
1087 }
1088
1089 static int i915_drm_prepare(struct drm_device *dev)
1090 {
1091         struct drm_i915_private *i915 = to_i915(dev);
1092
1093         /*
1094          * NB intel_display_suspend() may issue new requests after we've
1095          * ostensibly marked the GPU as ready-to-sleep here. We need to
1096          * split out that work and pull it forward so that after point,
1097          * the GPU is not woken again.
1098          */
1099         i915_gem_suspend(i915);
1100
1101         return 0;
1102 }
1103
1104 static int i915_drm_suspend(struct drm_device *dev)
1105 {
1106         struct drm_i915_private *dev_priv = to_i915(dev);
1107         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1108         pci_power_t opregion_target_state;
1109
1110         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1111
1112         /* We do a lot of poking in a lot of registers, make sure they work
1113          * properly. */
1114         intel_power_domains_disable(dev_priv);
1115         if (HAS_DISPLAY(dev_priv))
1116                 drm_kms_helper_poll_disable(dev);
1117
1118         pci_save_state(pdev);
1119
1120         intel_display_suspend(dev);
1121
1122         intel_dp_mst_suspend(dev_priv);
1123
1124         intel_runtime_pm_disable_interrupts(dev_priv);
1125         intel_hpd_cancel_work(dev_priv);
1126
1127         intel_suspend_encoders(dev_priv);
1128
1129         intel_suspend_hw(dev_priv);
1130
1131         i915_ggtt_suspend(&dev_priv->ggtt);
1132
1133         i915_save_display(dev_priv);
1134
1135         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1136         intel_opregion_suspend(dev_priv, opregion_target_state);
1137
1138         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1139
1140         dev_priv->suspend_count++;
1141
1142         intel_dmc_ucode_suspend(dev_priv);
1143
1144         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1145
1146         return 0;
1147 }
1148
1149 static enum i915_drm_suspend_mode
1150 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1151 {
1152         if (hibernate)
1153                 return I915_DRM_SUSPEND_HIBERNATE;
1154
1155         if (suspend_to_idle(dev_priv))
1156                 return I915_DRM_SUSPEND_IDLE;
1157
1158         return I915_DRM_SUSPEND_MEM;
1159 }
1160
1161 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1162 {
1163         struct drm_i915_private *dev_priv = to_i915(dev);
1164         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1165         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1166         int ret;
1167
1168         disable_rpm_wakeref_asserts(rpm);
1169
1170         i915_gem_suspend_late(dev_priv);
1171
1172         intel_uncore_suspend(&dev_priv->uncore);
1173
1174         intel_power_domains_suspend(dev_priv,
1175                                     get_suspend_mode(dev_priv, hibernation));
1176
1177         intel_display_power_suspend_late(dev_priv);
1178
1179         ret = vlv_suspend_complete(dev_priv);
1180         if (ret) {
1181                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1182                 intel_power_domains_resume(dev_priv);
1183
1184                 goto out;
1185         }
1186
1187         pci_disable_device(pdev);
1188         /*
1189          * During hibernation on some platforms the BIOS may try to access
1190          * the device even though it's already in D3 and hang the machine. So
1191          * leave the device in D0 on those platforms and hope the BIOS will
1192          * power down the device properly. The issue was seen on multiple old
1193          * GENs with different BIOS vendors, so having an explicit blacklist
1194          * is inpractical; apply the workaround on everything pre GEN6. The
1195          * platforms where the issue was seen:
1196          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1197          * Fujitsu FSC S7110
1198          * Acer Aspire 1830T
1199          */
1200         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1201                 pci_set_power_state(pdev, PCI_D3hot);
1202
1203 out:
1204         enable_rpm_wakeref_asserts(rpm);
1205         if (!dev_priv->uncore.user_forcewake_count)
1206                 intel_runtime_pm_driver_release(rpm);
1207
1208         return ret;
1209 }
1210
1211 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1212 {
1213         int error;
1214
1215         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1216                              state.event != PM_EVENT_FREEZE))
1217                 return -EINVAL;
1218
1219         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1220                 return 0;
1221
1222         error = i915_drm_suspend(&i915->drm);
1223         if (error)
1224                 return error;
1225
1226         return i915_drm_suspend_late(&i915->drm, false);
1227 }
1228
1229 static int i915_drm_resume(struct drm_device *dev)
1230 {
1231         struct drm_i915_private *dev_priv = to_i915(dev);
1232         int ret;
1233
1234         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1235
1236         ret = intel_pcode_init(dev_priv);
1237         if (ret)
1238                 return ret;
1239
1240         sanitize_gpu(dev_priv);
1241
1242         ret = i915_ggtt_enable_hw(dev_priv);
1243         if (ret)
1244                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1245
1246         i915_ggtt_resume(&dev_priv->ggtt);
1247
1248         intel_dmc_ucode_resume(dev_priv);
1249
1250         i915_restore_display(dev_priv);
1251         intel_pps_unlock_regs_wa(dev_priv);
1252
1253         intel_init_pch_refclk(dev_priv);
1254
1255         /*
1256          * Interrupts have to be enabled before any batches are run. If not the
1257          * GPU will hang. i915_gem_init_hw() will initiate batches to
1258          * update/restore the context.
1259          *
1260          * drm_mode_config_reset() needs AUX interrupts.
1261          *
1262          * Modeset enabling in intel_modeset_init_hw() also needs working
1263          * interrupts.
1264          */
1265         intel_runtime_pm_enable_interrupts(dev_priv);
1266
1267         if (HAS_DISPLAY(dev_priv))
1268                 drm_mode_config_reset(dev);
1269
1270         i915_gem_resume(dev_priv);
1271
1272         intel_modeset_init_hw(dev_priv);
1273         intel_init_clock_gating(dev_priv);
1274         intel_hpd_init(dev_priv);
1275
1276         /* MST sideband requires HPD interrupts enabled */
1277         intel_dp_mst_resume(dev_priv);
1278         intel_display_resume(dev);
1279
1280         intel_hpd_poll_disable(dev_priv);
1281         if (HAS_DISPLAY(dev_priv))
1282                 drm_kms_helper_poll_enable(dev);
1283
1284         intel_opregion_resume(dev_priv);
1285
1286         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1287
1288         intel_power_domains_enable(dev_priv);
1289
1290         intel_gvt_resume(dev_priv);
1291
1292         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1293
1294         return 0;
1295 }
1296
1297 static int i915_drm_resume_early(struct drm_device *dev)
1298 {
1299         struct drm_i915_private *dev_priv = to_i915(dev);
1300         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1301         int ret;
1302
1303         /*
1304          * We have a resume ordering issue with the snd-hda driver also
1305          * requiring our device to be power up. Due to the lack of a
1306          * parent/child relationship we currently solve this with an early
1307          * resume hook.
1308          *
1309          * FIXME: This should be solved with a special hdmi sink device or
1310          * similar so that power domains can be employed.
1311          */
1312
1313         /*
1314          * Note that we need to set the power state explicitly, since we
1315          * powered off the device during freeze and the PCI core won't power
1316          * it back up for us during thaw. Powering off the device during
1317          * freeze is not a hard requirement though, and during the
1318          * suspend/resume phases the PCI core makes sure we get here with the
1319          * device powered on. So in case we change our freeze logic and keep
1320          * the device powered we can also remove the following set power state
1321          * call.
1322          */
1323         ret = pci_set_power_state(pdev, PCI_D0);
1324         if (ret) {
1325                 drm_err(&dev_priv->drm,
1326                         "failed to set PCI D0 power state (%d)\n", ret);
1327                 return ret;
1328         }
1329
1330         /*
1331          * Note that pci_enable_device() first enables any parent bridge
1332          * device and only then sets the power state for this device. The
1333          * bridge enabling is a nop though, since bridge devices are resumed
1334          * first. The order of enabling power and enabling the device is
1335          * imposed by the PCI core as described above, so here we preserve the
1336          * same order for the freeze/thaw phases.
1337          *
1338          * TODO: eventually we should remove pci_disable_device() /
1339          * pci_enable_enable_device() from suspend/resume. Due to how they
1340          * depend on the device enable refcount we can't anyway depend on them
1341          * disabling/enabling the device.
1342          */
1343         if (pci_enable_device(pdev))
1344                 return -EIO;
1345
1346         pci_set_master(pdev);
1347
1348         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1349
1350         ret = vlv_resume_prepare(dev_priv, false);
1351         if (ret)
1352                 drm_err(&dev_priv->drm,
1353                         "Resume prepare failed: %d, continuing anyway\n", ret);
1354
1355         intel_uncore_resume_early(&dev_priv->uncore);
1356
1357         intel_gt_check_and_clear_faults(&dev_priv->gt);
1358
1359         intel_display_power_resume_early(dev_priv);
1360
1361         intel_power_domains_resume(dev_priv);
1362
1363         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1364
1365         return ret;
1366 }
1367
1368 int i915_resume_switcheroo(struct drm_i915_private *i915)
1369 {
1370         int ret;
1371
1372         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1373                 return 0;
1374
1375         ret = i915_drm_resume_early(&i915->drm);
1376         if (ret)
1377                 return ret;
1378
1379         return i915_drm_resume(&i915->drm);
1380 }
1381
1382 static int i915_pm_prepare(struct device *kdev)
1383 {
1384         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1385
1386         if (!i915) {
1387                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1388                 return -ENODEV;
1389         }
1390
1391         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1392                 return 0;
1393
1394         return i915_drm_prepare(&i915->drm);
1395 }
1396
1397 static int i915_pm_suspend(struct device *kdev)
1398 {
1399         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1400
1401         if (!i915) {
1402                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1403                 return -ENODEV;
1404         }
1405
1406         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1407                 return 0;
1408
1409         return i915_drm_suspend(&i915->drm);
1410 }
1411
1412 static int i915_pm_suspend_late(struct device *kdev)
1413 {
1414         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1415
1416         /*
1417          * We have a suspend ordering issue with the snd-hda driver also
1418          * requiring our device to be power up. Due to the lack of a
1419          * parent/child relationship we currently solve this with an late
1420          * suspend hook.
1421          *
1422          * FIXME: This should be solved with a special hdmi sink device or
1423          * similar so that power domains can be employed.
1424          */
1425         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1426                 return 0;
1427
1428         return i915_drm_suspend_late(&i915->drm, false);
1429 }
1430
1431 static int i915_pm_poweroff_late(struct device *kdev)
1432 {
1433         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1434
1435         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1436                 return 0;
1437
1438         return i915_drm_suspend_late(&i915->drm, true);
1439 }
1440
1441 static int i915_pm_resume_early(struct device *kdev)
1442 {
1443         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1444
1445         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1446                 return 0;
1447
1448         return i915_drm_resume_early(&i915->drm);
1449 }
1450
1451 static int i915_pm_resume(struct device *kdev)
1452 {
1453         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1454
1455         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1456                 return 0;
1457
1458         return i915_drm_resume(&i915->drm);
1459 }
1460
1461 /* freeze: before creating the hibernation_image */
1462 static int i915_pm_freeze(struct device *kdev)
1463 {
1464         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1465         int ret;
1466
1467         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1468                 ret = i915_drm_suspend(&i915->drm);
1469                 if (ret)
1470                         return ret;
1471         }
1472
1473         ret = i915_gem_freeze(i915);
1474         if (ret)
1475                 return ret;
1476
1477         return 0;
1478 }
1479
1480 static int i915_pm_freeze_late(struct device *kdev)
1481 {
1482         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1483         int ret;
1484
1485         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1486                 ret = i915_drm_suspend_late(&i915->drm, true);
1487                 if (ret)
1488                         return ret;
1489         }
1490
1491         ret = i915_gem_freeze_late(i915);
1492         if (ret)
1493                 return ret;
1494
1495         return 0;
1496 }
1497
1498 /* thaw: called after creating the hibernation image, but before turning off. */
1499 static int i915_pm_thaw_early(struct device *kdev)
1500 {
1501         return i915_pm_resume_early(kdev);
1502 }
1503
1504 static int i915_pm_thaw(struct device *kdev)
1505 {
1506         return i915_pm_resume(kdev);
1507 }
1508
1509 /* restore: called after loading the hibernation image. */
1510 static int i915_pm_restore_early(struct device *kdev)
1511 {
1512         return i915_pm_resume_early(kdev);
1513 }
1514
1515 static int i915_pm_restore(struct device *kdev)
1516 {
1517         return i915_pm_resume(kdev);
1518 }
1519
1520 static int intel_runtime_suspend(struct device *kdev)
1521 {
1522         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1523         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1524         int ret;
1525
1526         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1527                 return -ENODEV;
1528
1529         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1530
1531         disable_rpm_wakeref_asserts(rpm);
1532
1533         /*
1534          * We are safe here against re-faults, since the fault handler takes
1535          * an RPM reference.
1536          */
1537         i915_gem_runtime_suspend(dev_priv);
1538
1539         intel_gt_runtime_suspend(&dev_priv->gt);
1540
1541         intel_runtime_pm_disable_interrupts(dev_priv);
1542
1543         intel_uncore_suspend(&dev_priv->uncore);
1544
1545         intel_display_power_suspend(dev_priv);
1546
1547         ret = vlv_suspend_complete(dev_priv);
1548         if (ret) {
1549                 drm_err(&dev_priv->drm,
1550                         "Runtime suspend failed, disabling it (%d)\n", ret);
1551                 intel_uncore_runtime_resume(&dev_priv->uncore);
1552
1553                 intel_runtime_pm_enable_interrupts(dev_priv);
1554
1555                 intel_gt_runtime_resume(&dev_priv->gt);
1556
1557                 enable_rpm_wakeref_asserts(rpm);
1558
1559                 return ret;
1560         }
1561
1562         enable_rpm_wakeref_asserts(rpm);
1563         intel_runtime_pm_driver_release(rpm);
1564
1565         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1566                 drm_err(&dev_priv->drm,
1567                         "Unclaimed access detected prior to suspending\n");
1568
1569         rpm->suspended = true;
1570
1571         /*
1572          * FIXME: We really should find a document that references the arguments
1573          * used below!
1574          */
1575         if (IS_BROADWELL(dev_priv)) {
1576                 /*
1577                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1578                  * being detected, and the call we do at intel_runtime_resume()
1579                  * won't be able to restore them. Since PCI_D3hot matches the
1580                  * actual specification and appears to be working, use it.
1581                  */
1582                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1583         } else {
1584                 /*
1585                  * current versions of firmware which depend on this opregion
1586                  * notification have repurposed the D1 definition to mean
1587                  * "runtime suspended" vs. what you would normally expect (D3)
1588                  * to distinguish it from notifications that might be sent via
1589                  * the suspend path.
1590                  */
1591                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1592         }
1593
1594         assert_forcewakes_inactive(&dev_priv->uncore);
1595
1596         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1597                 intel_hpd_poll_enable(dev_priv);
1598
1599         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1600         return 0;
1601 }
1602
1603 static int intel_runtime_resume(struct device *kdev)
1604 {
1605         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1606         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1607         int ret;
1608
1609         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1610                 return -ENODEV;
1611
1612         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1613
1614         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1615         disable_rpm_wakeref_asserts(rpm);
1616
1617         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1618         rpm->suspended = false;
1619         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1620                 drm_dbg(&dev_priv->drm,
1621                         "Unclaimed access during suspend, bios?\n");
1622
1623         intel_display_power_resume(dev_priv);
1624
1625         ret = vlv_resume_prepare(dev_priv, true);
1626
1627         intel_uncore_runtime_resume(&dev_priv->uncore);
1628
1629         intel_runtime_pm_enable_interrupts(dev_priv);
1630
1631         /*
1632          * No point of rolling back things in case of an error, as the best
1633          * we can do is to hope that things will still work (and disable RPM).
1634          */
1635         intel_gt_runtime_resume(&dev_priv->gt);
1636
1637         /*
1638          * On VLV/CHV display interrupts are part of the display
1639          * power well, so hpd is reinitialized from there. For
1640          * everyone else do it here.
1641          */
1642         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1643                 intel_hpd_init(dev_priv);
1644                 intel_hpd_poll_disable(dev_priv);
1645         }
1646
1647         intel_enable_ipc(dev_priv);
1648
1649         enable_rpm_wakeref_asserts(rpm);
1650
1651         if (ret)
1652                 drm_err(&dev_priv->drm,
1653                         "Runtime resume failed, disabling it (%d)\n", ret);
1654         else
1655                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1656
1657         return ret;
1658 }
1659
1660 const struct dev_pm_ops i915_pm_ops = {
1661         /*
1662          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1663          * PMSG_RESUME]
1664          */
1665         .prepare = i915_pm_prepare,
1666         .suspend = i915_pm_suspend,
1667         .suspend_late = i915_pm_suspend_late,
1668         .resume_early = i915_pm_resume_early,
1669         .resume = i915_pm_resume,
1670
1671         /*
1672          * S4 event handlers
1673          * @freeze, @freeze_late    : called (1) before creating the
1674          *                            hibernation image [PMSG_FREEZE] and
1675          *                            (2) after rebooting, before restoring
1676          *                            the image [PMSG_QUIESCE]
1677          * @thaw, @thaw_early       : called (1) after creating the hibernation
1678          *                            image, before writing it [PMSG_THAW]
1679          *                            and (2) after failing to create or
1680          *                            restore the image [PMSG_RECOVER]
1681          * @poweroff, @poweroff_late: called after writing the hibernation
1682          *                            image, before rebooting [PMSG_HIBERNATE]
1683          * @restore, @restore_early : called after rebooting and restoring the
1684          *                            hibernation image [PMSG_RESTORE]
1685          */
1686         .freeze = i915_pm_freeze,
1687         .freeze_late = i915_pm_freeze_late,
1688         .thaw_early = i915_pm_thaw_early,
1689         .thaw = i915_pm_thaw,
1690         .poweroff = i915_pm_suspend,
1691         .poweroff_late = i915_pm_poweroff_late,
1692         .restore_early = i915_pm_restore_early,
1693         .restore = i915_pm_restore,
1694
1695         /* S0ix (via runtime suspend) event handlers */
1696         .runtime_suspend = intel_runtime_suspend,
1697         .runtime_resume = intel_runtime_resume,
1698 };
1699
1700 static const struct file_operations i915_driver_fops = {
1701         .owner = THIS_MODULE,
1702         .open = drm_open,
1703         .release = drm_release_noglobal,
1704         .unlocked_ioctl = drm_ioctl,
1705         .mmap = i915_gem_mmap,
1706         .poll = drm_poll,
1707         .read = drm_read,
1708         .compat_ioctl = i915_ioc32_compat_ioctl,
1709         .llseek = noop_llseek,
1710 };
1711
1712 static int
1713 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1714                           struct drm_file *file)
1715 {
1716         return -ENODEV;
1717 }
1718
1719 static const struct drm_ioctl_desc i915_ioctls[] = {
1720         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1721         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1722         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1724         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1725         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1726         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1728         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1729         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1730         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1731         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1732         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1733         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1734         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1735         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1736         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1760         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1762         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1763         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1764         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1773         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1774         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1775         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1776         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1779 };
1780
1781 static const struct drm_driver driver = {
1782         /* Don't use MTRRs here; the Xserver or userspace app should
1783          * deal with them for Intel hardware.
1784          */
1785         .driver_features =
1786             DRIVER_GEM |
1787             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1788             DRIVER_SYNCOBJ_TIMELINE,
1789         .release = i915_driver_release,
1790         .open = i915_driver_open,
1791         .lastclose = i915_driver_lastclose,
1792         .postclose = i915_driver_postclose,
1793
1794         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1795         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1796         .gem_prime_import = i915_gem_prime_import,
1797
1798         .dumb_create = i915_gem_dumb_create,
1799         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1800
1801         .ioctls = i915_ioctls,
1802         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1803         .fops = &i915_driver_fops,
1804         .name = DRIVER_NAME,
1805         .desc = DRIVER_DESC,
1806         .date = DRIVER_DATE,
1807         .major = DRIVER_MAJOR,
1808         .minor = DRIVER_MINOR,
1809         .patchlevel = DRIVER_PATCHLEVEL,
1810 };