drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158 #if IS_ENABLED(CONFIG_AGP_INTEL)
 159 extern int intel_agp_enabled;
 160 #else
 161 static int intel_agp_enabled;
 162 #endif
 163
 164 static const struct intel_device_info intel_i830_info = {
 165         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167         .ring_mask = RENDER_RING,
 168 };
 169
 170 static const struct intel_device_info intel_845g_info = {
 171         .gen = 2, .num_pipes = 1,
 172         .has_overlay = 1, .overlay_needs_physical = 1,
 173         .ring_mask = RENDER_RING,
 174 };
 175
 176 static const struct intel_device_info intel_i85x_info = {
 177         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 178         .cursor_needs_physical = 1,
 179         .has_overlay = 1, .overlay_needs_physical = 1,
 180         .ring_mask = RENDER_RING,
 181 };
 182
 183 static const struct intel_device_info intel_i865g_info = {
 184         .gen = 2, .num_pipes = 1,
 185         .has_overlay = 1, .overlay_needs_physical = 1,
 186         .ring_mask = RENDER_RING,
 187 };
 188
 189 static const struct intel_device_info intel_i915g_info = {
 190         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 191         .has_overlay = 1, .overlay_needs_physical = 1,
 192         .ring_mask = RENDER_RING,
 193 };
 194 static const struct intel_device_info intel_i915gm_info = {
 195         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 196         .cursor_needs_physical = 1,
 197         .has_overlay = 1, .overlay_needs_physical = 1,
 198         .supports_tv = 1,
 199         .ring_mask = RENDER_RING,
 200 };
 201 static const struct intel_device_info intel_i945g_info = {
 202         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 203         .has_overlay = 1, .overlay_needs_physical = 1,
 204         .ring_mask = RENDER_RING,
 205 };
 206 static const struct intel_device_info intel_i945gm_info = {
 207         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 208         .has_hotplug = 1, .cursor_needs_physical = 1,
 209         .has_overlay = 1, .overlay_needs_physical = 1,
 210         .supports_tv = 1,
 211         .ring_mask = RENDER_RING,
 212 };
 213
 214 static const struct intel_device_info intel_i965g_info = {
 215         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 216         .has_hotplug = 1,
 217         .has_overlay = 1,
 218         .ring_mask = RENDER_RING,
 219 };
 220
 221 static const struct intel_device_info intel_i965gm_info = {
 222         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 223         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 224         .has_overlay = 1,
 225         .supports_tv = 1,
 226         .ring_mask = RENDER_RING,
 227 };
 228
 229 static const struct intel_device_info intel_g33_info = {
 230         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_overlay = 1,
 233         .ring_mask = RENDER_RING,
 234 };
 235
 236 static const struct intel_device_info intel_g45_info = {
 237         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 238         .has_pipe_cxsr = 1, .has_hotplug = 1,
 239         .ring_mask = RENDER_RING | BSD_RING,
 240 };
 241
 242 static const struct intel_device_info intel_gm45_info = {
 243         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 244         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 245         .has_pipe_cxsr = 1, .has_hotplug = 1,
 246         .supports_tv = 1,
 247         .ring_mask = RENDER_RING | BSD_RING,
 248 };
 249
 250 static const struct intel_device_info intel_pineview_info = {
 251         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 252         .need_gfx_hws = 1, .has_hotplug = 1,
 253         .has_overlay = 1,
 254 };
 255
 256 static const struct intel_device_info intel_ironlake_d_info = {
 257         .gen = 5, .num_pipes = 2,
 258         .need_gfx_hws = 1, .has_hotplug = 1,
 259         .ring_mask = RENDER_RING | BSD_RING,
 260 };
 261
 262 static const struct intel_device_info intel_ironlake_m_info = {
 263         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 264         .need_gfx_hws = 1, .has_hotplug = 1,
 265         .has_fbc = 1,
 266         .ring_mask = RENDER_RING | BSD_RING,
 267 };
 268
 269 static const struct intel_device_info intel_sandybridge_d_info = {
 270         .gen = 6, .num_pipes = 2,
 271         .need_gfx_hws = 1, .has_hotplug = 1,
 272         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 273         .has_llc = 1,
 274 };
 275
 276 static const struct intel_device_info intel_sandybridge_m_info = {
 277         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 278         .need_gfx_hws = 1, .has_hotplug = 1,
 279         .has_fbc = 1,
 280         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 281         .has_llc = 1,
 282 };
 283
 284 #define GEN7_FEATURES  \
 285         .gen = 7, .num_pipes = 3, \
 286         .need_gfx_hws = 1, .has_hotplug = 1, \
 287         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 288         .has_llc = 1
 289
 290 static const struct intel_device_info intel_ivybridge_d_info = {
 291         GEN7_FEATURES,
 292         .is_ivybridge = 1,
 293 };
 294
 295 static const struct intel_device_info intel_ivybridge_m_info = {
 296         GEN7_FEATURES,
 297         .is_ivybridge = 1,
 298         .is_mobile = 1,
 299         .has_fbc = 1,
 300 };
 301
 302 static const struct intel_device_info intel_ivybridge_q_info = {
 303         GEN7_FEATURES,
 304         .is_ivybridge = 1,
 305         .num_pipes = 0, /* legal, last one wins */
 306 };
 307
 308 static const struct intel_device_info intel_valleyview_m_info = {
 309         GEN7_FEATURES,
 310         .is_mobile = 1,
 311         .num_pipes = 2,
 312         .is_valleyview = 1,
 313         .display_mmio_offset = VLV_DISPLAY_BASE,
 314         .has_llc = 0, /* legal, last one wins */
 315 };
 316
 317 static const struct intel_device_info intel_valleyview_d_info = {
 318         GEN7_FEATURES,
 319         .num_pipes = 2,
 320         .is_valleyview = 1,
 321         .display_mmio_offset = VLV_DISPLAY_BASE,
 322         .has_llc = 0, /* legal, last one wins */
 323 };
 324
 325 static const struct intel_device_info intel_haswell_d_info = {
 326         GEN7_FEATURES,
 327         .is_haswell = 1,
 328         .has_ddi = 1,
 329         .has_fpga_dbg = 1,
 330         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 331 };
 332
 333 static const struct intel_device_info intel_haswell_m_info = {
 334         GEN7_FEATURES,
 335         .is_haswell = 1,
 336         .is_mobile = 1,
 337         .has_ddi = 1,
 338         .has_fpga_dbg = 1,
 339         .has_fbc = 1,
 340         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 341 };
 342
 343 /*
 344  * Make sure any device matches here are from most specific to most
 345  * general.  For example, since the Quanta match is based on the subsystem
 346  * and subvendor IDs, we need it to come before the more general IVB
 347  * PCI ID matches, otherwise we'll use the wrong info struct above.
 348  */
 349 #define INTEL_PCI_IDS \
 350         INTEL_I830_IDS(&intel_i830_info),       \
 351         INTEL_I845G_IDS(&intel_845g_info),      \
 352         INTEL_I85X_IDS(&intel_i85x_info),       \
 353         INTEL_I865G_IDS(&intel_i865g_info),     \
 354         INTEL_I915G_IDS(&intel_i915g_info),     \
 355         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 356         INTEL_I945G_IDS(&intel_i945g_info),     \
 357         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 358         INTEL_I965G_IDS(&intel_i965g_info),     \
 359         INTEL_G33_IDS(&intel_g33_info),         \
 360         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 361         INTEL_GM45_IDS(&intel_gm45_info),       \
 362         INTEL_G45_IDS(&intel_g45_info),         \
 363         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 364         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 365         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 366         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 367         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 368         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 369         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 370         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 371         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 372         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 373         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 374         INTEL_VLV_D_IDS(&intel_valleyview_d_info)
 375
 376 static const struct pci_device_id pciidlist[] = {               /* aka */
 377         INTEL_PCI_IDS,
 378         {0, 0, 0}
 379 };
 380
 381 #if defined(CONFIG_DRM_I915_KMS)
 382 MODULE_DEVICE_TABLE(pci, pciidlist);
 383 #endif
 384
 385 void intel_detect_pch(struct drm_device *dev)
 386 {
 387         struct drm_i915_private *dev_priv = dev->dev_private;
 388         struct pci_dev *pch;
 389
 390         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 391          * (which really amounts to a PCH but no South Display).
 392          */
 393         if (INTEL_INFO(dev)->num_pipes == 0) {
 394                 dev_priv->pch_type = PCH_NOP;
 395                 return;
 396         }
 397
 398         /*
 399          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 400          * make graphics device passthrough work easy for VMM, that only
 401          * need to expose ISA bridge to let driver know the real hardware
 402          * underneath. This is a requirement from virtualization team.
 403          *
 404          * In some virtualized environments (e.g. XEN), there is irrelevant
 405          * ISA bridge in the system. To work reliably, we should scan trhough
 406          * all the ISA bridge devices and check for the first match, instead
 407          * of only checking the first one.
 408          */
 409         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 410         while (pch) {
 411                 struct pci_dev *curr = pch;
 412                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 413                         unsigned short id;
 414                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 415                         dev_priv->pch_id = id;
 416
 417                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 418                                 dev_priv->pch_type = PCH_IBX;
 419                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 420                                 WARN_ON(!IS_GEN5(dev));
 421                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 422                                 dev_priv->pch_type = PCH_CPT;
 423                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 424                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 425                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 426                                 /* PantherPoint is CPT compatible */
 427                                 dev_priv->pch_type = PCH_CPT;
 428                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 429                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 430                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 431                                 dev_priv->pch_type = PCH_LPT;
 432                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 433                                 WARN_ON(!IS_HASWELL(dev));
 434                                 WARN_ON(IS_ULT(dev));
 435                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_LPT;
 437                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 438                                 WARN_ON(!IS_HASWELL(dev));
 439                                 WARN_ON(!IS_ULT(dev));
 440                         } else {
 441                                 goto check_next;
 442                         }
 443                         pci_dev_put(pch);
 444                         break;
 445                 }
 446 check_next:
 447                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 448                 pci_dev_put(curr);
 449         }
 450         if (!pch)
 451                 DRM_DEBUG_KMS("No PCH found?\n");
 452 }
 453
 454 bool i915_semaphore_is_enabled(struct drm_device *dev)
 455 {
 456         if (INTEL_INFO(dev)->gen < 6)
 457                 return 0;
 458
 459         if (i915_semaphores >= 0)
 460                 return i915_semaphores;
 461
 462 #ifdef CONFIG_INTEL_IOMMU
 463         /* Enable semaphores on SNB when IO remapping is off */
 464         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 465                 return false;
 466 #endif
 467
 468         return 1;
 469 }
 470
 471 static int i915_drm_freeze(struct drm_device *dev)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         struct drm_crtc *crtc;
 475
 476         /* ignore lid events during suspend */
 477         mutex_lock(&dev_priv->modeset_restore_lock);
 478         dev_priv->modeset_restore = MODESET_SUSPENDED;
 479         mutex_unlock(&dev_priv->modeset_restore_lock);
 480
 481         /* We do a lot of poking in a lot of registers, make sure they work
 482          * properly. */
 483         hsw_disable_package_c8(dev_priv);
 484         intel_display_set_init_power(dev, true);
 485
 486         drm_kms_helper_poll_disable(dev);
 487
 488         pci_save_state(dev->pdev);
 489
 490         /* If KMS is active, we do the leavevt stuff here */
 491         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 492                 int error;
 493
 494                 error = i915_gem_suspend(dev);
 495                 if (error) {
 496                         dev_err(&dev->pdev->dev,
 497                                 "GEM idle failed, resume might fail\n");
 498                         return error;
 499                 }
 500
 501                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 502
 503                 drm_irq_uninstall(dev);
 504                 dev_priv->enable_hotplug_processing = false;
 505                 /*
 506                  * Disable CRTCs directly since we want to preserve sw state
 507                  * for _thaw.
 508                  */
 509                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 510                         dev_priv->display.crtc_disable(crtc);
 511
 512                 intel_modeset_suspend_hw(dev);
 513         }
 514
 515         i915_gem_suspend_gtt_mappings(dev);
 516
 517         i915_save_state(dev);
 518
 519         intel_opregion_fini(dev);
 520
 521         console_lock();
 522         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 523         console_unlock();
 524
 525         return 0;
 526 }
 527
 528 int i915_suspend(struct drm_device *dev, pm_message_t state)
 529 {
 530         int error;
 531
 532         if (!dev || !dev->dev_private) {
 533                 DRM_ERROR("dev: %p\n", dev);
 534                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 535                 return -ENODEV;
 536         }
 537
 538         if (state.event == PM_EVENT_PRETHAW)
 539                 return 0;
 540
 541
 542         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 543                 return 0;
 544
 545         error = i915_drm_freeze(dev);
 546         if (error)
 547                 return error;
 548
 549         if (state.event == PM_EVENT_SUSPEND) {
 550                 /* Shut down the device */
 551                 pci_disable_device(dev->pdev);
 552                 pci_set_power_state(dev->pdev, PCI_D3hot);
 553         }
 554
 555         return 0;
 556 }
 557
 558 void intel_console_resume(struct work_struct *work)
 559 {
 560         struct drm_i915_private *dev_priv =
 561                 container_of(work, struct drm_i915_private,
 562                              console_resume_work);
 563         struct drm_device *dev = dev_priv->dev;
 564
 565         console_lock();
 566         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 567         console_unlock();
 568 }
 569
 570 static void intel_resume_hotplug(struct drm_device *dev)
 571 {
 572         struct drm_mode_config *mode_config = &dev->mode_config;
 573         struct intel_encoder *encoder;
 574
 575         mutex_lock(&mode_config->mutex);
 576         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 577
 578         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 579                 if (encoder->hot_plug)
 580                         encoder->hot_plug(encoder);
 581
 582         mutex_unlock(&mode_config->mutex);
 583
 584         /* Just fire off a uevent and let userspace tell us what to do */
 585         drm_helper_hpd_irq_event(dev);
 586 }
 587
 588 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         int error = 0;
 592
 593         intel_uncore_early_sanitize(dev);
 594
 595         intel_uncore_sanitize(dev);
 596
 597         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 598             restore_gtt_mappings) {
 599                 mutex_lock(&dev->struct_mutex);
 600                 i915_gem_restore_gtt_mappings(dev);
 601                 mutex_unlock(&dev->struct_mutex);
 602         }
 603
 604         intel_power_domains_init_hw(dev);
 605
 606         i915_restore_state(dev);
 607         intel_opregion_setup(dev);
 608
 609         /* KMS EnterVT equivalent */
 610         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 611                 intel_init_pch_refclk(dev);
 612
 613                 mutex_lock(&dev->struct_mutex);
 614
 615                 error = i915_gem_init_hw(dev);
 616                 mutex_unlock(&dev->struct_mutex);
 617
 618                 /* We need working interrupts for modeset enabling ... */
 619                 drm_irq_install(dev);
 620
 621                 intel_modeset_init_hw(dev);
 622
 623                 drm_modeset_lock_all(dev);
 624                 intel_modeset_setup_hw_state(dev, true);
 625                 drm_modeset_unlock_all(dev);
 626
 627                 /*
 628                  * ... but also need to make sure that hotplug processing
 629                  * doesn't cause havoc. Like in the driver load code we don't
 630                  * bother with the tiny race here where we might loose hotplug
 631                  * notifications.
 632                  * */
 633                 intel_hpd_init(dev);
 634                 dev_priv->enable_hotplug_processing = true;
 635                 /* Config may have changed between suspend and resume */
 636                 intel_resume_hotplug(dev);
 637         }
 638
 639         intel_opregion_init(dev);
 640
 641         /*
 642          * The console lock can be pretty contented on resume due
 643          * to all the printk activity.  Try to keep it out of the hot
 644          * path of resume if possible.
 645          */
 646         if (console_trylock()) {
 647                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 648                 console_unlock();
 649         } else {
 650                 schedule_work(&dev_priv->console_resume_work);
 651         }
 652
 653         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 654          * expected level. */
 655         hsw_enable_package_c8(dev_priv);
 656
 657         mutex_lock(&dev_priv->modeset_restore_lock);
 658         dev_priv->modeset_restore = MODESET_DONE;
 659         mutex_unlock(&dev_priv->modeset_restore_lock);
 660         return error;
 661 }
 662
 663 static int i915_drm_thaw(struct drm_device *dev)
 664 {
 665         if (drm_core_check_feature(dev, DRIVER_MODESET))
 666                 i915_check_and_clear_faults(dev);
 667
 668         return __i915_drm_thaw(dev, true);
 669 }
 670
 671 int i915_resume(struct drm_device *dev)
 672 {
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674         int ret;
 675
 676         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 677                 return 0;
 678
 679         if (pci_enable_device(dev->pdev))
 680                 return -EIO;
 681
 682         pci_set_master(dev->pdev);
 683
 684         /*
 685          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 686          * earlier) need to restore the GTT mappings since the BIOS might clear
 687          * all our scratch PTEs.
 688          */
 689         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 690         if (ret)
 691                 return ret;
 692
 693         drm_kms_helper_poll_enable(dev);
 694         return 0;
 695 }
 696
 697 /**
 698  * i915_reset - reset chip after a hang
 699  * @dev: drm device to reset
 700  *
 701  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 702  * reset or otherwise an error code.
 703  *
 704  * Procedure is fairly simple:
 705  *   - reset the chip using the reset reg
 706  *   - re-init context state
 707  *   - re-init hardware status page
 708  *   - re-init ring buffer
 709  *   - re-init interrupt state
 710  *   - re-init display
 711  */
 712 int i915_reset(struct drm_device *dev)
 713 {
 714         drm_i915_private_t *dev_priv = dev->dev_private;
 715         bool simulated;
 716         int ret;
 717
 718         if (!i915_try_reset)
 719                 return 0;
 720
 721         mutex_lock(&dev->struct_mutex);
 722
 723         i915_gem_reset(dev);
 724
 725         simulated = dev_priv->gpu_error.stop_rings != 0;
 726
 727         ret = intel_gpu_reset(dev);
 728
 729         /* Also reset the gpu hangman. */
 730         if (simulated) {
 731                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 732                 dev_priv->gpu_error.stop_rings = 0;
 733                 if (ret == -ENODEV) {
 734                         DRM_ERROR("Reset not implemented, but ignoring "
 735                                   "error for simulated gpu hangs\n");
 736                         ret = 0;
 737                 }
 738         }
 739
 740         if (ret) {
 741                 DRM_ERROR("Failed to reset chip.\n");
 742                 mutex_unlock(&dev->struct_mutex);
 743                 return ret;
 744         }
 745
 746         /* Ok, now get things going again... */
 747
 748         /*
 749          * Everything depends on having the GTT running, so we need to start
 750          * there.  Fortunately we don't need to do this unless we reset the
 751          * chip at a PCI level.
 752          *
 753          * Next we need to restore the context, but we don't use those
 754          * yet either...
 755          *
 756          * Ring buffer needs to be re-initialized in the KMS case, or if X
 757          * was running at the time of the reset (i.e. we weren't VT
 758          * switched away).
 759          */
 760         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 761                         !dev_priv->ums.mm_suspended) {
 762                 dev_priv->ums.mm_suspended = 0;
 763
 764                 ret = i915_gem_init_hw(dev);
 765                 mutex_unlock(&dev->struct_mutex);
 766                 if (ret) {
 767                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 768                         return ret;
 769                 }
 770
 771                 drm_irq_uninstall(dev);
 772                 drm_irq_install(dev);
 773                 intel_hpd_init(dev);
 774         } else {
 775                 mutex_unlock(&dev->struct_mutex);
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 782 {
 783         struct intel_device_info *intel_info =
 784                 (struct intel_device_info *) ent->driver_data;
 785
 786         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 787                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 788                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 789                 return -ENODEV;
 790         }
 791
 792         /* Only bind to function 0 of the device. Early generations
 793          * used function 1 as a placeholder for multi-head. This causes
 794          * us confusion instead, especially on the systems where both
 795          * functions have the same PCI-ID!
 796          */
 797         if (PCI_FUNC(pdev->devfn))
 798                 return -ENODEV;
 799
 800         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 801          * implementation for gen3 (and only gen3) that used legacy drm maps
 802          * (gasp!) to share buffers between X and the client. Hence we need to
 803          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 804         if (intel_info->gen != 3) {
 805                 driver.driver_features &=
 806                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 807         } else if (!intel_agp_enabled) {
 808                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 809                 return -ENODEV;
 810         }
 811
 812         return drm_get_pci_dev(pdev, ent, &driver);
 813 }
 814
 815 static void
 816 i915_pci_remove(struct pci_dev *pdev)
 817 {
 818         struct drm_device *dev = pci_get_drvdata(pdev);
 819
 820         drm_put_dev(dev);
 821 }
 822
 823 static int i915_pm_suspend(struct device *dev)
 824 {
 825         struct pci_dev *pdev = to_pci_dev(dev);
 826         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 827         int error;
 828
 829         if (!drm_dev || !drm_dev->dev_private) {
 830                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 831                 return -ENODEV;
 832         }
 833
 834         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 835                 return 0;
 836
 837         error = i915_drm_freeze(drm_dev);
 838         if (error)
 839                 return error;
 840
 841         pci_disable_device(pdev);
 842         pci_set_power_state(pdev, PCI_D3hot);
 843
 844         return 0;
 845 }
 846
 847 static int i915_pm_resume(struct device *dev)
 848 {
 849         struct pci_dev *pdev = to_pci_dev(dev);
 850         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 851
 852         return i915_resume(drm_dev);
 853 }
 854
 855 static int i915_pm_freeze(struct device *dev)
 856 {
 857         struct pci_dev *pdev = to_pci_dev(dev);
 858         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 859
 860         if (!drm_dev || !drm_dev->dev_private) {
 861                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 862                 return -ENODEV;
 863         }
 864
 865         return i915_drm_freeze(drm_dev);
 866 }
 867
 868 static int i915_pm_thaw(struct device *dev)
 869 {
 870         struct pci_dev *pdev = to_pci_dev(dev);
 871         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 872
 873         return i915_drm_thaw(drm_dev);
 874 }
 875
 876 static int i915_pm_poweroff(struct device *dev)
 877 {
 878         struct pci_dev *pdev = to_pci_dev(dev);
 879         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 880
 881         return i915_drm_freeze(drm_dev);
 882 }
 883
 884 static const struct dev_pm_ops i915_pm_ops = {
 885         .suspend = i915_pm_suspend,
 886         .resume = i915_pm_resume,
 887         .freeze = i915_pm_freeze,
 888         .thaw = i915_pm_thaw,
 889         .poweroff = i915_pm_poweroff,
 890         .restore = i915_pm_resume,
 891 };
 892
 893 static const struct vm_operations_struct i915_gem_vm_ops = {
 894         .fault = i915_gem_fault,
 895         .open = drm_gem_vm_open,
 896         .close = drm_gem_vm_close,
 897 };
 898
 899 static const struct file_operations i915_driver_fops = {
 900         .owner = THIS_MODULE,
 901         .open = drm_open,
 902         .release = drm_release,
 903         .unlocked_ioctl = drm_ioctl,
 904         .mmap = drm_gem_mmap,
 905         .poll = drm_poll,
 906         .read = drm_read,
 907 #ifdef CONFIG_COMPAT
 908         .compat_ioctl = i915_compat_ioctl,
 909 #endif
 910         .llseek = noop_llseek,
 911 };
 912
 913 static struct drm_driver driver = {
 914         /* Don't use MTRRs here; the Xserver or userspace app should
 915          * deal with them for Intel hardware.
 916          */
 917         .driver_features =
 918             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 919             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 920             DRIVER_RENDER,
 921         .load = i915_driver_load,
 922         .unload = i915_driver_unload,
 923         .open = i915_driver_open,
 924         .lastclose = i915_driver_lastclose,
 925         .preclose = i915_driver_preclose,
 926         .postclose = i915_driver_postclose,
 927
 928         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 929         .suspend = i915_suspend,
 930         .resume = i915_resume,
 931
 932         .device_is_agp = i915_driver_device_is_agp,
 933         .master_create = i915_master_create,
 934         .master_destroy = i915_master_destroy,
 935 #if defined(CONFIG_DEBUG_FS)
 936         .debugfs_init = i915_debugfs_init,
 937         .debugfs_cleanup = i915_debugfs_cleanup,
 938 #endif
 939         .gem_free_object = i915_gem_free_object,
 940         .gem_vm_ops = &i915_gem_vm_ops,
 941
 942         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 943         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 944         .gem_prime_export = i915_gem_prime_export,
 945         .gem_prime_import = i915_gem_prime_import,
 946
 947         .dumb_create = i915_gem_dumb_create,
 948         .dumb_map_offset = i915_gem_mmap_gtt,
 949         .dumb_destroy = drm_gem_dumb_destroy,
 950         .ioctls = i915_ioctls,
 951         .fops = &i915_driver_fops,
 952         .name = DRIVER_NAME,
 953         .desc = DRIVER_DESC,
 954         .date = DRIVER_DATE,
 955         .major = DRIVER_MAJOR,
 956         .minor = DRIVER_MINOR,
 957         .patchlevel = DRIVER_PATCHLEVEL,
 958 };
 959
 960 static struct pci_driver i915_pci_driver = {
 961         .name = DRIVER_NAME,
 962         .id_table = pciidlist,
 963         .probe = i915_pci_probe,
 964         .remove = i915_pci_remove,
 965         .driver.pm = &i915_pm_ops,
 966 };
 967
 968 static int __init i915_init(void)
 969 {
 970         driver.num_ioctls = i915_max_ioctl;
 971
 972         /*
 973          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 974          * explicitly disabled with the module pararmeter.
 975          *
 976          * Otherwise, just follow the parameter (defaulting to off).
 977          *
 978          * Allow optional vga_text_mode_force boot option to override
 979          * the default behavior.
 980          */
 981 #if defined(CONFIG_DRM_I915_KMS)
 982         if (i915_modeset != 0)
 983                 driver.driver_features |= DRIVER_MODESET;
 984 #endif
 985         if (i915_modeset == 1)
 986                 driver.driver_features |= DRIVER_MODESET;
 987
 988 #ifdef CONFIG_VGA_CONSOLE
 989         if (vgacon_text_force() && i915_modeset == -1)
 990                 driver.driver_features &= ~DRIVER_MODESET;
 991 #endif
 992
 993         if (!(driver.driver_features & DRIVER_MODESET))
 994                 driver.get_vblank_timestamp = NULL;
 995
 996         return drm_pci_init(&driver, &i915_pci_driver);
 997 }
 998
 999 static void __exit i915_exit(void)
1000 {
1001         drm_pci_exit(&driver, &i915_pci_driver);
1002 }
1003
1004 module_init(i915_init);
1005 module_exit(i915_exit);
1006
1007 MODULE_AUTHOR(DRIVER_AUTHOR);
1008 MODULE_DESCRIPTION(DRIVER_DESC);
1009 MODULE_LICENSE("GPL and additional rights");