drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_types.h"
  52 #include "display/intel_dmc.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_dpt.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_hotplug.h"
  57 #include "display/intel_overlay.h"
  58 #include "display/intel_pch_refclk.h"
  59 #include "display/intel_pipe_crc.h"
  60 #include "display/intel_pps.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63
  64 #include "gem/i915_gem_context.h"
  65 #include "gem/i915_gem_ioctls.h"
  66 #include "gem/i915_gem_mman.h"
  67 #include "gem/i915_gem_pm.h"
  68 #include "gt/intel_gt.h"
  69 #include "gt/intel_gt_pm.h"
  70 #include "gt/intel_rc6.h"
  71
  72 #include "pxp/intel_pxp_pm.h"
  73
  74 #include "i915_debugfs.h"
  75 #include "i915_driver.h"
  76 #include "i915_drv.h"
  77 #include "i915_ioc32.h"
  78 #include "i915_irq.h"
  79 #include "i915_memcpy.h"
  80 #include "i915_perf.h"
  81 #include "i915_query.h"
  82 #include "i915_suspend.h"
  83 #include "i915_switcheroo.h"
  84 #include "i915_sysfs.h"
  85 #include "i915_trace.h"
  86 #include "i915_vgpu.h"
  87 #include "intel_dram.h"
  88 #include "intel_gvt.h"
  89 #include "intel_memory_region.h"
  90 #include "intel_pcode.h"
  91 #include "intel_pm.h"
  92 #include "intel_region_ttm.h"
  93 #include "vlv_suspend.h"
  94
  95 static const struct drm_driver i915_drm_driver;
  96
  97 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  98 {
  99         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 100
 101         dev_priv->bridge_dev =
 102                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 103         if (!dev_priv->bridge_dev) {
 104                 drm_err(&dev_priv->drm, "bridge device not found\n");
 105                 return -EIO;
 106         }
 107         return 0;
 108 }
 109
 110 /* Allocate space for the MCH regs if needed, return nonzero on error */
 111 static int
 112 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 113 {
 114         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 115         u32 temp_lo, temp_hi = 0;
 116         u64 mchbar_addr;
 117         int ret;
 118
 119         if (GRAPHICS_VER(dev_priv) >= 4)
 120                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 121         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 122         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 123
 124         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 125 #ifdef CONFIG_PNP
 126         if (mchbar_addr &&
 127             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 128                 return 0;
 129 #endif
 130
 131         /* Get some space for it */
 132         dev_priv->mch_res.name = "i915 MCHBAR";
 133         dev_priv->mch_res.flags = IORESOURCE_MEM;
 134         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 135                                      &dev_priv->mch_res,
 136                                      MCHBAR_SIZE, MCHBAR_SIZE,
 137                                      PCIBIOS_MIN_MEM,
 138                                      0, pcibios_align_resource,
 139                                      dev_priv->bridge_dev);
 140         if (ret) {
 141                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 142                 dev_priv->mch_res.start = 0;
 143                 return ret;
 144         }
 145
 146         if (GRAPHICS_VER(dev_priv) >= 4)
 147                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 148                                        upper_32_bits(dev_priv->mch_res.start));
 149
 150         pci_write_config_dword(dev_priv->bridge_dev, reg,
 151                                lower_32_bits(dev_priv->mch_res.start));
 152         return 0;
 153 }
 154
 155 /* Setup MCHBAR if possible, return true if we should disable it again */
 156 static void
 157 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 158 {
 159         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 160         u32 temp;
 161         bool enabled;
 162
 163         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 164                 return;
 165
 166         dev_priv->mchbar_need_disable = false;
 167
 168         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 169                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 170                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 171         } else {
 172                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 173                 enabled = temp & 1;
 174         }
 175
 176         /* If it's already enabled, don't have to do anything */
 177         if (enabled)
 178                 return;
 179
 180         if (intel_alloc_mchbar_resource(dev_priv))
 181                 return;
 182
 183         dev_priv->mchbar_need_disable = true;
 184
 185         /* Space is allocated or reserved, so enable it. */
 186         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 187                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 188                                        temp | DEVEN_MCHBAR_EN);
 189         } else {
 190                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 191                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 192         }
 193 }
 194
 195 static void
 196 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 197 {
 198         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 199
 200         if (dev_priv->mchbar_need_disable) {
 201                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 202                         u32 deven_val;
 203
 204                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 205                                               &deven_val);
 206                         deven_val &= ~DEVEN_MCHBAR_EN;
 207                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 208                                                deven_val);
 209                 } else {
 210                         u32 mchbar_val;
 211
 212                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 213                                               &mchbar_val);
 214                         mchbar_val &= ~1;
 215                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 216                                                mchbar_val);
 217                 }
 218         }
 219
 220         if (dev_priv->mch_res.start)
 221                 release_resource(&dev_priv->mch_res);
 222 }
 223
 224 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 225 {
 226         /*
 227          * The i915 workqueue is primarily used for batched retirement of
 228          * requests (and thus managing bo) once the task has been completed
 229          * by the GPU. i915_retire_requests() is called directly when we
 230          * need high-priority retirement, such as waiting for an explicit
 231          * bo.
 232          *
 233          * It is also used for periodic low-priority events, such as
 234          * idle-timers and recording error state.
 235          *
 236          * All tasks on the workqueue are expected to acquire the dev mutex
 237          * so there is no point in running more than one instance of the
 238          * workqueue at any time.  Use an ordered one.
 239          */
 240         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 241         if (dev_priv->wq == NULL)
 242                 goto out_err;
 243
 244         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 245         if (dev_priv->hotplug.dp_wq == NULL)
 246                 goto out_free_wq;
 247
 248         return 0;
 249
 250 out_free_wq:
 251         destroy_workqueue(dev_priv->wq);
 252 out_err:
 253         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 254
 255         return -ENOMEM;
 256 }
 257
 258 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 259 {
 260         destroy_workqueue(dev_priv->hotplug.dp_wq);
 261         destroy_workqueue(dev_priv->wq);
 262 }
 263
 264 /*
 265  * We don't keep the workarounds for pre-production hardware, so we expect our
 266  * driver to fail on these machines in one way or another. A little warning on
 267  * dmesg may help both the user and the bug triagers.
 268  *
 269  * Our policy for removing pre-production workarounds is to keep the
 270  * current gen workarounds as a guide to the bring-up of the next gen
 271  * (workarounds have a habit of persisting!). Anything older than that
 272  * should be removed along with the complications they introduce.
 273  */
 274 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 275 {
 276         bool pre = false;
 277
 278         pre |= IS_HSW_EARLY_SDV(dev_priv);
 279         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 280         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 281         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 282         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 283         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 284
 285         if (pre) {
 286                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 287                           "It may not be fully functional.\n");
 288                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 289         }
 290 }
 291
 292 static void sanitize_gpu(struct drm_i915_private *i915)
 293 {
 294         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 295                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 296 }
 297
 298 /**
 299  * i915_driver_early_probe - setup state not requiring device access
 300  * @dev_priv: device private
 301  *
 302  * Initialize everything that is a "SW-only" state, that is state not
 303  * requiring accessing the device or exposing the driver via kernel internal
 304  * or userspace interfaces. Example steps belonging here: lock initialization,
 305  * system memory allocation, setting up device specific attributes and
 306  * function hooks not requiring accessing the device.
 307  */
 308 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 309 {
 310         int ret = 0;
 311
 312         if (i915_inject_probe_failure(dev_priv))
 313                 return -ENODEV;
 314
 315         intel_device_info_subplatform_init(dev_priv);
 316         intel_step_init(dev_priv);
 317
 318         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 319         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 320
 321         spin_lock_init(&dev_priv->irq_lock);
 322         spin_lock_init(&dev_priv->gpu_error.lock);
 323         mutex_init(&dev_priv->backlight_lock);
 324
 325         mutex_init(&dev_priv->sb_lock);
 326         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 327
 328         mutex_init(&dev_priv->audio.mutex);
 329         mutex_init(&dev_priv->wm.wm_mutex);
 330         mutex_init(&dev_priv->pps_mutex);
 331         mutex_init(&dev_priv->hdcp_comp_mutex);
 332
 333         i915_memcpy_init_early(dev_priv);
 334         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 335
 336         ret = i915_workqueues_init(dev_priv);
 337         if (ret < 0)
 338                 return ret;
 339
 340         ret = vlv_suspend_init(dev_priv);
 341         if (ret < 0)
 342                 goto err_workqueues;
 343
 344         ret = intel_region_ttm_device_init(dev_priv);
 345         if (ret)
 346                 goto err_ttm;
 347
 348         intel_wopcm_init_early(&dev_priv->wopcm);
 349
 350         intel_gt_init_early(&dev_priv->gt, dev_priv);
 351
 352         i915_gem_init_early(dev_priv);
 353
 354         /* This must be called before any calls to HAS_PCH_* */
 355         intel_detect_pch(dev_priv);
 356
 357         intel_pm_setup(dev_priv);
 358         ret = intel_power_domains_init(dev_priv);
 359         if (ret < 0)
 360                 goto err_gem;
 361         intel_irq_init(dev_priv);
 362         intel_init_display_hooks(dev_priv);
 363         intel_init_clock_gating_hooks(dev_priv);
 364
 365         intel_detect_preproduction_hw(dev_priv);
 366
 367         return 0;
 368
 369 err_gem:
 370         i915_gem_cleanup_early(dev_priv);
 371         intel_gt_driver_late_release(&dev_priv->gt);
 372         intel_region_ttm_device_fini(dev_priv);
 373 err_ttm:
 374         vlv_suspend_cleanup(dev_priv);
 375 err_workqueues:
 376         i915_workqueues_cleanup(dev_priv);
 377         return ret;
 378 }
 379
 380 /**
 381  * i915_driver_late_release - cleanup the setup done in
 382  *                             i915_driver_early_probe()
 383  * @dev_priv: device private
 384  */
 385 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 386 {
 387         intel_irq_fini(dev_priv);
 388         intel_power_domains_cleanup(dev_priv);
 389         i915_gem_cleanup_early(dev_priv);
 390         intel_gt_driver_late_release(&dev_priv->gt);
 391         intel_region_ttm_device_fini(dev_priv);
 392         vlv_suspend_cleanup(dev_priv);
 393         i915_workqueues_cleanup(dev_priv);
 394
 395         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 396         mutex_destroy(&dev_priv->sb_lock);
 397
 398         i915_params_free(&dev_priv->params);
 399 }
 400
 401 /**
 402  * i915_driver_mmio_probe - setup device MMIO
 403  * @dev_priv: device private
 404  *
 405  * Setup minimal device state necessary for MMIO accesses later in the
 406  * initialization sequence. The setup here should avoid any other device-wide
 407  * side effects or exposing the driver via kernel internal or user space
 408  * interfaces.
 409  */
 410 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 411 {
 412         int ret;
 413
 414         if (i915_inject_probe_failure(dev_priv))
 415                 return -ENODEV;
 416
 417         ret = i915_get_bridge_dev(dev_priv);
 418         if (ret < 0)
 419                 return ret;
 420
 421         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 422         if (ret < 0)
 423                 goto err_bridge;
 424
 425         /* Try to make sure MCHBAR is enabled before poking at it */
 426         intel_setup_mchbar(dev_priv);
 427         intel_device_info_runtime_init(dev_priv);
 428
 429         ret = intel_gt_init_mmio(&dev_priv->gt);
 430         if (ret)
 431                 goto err_uncore;
 432
 433         /* As early as possible, scrub existing GPU state before clobbering */
 434         sanitize_gpu(dev_priv);
 435
 436         return 0;
 437
 438 err_uncore:
 439         intel_teardown_mchbar(dev_priv);
 440         intel_uncore_fini_mmio(&dev_priv->uncore);
 441 err_bridge:
 442         pci_dev_put(dev_priv->bridge_dev);
 443
 444         return ret;
 445 }
 446
 447 /**
 448  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 449  * @dev_priv: device private
 450  */
 451 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 452 {
 453         intel_teardown_mchbar(dev_priv);
 454         intel_uncore_fini_mmio(&dev_priv->uncore);
 455         pci_dev_put(dev_priv->bridge_dev);
 456 }
 457
 458 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 459 {
 460         intel_gvt_sanitize_options(dev_priv);
 461 }
 462
 463 /**
 464  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 465  * platform
 466  * @i915: valid i915 instance
 467  *
 468  * Set the dma max segment size, device and coherent masks.  The dma mask set
 469  * needs to occur before i915_ggtt_probe_hw.
 470  *
 471  * A couple of platforms have special needs.  Address them as well.
 472  *
 473  */
 474 static int i915_set_dma_info(struct drm_i915_private *i915)
 475 {
 476         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 477         int ret;
 478
 479         GEM_BUG_ON(!mask_size);
 480
 481         /*
 482          * We don't have a max segment size, so set it to the max so sg's
 483          * debugging layer doesn't complain
 484          */
 485         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 486
 487         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 488         if (ret)
 489                 goto mask_err;
 490
 491         /* overlay on gen2 is broken and can't address above 1G */
 492         if (GRAPHICS_VER(i915) == 2)
 493                 mask_size = 30;
 494
 495         /*
 496          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 497          * using 32bit addressing, overwriting memory if HWS is located
 498          * above 4GB.
 499          *
 500          * The documentation also mentions an issue with undefined
 501          * behaviour if any general state is accessed within a page above 4GB,
 502          * which also needs to be handled carefully.
 503          */
 504         if (IS_I965G(i915) || IS_I965GM(i915))
 505                 mask_size = 32;
 506
 507         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 508         if (ret)
 509                 goto mask_err;
 510
 511         return 0;
 512
 513 mask_err:
 514         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 515         return ret;
 516 }
 517
 518 /**
 519  * i915_driver_hw_probe - setup state requiring device access
 520  * @dev_priv: device private
 521  *
 522  * Setup state that requires accessing the device, but doesn't require
 523  * exposing the driver via kernel internal or userspace interfaces.
 524  */
 525 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 526 {
 527         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 528         int ret;
 529
 530         if (i915_inject_probe_failure(dev_priv))
 531                 return -ENODEV;
 532
 533         if (HAS_PPGTT(dev_priv)) {
 534                 if (intel_vgpu_active(dev_priv) &&
 535                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 536                         i915_report_error(dev_priv,
 537                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 538                         return -ENXIO;
 539                 }
 540         }
 541
 542         if (HAS_EXECLISTS(dev_priv)) {
 543                 /*
 544                  * Older GVT emulation depends upon intercepting CSB mmio,
 545                  * which we no longer use, preferring to use the HWSP cache
 546                  * instead.
 547                  */
 548                 if (intel_vgpu_active(dev_priv) &&
 549                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 550                         i915_report_error(dev_priv,
 551                                           "old vGPU host found, support for HWSP emulation required\n");
 552                         return -ENXIO;
 553                 }
 554         }
 555
 556         intel_sanitize_options(dev_priv);
 557
 558         /* needs to be done before ggtt probe */
 559         intel_dram_edram_detect(dev_priv);
 560
 561         ret = i915_set_dma_info(dev_priv);
 562         if (ret)
 563                 return ret;
 564
 565         i915_perf_init(dev_priv);
 566
 567         ret = i915_ggtt_probe_hw(dev_priv);
 568         if (ret)
 569                 goto err_perf;
 570
 571         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 572         if (ret)
 573                 goto err_ggtt;
 574
 575         ret = i915_ggtt_init_hw(dev_priv);
 576         if (ret)
 577                 goto err_ggtt;
 578
 579         ret = intel_memory_regions_hw_probe(dev_priv);
 580         if (ret)
 581                 goto err_ggtt;
 582
 583         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 584
 585         ret = intel_gt_probe_lmem(&dev_priv->gt);
 586         if (ret)
 587                 goto err_mem_regions;
 588
 589         ret = i915_ggtt_enable_hw(dev_priv);
 590         if (ret) {
 591                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 592                 goto err_mem_regions;
 593         }
 594
 595         pci_set_master(pdev);
 596
 597         /* On the 945G/GM, the chipset reports the MSI capability on the
 598          * integrated graphics even though the support isn't actually there
 599          * according to the published specs.  It doesn't appear to function
 600          * correctly in testing on 945G.
 601          * This may be a side effect of MSI having been made available for PEG
 602          * and the registers being closely associated.
 603          *
 604          * According to chipset errata, on the 965GM, MSI interrupts may
 605          * be lost or delayed, and was defeatured. MSI interrupts seem to
 606          * get lost on g4x as well, and interrupt delivery seems to stay
 607          * properly dead afterwards. So we'll just disable them for all
 608          * pre-gen5 chipsets.
 609          *
 610          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 611          * interrupts even when in MSI mode. This results in spurious
 612          * interrupt warnings if the legacy irq no. is shared with another
 613          * device. The kernel then disables that interrupt source and so
 614          * prevents the other device from working properly.
 615          */
 616         if (GRAPHICS_VER(dev_priv) >= 5) {
 617                 if (pci_enable_msi(pdev) < 0)
 618                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 619         }
 620
 621         ret = intel_gvt_init(dev_priv);
 622         if (ret)
 623                 goto err_msi;
 624
 625         intel_opregion_setup(dev_priv);
 626
 627         ret = intel_pcode_init(dev_priv);
 628         if (ret)
 629                 goto err_msi;
 630
 631         /*
 632          * Fill the dram structure to get the system dram info. This will be
 633          * used for memory latency calculation.
 634          */
 635         intel_dram_detect(dev_priv);
 636
 637         intel_bw_init_hw(dev_priv);
 638
 639         return 0;
 640
 641 err_msi:
 642         if (pdev->msi_enabled)
 643                 pci_disable_msi(pdev);
 644 err_mem_regions:
 645         intel_memory_regions_driver_release(dev_priv);
 646 err_ggtt:
 647         i915_ggtt_driver_release(dev_priv);
 648         i915_gem_drain_freed_objects(dev_priv);
 649         i915_ggtt_driver_late_release(dev_priv);
 650 err_perf:
 651         i915_perf_fini(dev_priv);
 652         return ret;
 653 }
 654
 655 /**
 656  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 657  * @dev_priv: device private
 658  */
 659 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 660 {
 661         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 662
 663         i915_perf_fini(dev_priv);
 664
 665         if (pdev->msi_enabled)
 666                 pci_disable_msi(pdev);
 667 }
 668
 669 /**
 670  * i915_driver_register - register the driver with the rest of the system
 671  * @dev_priv: device private
 672  *
 673  * Perform any steps necessary to make the driver available via kernel
 674  * internal or userspace interfaces.
 675  */
 676 static void i915_driver_register(struct drm_i915_private *dev_priv)
 677 {
 678         struct drm_device *dev = &dev_priv->drm;
 679
 680         i915_gem_driver_register(dev_priv);
 681         i915_pmu_register(dev_priv);
 682
 683         intel_vgpu_register(dev_priv);
 684
 685         /* Reveal our presence to userspace */
 686         if (drm_dev_register(dev, 0)) {
 687                 drm_err(&dev_priv->drm,
 688                         "Failed to register driver for userspace access!\n");
 689                 return;
 690         }
 691
 692         i915_debugfs_register(dev_priv);
 693         i915_setup_sysfs(dev_priv);
 694
 695         /* Depends on sysfs having been initialized */
 696         i915_perf_register(dev_priv);
 697
 698         intel_gt_driver_register(&dev_priv->gt);
 699
 700         intel_display_driver_register(dev_priv);
 701
 702         intel_power_domains_enable(dev_priv);
 703         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 704
 705         intel_register_dsm_handler();
 706
 707         if (i915_switcheroo_register(dev_priv))
 708                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 709 }
 710
 711 /**
 712  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 713  * @dev_priv: device private
 714  */
 715 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 716 {
 717         i915_switcheroo_unregister(dev_priv);
 718
 719         intel_unregister_dsm_handler();
 720
 721         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 722         intel_power_domains_disable(dev_priv);
 723
 724         intel_display_driver_unregister(dev_priv);
 725
 726         intel_gt_driver_unregister(&dev_priv->gt);
 727
 728         i915_perf_unregister(dev_priv);
 729         i915_pmu_unregister(dev_priv);
 730
 731         i915_teardown_sysfs(dev_priv);
 732         drm_dev_unplug(&dev_priv->drm);
 733
 734         i915_gem_driver_unregister(dev_priv);
 735 }
 736
 737 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 738 {
 739         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 740                 struct drm_printer p = drm_debug_printer("i915 device info:");
 741
 742                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 743                            INTEL_DEVID(dev_priv),
 744                            INTEL_REVID(dev_priv),
 745                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 746                            intel_subplatform(RUNTIME_INFO(dev_priv),
 747                                              INTEL_INFO(dev_priv)->platform),
 748                            GRAPHICS_VER(dev_priv));
 749
 750                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 751                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 752                 intel_gt_info_print(&dev_priv->gt.info, &p);
 753         }
 754
 755         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 756                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 757         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 758                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 759         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 760                 drm_info(&dev_priv->drm,
 761                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 762 }
 763
 764 static struct drm_i915_private *
 765 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 766 {
 767         const struct intel_device_info *match_info =
 768                 (struct intel_device_info *)ent->driver_data;
 769         struct intel_device_info *device_info;
 770         struct drm_i915_private *i915;
 771
 772         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 773                                   struct drm_i915_private, drm);
 774         if (IS_ERR(i915))
 775                 return i915;
 776
 777         pci_set_drvdata(pdev, i915);
 778
 779         /* Device parameters start as a copy of module parameters. */
 780         i915_params_copy(&i915->params, &i915_modparams);
 781
 782         /* Setup the write-once "constant" device info */
 783         device_info = mkwrite_device_info(i915);
 784         memcpy(device_info, match_info, sizeof(*device_info));
 785         RUNTIME_INFO(i915)->device_id = pdev->device;
 786
 787         return i915;
 788 }
 789
 790 /**
 791  * i915_driver_probe - setup chip and create an initial config
 792  * @pdev: PCI device
 793  * @ent: matching PCI ID entry
 794  *
 795  * The driver probe routine has to do several things:
 796  *   - drive output discovery via intel_modeset_init()
 797  *   - initialize the memory manager
 798  *   - allocate initial config memory
 799  *   - setup the DRM framebuffer with the allocated memory
 800  */
 801 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 802 {
 803         const struct intel_device_info *match_info =
 804                 (struct intel_device_info *)ent->driver_data;
 805         struct drm_i915_private *i915;
 806         int ret;
 807
 808         i915 = i915_driver_create(pdev, ent);
 809         if (IS_ERR(i915))
 810                 return PTR_ERR(i915);
 811
 812         /* Disable nuclear pageflip by default on pre-ILK */
 813         if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
 814                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 815
 816         /*
 817          * Check if we support fake LMEM -- for now we only unleash this for
 818          * the live selftests(test-and-exit).
 819          */
 820 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 821         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 822                 if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&
 823                     i915->params.fake_lmem_start) {
 824                         mkwrite_device_info(i915)->memory_regions =
 825                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
 826                         GEM_BUG_ON(!HAS_LMEM(i915));
 827                 }
 828         }
 829 #endif
 830
 831         ret = pci_enable_device(pdev);
 832         if (ret)
 833                 goto out_fini;
 834
 835         ret = i915_driver_early_probe(i915);
 836         if (ret < 0)
 837                 goto out_pci_disable;
 838
 839         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 840
 841         intel_vgpu_detect(i915);
 842
 843         ret = i915_driver_mmio_probe(i915);
 844         if (ret < 0)
 845                 goto out_runtime_pm_put;
 846
 847         ret = i915_driver_hw_probe(i915);
 848         if (ret < 0)
 849                 goto out_cleanup_mmio;
 850
 851         ret = intel_modeset_init_noirq(i915);
 852         if (ret < 0)
 853                 goto out_cleanup_hw;
 854
 855         ret = intel_irq_install(i915);
 856         if (ret)
 857                 goto out_cleanup_modeset;
 858
 859         ret = intel_modeset_init_nogem(i915);
 860         if (ret)
 861                 goto out_cleanup_irq;
 862
 863         ret = i915_gem_init(i915);
 864         if (ret)
 865                 goto out_cleanup_modeset2;
 866
 867         ret = intel_modeset_init(i915);
 868         if (ret)
 869                 goto out_cleanup_gem;
 870
 871         i915_driver_register(i915);
 872
 873         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 874
 875         i915_welcome_messages(i915);
 876
 877         i915->do_release = true;
 878
 879         return 0;
 880
 881 out_cleanup_gem:
 882         i915_gem_suspend(i915);
 883         i915_gem_driver_remove(i915);
 884         i915_gem_driver_release(i915);
 885 out_cleanup_modeset2:
 886         /* FIXME clean up the error path */
 887         intel_modeset_driver_remove(i915);
 888         intel_irq_uninstall(i915);
 889         intel_modeset_driver_remove_noirq(i915);
 890         goto out_cleanup_modeset;
 891 out_cleanup_irq:
 892         intel_irq_uninstall(i915);
 893 out_cleanup_modeset:
 894         intel_modeset_driver_remove_nogem(i915);
 895 out_cleanup_hw:
 896         i915_driver_hw_remove(i915);
 897         intel_memory_regions_driver_release(i915);
 898         i915_ggtt_driver_release(i915);
 899         i915_gem_drain_freed_objects(i915);
 900         i915_ggtt_driver_late_release(i915);
 901 out_cleanup_mmio:
 902         i915_driver_mmio_release(i915);
 903 out_runtime_pm_put:
 904         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 905         i915_driver_late_release(i915);
 906 out_pci_disable:
 907         pci_disable_device(pdev);
 908 out_fini:
 909         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 910         return ret;
 911 }
 912
 913 void i915_driver_remove(struct drm_i915_private *i915)
 914 {
 915         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 916
 917         i915_driver_unregister(i915);
 918
 919         /* Flush any external code that still may be under the RCU lock */
 920         synchronize_rcu();
 921
 922         i915_gem_suspend(i915);
 923
 924         intel_gvt_driver_remove(i915);
 925
 926         intel_modeset_driver_remove(i915);
 927
 928         intel_irq_uninstall(i915);
 929
 930         intel_modeset_driver_remove_noirq(i915);
 931
 932         i915_reset_error_state(i915);
 933         i915_gem_driver_remove(i915);
 934
 935         intel_modeset_driver_remove_nogem(i915);
 936
 937         i915_driver_hw_remove(i915);
 938
 939         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 940 }
 941
 942 static void i915_driver_release(struct drm_device *dev)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(dev);
 945         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 946
 947         if (!dev_priv->do_release)
 948                 return;
 949
 950         disable_rpm_wakeref_asserts(rpm);
 951
 952         i915_gem_driver_release(dev_priv);
 953
 954         intel_memory_regions_driver_release(dev_priv);
 955         i915_ggtt_driver_release(dev_priv);
 956         i915_gem_drain_freed_objects(dev_priv);
 957         i915_ggtt_driver_late_release(dev_priv);
 958
 959         i915_driver_mmio_release(dev_priv);
 960
 961         enable_rpm_wakeref_asserts(rpm);
 962         intel_runtime_pm_driver_release(rpm);
 963
 964         i915_driver_late_release(dev_priv);
 965 }
 966
 967 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 968 {
 969         struct drm_i915_private *i915 = to_i915(dev);
 970         int ret;
 971
 972         ret = i915_gem_open(i915, file);
 973         if (ret)
 974                 return ret;
 975
 976         return 0;
 977 }
 978
 979 /**
 980  * i915_driver_lastclose - clean up after all DRM clients have exited
 981  * @dev: DRM device
 982  *
 983  * Take care of cleaning up after all DRM clients have exited.  In the
 984  * mode setting case, we want to restore the kernel's initial mode (just
 985  * in case the last client left us in a bad state).
 986  *
 987  * Additionally, in the non-mode setting case, we'll tear down the GTT
 988  * and DMA structures, since the kernel won't be using them, and clea
 989  * up any GEM state.
 990  */
 991 static void i915_driver_lastclose(struct drm_device *dev)
 992 {
 993         struct drm_i915_private *i915 = to_i915(dev);
 994
 995         intel_fbdev_restore_mode(dev);
 996
 997         if (HAS_DISPLAY(i915))
 998                 vga_switcheroo_process_delayed_switch();
 999 }
1000
1001 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1002 {
1003         struct drm_i915_file_private *file_priv = file->driver_priv;
1004
1005         i915_gem_context_close(file);
1006
1007         kfree_rcu(file_priv, rcu);
1008
1009         /* Catch up with all the deferred frees from "this" client */
1010         i915_gem_flush_free_objects(to_i915(dev));
1011 }
1012
1013 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1014 {
1015         struct drm_device *dev = &dev_priv->drm;
1016         struct intel_encoder *encoder;
1017
1018         if (!HAS_DISPLAY(dev_priv))
1019                 return;
1020
1021         drm_modeset_lock_all(dev);
1022         for_each_intel_encoder(dev, encoder)
1023                 if (encoder->suspend)
1024                         encoder->suspend(encoder);
1025         drm_modeset_unlock_all(dev);
1026 }
1027
1028 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1029 {
1030         struct drm_device *dev = &dev_priv->drm;
1031         struct intel_encoder *encoder;
1032
1033         if (!HAS_DISPLAY(dev_priv))
1034                 return;
1035
1036         drm_modeset_lock_all(dev);
1037         for_each_intel_encoder(dev, encoder)
1038                 if (encoder->shutdown)
1039                         encoder->shutdown(encoder);
1040         drm_modeset_unlock_all(dev);
1041 }
1042
1043 void i915_driver_shutdown(struct drm_i915_private *i915)
1044 {
1045         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1046         intel_runtime_pm_disable(&i915->runtime_pm);
1047         intel_power_domains_disable(i915);
1048
1049         i915_gem_suspend(i915);
1050
1051         if (HAS_DISPLAY(i915)) {
1052                 drm_kms_helper_poll_disable(&i915->drm);
1053
1054                 drm_atomic_helper_shutdown(&i915->drm);
1055         }
1056
1057         intel_dp_mst_suspend(i915);
1058
1059         intel_runtime_pm_disable_interrupts(i915);
1060         intel_hpd_cancel_work(i915);
1061
1062         intel_suspend_encoders(i915);
1063         intel_shutdown_encoders(i915);
1064
1065         intel_dmc_ucode_suspend(i915);
1066
1067         /*
1068          * The only requirement is to reboot with display DC states disabled,
1069          * for now leaving all display power wells in the INIT power domain
1070          * enabled.
1071          *
1072          * TODO:
1073          * - unify the pci_driver::shutdown sequence here with the
1074          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1075          * - unify the driver remove and system/runtime suspend sequences with
1076          *   the above unified shutdown/poweroff sequence.
1077          */
1078         intel_power_domains_driver_remove(i915);
1079         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1080
1081         intel_runtime_pm_driver_release(&i915->runtime_pm);
1082 }
1083
1084 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1085 {
1086 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1087         if (acpi_target_system_state() < ACPI_STATE_S3)
1088                 return true;
1089 #endif
1090         return false;
1091 }
1092
1093 static int i915_drm_prepare(struct drm_device *dev)
1094 {
1095         struct drm_i915_private *i915 = to_i915(dev);
1096
1097         /*
1098          * NB intel_display_suspend() may issue new requests after we've
1099          * ostensibly marked the GPU as ready-to-sleep here. We need to
1100          * split out that work and pull it forward so that after point,
1101          * the GPU is not woken again.
1102          */
1103         return i915_gem_backup_suspend(i915);
1104 }
1105
1106 static int i915_drm_suspend(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = to_i915(dev);
1109         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1110         pci_power_t opregion_target_state;
1111
1112         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1113
1114         /* We do a lot of poking in a lot of registers, make sure they work
1115          * properly. */
1116         intel_power_domains_disable(dev_priv);
1117         if (HAS_DISPLAY(dev_priv))
1118                 drm_kms_helper_poll_disable(dev);
1119
1120         pci_save_state(pdev);
1121
1122         intel_display_suspend(dev);
1123
1124         intel_dp_mst_suspend(dev_priv);
1125
1126         intel_runtime_pm_disable_interrupts(dev_priv);
1127         intel_hpd_cancel_work(dev_priv);
1128
1129         intel_suspend_encoders(dev_priv);
1130
1131         intel_suspend_hw(dev_priv);
1132
1133         /* Must be called before GGTT is suspended. */
1134         intel_dpt_suspend(dev_priv);
1135         i915_ggtt_suspend(&dev_priv->ggtt);
1136
1137         i915_save_display(dev_priv);
1138
1139         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1140         intel_opregion_suspend(dev_priv, opregion_target_state);
1141
1142         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1143
1144         dev_priv->suspend_count++;
1145
1146         intel_dmc_ucode_suspend(dev_priv);
1147
1148         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1149
1150         return 0;
1151 }
1152
1153 static enum i915_drm_suspend_mode
1154 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1155 {
1156         if (hibernate)
1157                 return I915_DRM_SUSPEND_HIBERNATE;
1158
1159         if (suspend_to_idle(dev_priv))
1160                 return I915_DRM_SUSPEND_IDLE;
1161
1162         return I915_DRM_SUSPEND_MEM;
1163 }
1164
1165 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1166 {
1167         struct drm_i915_private *dev_priv = to_i915(dev);
1168         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1169         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1170         int ret;
1171
1172         disable_rpm_wakeref_asserts(rpm);
1173
1174         i915_gem_suspend_late(dev_priv);
1175
1176         intel_uncore_suspend(&dev_priv->uncore);
1177
1178         intel_power_domains_suspend(dev_priv,
1179                                     get_suspend_mode(dev_priv, hibernation));
1180
1181         intel_display_power_suspend_late(dev_priv);
1182
1183         ret = vlv_suspend_complete(dev_priv);
1184         if (ret) {
1185                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1186                 intel_power_domains_resume(dev_priv);
1187
1188                 goto out;
1189         }
1190
1191         /*
1192          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1193          * This should be totally removed when we handle the pci states properly
1194          * on runtime PM and on s2idle cases.
1195          */
1196         if (suspend_to_idle(dev_priv))
1197                 pci_d3cold_disable(pdev);
1198
1199         pci_disable_device(pdev);
1200         /*
1201          * During hibernation on some platforms the BIOS may try to access
1202          * the device even though it's already in D3 and hang the machine. So
1203          * leave the device in D0 on those platforms and hope the BIOS will
1204          * power down the device properly. The issue was seen on multiple old
1205          * GENs with different BIOS vendors, so having an explicit blacklist
1206          * is inpractical; apply the workaround on everything pre GEN6. The
1207          * platforms where the issue was seen:
1208          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1209          * Fujitsu FSC S7110
1210          * Acer Aspire 1830T
1211          */
1212         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1213                 pci_set_power_state(pdev, PCI_D3hot);
1214
1215 out:
1216         enable_rpm_wakeref_asserts(rpm);
1217         if (!dev_priv->uncore.user_forcewake_count)
1218                 intel_runtime_pm_driver_release(rpm);
1219
1220         return ret;
1221 }
1222
1223 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1224                                    pm_message_t state)
1225 {
1226         int error;
1227
1228         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1229                              state.event != PM_EVENT_FREEZE))
1230                 return -EINVAL;
1231
1232         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1233                 return 0;
1234
1235         error = i915_drm_suspend(&i915->drm);
1236         if (error)
1237                 return error;
1238
1239         return i915_drm_suspend_late(&i915->drm, false);
1240 }
1241
1242 static int i915_drm_resume(struct drm_device *dev)
1243 {
1244         struct drm_i915_private *dev_priv = to_i915(dev);
1245         int ret;
1246
1247         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1248
1249         ret = intel_pcode_init(dev_priv);
1250         if (ret)
1251                 return ret;
1252
1253         sanitize_gpu(dev_priv);
1254
1255         ret = i915_ggtt_enable_hw(dev_priv);
1256         if (ret)
1257                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1258
1259         i915_ggtt_resume(&dev_priv->ggtt);
1260         /* Must be called after GGTT is resumed. */
1261         intel_dpt_resume(dev_priv);
1262
1263         intel_dmc_ucode_resume(dev_priv);
1264
1265         i915_restore_display(dev_priv);
1266         intel_pps_unlock_regs_wa(dev_priv);
1267
1268         intel_init_pch_refclk(dev_priv);
1269
1270         /*
1271          * Interrupts have to be enabled before any batches are run. If not the
1272          * GPU will hang. i915_gem_init_hw() will initiate batches to
1273          * update/restore the context.
1274          *
1275          * drm_mode_config_reset() needs AUX interrupts.
1276          *
1277          * Modeset enabling in intel_modeset_init_hw() also needs working
1278          * interrupts.
1279          */
1280         intel_runtime_pm_enable_interrupts(dev_priv);
1281
1282         if (HAS_DISPLAY(dev_priv))
1283                 drm_mode_config_reset(dev);
1284
1285         i915_gem_resume(dev_priv);
1286
1287         intel_modeset_init_hw(dev_priv);
1288         intel_init_clock_gating(dev_priv);
1289         intel_hpd_init(dev_priv);
1290
1291         /* MST sideband requires HPD interrupts enabled */
1292         intel_dp_mst_resume(dev_priv);
1293         intel_display_resume(dev);
1294
1295         intel_hpd_poll_disable(dev_priv);
1296         if (HAS_DISPLAY(dev_priv))
1297                 drm_kms_helper_poll_enable(dev);
1298
1299         intel_opregion_resume(dev_priv);
1300
1301         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1302
1303         intel_power_domains_enable(dev_priv);
1304
1305         intel_gvt_resume(dev_priv);
1306
1307         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1308
1309         return 0;
1310 }
1311
1312 static int i915_drm_resume_early(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = to_i915(dev);
1315         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1316         int ret;
1317
1318         /*
1319          * We have a resume ordering issue with the snd-hda driver also
1320          * requiring our device to be power up. Due to the lack of a
1321          * parent/child relationship we currently solve this with an early
1322          * resume hook.
1323          *
1324          * FIXME: This should be solved with a special hdmi sink device or
1325          * similar so that power domains can be employed.
1326          */
1327
1328         /*
1329          * Note that we need to set the power state explicitly, since we
1330          * powered off the device during freeze and the PCI core won't power
1331          * it back up for us during thaw. Powering off the device during
1332          * freeze is not a hard requirement though, and during the
1333          * suspend/resume phases the PCI core makes sure we get here with the
1334          * device powered on. So in case we change our freeze logic and keep
1335          * the device powered we can also remove the following set power state
1336          * call.
1337          */
1338         ret = pci_set_power_state(pdev, PCI_D0);
1339         if (ret) {
1340                 drm_err(&dev_priv->drm,
1341                         "failed to set PCI D0 power state (%d)\n", ret);
1342                 return ret;
1343         }
1344
1345         /*
1346          * Note that pci_enable_device() first enables any parent bridge
1347          * device and only then sets the power state for this device. The
1348          * bridge enabling is a nop though, since bridge devices are resumed
1349          * first. The order of enabling power and enabling the device is
1350          * imposed by the PCI core as described above, so here we preserve the
1351          * same order for the freeze/thaw phases.
1352          *
1353          * TODO: eventually we should remove pci_disable_device() /
1354          * pci_enable_enable_device() from suspend/resume. Due to how they
1355          * depend on the device enable refcount we can't anyway depend on them
1356          * disabling/enabling the device.
1357          */
1358         if (pci_enable_device(pdev))
1359                 return -EIO;
1360
1361         pci_set_master(pdev);
1362
1363         pci_d3cold_enable(pdev);
1364
1365         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1366
1367         ret = vlv_resume_prepare(dev_priv, false);
1368         if (ret)
1369                 drm_err(&dev_priv->drm,
1370                         "Resume prepare failed: %d, continuing anyway\n", ret);
1371
1372         intel_uncore_resume_early(&dev_priv->uncore);
1373
1374         intel_gt_check_and_clear_faults(&dev_priv->gt);
1375
1376         intel_display_power_resume_early(dev_priv);
1377
1378         intel_power_domains_resume(dev_priv);
1379
1380         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1381
1382         return ret;
1383 }
1384
1385 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1386 {
1387         int ret;
1388
1389         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1390                 return 0;
1391
1392         ret = i915_drm_resume_early(&i915->drm);
1393         if (ret)
1394                 return ret;
1395
1396         return i915_drm_resume(&i915->drm);
1397 }
1398
1399 static int i915_pm_prepare(struct device *kdev)
1400 {
1401         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1402
1403         if (!i915) {
1404                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1405                 return -ENODEV;
1406         }
1407
1408         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1409                 return 0;
1410
1411         return i915_drm_prepare(&i915->drm);
1412 }
1413
1414 static int i915_pm_suspend(struct device *kdev)
1415 {
1416         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1417
1418         if (!i915) {
1419                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1420                 return -ENODEV;
1421         }
1422
1423         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1424                 return 0;
1425
1426         return i915_drm_suspend(&i915->drm);
1427 }
1428
1429 static int i915_pm_suspend_late(struct device *kdev)
1430 {
1431         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1432
1433         /*
1434          * We have a suspend ordering issue with the snd-hda driver also
1435          * requiring our device to be power up. Due to the lack of a
1436          * parent/child relationship we currently solve this with an late
1437          * suspend hook.
1438          *
1439          * FIXME: This should be solved with a special hdmi sink device or
1440          * similar so that power domains can be employed.
1441          */
1442         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1443                 return 0;
1444
1445         return i915_drm_suspend_late(&i915->drm, false);
1446 }
1447
1448 static int i915_pm_poweroff_late(struct device *kdev)
1449 {
1450         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1451
1452         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1453                 return 0;
1454
1455         return i915_drm_suspend_late(&i915->drm, true);
1456 }
1457
1458 static int i915_pm_resume_early(struct device *kdev)
1459 {
1460         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1461
1462         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1463                 return 0;
1464
1465         return i915_drm_resume_early(&i915->drm);
1466 }
1467
1468 static int i915_pm_resume(struct device *kdev)
1469 {
1470         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1471
1472         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1473                 return 0;
1474
1475         return i915_drm_resume(&i915->drm);
1476 }
1477
1478 /* freeze: before creating the hibernation_image */
1479 static int i915_pm_freeze(struct device *kdev)
1480 {
1481         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1482         int ret;
1483
1484         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1485                 ret = i915_drm_suspend(&i915->drm);
1486                 if (ret)
1487                         return ret;
1488         }
1489
1490         ret = i915_gem_freeze(i915);
1491         if (ret)
1492                 return ret;
1493
1494         return 0;
1495 }
1496
1497 static int i915_pm_freeze_late(struct device *kdev)
1498 {
1499         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1500         int ret;
1501
1502         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1503                 ret = i915_drm_suspend_late(&i915->drm, true);
1504                 if (ret)
1505                         return ret;
1506         }
1507
1508         ret = i915_gem_freeze_late(i915);
1509         if (ret)
1510                 return ret;
1511
1512         return 0;
1513 }
1514
1515 /* thaw: called after creating the hibernation image, but before turning off. */
1516 static int i915_pm_thaw_early(struct device *kdev)
1517 {
1518         return i915_pm_resume_early(kdev);
1519 }
1520
1521 static int i915_pm_thaw(struct device *kdev)
1522 {
1523         return i915_pm_resume(kdev);
1524 }
1525
1526 /* restore: called after loading the hibernation image. */
1527 static int i915_pm_restore_early(struct device *kdev)
1528 {
1529         return i915_pm_resume_early(kdev);
1530 }
1531
1532 static int i915_pm_restore(struct device *kdev)
1533 {
1534         return i915_pm_resume(kdev);
1535 }
1536
1537 static int intel_runtime_suspend(struct device *kdev)
1538 {
1539         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1540         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1541         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1542         int ret;
1543
1544         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1545                 return -ENODEV;
1546
1547         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1548
1549         disable_rpm_wakeref_asserts(rpm);
1550
1551         /*
1552          * We are safe here against re-faults, since the fault handler takes
1553          * an RPM reference.
1554          */
1555         i915_gem_runtime_suspend(dev_priv);
1556
1557         intel_gt_runtime_suspend(&dev_priv->gt);
1558
1559         intel_runtime_pm_disable_interrupts(dev_priv);
1560
1561         intel_uncore_suspend(&dev_priv->uncore);
1562
1563         intel_display_power_suspend(dev_priv);
1564
1565         ret = vlv_suspend_complete(dev_priv);
1566         if (ret) {
1567                 drm_err(&dev_priv->drm,
1568                         "Runtime suspend failed, disabling it (%d)\n", ret);
1569                 intel_uncore_runtime_resume(&dev_priv->uncore);
1570
1571                 intel_runtime_pm_enable_interrupts(dev_priv);
1572
1573                 intel_gt_runtime_resume(&dev_priv->gt);
1574
1575                 enable_rpm_wakeref_asserts(rpm);
1576
1577                 return ret;
1578         }
1579
1580         enable_rpm_wakeref_asserts(rpm);
1581         intel_runtime_pm_driver_release(rpm);
1582
1583         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1584                 drm_err(&dev_priv->drm,
1585                         "Unclaimed access detected prior to suspending\n");
1586
1587         /*
1588          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1589          * This should be totally removed when we handle the pci states properly
1590          * on runtime PM and on s2idle cases.
1591          */
1592         pci_d3cold_disable(pdev);
1593         rpm->suspended = true;
1594
1595         /*
1596          * FIXME: We really should find a document that references the arguments
1597          * used below!
1598          */
1599         if (IS_BROADWELL(dev_priv)) {
1600                 /*
1601                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1602                  * being detected, and the call we do at intel_runtime_resume()
1603                  * won't be able to restore them. Since PCI_D3hot matches the
1604                  * actual specification and appears to be working, use it.
1605                  */
1606                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1607         } else {
1608                 /*
1609                  * current versions of firmware which depend on this opregion
1610                  * notification have repurposed the D1 definition to mean
1611                  * "runtime suspended" vs. what you would normally expect (D3)
1612                  * to distinguish it from notifications that might be sent via
1613                  * the suspend path.
1614                  */
1615                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1616         }
1617
1618         assert_forcewakes_inactive(&dev_priv->uncore);
1619
1620         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1621                 intel_hpd_poll_enable(dev_priv);
1622
1623         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1624         return 0;
1625 }
1626
1627 static int intel_runtime_resume(struct device *kdev)
1628 {
1629         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1630         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1631         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1632         int ret;
1633
1634         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1635                 return -ENODEV;
1636
1637         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1638
1639         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1640         disable_rpm_wakeref_asserts(rpm);
1641
1642         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1643         rpm->suspended = false;
1644         pci_d3cold_enable(pdev);
1645         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1646                 drm_dbg(&dev_priv->drm,
1647                         "Unclaimed access during suspend, bios?\n");
1648
1649         intel_display_power_resume(dev_priv);
1650
1651         ret = vlv_resume_prepare(dev_priv, true);
1652
1653         intel_uncore_runtime_resume(&dev_priv->uncore);
1654
1655         intel_runtime_pm_enable_interrupts(dev_priv);
1656
1657         /*
1658          * No point of rolling back things in case of an error, as the best
1659          * we can do is to hope that things will still work (and disable RPM).
1660          */
1661         intel_gt_runtime_resume(&dev_priv->gt);
1662
1663         /*
1664          * On VLV/CHV display interrupts are part of the display
1665          * power well, so hpd is reinitialized from there. For
1666          * everyone else do it here.
1667          */
1668         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1669                 intel_hpd_init(dev_priv);
1670                 intel_hpd_poll_disable(dev_priv);
1671         }
1672
1673         intel_enable_ipc(dev_priv);
1674
1675         enable_rpm_wakeref_asserts(rpm);
1676
1677         if (ret)
1678                 drm_err(&dev_priv->drm,
1679                         "Runtime resume failed, disabling it (%d)\n", ret);
1680         else
1681                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1682
1683         return ret;
1684 }
1685
1686 const struct dev_pm_ops i915_pm_ops = {
1687         /*
1688          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1689          * PMSG_RESUME]
1690          */
1691         .prepare = i915_pm_prepare,
1692         .suspend = i915_pm_suspend,
1693         .suspend_late = i915_pm_suspend_late,
1694         .resume_early = i915_pm_resume_early,
1695         .resume = i915_pm_resume,
1696
1697         /*
1698          * S4 event handlers
1699          * @freeze, @freeze_late    : called (1) before creating the
1700          *                            hibernation image [PMSG_FREEZE] and
1701          *                            (2) after rebooting, before restoring
1702          *                            the image [PMSG_QUIESCE]
1703          * @thaw, @thaw_early       : called (1) after creating the hibernation
1704          *                            image, before writing it [PMSG_THAW]
1705          *                            and (2) after failing to create or
1706          *                            restore the image [PMSG_RECOVER]
1707          * @poweroff, @poweroff_late: called after writing the hibernation
1708          *                            image, before rebooting [PMSG_HIBERNATE]
1709          * @restore, @restore_early : called after rebooting and restoring the
1710          *                            hibernation image [PMSG_RESTORE]
1711          */
1712         .freeze = i915_pm_freeze,
1713         .freeze_late = i915_pm_freeze_late,
1714         .thaw_early = i915_pm_thaw_early,
1715         .thaw = i915_pm_thaw,
1716         .poweroff = i915_pm_suspend,
1717         .poweroff_late = i915_pm_poweroff_late,
1718         .restore_early = i915_pm_restore_early,
1719         .restore = i915_pm_restore,
1720
1721         /* S0ix (via runtime suspend) event handlers */
1722         .runtime_suspend = intel_runtime_suspend,
1723         .runtime_resume = intel_runtime_resume,
1724 };
1725
1726 static const struct file_operations i915_driver_fops = {
1727         .owner = THIS_MODULE,
1728         .open = drm_open,
1729         .release = drm_release_noglobal,
1730         .unlocked_ioctl = drm_ioctl,
1731         .mmap = i915_gem_mmap,
1732         .poll = drm_poll,
1733         .read = drm_read,
1734         .compat_ioctl = i915_ioc32_compat_ioctl,
1735         .llseek = noop_llseek,
1736 };
1737
1738 static int
1739 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1740                           struct drm_file *file)
1741 {
1742         return -ENODEV;
1743 }
1744
1745 static const struct drm_ioctl_desc i915_ioctls[] = {
1746         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1747         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1748         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1749         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1750         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1751         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1752         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1754         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1755         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1756         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1757         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1758         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1759         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1760         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1761         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1762         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1767         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1781         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1783         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1785         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1786         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1787         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1788         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1789         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1790         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1794         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1795         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1796         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1797         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1798         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1799         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1800         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1801         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1802         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1803         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1804         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1805 };
1806
1807 static const struct drm_driver i915_drm_driver = {
1808         /* Don't use MTRRs here; the Xserver or userspace app should
1809          * deal with them for Intel hardware.
1810          */
1811         .driver_features =
1812             DRIVER_GEM |
1813             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1814             DRIVER_SYNCOBJ_TIMELINE,
1815         .release = i915_driver_release,
1816         .open = i915_driver_open,
1817         .lastclose = i915_driver_lastclose,
1818         .postclose = i915_driver_postclose,
1819
1820         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1821         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1822         .gem_prime_import = i915_gem_prime_import,
1823
1824         .dumb_create = i915_gem_dumb_create,
1825         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1826
1827         .ioctls = i915_ioctls,
1828         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1829         .fops = &i915_driver_fops,
1830         .name = DRIVER_NAME,
1831         .desc = DRIVER_DESC,
1832         .date = DRIVER_DATE,
1833         .major = DRIVER_MAJOR,
1834         .minor = DRIVER_MINOR,
1835         .patchlevel = DRIVER_PATCHLEVEL,
1836 };