drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/slab.h>
  38 #include <linux/string_helpers.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_driver.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64 #include "display/skl_watermark.h"
  65
  66 #include "gem/i915_gem_context.h"
  67 #include "gem/i915_gem_create.h"
  68 #include "gem/i915_gem_dmabuf.h"
  69 #include "gem/i915_gem_ioctls.h"
  70 #include "gem/i915_gem_mman.h"
  71 #include "gem/i915_gem_pm.h"
  72 #include "gt/intel_gt.h"
  73 #include "gt/intel_gt_pm.h"
  74 #include "gt/intel_rc6.h"
  75
  76 #include "pxp/intel_pxp.h"
  77 #include "pxp/intel_pxp_debugfs.h"
  78 #include "pxp/intel_pxp_pm.h"
  79
  80 #include "soc/intel_dram.h"
  81 #include "soc/intel_gmch.h"
  82
  83 #include "i915_debugfs.h"
  84 #include "i915_driver.h"
  85 #include "i915_drm_client.h"
  86 #include "i915_drv.h"
  87 #include "i915_file_private.h"
  88 #include "i915_getparam.h"
  89 #include "i915_hwmon.h"
  90 #include "i915_ioc32.h"
  91 #include "i915_ioctl.h"
  92 #include "i915_irq.h"
  93 #include "i915_memcpy.h"
  94 #include "i915_perf.h"
  95 #include "i915_query.h"
  96 #include "i915_suspend.h"
  97 #include "i915_switcheroo.h"
  98 #include "i915_sysfs.h"
  99 #include "i915_utils.h"
 100 #include "i915_vgpu.h"
 101 #include "intel_clock_gating.h"
 102 #include "intel_gvt.h"
 103 #include "intel_memory_region.h"
 104 #include "intel_pci_config.h"
 105 #include "intel_pcode.h"
 106 #include "intel_region_ttm.h"
 107 #include "vlv_suspend.h"
 108
 109 static const struct drm_driver i915_drm_driver;
 110
 111 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 112 {
 113         /*
 114          * The i915 workqueue is primarily used for batched retirement of
 115          * requests (and thus managing bo) once the task has been completed
 116          * by the GPU. i915_retire_requests() is called directly when we
 117          * need high-priority retirement, such as waiting for an explicit
 118          * bo.
 119          *
 120          * It is also used for periodic low-priority events, such as
 121          * idle-timers and recording error state.
 122          *
 123          * All tasks on the workqueue are expected to acquire the dev mutex
 124          * so there is no point in running more than one instance of the
 125          * workqueue at any time.  Use an ordered one.
 126          */
 127         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 128         if (dev_priv->wq == NULL)
 129                 goto out_err;
 130
 131         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 132         if (dev_priv->display.hotplug.dp_wq == NULL)
 133                 goto out_free_wq;
 134
 135         return 0;
 136
 137 out_free_wq:
 138         destroy_workqueue(dev_priv->wq);
 139 out_err:
 140         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 141
 142         return -ENOMEM;
 143 }
 144
 145 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 146 {
 147         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 148         destroy_workqueue(dev_priv->wq);
 149 }
 150
 151 /*
 152  * We don't keep the workarounds for pre-production hardware, so we expect our
 153  * driver to fail on these machines in one way or another. A little warning on
 154  * dmesg may help both the user and the bug triagers.
 155  *
 156  * Our policy for removing pre-production workarounds is to keep the
 157  * current gen workarounds as a guide to the bring-up of the next gen
 158  * (workarounds have a habit of persisting!). Anything older than that
 159  * should be removed along with the complications they introduce.
 160  */
 161 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 162 {
 163         bool pre = false;
 164
 165         pre |= IS_HSW_EARLY_SDV(dev_priv);
 166         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 167         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 168         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 169         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 170         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 171         pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 172         pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 173
 174         if (pre) {
 175                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 176                           "It may not be fully functional.\n");
 177                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 178         }
 179 }
 180
 181 static void sanitize_gpu(struct drm_i915_private *i915)
 182 {
 183         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 184                 struct intel_gt *gt;
 185                 unsigned int i;
 186
 187                 for_each_gt(gt, i915, i)
 188                         __intel_gt_reset(gt, ALL_ENGINES);
 189         }
 190 }
 191
 192 /**
 193  * i915_driver_early_probe - setup state not requiring device access
 194  * @dev_priv: device private
 195  *
 196  * Initialize everything that is a "SW-only" state, that is state not
 197  * requiring accessing the device or exposing the driver via kernel internal
 198  * or userspace interfaces. Example steps belonging here: lock initialization,
 199  * system memory allocation, setting up device specific attributes and
 200  * function hooks not requiring accessing the device.
 201  */
 202 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 203 {
 204         int ret = 0;
 205
 206         if (i915_inject_probe_failure(dev_priv))
 207                 return -ENODEV;
 208
 209         intel_device_info_runtime_init_early(dev_priv);
 210
 211         intel_step_init(dev_priv);
 212
 213         intel_uncore_mmio_debug_init_early(dev_priv);
 214
 215         spin_lock_init(&dev_priv->irq_lock);
 216         spin_lock_init(&dev_priv->gpu_error.lock);
 217         mutex_init(&dev_priv->display.backlight.lock);
 218
 219         mutex_init(&dev_priv->sb_lock);
 220         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 221
 222         mutex_init(&dev_priv->display.audio.mutex);
 223         mutex_init(&dev_priv->display.wm.wm_mutex);
 224         mutex_init(&dev_priv->display.pps.mutex);
 225         mutex_init(&dev_priv->display.hdcp.comp_mutex);
 226         spin_lock_init(&dev_priv->display.dkl.phy_lock);
 227
 228         i915_memcpy_init_early(dev_priv);
 229         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 230
 231         ret = i915_workqueues_init(dev_priv);
 232         if (ret < 0)
 233                 return ret;
 234
 235         ret = vlv_suspend_init(dev_priv);
 236         if (ret < 0)
 237                 goto err_workqueues;
 238
 239         ret = intel_region_ttm_device_init(dev_priv);
 240         if (ret)
 241                 goto err_ttm;
 242
 243         ret = intel_root_gt_init_early(dev_priv);
 244         if (ret < 0)
 245                 goto err_rootgt;
 246
 247         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 248
 249         i915_gem_init_early(dev_priv);
 250
 251         /* This must be called before any calls to HAS_PCH_* */
 252         intel_detect_pch(dev_priv);
 253
 254         intel_irq_init(dev_priv);
 255         intel_display_driver_early_probe(dev_priv);
 256         intel_clock_gating_hooks_init(dev_priv);
 257
 258         intel_detect_preproduction_hw(dev_priv);
 259
 260         return 0;
 261
 262 err_rootgt:
 263         intel_region_ttm_device_fini(dev_priv);
 264 err_ttm:
 265         vlv_suspend_cleanup(dev_priv);
 266 err_workqueues:
 267         i915_workqueues_cleanup(dev_priv);
 268         return ret;
 269 }
 270
 271 /**
 272  * i915_driver_late_release - cleanup the setup done in
 273  *                             i915_driver_early_probe()
 274  * @dev_priv: device private
 275  */
 276 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 277 {
 278         intel_irq_fini(dev_priv);
 279         intel_power_domains_cleanup(dev_priv);
 280         i915_gem_cleanup_early(dev_priv);
 281         intel_gt_driver_late_release_all(dev_priv);
 282         i915_drm_clients_fini(&dev_priv->clients);
 283         intel_region_ttm_device_fini(dev_priv);
 284         vlv_suspend_cleanup(dev_priv);
 285         i915_workqueues_cleanup(dev_priv);
 286
 287         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 288         mutex_destroy(&dev_priv->sb_lock);
 289
 290         i915_params_free(&dev_priv->params);
 291 }
 292
 293 /**
 294  * i915_driver_mmio_probe - setup device MMIO
 295  * @dev_priv: device private
 296  *
 297  * Setup minimal device state necessary for MMIO accesses later in the
 298  * initialization sequence. The setup here should avoid any other device-wide
 299  * side effects or exposing the driver via kernel internal or user space
 300  * interfaces.
 301  */
 302 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 303 {
 304         struct intel_gt *gt;
 305         int ret, i;
 306
 307         if (i915_inject_probe_failure(dev_priv))
 308                 return -ENODEV;
 309
 310         ret = intel_gmch_bridge_setup(dev_priv);
 311         if (ret < 0)
 312                 return ret;
 313
 314         for_each_gt(gt, dev_priv, i) {
 315                 ret = intel_uncore_init_mmio(gt->uncore);
 316                 if (ret)
 317                         return ret;
 318
 319                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 320                                                intel_uncore_fini_mmio,
 321                                                gt->uncore);
 322                 if (ret)
 323                         return ret;
 324         }
 325
 326         /* Try to make sure MCHBAR is enabled before poking at it */
 327         intel_gmch_bar_setup(dev_priv);
 328         intel_device_info_runtime_init(dev_priv);
 329
 330         for_each_gt(gt, dev_priv, i) {
 331                 ret = intel_gt_init_mmio(gt);
 332                 if (ret)
 333                         goto err_uncore;
 334         }
 335
 336         /* As early as possible, scrub existing GPU state before clobbering */
 337         sanitize_gpu(dev_priv);
 338
 339         return 0;
 340
 341 err_uncore:
 342         intel_gmch_bar_teardown(dev_priv);
 343
 344         return ret;
 345 }
 346
 347 /**
 348  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 349  * @dev_priv: device private
 350  */
 351 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 352 {
 353         intel_gmch_bar_teardown(dev_priv);
 354 }
 355
 356 /**
 357  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 358  * platform
 359  * @i915: valid i915 instance
 360  *
 361  * Set the dma max segment size, device and coherent masks.  The dma mask set
 362  * needs to occur before i915_ggtt_probe_hw.
 363  *
 364  * A couple of platforms have special needs.  Address them as well.
 365  *
 366  */
 367 static int i915_set_dma_info(struct drm_i915_private *i915)
 368 {
 369         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 370         int ret;
 371
 372         GEM_BUG_ON(!mask_size);
 373
 374         /*
 375          * We don't have a max segment size, so set it to the max so sg's
 376          * debugging layer doesn't complain
 377          */
 378         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 379
 380         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 381         if (ret)
 382                 goto mask_err;
 383
 384         /* overlay on gen2 is broken and can't address above 1G */
 385         if (GRAPHICS_VER(i915) == 2)
 386                 mask_size = 30;
 387
 388         /*
 389          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 390          * using 32bit addressing, overwriting memory if HWS is located
 391          * above 4GB.
 392          *
 393          * The documentation also mentions an issue with undefined
 394          * behaviour if any general state is accessed within a page above 4GB,
 395          * which also needs to be handled carefully.
 396          */
 397         if (IS_I965G(i915) || IS_I965GM(i915))
 398                 mask_size = 32;
 399
 400         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 401         if (ret)
 402                 goto mask_err;
 403
 404         return 0;
 405
 406 mask_err:
 407         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 408         return ret;
 409 }
 410
 411 static int i915_pcode_init(struct drm_i915_private *i915)
 412 {
 413         struct intel_gt *gt;
 414         int id, ret;
 415
 416         for_each_gt(gt, i915, id) {
 417                 ret = intel_pcode_init(gt->uncore);
 418                 if (ret) {
 419                         drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
 420                         return ret;
 421                 }
 422         }
 423
 424         return 0;
 425 }
 426
 427 /**
 428  * i915_driver_hw_probe - setup state requiring device access
 429  * @dev_priv: device private
 430  *
 431  * Setup state that requires accessing the device, but doesn't require
 432  * exposing the driver via kernel internal or userspace interfaces.
 433  */
 434 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 435 {
 436         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 437         struct pci_dev *root_pdev;
 438         int ret;
 439
 440         if (i915_inject_probe_failure(dev_priv))
 441                 return -ENODEV;
 442
 443         if (HAS_PPGTT(dev_priv)) {
 444                 if (intel_vgpu_active(dev_priv) &&
 445                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 446                         i915_report_error(dev_priv,
 447                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 448                         return -ENXIO;
 449                 }
 450         }
 451
 452         if (HAS_EXECLISTS(dev_priv)) {
 453                 /*
 454                  * Older GVT emulation depends upon intercepting CSB mmio,
 455                  * which we no longer use, preferring to use the HWSP cache
 456                  * instead.
 457                  */
 458                 if (intel_vgpu_active(dev_priv) &&
 459                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 460                         i915_report_error(dev_priv,
 461                                           "old vGPU host found, support for HWSP emulation required\n");
 462                         return -ENXIO;
 463                 }
 464         }
 465
 466         /* needs to be done before ggtt probe */
 467         intel_dram_edram_detect(dev_priv);
 468
 469         ret = i915_set_dma_info(dev_priv);
 470         if (ret)
 471                 return ret;
 472
 473         i915_perf_init(dev_priv);
 474
 475         ret = i915_ggtt_probe_hw(dev_priv);
 476         if (ret)
 477                 goto err_perf;
 478
 479         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 480         if (ret)
 481                 goto err_ggtt;
 482
 483         ret = i915_ggtt_init_hw(dev_priv);
 484         if (ret)
 485                 goto err_ggtt;
 486
 487         /*
 488          * Make sure we probe lmem before we probe stolen-lmem. The BAR size
 489          * might be different due to bar resizing.
 490          */
 491         ret = intel_gt_tiles_init(dev_priv);
 492         if (ret)
 493                 goto err_ggtt;
 494
 495         ret = intel_memory_regions_hw_probe(dev_priv);
 496         if (ret)
 497                 goto err_ggtt;
 498
 499         ret = i915_ggtt_enable_hw(dev_priv);
 500         if (ret) {
 501                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 502                 goto err_mem_regions;
 503         }
 504
 505         pci_set_master(pdev);
 506
 507         /* On the 945G/GM, the chipset reports the MSI capability on the
 508          * integrated graphics even though the support isn't actually there
 509          * according to the published specs.  It doesn't appear to function
 510          * correctly in testing on 945G.
 511          * This may be a side effect of MSI having been made available for PEG
 512          * and the registers being closely associated.
 513          *
 514          * According to chipset errata, on the 965GM, MSI interrupts may
 515          * be lost or delayed, and was defeatured. MSI interrupts seem to
 516          * get lost on g4x as well, and interrupt delivery seems to stay
 517          * properly dead afterwards. So we'll just disable them for all
 518          * pre-gen5 chipsets.
 519          *
 520          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 521          * interrupts even when in MSI mode. This results in spurious
 522          * interrupt warnings if the legacy irq no. is shared with another
 523          * device. The kernel then disables that interrupt source and so
 524          * prevents the other device from working properly.
 525          */
 526         if (GRAPHICS_VER(dev_priv) >= 5) {
 527                 if (pci_enable_msi(pdev) < 0)
 528                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 529         }
 530
 531         ret = intel_gvt_init(dev_priv);
 532         if (ret)
 533                 goto err_msi;
 534
 535         intel_opregion_setup(dev_priv);
 536
 537         ret = i915_pcode_init(dev_priv);
 538         if (ret)
 539                 goto err_opregion;
 540
 541         /*
 542          * Fill the dram structure to get the system dram info. This will be
 543          * used for memory latency calculation.
 544          */
 545         intel_dram_detect(dev_priv);
 546
 547         intel_bw_init_hw(dev_priv);
 548
 549         /*
 550          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
 551          * This should be totally removed when we handle the pci states properly
 552          * on runtime PM and on s2idle cases.
 553          */
 554         root_pdev = pcie_find_root_port(pdev);
 555         if (root_pdev)
 556                 pci_d3cold_disable(root_pdev);
 557
 558         return 0;
 559
 560 err_opregion:
 561         intel_opregion_cleanup(dev_priv);
 562 err_msi:
 563         if (pdev->msi_enabled)
 564                 pci_disable_msi(pdev);
 565 err_mem_regions:
 566         intel_memory_regions_driver_release(dev_priv);
 567 err_ggtt:
 568         i915_ggtt_driver_release(dev_priv);
 569         i915_gem_drain_freed_objects(dev_priv);
 570         i915_ggtt_driver_late_release(dev_priv);
 571 err_perf:
 572         i915_perf_fini(dev_priv);
 573         return ret;
 574 }
 575
 576 /**
 577  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 578  * @dev_priv: device private
 579  */
 580 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 581 {
 582         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 583         struct pci_dev *root_pdev;
 584
 585         i915_perf_fini(dev_priv);
 586
 587         intel_opregion_cleanup(dev_priv);
 588
 589         if (pdev->msi_enabled)
 590                 pci_disable_msi(pdev);
 591
 592         root_pdev = pcie_find_root_port(pdev);
 593         if (root_pdev)
 594                 pci_d3cold_enable(root_pdev);
 595 }
 596
 597 /**
 598  * i915_driver_register - register the driver with the rest of the system
 599  * @dev_priv: device private
 600  *
 601  * Perform any steps necessary to make the driver available via kernel
 602  * internal or userspace interfaces.
 603  */
 604 static void i915_driver_register(struct drm_i915_private *dev_priv)
 605 {
 606         struct intel_gt *gt;
 607         unsigned int i;
 608
 609         i915_gem_driver_register(dev_priv);
 610         i915_pmu_register(dev_priv);
 611
 612         intel_vgpu_register(dev_priv);
 613
 614         /* Reveal our presence to userspace */
 615         if (drm_dev_register(&dev_priv->drm, 0)) {
 616                 drm_err(&dev_priv->drm,
 617                         "Failed to register driver for userspace access!\n");
 618                 return;
 619         }
 620
 621         i915_debugfs_register(dev_priv);
 622         i915_setup_sysfs(dev_priv);
 623
 624         /* Depends on sysfs having been initialized */
 625         i915_perf_register(dev_priv);
 626
 627         for_each_gt(gt, dev_priv, i)
 628                 intel_gt_driver_register(gt);
 629
 630         intel_pxp_debugfs_register(dev_priv->pxp);
 631
 632         i915_hwmon_register(dev_priv);
 633
 634         intel_display_driver_register(dev_priv);
 635
 636         intel_power_domains_enable(dev_priv);
 637         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 638
 639         intel_register_dsm_handler();
 640
 641         if (i915_switcheroo_register(dev_priv))
 642                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 643 }
 644
 645 /**
 646  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 647  * @dev_priv: device private
 648  */
 649 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 650 {
 651         struct intel_gt *gt;
 652         unsigned int i;
 653
 654         i915_switcheroo_unregister(dev_priv);
 655
 656         intel_unregister_dsm_handler();
 657
 658         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 659         intel_power_domains_disable(dev_priv);
 660
 661         intel_display_driver_unregister(dev_priv);
 662
 663         intel_pxp_fini(dev_priv);
 664
 665         for_each_gt(gt, dev_priv, i)
 666                 intel_gt_driver_unregister(gt);
 667
 668         i915_hwmon_unregister(dev_priv);
 669
 670         i915_perf_unregister(dev_priv);
 671         i915_pmu_unregister(dev_priv);
 672
 673         i915_teardown_sysfs(dev_priv);
 674         drm_dev_unplug(&dev_priv->drm);
 675
 676         i915_gem_driver_unregister(dev_priv);
 677 }
 678
 679 void
 680 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 681 {
 682         drm_printf(p, "iommu: %s\n",
 683                    str_enabled_disabled(i915_vtd_active(i915)));
 684 }
 685
 686 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 687 {
 688         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 689                 struct drm_printer p = drm_debug_printer("i915 device info:");
 690                 struct intel_gt *gt;
 691                 unsigned int i;
 692
 693                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 694                            INTEL_DEVID(dev_priv),
 695                            INTEL_REVID(dev_priv),
 696                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 697                            intel_subplatform(RUNTIME_INFO(dev_priv),
 698                                              INTEL_INFO(dev_priv)->platform),
 699                            GRAPHICS_VER(dev_priv));
 700
 701                 intel_device_info_print(INTEL_INFO(dev_priv),
 702                                         RUNTIME_INFO(dev_priv), &p);
 703                 i915_print_iommu_status(dev_priv, &p);
 704                 for_each_gt(gt, dev_priv, i)
 705                         intel_gt_info_print(&gt->info, &p);
 706         }
 707
 708         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 709                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 710         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 711                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 712         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 713                 drm_info(&dev_priv->drm,
 714                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 715 }
 716
 717 static struct drm_i915_private *
 718 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 719 {
 720         const struct intel_device_info *match_info =
 721                 (struct intel_device_info *)ent->driver_data;
 722         struct drm_i915_private *i915;
 723
 724         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 725                                   struct drm_i915_private, drm);
 726         if (IS_ERR(i915))
 727                 return i915;
 728
 729         pci_set_drvdata(pdev, i915);
 730
 731         /* Device parameters start as a copy of module parameters. */
 732         i915_params_copy(&i915->params, &i915_modparams);
 733
 734         /* Set up device info and initial runtime info. */
 735         intel_device_info_driver_create(i915, pdev->device, match_info);
 736
 737         return i915;
 738 }
 739
 740 /**
 741  * i915_driver_probe - setup chip and create an initial config
 742  * @pdev: PCI device
 743  * @ent: matching PCI ID entry
 744  *
 745  * The driver probe routine has to do several things:
 746  *   - drive output discovery via intel_display_driver_probe()
 747  *   - initialize the memory manager
 748  *   - allocate initial config memory
 749  *   - setup the DRM framebuffer with the allocated memory
 750  */
 751 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 752 {
 753         struct drm_i915_private *i915;
 754         int ret;
 755
 756         i915 = i915_driver_create(pdev, ent);
 757         if (IS_ERR(i915))
 758                 return PTR_ERR(i915);
 759
 760         ret = pci_enable_device(pdev);
 761         if (ret)
 762                 goto out_fini;
 763
 764         ret = i915_driver_early_probe(i915);
 765         if (ret < 0)
 766                 goto out_pci_disable;
 767
 768         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 769
 770         intel_vgpu_detect(i915);
 771
 772         ret = intel_gt_probe_all(i915);
 773         if (ret < 0)
 774                 goto out_runtime_pm_put;
 775
 776         ret = i915_driver_mmio_probe(i915);
 777         if (ret < 0)
 778                 goto out_tiles_cleanup;
 779
 780         ret = i915_driver_hw_probe(i915);
 781         if (ret < 0)
 782                 goto out_cleanup_mmio;
 783
 784         ret = intel_display_driver_probe_noirq(i915);
 785         if (ret < 0)
 786                 goto out_cleanup_hw;
 787
 788         ret = intel_irq_install(i915);
 789         if (ret)
 790                 goto out_cleanup_modeset;
 791
 792         ret = intel_display_driver_probe_nogem(i915);
 793         if (ret)
 794                 goto out_cleanup_irq;
 795
 796         ret = i915_gem_init(i915);
 797         if (ret)
 798                 goto out_cleanup_modeset2;
 799
 800         intel_pxp_init(i915);
 801
 802         ret = intel_display_driver_probe(i915);
 803         if (ret)
 804                 goto out_cleanup_gem;
 805
 806         i915_driver_register(i915);
 807
 808         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 809
 810         i915_welcome_messages(i915);
 811
 812         i915->do_release = true;
 813
 814         return 0;
 815
 816 out_cleanup_gem:
 817         i915_gem_suspend(i915);
 818         i915_gem_driver_remove(i915);
 819         i915_gem_driver_release(i915);
 820 out_cleanup_modeset2:
 821         /* FIXME clean up the error path */
 822         intel_display_driver_remove(i915);
 823         intel_irq_uninstall(i915);
 824         intel_display_driver_remove_noirq(i915);
 825         goto out_cleanup_modeset;
 826 out_cleanup_irq:
 827         intel_irq_uninstall(i915);
 828 out_cleanup_modeset:
 829         intel_display_driver_remove_nogem(i915);
 830 out_cleanup_hw:
 831         i915_driver_hw_remove(i915);
 832         intel_memory_regions_driver_release(i915);
 833         i915_ggtt_driver_release(i915);
 834         i915_gem_drain_freed_objects(i915);
 835         i915_ggtt_driver_late_release(i915);
 836 out_cleanup_mmio:
 837         i915_driver_mmio_release(i915);
 838 out_tiles_cleanup:
 839         intel_gt_release_all(i915);
 840 out_runtime_pm_put:
 841         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 842         i915_driver_late_release(i915);
 843 out_pci_disable:
 844         pci_disable_device(pdev);
 845 out_fini:
 846         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 847         return ret;
 848 }
 849
 850 void i915_driver_remove(struct drm_i915_private *i915)
 851 {
 852         intel_wakeref_t wakeref;
 853
 854         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 855
 856         i915_driver_unregister(i915);
 857
 858         /* Flush any external code that still may be under the RCU lock */
 859         synchronize_rcu();
 860
 861         i915_gem_suspend(i915);
 862
 863         intel_gvt_driver_remove(i915);
 864
 865         intel_display_driver_remove(i915);
 866
 867         intel_irq_uninstall(i915);
 868
 869         intel_display_driver_remove_noirq(i915);
 870
 871         i915_reset_error_state(i915);
 872         i915_gem_driver_remove(i915);
 873
 874         intel_display_driver_remove_nogem(i915);
 875
 876         i915_driver_hw_remove(i915);
 877
 878         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 879 }
 880
 881 static void i915_driver_release(struct drm_device *dev)
 882 {
 883         struct drm_i915_private *dev_priv = to_i915(dev);
 884         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 885         intel_wakeref_t wakeref;
 886
 887         if (!dev_priv->do_release)
 888                 return;
 889
 890         wakeref = intel_runtime_pm_get(rpm);
 891
 892         i915_gem_driver_release(dev_priv);
 893
 894         intel_memory_regions_driver_release(dev_priv);
 895         i915_ggtt_driver_release(dev_priv);
 896         i915_gem_drain_freed_objects(dev_priv);
 897         i915_ggtt_driver_late_release(dev_priv);
 898
 899         i915_driver_mmio_release(dev_priv);
 900
 901         intel_runtime_pm_put(rpm, wakeref);
 902
 903         intel_runtime_pm_driver_release(rpm);
 904
 905         i915_driver_late_release(dev_priv);
 906 }
 907
 908 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 909 {
 910         struct drm_i915_private *i915 = to_i915(dev);
 911         int ret;
 912
 913         ret = i915_gem_open(i915, file);
 914         if (ret)
 915                 return ret;
 916
 917         return 0;
 918 }
 919
 920 /**
 921  * i915_driver_lastclose - clean up after all DRM clients have exited
 922  * @dev: DRM device
 923  *
 924  * Take care of cleaning up after all DRM clients have exited.  In the
 925  * mode setting case, we want to restore the kernel's initial mode (just
 926  * in case the last client left us in a bad state).
 927  *
 928  * Additionally, in the non-mode setting case, we'll tear down the GTT
 929  * and DMA structures, since the kernel won't be using them, and clea
 930  * up any GEM state.
 931  */
 932 static void i915_driver_lastclose(struct drm_device *dev)
 933 {
 934         struct drm_i915_private *i915 = to_i915(dev);
 935
 936         intel_fbdev_restore_mode(i915);
 937
 938         vga_switcheroo_process_delayed_switch();
 939 }
 940
 941 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 942 {
 943         struct drm_i915_file_private *file_priv = file->driver_priv;
 944
 945         i915_gem_context_close(file);
 946         i915_drm_client_put(file_priv->client);
 947
 948         kfree_rcu(file_priv, rcu);
 949
 950         /* Catch up with all the deferred frees from "this" client */
 951         i915_gem_flush_free_objects(to_i915(dev));
 952 }
 953
 954 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 955 {
 956         struct intel_encoder *encoder;
 957
 958         if (!HAS_DISPLAY(dev_priv))
 959                 return;
 960
 961         drm_modeset_lock_all(&dev_priv->drm);
 962         for_each_intel_encoder(&dev_priv->drm, encoder)
 963                 if (encoder->suspend)
 964                         encoder->suspend(encoder);
 965         drm_modeset_unlock_all(&dev_priv->drm);
 966 }
 967
 968 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
 969 {
 970         struct intel_encoder *encoder;
 971
 972         if (!HAS_DISPLAY(dev_priv))
 973                 return;
 974
 975         drm_modeset_lock_all(&dev_priv->drm);
 976         for_each_intel_encoder(&dev_priv->drm, encoder)
 977                 if (encoder->shutdown)
 978                         encoder->shutdown(encoder);
 979         drm_modeset_unlock_all(&dev_priv->drm);
 980 }
 981
 982 void i915_driver_shutdown(struct drm_i915_private *i915)
 983 {
 984         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 985         intel_runtime_pm_disable(&i915->runtime_pm);
 986         intel_power_domains_disable(i915);
 987
 988         if (HAS_DISPLAY(i915)) {
 989                 drm_kms_helper_poll_disable(&i915->drm);
 990
 991                 drm_atomic_helper_shutdown(&i915->drm);
 992         }
 993
 994         intel_dp_mst_suspend(i915);
 995
 996         intel_runtime_pm_disable_interrupts(i915);
 997         intel_hpd_cancel_work(i915);
 998
 999         intel_suspend_encoders(i915);
1000         intel_shutdown_encoders(i915);
1001
1002         intel_dmc_suspend(i915);
1003
1004         i915_gem_suspend(i915);
1005
1006         /*
1007          * The only requirement is to reboot with display DC states disabled,
1008          * for now leaving all display power wells in the INIT power domain
1009          * enabled.
1010          *
1011          * TODO:
1012          * - unify the pci_driver::shutdown sequence here with the
1013          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1014          * - unify the driver remove and system/runtime suspend sequences with
1015          *   the above unified shutdown/poweroff sequence.
1016          */
1017         intel_power_domains_driver_remove(i915);
1018         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1019
1020         intel_runtime_pm_driver_release(&i915->runtime_pm);
1021 }
1022
1023 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1024 {
1025 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1026         if (acpi_target_system_state() < ACPI_STATE_S3)
1027                 return true;
1028 #endif
1029         return false;
1030 }
1031
1032 static void i915_drm_complete(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *i915 = to_i915(dev);
1035
1036         intel_pxp_resume_complete(i915->pxp);
1037 }
1038
1039 static int i915_drm_prepare(struct drm_device *dev)
1040 {
1041         struct drm_i915_private *i915 = to_i915(dev);
1042
1043         intel_pxp_suspend_prepare(i915->pxp);
1044
1045         /*
1046          * NB intel_display_driver_suspend() may issue new requests after we've
1047          * ostensibly marked the GPU as ready-to-sleep here. We need to
1048          * split out that work and pull it forward so that after point,
1049          * the GPU is not woken again.
1050          */
1051         return i915_gem_backup_suspend(i915);
1052 }
1053
1054 static int i915_drm_suspend(struct drm_device *dev)
1055 {
1056         struct drm_i915_private *dev_priv = to_i915(dev);
1057         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1058         pci_power_t opregion_target_state;
1059
1060         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1061
1062         /* We do a lot of poking in a lot of registers, make sure they work
1063          * properly. */
1064         intel_power_domains_disable(dev_priv);
1065         if (HAS_DISPLAY(dev_priv))
1066                 drm_kms_helper_poll_disable(dev);
1067
1068         pci_save_state(pdev);
1069
1070         intel_display_driver_suspend(dev_priv);
1071
1072         intel_dp_mst_suspend(dev_priv);
1073
1074         intel_runtime_pm_disable_interrupts(dev_priv);
1075         intel_hpd_cancel_work(dev_priv);
1076
1077         intel_suspend_encoders(dev_priv);
1078
1079         /* Must be called before GGTT is suspended. */
1080         intel_dpt_suspend(dev_priv);
1081         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1082
1083         i915_save_display(dev_priv);
1084
1085         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1086         intel_opregion_suspend(dev_priv, opregion_target_state);
1087
1088         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1089
1090         dev_priv->suspend_count++;
1091
1092         intel_dmc_suspend(dev_priv);
1093
1094         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1095
1096         i915_gem_drain_freed_objects(dev_priv);
1097
1098         return 0;
1099 }
1100
1101 static enum i915_drm_suspend_mode
1102 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1103 {
1104         if (hibernate)
1105                 return I915_DRM_SUSPEND_HIBERNATE;
1106
1107         if (suspend_to_idle(dev_priv))
1108                 return I915_DRM_SUSPEND_IDLE;
1109
1110         return I915_DRM_SUSPEND_MEM;
1111 }
1112
1113 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1114 {
1115         struct drm_i915_private *dev_priv = to_i915(dev);
1116         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1117         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1118         struct intel_gt *gt;
1119         int ret, i;
1120
1121         disable_rpm_wakeref_asserts(rpm);
1122
1123         intel_pxp_suspend(dev_priv->pxp);
1124
1125         i915_gem_suspend_late(dev_priv);
1126
1127         for_each_gt(gt, dev_priv, i)
1128                 intel_uncore_suspend(gt->uncore);
1129
1130         intel_power_domains_suspend(dev_priv,
1131                                     get_suspend_mode(dev_priv, hibernation));
1132
1133         intel_display_power_suspend_late(dev_priv);
1134
1135         ret = vlv_suspend_complete(dev_priv);
1136         if (ret) {
1137                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1138                 intel_power_domains_resume(dev_priv);
1139
1140                 goto out;
1141         }
1142
1143         pci_disable_device(pdev);
1144         /*
1145          * During hibernation on some platforms the BIOS may try to access
1146          * the device even though it's already in D3 and hang the machine. So
1147          * leave the device in D0 on those platforms and hope the BIOS will
1148          * power down the device properly. The issue was seen on multiple old
1149          * GENs with different BIOS vendors, so having an explicit blacklist
1150          * is inpractical; apply the workaround on everything pre GEN6. The
1151          * platforms where the issue was seen:
1152          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1153          * Fujitsu FSC S7110
1154          * Acer Aspire 1830T
1155          */
1156         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1157                 pci_set_power_state(pdev, PCI_D3hot);
1158
1159 out:
1160         enable_rpm_wakeref_asserts(rpm);
1161         if (!dev_priv->uncore.user_forcewake_count)
1162                 intel_runtime_pm_driver_release(rpm);
1163
1164         return ret;
1165 }
1166
1167 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1168                                    pm_message_t state)
1169 {
1170         int error;
1171
1172         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1173                              state.event != PM_EVENT_FREEZE))
1174                 return -EINVAL;
1175
1176         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1177                 return 0;
1178
1179         error = i915_drm_suspend(&i915->drm);
1180         if (error)
1181                 return error;
1182
1183         return i915_drm_suspend_late(&i915->drm, false);
1184 }
1185
1186 static int i915_drm_resume(struct drm_device *dev)
1187 {
1188         struct drm_i915_private *dev_priv = to_i915(dev);
1189         struct intel_gt *gt;
1190         int ret, i;
1191
1192         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1193
1194         ret = i915_pcode_init(dev_priv);
1195         if (ret)
1196                 return ret;
1197
1198         sanitize_gpu(dev_priv);
1199
1200         ret = i915_ggtt_enable_hw(dev_priv);
1201         if (ret)
1202                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1203
1204         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1205
1206         for_each_gt(gt, dev_priv, i)
1207                 if (GRAPHICS_VER(gt->i915) >= 8)
1208                         setup_private_pat(gt);
1209
1210         /* Must be called after GGTT is resumed. */
1211         intel_dpt_resume(dev_priv);
1212
1213         intel_dmc_resume(dev_priv);
1214
1215         i915_restore_display(dev_priv);
1216         intel_pps_unlock_regs_wa(dev_priv);
1217
1218         intel_init_pch_refclk(dev_priv);
1219
1220         /*
1221          * Interrupts have to be enabled before any batches are run. If not the
1222          * GPU will hang. i915_gem_init_hw() will initiate batches to
1223          * update/restore the context.
1224          *
1225          * drm_mode_config_reset() needs AUX interrupts.
1226          *
1227          * Modeset enabling in intel_display_driver_init_hw() also needs working
1228          * interrupts.
1229          */
1230         intel_runtime_pm_enable_interrupts(dev_priv);
1231
1232         if (HAS_DISPLAY(dev_priv))
1233                 drm_mode_config_reset(dev);
1234
1235         i915_gem_resume(dev_priv);
1236
1237         intel_display_driver_init_hw(dev_priv);
1238
1239         intel_clock_gating_init(dev_priv);
1240         intel_hpd_init(dev_priv);
1241
1242         /* MST sideband requires HPD interrupts enabled */
1243         intel_dp_mst_resume(dev_priv);
1244         intel_display_driver_resume(dev_priv);
1245
1246         intel_hpd_poll_disable(dev_priv);
1247         if (HAS_DISPLAY(dev_priv))
1248                 drm_kms_helper_poll_enable(dev);
1249
1250         intel_opregion_resume(dev_priv);
1251
1252         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1253
1254         intel_power_domains_enable(dev_priv);
1255
1256         intel_gvt_resume(dev_priv);
1257
1258         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1259
1260         return 0;
1261 }
1262
1263 static int i915_drm_resume_early(struct drm_device *dev)
1264 {
1265         struct drm_i915_private *dev_priv = to_i915(dev);
1266         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1267         struct intel_gt *gt;
1268         int ret, i;
1269
1270         /*
1271          * We have a resume ordering issue with the snd-hda driver also
1272          * requiring our device to be power up. Due to the lack of a
1273          * parent/child relationship we currently solve this with an early
1274          * resume hook.
1275          *
1276          * FIXME: This should be solved with a special hdmi sink device or
1277          * similar so that power domains can be employed.
1278          */
1279
1280         /*
1281          * Note that we need to set the power state explicitly, since we
1282          * powered off the device during freeze and the PCI core won't power
1283          * it back up for us during thaw. Powering off the device during
1284          * freeze is not a hard requirement though, and during the
1285          * suspend/resume phases the PCI core makes sure we get here with the
1286          * device powered on. So in case we change our freeze logic and keep
1287          * the device powered we can also remove the following set power state
1288          * call.
1289          */
1290         ret = pci_set_power_state(pdev, PCI_D0);
1291         if (ret) {
1292                 drm_err(&dev_priv->drm,
1293                         "failed to set PCI D0 power state (%d)\n", ret);
1294                 return ret;
1295         }
1296
1297         /*
1298          * Note that pci_enable_device() first enables any parent bridge
1299          * device and only then sets the power state for this device. The
1300          * bridge enabling is a nop though, since bridge devices are resumed
1301          * first. The order of enabling power and enabling the device is
1302          * imposed by the PCI core as described above, so here we preserve the
1303          * same order for the freeze/thaw phases.
1304          *
1305          * TODO: eventually we should remove pci_disable_device() /
1306          * pci_enable_enable_device() from suspend/resume. Due to how they
1307          * depend on the device enable refcount we can't anyway depend on them
1308          * disabling/enabling the device.
1309          */
1310         if (pci_enable_device(pdev))
1311                 return -EIO;
1312
1313         pci_set_master(pdev);
1314
1315         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1316
1317         ret = vlv_resume_prepare(dev_priv, false);
1318         if (ret)
1319                 drm_err(&dev_priv->drm,
1320                         "Resume prepare failed: %d, continuing anyway\n", ret);
1321
1322         for_each_gt(gt, dev_priv, i) {
1323                 intel_uncore_resume_early(gt->uncore);
1324                 intel_gt_check_and_clear_faults(gt);
1325         }
1326
1327         intel_display_power_resume_early(dev_priv);
1328
1329         intel_power_domains_resume(dev_priv);
1330
1331         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1332
1333         return ret;
1334 }
1335
1336 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1337 {
1338         int ret;
1339
1340         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1341                 return 0;
1342
1343         ret = i915_drm_resume_early(&i915->drm);
1344         if (ret)
1345                 return ret;
1346
1347         return i915_drm_resume(&i915->drm);
1348 }
1349
1350 static int i915_pm_prepare(struct device *kdev)
1351 {
1352         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1353
1354         if (!i915) {
1355                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1356                 return -ENODEV;
1357         }
1358
1359         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1360                 return 0;
1361
1362         return i915_drm_prepare(&i915->drm);
1363 }
1364
1365 static int i915_pm_suspend(struct device *kdev)
1366 {
1367         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1368
1369         if (!i915) {
1370                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1371                 return -ENODEV;
1372         }
1373
1374         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1375                 return 0;
1376
1377         return i915_drm_suspend(&i915->drm);
1378 }
1379
1380 static int i915_pm_suspend_late(struct device *kdev)
1381 {
1382         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1383
1384         /*
1385          * We have a suspend ordering issue with the snd-hda driver also
1386          * requiring our device to be power up. Due to the lack of a
1387          * parent/child relationship we currently solve this with an late
1388          * suspend hook.
1389          *
1390          * FIXME: This should be solved with a special hdmi sink device or
1391          * similar so that power domains can be employed.
1392          */
1393         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1394                 return 0;
1395
1396         return i915_drm_suspend_late(&i915->drm, false);
1397 }
1398
1399 static int i915_pm_poweroff_late(struct device *kdev)
1400 {
1401         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1402
1403         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1404                 return 0;
1405
1406         return i915_drm_suspend_late(&i915->drm, true);
1407 }
1408
1409 static int i915_pm_resume_early(struct device *kdev)
1410 {
1411         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1412
1413         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1414                 return 0;
1415
1416         return i915_drm_resume_early(&i915->drm);
1417 }
1418
1419 static int i915_pm_resume(struct device *kdev)
1420 {
1421         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1422
1423         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1424                 return 0;
1425
1426         return i915_drm_resume(&i915->drm);
1427 }
1428
1429 static void i915_pm_complete(struct device *kdev)
1430 {
1431         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1432
1433         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1434                 return;
1435
1436         i915_drm_complete(&i915->drm);
1437 }
1438
1439 /* freeze: before creating the hibernation_image */
1440 static int i915_pm_freeze(struct device *kdev)
1441 {
1442         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1443         int ret;
1444
1445         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1446                 ret = i915_drm_suspend(&i915->drm);
1447                 if (ret)
1448                         return ret;
1449         }
1450
1451         ret = i915_gem_freeze(i915);
1452         if (ret)
1453                 return ret;
1454
1455         return 0;
1456 }
1457
1458 static int i915_pm_freeze_late(struct device *kdev)
1459 {
1460         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1461         int ret;
1462
1463         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1464                 ret = i915_drm_suspend_late(&i915->drm, true);
1465                 if (ret)
1466                         return ret;
1467         }
1468
1469         ret = i915_gem_freeze_late(i915);
1470         if (ret)
1471                 return ret;
1472
1473         return 0;
1474 }
1475
1476 /* thaw: called after creating the hibernation image, but before turning off. */
1477 static int i915_pm_thaw_early(struct device *kdev)
1478 {
1479         return i915_pm_resume_early(kdev);
1480 }
1481
1482 static int i915_pm_thaw(struct device *kdev)
1483 {
1484         return i915_pm_resume(kdev);
1485 }
1486
1487 /* restore: called after loading the hibernation image. */
1488 static int i915_pm_restore_early(struct device *kdev)
1489 {
1490         return i915_pm_resume_early(kdev);
1491 }
1492
1493 static int i915_pm_restore(struct device *kdev)
1494 {
1495         return i915_pm_resume(kdev);
1496 }
1497
1498 static int intel_runtime_suspend(struct device *kdev)
1499 {
1500         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1501         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1502         struct intel_gt *gt;
1503         int ret, i;
1504
1505         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1506                 return -ENODEV;
1507
1508         drm_dbg(&dev_priv->drm, "Suspending device\n");
1509
1510         disable_rpm_wakeref_asserts(rpm);
1511
1512         /*
1513          * We are safe here against re-faults, since the fault handler takes
1514          * an RPM reference.
1515          */
1516         i915_gem_runtime_suspend(dev_priv);
1517
1518         intel_pxp_runtime_suspend(dev_priv->pxp);
1519
1520         for_each_gt(gt, dev_priv, i)
1521                 intel_gt_runtime_suspend(gt);
1522
1523         intel_runtime_pm_disable_interrupts(dev_priv);
1524
1525         for_each_gt(gt, dev_priv, i)
1526                 intel_uncore_suspend(gt->uncore);
1527
1528         intel_display_power_suspend(dev_priv);
1529
1530         ret = vlv_suspend_complete(dev_priv);
1531         if (ret) {
1532                 drm_err(&dev_priv->drm,
1533                         "Runtime suspend failed, disabling it (%d)\n", ret);
1534                 intel_uncore_runtime_resume(&dev_priv->uncore);
1535
1536                 intel_runtime_pm_enable_interrupts(dev_priv);
1537
1538                 for_each_gt(gt, dev_priv, i)
1539                         intel_gt_runtime_resume(gt);
1540
1541                 enable_rpm_wakeref_asserts(rpm);
1542
1543                 return ret;
1544         }
1545
1546         enable_rpm_wakeref_asserts(rpm);
1547         intel_runtime_pm_driver_release(rpm);
1548
1549         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1550                 drm_err(&dev_priv->drm,
1551                         "Unclaimed access detected prior to suspending\n");
1552
1553         rpm->suspended = true;
1554
1555         /*
1556          * FIXME: We really should find a document that references the arguments
1557          * used below!
1558          */
1559         if (IS_BROADWELL(dev_priv)) {
1560                 /*
1561                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1562                  * being detected, and the call we do at intel_runtime_resume()
1563                  * won't be able to restore them. Since PCI_D3hot matches the
1564                  * actual specification and appears to be working, use it.
1565                  */
1566                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1567         } else {
1568                 /*
1569                  * current versions of firmware which depend on this opregion
1570                  * notification have repurposed the D1 definition to mean
1571                  * "runtime suspended" vs. what you would normally expect (D3)
1572                  * to distinguish it from notifications that might be sent via
1573                  * the suspend path.
1574                  */
1575                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1576         }
1577
1578         assert_forcewakes_inactive(&dev_priv->uncore);
1579
1580         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1581                 intel_hpd_poll_enable(dev_priv);
1582
1583         drm_dbg(&dev_priv->drm, "Device suspended\n");
1584         return 0;
1585 }
1586
1587 static int intel_runtime_resume(struct device *kdev)
1588 {
1589         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1590         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1591         struct intel_gt *gt;
1592         int ret, i;
1593
1594         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1595                 return -ENODEV;
1596
1597         drm_dbg(&dev_priv->drm, "Resuming device\n");
1598
1599         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1600         disable_rpm_wakeref_asserts(rpm);
1601
1602         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1603         rpm->suspended = false;
1604         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1605                 drm_dbg(&dev_priv->drm,
1606                         "Unclaimed access during suspend, bios?\n");
1607
1608         intel_display_power_resume(dev_priv);
1609
1610         ret = vlv_resume_prepare(dev_priv, true);
1611
1612         for_each_gt(gt, dev_priv, i)
1613                 intel_uncore_runtime_resume(gt->uncore);
1614
1615         intel_runtime_pm_enable_interrupts(dev_priv);
1616
1617         /*
1618          * No point of rolling back things in case of an error, as the best
1619          * we can do is to hope that things will still work (and disable RPM).
1620          */
1621         for_each_gt(gt, dev_priv, i)
1622                 intel_gt_runtime_resume(gt);
1623
1624         intel_pxp_runtime_resume(dev_priv->pxp);
1625
1626         /*
1627          * On VLV/CHV display interrupts are part of the display
1628          * power well, so hpd is reinitialized from there. For
1629          * everyone else do it here.
1630          */
1631         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1632                 intel_hpd_init(dev_priv);
1633                 intel_hpd_poll_disable(dev_priv);
1634         }
1635
1636         skl_watermark_ipc_update(dev_priv);
1637
1638         enable_rpm_wakeref_asserts(rpm);
1639
1640         if (ret)
1641                 drm_err(&dev_priv->drm,
1642                         "Runtime resume failed, disabling it (%d)\n", ret);
1643         else
1644                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1645
1646         return ret;
1647 }
1648
1649 const struct dev_pm_ops i915_pm_ops = {
1650         /*
1651          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1652          * PMSG_RESUME]
1653          */
1654         .prepare = i915_pm_prepare,
1655         .suspend = i915_pm_suspend,
1656         .suspend_late = i915_pm_suspend_late,
1657         .resume_early = i915_pm_resume_early,
1658         .resume = i915_pm_resume,
1659         .complete = i915_pm_complete,
1660
1661         /*
1662          * S4 event handlers
1663          * @freeze, @freeze_late    : called (1) before creating the
1664          *                            hibernation image [PMSG_FREEZE] and
1665          *                            (2) after rebooting, before restoring
1666          *                            the image [PMSG_QUIESCE]
1667          * @thaw, @thaw_early       : called (1) after creating the hibernation
1668          *                            image, before writing it [PMSG_THAW]
1669          *                            and (2) after failing to create or
1670          *                            restore the image [PMSG_RECOVER]
1671          * @poweroff, @poweroff_late: called after writing the hibernation
1672          *                            image, before rebooting [PMSG_HIBERNATE]
1673          * @restore, @restore_early : called after rebooting and restoring the
1674          *                            hibernation image [PMSG_RESTORE]
1675          */
1676         .freeze = i915_pm_freeze,
1677         .freeze_late = i915_pm_freeze_late,
1678         .thaw_early = i915_pm_thaw_early,
1679         .thaw = i915_pm_thaw,
1680         .poweroff = i915_pm_suspend,
1681         .poweroff_late = i915_pm_poweroff_late,
1682         .restore_early = i915_pm_restore_early,
1683         .restore = i915_pm_restore,
1684
1685         /* S0ix (via runtime suspend) event handlers */
1686         .runtime_suspend = intel_runtime_suspend,
1687         .runtime_resume = intel_runtime_resume,
1688 };
1689
1690 static const struct file_operations i915_driver_fops = {
1691         .owner = THIS_MODULE,
1692         .open = drm_open,
1693         .release = drm_release_noglobal,
1694         .unlocked_ioctl = drm_ioctl,
1695         .mmap = i915_gem_mmap,
1696         .poll = drm_poll,
1697         .read = drm_read,
1698         .compat_ioctl = i915_ioc32_compat_ioctl,
1699         .llseek = noop_llseek,
1700 #ifdef CONFIG_PROC_FS
1701         .show_fdinfo = i915_drm_client_fdinfo,
1702 #endif
1703 };
1704
1705 static int
1706 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1707                           struct drm_file *file)
1708 {
1709         return -ENODEV;
1710 }
1711
1712 static const struct drm_ioctl_desc i915_ioctls[] = {
1713         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1714         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1715         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1716         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1717         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1718         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1719         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1720         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1721         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1722         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1724         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1725         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1726         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1727         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1728         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1729         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1755         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1756         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1757         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1760         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1762         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1772 };
1773
1774 /*
1775  * Interface history:
1776  *
1777  * 1.1: Original.
1778  * 1.2: Add Power Management
1779  * 1.3: Add vblank support
1780  * 1.4: Fix cmdbuffer path, add heap destroy
1781  * 1.5: Add vblank pipe configuration
1782  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1783  *      - Support vertical blank on secondary display pipe
1784  */
1785 #define DRIVER_MAJOR            1
1786 #define DRIVER_MINOR            6
1787 #define DRIVER_PATCHLEVEL       0
1788
1789 static const struct drm_driver i915_drm_driver = {
1790         /* Don't use MTRRs here; the Xserver or userspace app should
1791          * deal with them for Intel hardware.
1792          */
1793         .driver_features =
1794             DRIVER_GEM |
1795             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1796             DRIVER_SYNCOBJ_TIMELINE,
1797         .release = i915_driver_release,
1798         .open = i915_driver_open,
1799         .lastclose = i915_driver_lastclose,
1800         .postclose = i915_driver_postclose,
1801
1802         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1803         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1804         .gem_prime_import = i915_gem_prime_import,
1805
1806         .dumb_create = i915_gem_dumb_create,
1807         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1808
1809         .ioctls = i915_ioctls,
1810         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1811         .fops = &i915_driver_fops,
1812         .name = DRIVER_NAME,
1813         .desc = DRIVER_DESC,
1814         .date = DRIVER_DATE,
1815         .major = DRIVER_MAJOR,
1816         .minor = DRIVER_MINOR,
1817         .patchlevel = DRIVER_PATCHLEVEL,
1818 };