drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45 #include <linux/pm.h>
  46 #include <linux/pm_runtime.h>
  47
  48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  49
  50 #define BEGIN_LP_RING(n) \
  51         intel_ring_begin(LP_RING(dev_priv), (n))
  52
  53 #define OUT_RING(x) \
  54         intel_ring_emit(LP_RING(dev_priv), x)
  55
  56 #define ADVANCE_LP_RING() \
  57         __intel_ring_advance(LP_RING(dev_priv))
  58
  59 /**
  60  * Lock test for when it's just for synchronization of ring access.
  61  *
  62  * In that case, we don't need to do it when GEM is initialized as nobody else
  63  * has access to the ring.
  64  */
  65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  66         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  67                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  68 } while (0)
  69
  70 static inline u32
  71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  72 {
  73         if (I915_NEED_GFX_HWS(dev_priv->dev))
  74                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  75         else
  76                 return intel_read_status_page(LP_RING(dev_priv), reg);
  77 }
  78
  79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  81 #define I915_BREADCRUMB_INDEX           0x21
  82
  83 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  84 {
  85         drm_i915_private_t *dev_priv = dev->dev_private;
  86         struct drm_i915_master_private *master_priv;
  87
  88         /*
  89          * The dri breadcrumb update races against the drm master disappearing.
  90          * Instead of trying to fix this (this is by far not the only ums issue)
  91          * just don't do the update in kms mode.
  92          */
  93         if (drm_core_check_feature(dev, DRIVER_MODESET))
  94                 return;
  95
  96         if (dev->primary->master) {
  97                 master_priv = dev->primary->master->driver_priv;
  98                 if (master_priv->sarea_priv)
  99                         master_priv->sarea_priv->last_dispatch =
 100                                 READ_BREADCRUMB(dev_priv);
 101         }
 102 }
 103
 104 static void i915_write_hws_pga(struct drm_device *dev)
 105 {
 106         drm_i915_private_t *dev_priv = dev->dev_private;
 107         u32 addr;
 108
 109         addr = dev_priv->status_page_dmah->busaddr;
 110         if (INTEL_INFO(dev)->gen >= 4)
 111                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 112         I915_WRITE(HWS_PGA, addr);
 113 }
 114
 115 /**
 116  * Frees the hardware status page, whether it's a physical address or a virtual
 117  * address set up by the X Server.
 118  */
 119 static void i915_free_hws(struct drm_device *dev)
 120 {
 121         drm_i915_private_t *dev_priv = dev->dev_private;
 122         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 123
 124         if (dev_priv->status_page_dmah) {
 125                 drm_pci_free(dev, dev_priv->status_page_dmah);
 126                 dev_priv->status_page_dmah = NULL;
 127         }
 128
 129         if (ring->status_page.gfx_addr) {
 130                 ring->status_page.gfx_addr = 0;
 131                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 132         }
 133
 134         /* Need to rewrite hardware status page */
 135         I915_WRITE(HWS_PGA, 0x1ffff000);
 136 }
 137
 138 void i915_kernel_lost_context(struct drm_device * dev)
 139 {
 140         drm_i915_private_t *dev_priv = dev->dev_private;
 141         struct drm_i915_master_private *master_priv;
 142         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 143
 144         /*
 145          * We should never lose context on the ring with modesetting
 146          * as we don't expose it to userspace
 147          */
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return;
 150
 151         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 152         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 153         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 154         if (ring->space < 0)
 155                 ring->space += ring->size;
 156
 157         if (!dev->primary->master)
 158                 return;
 159
 160         master_priv = dev->primary->master->driver_priv;
 161         if (ring->head == ring->tail && master_priv->sarea_priv)
 162                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 163 }
 164
 165 static int i915_dma_cleanup(struct drm_device * dev)
 166 {
 167         drm_i915_private_t *dev_priv = dev->dev_private;
 168         int i;
 169
 170         /* Make sure interrupts are disabled here because the uninstall ioctl
 171          * may not have been called from userspace and after dev_private
 172          * is freed, it's too late.
 173          */
 174         if (dev->irq_enabled)
 175                 drm_irq_uninstall(dev);
 176
 177         mutex_lock(&dev->struct_mutex);
 178         for (i = 0; i < I915_NUM_RINGS; i++)
 179                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 180         mutex_unlock(&dev->struct_mutex);
 181
 182         /* Clear the HWS virtual address at teardown */
 183         if (I915_NEED_GFX_HWS(dev))
 184                 i915_free_hws(dev);
 185
 186         return 0;
 187 }
 188
 189 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 190 {
 191         drm_i915_private_t *dev_priv = dev->dev_private;
 192         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 193         int ret;
 194
 195         master_priv->sarea = drm_getsarea(dev);
 196         if (master_priv->sarea) {
 197                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 198                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 199         } else {
 200                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 201         }
 202
 203         if (init->ring_size != 0) {
 204                 if (LP_RING(dev_priv)->obj != NULL) {
 205                         i915_dma_cleanup(dev);
 206                         DRM_ERROR("Client tried to initialize ringbuffer in "
 207                                   "GEM mode\n");
 208                         return -EINVAL;
 209                 }
 210
 211                 ret = intel_render_ring_init_dri(dev,
 212                                                  init->ring_start,
 213                                                  init->ring_size);
 214                 if (ret) {
 215                         i915_dma_cleanup(dev);
 216                         return ret;
 217                 }
 218         }
 219
 220         dev_priv->dri1.cpp = init->cpp;
 221         dev_priv->dri1.back_offset = init->back_offset;
 222         dev_priv->dri1.front_offset = init->front_offset;
 223         dev_priv->dri1.current_page = 0;
 224         if (master_priv->sarea_priv)
 225                 master_priv->sarea_priv->pf_current_page = 0;
 226
 227         /* Allow hardware batchbuffers unless told otherwise.
 228          */
 229         dev_priv->dri1.allow_batchbuffer = 1;
 230
 231         return 0;
 232 }
 233
 234 static int i915_dma_resume(struct drm_device * dev)
 235 {
 236         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 237         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 238
 239         DRM_DEBUG_DRIVER("%s\n", __func__);
 240
 241         if (ring->virtual_start == NULL) {
 242                 DRM_ERROR("can not ioremap virtual address for"
 243                           " ring buffer\n");
 244                 return -ENOMEM;
 245         }
 246
 247         /* Program Hardware Status Page */
 248         if (!ring->status_page.page_addr) {
 249                 DRM_ERROR("Can not find hardware status page\n");
 250                 return -EINVAL;
 251         }
 252         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 253                                 ring->status_page.page_addr);
 254         if (ring->status_page.gfx_addr != 0)
 255                 intel_ring_setup_status_page(ring);
 256         else
 257                 i915_write_hws_pga(dev);
 258
 259         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 260
 261         return 0;
 262 }
 263
 264 static int i915_dma_init(struct drm_device *dev, void *data,
 265                          struct drm_file *file_priv)
 266 {
 267         drm_i915_init_t *init = data;
 268         int retcode = 0;
 269
 270         if (drm_core_check_feature(dev, DRIVER_MODESET))
 271                 return -ENODEV;
 272
 273         switch (init->func) {
 274         case I915_INIT_DMA:
 275                 retcode = i915_initialize(dev, init);
 276                 break;
 277         case I915_CLEANUP_DMA:
 278                 retcode = i915_dma_cleanup(dev);
 279                 break;
 280         case I915_RESUME_DMA:
 281                 retcode = i915_dma_resume(dev);
 282                 break;
 283         default:
 284                 retcode = -EINVAL;
 285                 break;
 286         }
 287
 288         return retcode;
 289 }
 290
 291 /* Implement basically the same security restrictions as hardware does
 292  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 293  *
 294  * Most of the calculations below involve calculating the size of a
 295  * particular instruction.  It's important to get the size right as
 296  * that tells us where the next instruction to check is.  Any illegal
 297  * instruction detected will be given a size of zero, which is a
 298  * signal to abort the rest of the buffer.
 299  */
 300 static int validate_cmd(int cmd)
 301 {
 302         switch (((cmd >> 29) & 0x7)) {
 303         case 0x0:
 304                 switch ((cmd >> 23) & 0x3f) {
 305                 case 0x0:
 306                         return 1;       /* MI_NOOP */
 307                 case 0x4:
 308                         return 1;       /* MI_FLUSH */
 309                 default:
 310                         return 0;       /* disallow everything else */
 311                 }
 312                 break;
 313         case 0x1:
 314                 return 0;       /* reserved */
 315         case 0x2:
 316                 return (cmd & 0xff) + 2;        /* 2d commands */
 317         case 0x3:
 318                 if (((cmd >> 24) & 0x1f) <= 0x18)
 319                         return 1;
 320
 321                 switch ((cmd >> 24) & 0x1f) {
 322                 case 0x1c:
 323                         return 1;
 324                 case 0x1d:
 325                         switch ((cmd >> 16) & 0xff) {
 326                         case 0x3:
 327                                 return (cmd & 0x1f) + 2;
 328                         case 0x4:
 329                                 return (cmd & 0xf) + 2;
 330                         default:
 331                                 return (cmd & 0xffff) + 2;
 332                         }
 333                 case 0x1e:
 334                         if (cmd & (1 << 23))
 335                                 return (cmd & 0xffff) + 1;
 336                         else
 337                                 return 1;
 338                 case 0x1f:
 339                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 340                                 return (cmd & 0x1ffff) + 2;
 341                         else if (cmd & (1 << 17))       /* indirect random */
 342                                 if ((cmd & 0xffff) == 0)
 343                                         return 0;       /* unknown length, too hard */
 344                                 else
 345                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 346                         else
 347                                 return 2;       /* indirect sequential */
 348                 default:
 349                         return 0;
 350                 }
 351         default:
 352                 return 0;
 353         }
 354
 355         return 0;
 356 }
 357
 358 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 359 {
 360         drm_i915_private_t *dev_priv = dev->dev_private;
 361         int i, ret;
 362
 363         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 364                 return -EINVAL;
 365
 366         for (i = 0; i < dwords;) {
 367                 int sz = validate_cmd(buffer[i]);
 368                 if (sz == 0 || i + sz > dwords)
 369                         return -EINVAL;
 370                 i += sz;
 371         }
 372
 373         ret = BEGIN_LP_RING((dwords+1)&~1);
 374         if (ret)
 375                 return ret;
 376
 377         for (i = 0; i < dwords; i++)
 378                 OUT_RING(buffer[i]);
 379         if (dwords & 1)
 380                 OUT_RING(0);
 381
 382         ADVANCE_LP_RING();
 383
 384         return 0;
 385 }
 386
 387 int
 388 i915_emit_box(struct drm_device *dev,
 389               struct drm_clip_rect *box,
 390               int DR1, int DR4)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         int ret;
 394
 395         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 396             box->y2 <= 0 || box->x2 <= 0) {
 397                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 398                           box->x1, box->y1, box->x2, box->y2);
 399                 return -EINVAL;
 400         }
 401
 402         if (INTEL_INFO(dev)->gen >= 4) {
 403                 ret = BEGIN_LP_RING(4);
 404                 if (ret)
 405                         return ret;
 406
 407                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 408                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 409                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 410                 OUT_RING(DR4);
 411         } else {
 412                 ret = BEGIN_LP_RING(6);
 413                 if (ret)
 414                         return ret;
 415
 416                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 417                 OUT_RING(DR1);
 418                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 419                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 420                 OUT_RING(DR4);
 421                 OUT_RING(0);
 422         }
 423         ADVANCE_LP_RING();
 424
 425         return 0;
 426 }
 427
 428 /* XXX: Emitting the counter should really be moved to part of the IRQ
 429  * emit. For now, do it in both places:
 430  */
 431
 432 static void i915_emit_breadcrumb(struct drm_device *dev)
 433 {
 434         drm_i915_private_t *dev_priv = dev->dev_private;
 435         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 436
 437         dev_priv->dri1.counter++;
 438         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 439                 dev_priv->dri1.counter = 0;
 440         if (master_priv->sarea_priv)
 441                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 442
 443         if (BEGIN_LP_RING(4) == 0) {
 444                 OUT_RING(MI_STORE_DWORD_INDEX);
 445                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 446                 OUT_RING(dev_priv->dri1.counter);
 447                 OUT_RING(0);
 448                 ADVANCE_LP_RING();
 449         }
 450 }
 451
 452 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 453                                    drm_i915_cmdbuffer_t *cmd,
 454                                    struct drm_clip_rect *cliprects,
 455                                    void *cmdbuf)
 456 {
 457         int nbox = cmd->num_cliprects;
 458         int i = 0, count, ret;
 459
 460         if (cmd->sz & 0x3) {
 461                 DRM_ERROR("alignment");
 462                 return -EINVAL;
 463         }
 464
 465         i915_kernel_lost_context(dev);
 466
 467         count = nbox ? nbox : 1;
 468
 469         for (i = 0; i < count; i++) {
 470                 if (i < nbox) {
 471                         ret = i915_emit_box(dev, &cliprects[i],
 472                                             cmd->DR1, cmd->DR4);
 473                         if (ret)
 474                                 return ret;
 475                 }
 476
 477                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 478                 if (ret)
 479                         return ret;
 480         }
 481
 482         i915_emit_breadcrumb(dev);
 483         return 0;
 484 }
 485
 486 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 487                                      drm_i915_batchbuffer_t * batch,
 488                                      struct drm_clip_rect *cliprects)
 489 {
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         int nbox = batch->num_cliprects;
 492         int i, count, ret;
 493
 494         if ((batch->start | batch->used) & 0x7) {
 495                 DRM_ERROR("alignment");
 496                 return -EINVAL;
 497         }
 498
 499         i915_kernel_lost_context(dev);
 500
 501         count = nbox ? nbox : 1;
 502         for (i = 0; i < count; i++) {
 503                 if (i < nbox) {
 504                         ret = i915_emit_box(dev, &cliprects[i],
 505                                             batch->DR1, batch->DR4);
 506                         if (ret)
 507                                 return ret;
 508                 }
 509
 510                 if (!IS_I830(dev) && !IS_845G(dev)) {
 511                         ret = BEGIN_LP_RING(2);
 512                         if (ret)
 513                                 return ret;
 514
 515                         if (INTEL_INFO(dev)->gen >= 4) {
 516                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 517                                 OUT_RING(batch->start);
 518                         } else {
 519                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 520                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 521                         }
 522                 } else {
 523                         ret = BEGIN_LP_RING(4);
 524                         if (ret)
 525                                 return ret;
 526
 527                         OUT_RING(MI_BATCH_BUFFER);
 528                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 529                         OUT_RING(batch->start + batch->used - 4);
 530                         OUT_RING(0);
 531                 }
 532                 ADVANCE_LP_RING();
 533         }
 534
 535
 536         if (IS_G4X(dev) || IS_GEN5(dev)) {
 537                 if (BEGIN_LP_RING(2) == 0) {
 538                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 539                         OUT_RING(MI_NOOP);
 540                         ADVANCE_LP_RING();
 541                 }
 542         }
 543
 544         i915_emit_breadcrumb(dev);
 545         return 0;
 546 }
 547
 548 static int i915_dispatch_flip(struct drm_device * dev)
 549 {
 550         drm_i915_private_t *dev_priv = dev->dev_private;
 551         struct drm_i915_master_private *master_priv =
 552                 dev->primary->master->driver_priv;
 553         int ret;
 554
 555         if (!master_priv->sarea_priv)
 556                 return -EINVAL;
 557
 558         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 559                           __func__,
 560                          dev_priv->dri1.current_page,
 561                          master_priv->sarea_priv->pf_current_page);
 562
 563         i915_kernel_lost_context(dev);
 564
 565         ret = BEGIN_LP_RING(10);
 566         if (ret)
 567                 return ret;
 568
 569         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 570         OUT_RING(0);
 571
 572         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 573         OUT_RING(0);
 574         if (dev_priv->dri1.current_page == 0) {
 575                 OUT_RING(dev_priv->dri1.back_offset);
 576                 dev_priv->dri1.current_page = 1;
 577         } else {
 578                 OUT_RING(dev_priv->dri1.front_offset);
 579                 dev_priv->dri1.current_page = 0;
 580         }
 581         OUT_RING(0);
 582
 583         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 584         OUT_RING(0);
 585
 586         ADVANCE_LP_RING();
 587
 588         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 589
 590         if (BEGIN_LP_RING(4) == 0) {
 591                 OUT_RING(MI_STORE_DWORD_INDEX);
 592                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 593                 OUT_RING(dev_priv->dri1.counter);
 594                 OUT_RING(0);
 595                 ADVANCE_LP_RING();
 596         }
 597
 598         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 599         return 0;
 600 }
 601
 602 static int i915_quiescent(struct drm_device *dev)
 603 {
 604         i915_kernel_lost_context(dev);
 605         return intel_ring_idle(LP_RING(dev->dev_private));
 606 }
 607
 608 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 609                             struct drm_file *file_priv)
 610 {
 611         int ret;
 612
 613         if (drm_core_check_feature(dev, DRIVER_MODESET))
 614                 return -ENODEV;
 615
 616         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 617
 618         mutex_lock(&dev->struct_mutex);
 619         ret = i915_quiescent(dev);
 620         mutex_unlock(&dev->struct_mutex);
 621
 622         return ret;
 623 }
 624
 625 static int i915_batchbuffer(struct drm_device *dev, void *data,
 626                             struct drm_file *file_priv)
 627 {
 628         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 629         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 630         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 631             master_priv->sarea_priv;
 632         drm_i915_batchbuffer_t *batch = data;
 633         int ret;
 634         struct drm_clip_rect *cliprects = NULL;
 635
 636         if (drm_core_check_feature(dev, DRIVER_MODESET))
 637                 return -ENODEV;
 638
 639         if (!dev_priv->dri1.allow_batchbuffer) {
 640                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 641                 return -EINVAL;
 642         }
 643
 644         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 645                         batch->start, batch->used, batch->num_cliprects);
 646
 647         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 648
 649         if (batch->num_cliprects < 0)
 650                 return -EINVAL;
 651
 652         if (batch->num_cliprects) {
 653                 cliprects = kcalloc(batch->num_cliprects,
 654                                     sizeof(*cliprects),
 655                                     GFP_KERNEL);
 656                 if (cliprects == NULL)
 657                         return -ENOMEM;
 658
 659                 ret = copy_from_user(cliprects, batch->cliprects,
 660                                      batch->num_cliprects *
 661                                      sizeof(struct drm_clip_rect));
 662                 if (ret != 0) {
 663                         ret = -EFAULT;
 664                         goto fail_free;
 665                 }
 666         }
 667
 668         mutex_lock(&dev->struct_mutex);
 669         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 670         mutex_unlock(&dev->struct_mutex);
 671
 672         if (sarea_priv)
 673                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 674
 675 fail_free:
 676         kfree(cliprects);
 677
 678         return ret;
 679 }
 680
 681 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 682                           struct drm_file *file_priv)
 683 {
 684         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 685         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 686         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 687             master_priv->sarea_priv;
 688         drm_i915_cmdbuffer_t *cmdbuf = data;
 689         struct drm_clip_rect *cliprects = NULL;
 690         void *batch_data;
 691         int ret;
 692
 693         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 694                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 695
 696         if (drm_core_check_feature(dev, DRIVER_MODESET))
 697                 return -ENODEV;
 698
 699         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 700
 701         if (cmdbuf->num_cliprects < 0)
 702                 return -EINVAL;
 703
 704         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 705         if (batch_data == NULL)
 706                 return -ENOMEM;
 707
 708         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 709         if (ret != 0) {
 710                 ret = -EFAULT;
 711                 goto fail_batch_free;
 712         }
 713
 714         if (cmdbuf->num_cliprects) {
 715                 cliprects = kcalloc(cmdbuf->num_cliprects,
 716                                     sizeof(*cliprects), GFP_KERNEL);
 717                 if (cliprects == NULL) {
 718                         ret = -ENOMEM;
 719                         goto fail_batch_free;
 720                 }
 721
 722                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 723                                      cmdbuf->num_cliprects *
 724                                      sizeof(struct drm_clip_rect));
 725                 if (ret != 0) {
 726                         ret = -EFAULT;
 727                         goto fail_clip_free;
 728                 }
 729         }
 730
 731         mutex_lock(&dev->struct_mutex);
 732         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 733         mutex_unlock(&dev->struct_mutex);
 734         if (ret) {
 735                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 736                 goto fail_clip_free;
 737         }
 738
 739         if (sarea_priv)
 740                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 741
 742 fail_clip_free:
 743         kfree(cliprects);
 744 fail_batch_free:
 745         kfree(batch_data);
 746
 747         return ret;
 748 }
 749
 750 static int i915_emit_irq(struct drm_device * dev)
 751 {
 752         drm_i915_private_t *dev_priv = dev->dev_private;
 753         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 754
 755         i915_kernel_lost_context(dev);
 756
 757         DRM_DEBUG_DRIVER("\n");
 758
 759         dev_priv->dri1.counter++;
 760         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 761                 dev_priv->dri1.counter = 1;
 762         if (master_priv->sarea_priv)
 763                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 764
 765         if (BEGIN_LP_RING(4) == 0) {
 766                 OUT_RING(MI_STORE_DWORD_INDEX);
 767                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 768                 OUT_RING(dev_priv->dri1.counter);
 769                 OUT_RING(MI_USER_INTERRUPT);
 770                 ADVANCE_LP_RING();
 771         }
 772
 773         return dev_priv->dri1.counter;
 774 }
 775
 776 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 777 {
 778         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 779         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 780         int ret = 0;
 781         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 782
 783         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 784                   READ_BREADCRUMB(dev_priv));
 785
 786         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 787                 if (master_priv->sarea_priv)
 788                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 789                 return 0;
 790         }
 791
 792         if (master_priv->sarea_priv)
 793                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 794
 795         if (ring->irq_get(ring)) {
 796                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
 797                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 798                 ring->irq_put(ring);
 799         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 800                 ret = -EBUSY;
 801
 802         if (ret == -EBUSY) {
 803                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 804                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 805         }
 806
 807         return ret;
 808 }
 809
 810 /* Needs the lock as it touches the ring.
 811  */
 812 static int i915_irq_emit(struct drm_device *dev, void *data,
 813                          struct drm_file *file_priv)
 814 {
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         drm_i915_irq_emit_t *emit = data;
 817         int result;
 818
 819         if (drm_core_check_feature(dev, DRIVER_MODESET))
 820                 return -ENODEV;
 821
 822         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 823                 DRM_ERROR("called with no initialization\n");
 824                 return -EINVAL;
 825         }
 826
 827         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 828
 829         mutex_lock(&dev->struct_mutex);
 830         result = i915_emit_irq(dev);
 831         mutex_unlock(&dev->struct_mutex);
 832
 833         if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
 834                 DRM_ERROR("copy_to_user\n");
 835                 return -EFAULT;
 836         }
 837
 838         return 0;
 839 }
 840
 841 /* Doesn't need the hardware lock.
 842  */
 843 static int i915_irq_wait(struct drm_device *dev, void *data,
 844                          struct drm_file *file_priv)
 845 {
 846         drm_i915_private_t *dev_priv = dev->dev_private;
 847         drm_i915_irq_wait_t *irqwait = data;
 848
 849         if (drm_core_check_feature(dev, DRIVER_MODESET))
 850                 return -ENODEV;
 851
 852         if (!dev_priv) {
 853                 DRM_ERROR("called with no initialization\n");
 854                 return -EINVAL;
 855         }
 856
 857         return i915_wait_irq(dev, irqwait->irq_seq);
 858 }
 859
 860 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 861                          struct drm_file *file_priv)
 862 {
 863         drm_i915_private_t *dev_priv = dev->dev_private;
 864         drm_i915_vblank_pipe_t *pipe = data;
 865
 866         if (drm_core_check_feature(dev, DRIVER_MODESET))
 867                 return -ENODEV;
 868
 869         if (!dev_priv) {
 870                 DRM_ERROR("called with no initialization\n");
 871                 return -EINVAL;
 872         }
 873
 874         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 875
 876         return 0;
 877 }
 878
 879 /**
 880  * Schedule buffer swap at given vertical blank.
 881  */
 882 static int i915_vblank_swap(struct drm_device *dev, void *data,
 883                      struct drm_file *file_priv)
 884 {
 885         /* The delayed swap mechanism was fundamentally racy, and has been
 886          * removed.  The model was that the client requested a delayed flip/swap
 887          * from the kernel, then waited for vblank before continuing to perform
 888          * rendering.  The problem was that the kernel might wake the client
 889          * up before it dispatched the vblank swap (since the lock has to be
 890          * held while touching the ringbuffer), in which case the client would
 891          * clear and start the next frame before the swap occurred, and
 892          * flicker would occur in addition to likely missing the vblank.
 893          *
 894          * In the absence of this ioctl, userland falls back to a correct path
 895          * of waiting for a vblank, then dispatching the swap on its own.
 896          * Context switching to userland and back is plenty fast enough for
 897          * meeting the requirements of vblank swapping.
 898          */
 899         return -EINVAL;
 900 }
 901
 902 static int i915_flip_bufs(struct drm_device *dev, void *data,
 903                           struct drm_file *file_priv)
 904 {
 905         int ret;
 906
 907         if (drm_core_check_feature(dev, DRIVER_MODESET))
 908                 return -ENODEV;
 909
 910         DRM_DEBUG_DRIVER("%s\n", __func__);
 911
 912         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 913
 914         mutex_lock(&dev->struct_mutex);
 915         ret = i915_dispatch_flip(dev);
 916         mutex_unlock(&dev->struct_mutex);
 917
 918         return ret;
 919 }
 920
 921 static int i915_getparam(struct drm_device *dev, void *data,
 922                          struct drm_file *file_priv)
 923 {
 924         drm_i915_private_t *dev_priv = dev->dev_private;
 925         drm_i915_getparam_t *param = data;
 926         int value;
 927
 928         if (!dev_priv) {
 929                 DRM_ERROR("called with no initialization\n");
 930                 return -EINVAL;
 931         }
 932
 933         switch (param->param) {
 934         case I915_PARAM_IRQ_ACTIVE:
 935                 value = dev->pdev->irq ? 1 : 0;
 936                 break;
 937         case I915_PARAM_ALLOW_BATCHBUFFER:
 938                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 939                 break;
 940         case I915_PARAM_LAST_DISPATCH:
 941                 value = READ_BREADCRUMB(dev_priv);
 942                 break;
 943         case I915_PARAM_CHIPSET_ID:
 944                 value = dev->pdev->device;
 945                 break;
 946         case I915_PARAM_HAS_GEM:
 947                 value = 1;
 948                 break;
 949         case I915_PARAM_NUM_FENCES_AVAIL:
 950                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 951                 break;
 952         case I915_PARAM_HAS_OVERLAY:
 953                 value = dev_priv->overlay ? 1 : 0;
 954                 break;
 955         case I915_PARAM_HAS_PAGEFLIPPING:
 956                 value = 1;
 957                 break;
 958         case I915_PARAM_HAS_EXECBUF2:
 959                 /* depends on GEM */
 960                 value = 1;
 961                 break;
 962         case I915_PARAM_HAS_BSD:
 963                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 964                 break;
 965         case I915_PARAM_HAS_BLT:
 966                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 967                 break;
 968         case I915_PARAM_HAS_VEBOX:
 969                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 970                 break;
 971         case I915_PARAM_HAS_RELAXED_FENCING:
 972                 value = 1;
 973                 break;
 974         case I915_PARAM_HAS_COHERENT_RINGS:
 975                 value = 1;
 976                 break;
 977         case I915_PARAM_HAS_EXEC_CONSTANTS:
 978                 value = INTEL_INFO(dev)->gen >= 4;
 979                 break;
 980         case I915_PARAM_HAS_RELAXED_DELTA:
 981                 value = 1;
 982                 break;
 983         case I915_PARAM_HAS_GEN7_SOL_RESET:
 984                 value = 1;
 985                 break;
 986         case I915_PARAM_HAS_LLC:
 987                 value = HAS_LLC(dev);
 988                 break;
 989         case I915_PARAM_HAS_WT:
 990                 value = HAS_WT(dev);
 991                 break;
 992         case I915_PARAM_HAS_ALIASING_PPGTT:
 993                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 994                 break;
 995         case I915_PARAM_HAS_WAIT_TIMEOUT:
 996                 value = 1;
 997                 break;
 998         case I915_PARAM_HAS_SEMAPHORES:
 999                 value = i915_semaphore_is_enabled(dev);
1000                 break;
1001         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1002                 value = 1;
1003                 break;
1004         case I915_PARAM_HAS_SECURE_BATCHES:
1005                 value = capable(CAP_SYS_ADMIN);
1006                 break;
1007         case I915_PARAM_HAS_PINNED_BATCHES:
1008                 value = 1;
1009                 break;
1010         case I915_PARAM_HAS_EXEC_NO_RELOC:
1011                 value = 1;
1012                 break;
1013         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1014                 value = 1;
1015                 break;
1016         default:
1017                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1018                 return -EINVAL;
1019         }
1020
1021         if (copy_to_user(param->value, &value, sizeof(int))) {
1022                 DRM_ERROR("copy_to_user failed\n");
1023                 return -EFAULT;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int i915_setparam(struct drm_device *dev, void *data,
1030                          struct drm_file *file_priv)
1031 {
1032         drm_i915_private_t *dev_priv = dev->dev_private;
1033         drm_i915_setparam_t *param = data;
1034
1035         if (!dev_priv) {
1036                 DRM_ERROR("called with no initialization\n");
1037                 return -EINVAL;
1038         }
1039
1040         switch (param->param) {
1041         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1042                 break;
1043         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1044                 break;
1045         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1046                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1047                 break;
1048         case I915_SETPARAM_NUM_USED_FENCES:
1049                 if (param->value > dev_priv->num_fence_regs ||
1050                     param->value < 0)
1051                         return -EINVAL;
1052                 /* Userspace can use first N regs */
1053                 dev_priv->fence_reg_start = param->value;
1054                 break;
1055         default:
1056                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1057                                         param->param);
1058                 return -EINVAL;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int i915_set_status_page(struct drm_device *dev, void *data,
1065                                 struct drm_file *file_priv)
1066 {
1067         drm_i915_private_t *dev_priv = dev->dev_private;
1068         drm_i915_hws_addr_t *hws = data;
1069         struct intel_ring_buffer *ring;
1070
1071         if (drm_core_check_feature(dev, DRIVER_MODESET))
1072                 return -ENODEV;
1073
1074         if (!I915_NEED_GFX_HWS(dev))
1075                 return -EINVAL;
1076
1077         if (!dev_priv) {
1078                 DRM_ERROR("called with no initialization\n");
1079                 return -EINVAL;
1080         }
1081
1082         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1083                 WARN(1, "tried to set status page when mode setting active\n");
1084                 return 0;
1085         }
1086
1087         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1088
1089         ring = LP_RING(dev_priv);
1090         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1091
1092         dev_priv->dri1.gfx_hws_cpu_addr =
1093                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1094         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1095                 i915_dma_cleanup(dev);
1096                 ring->status_page.gfx_addr = 0;
1097                 DRM_ERROR("can not ioremap virtual address for"
1098                                 " G33 hw status page\n");
1099                 return -ENOMEM;
1100         }
1101
1102         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1103         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1104
1105         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1106                          ring->status_page.gfx_addr);
1107         DRM_DEBUG_DRIVER("load hws at %p\n",
1108                          ring->status_page.page_addr);
1109         return 0;
1110 }
1111
1112 static int i915_get_bridge_dev(struct drm_device *dev)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115
1116         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1117         if (!dev_priv->bridge_dev) {
1118                 DRM_ERROR("bridge device not found\n");
1119                 return -1;
1120         }
1121         return 0;
1122 }
1123
1124 #define MCHBAR_I915 0x44
1125 #define MCHBAR_I965 0x48
1126 #define MCHBAR_SIZE (4*4096)
1127
1128 #define DEVEN_REG 0x54
1129 #define   DEVEN_MCHBAR_EN (1 << 28)
1130
1131 /* Allocate space for the MCH regs if needed, return nonzero on error */
1132 static int
1133 intel_alloc_mchbar_resource(struct drm_device *dev)
1134 {
1135         drm_i915_private_t *dev_priv = dev->dev_private;
1136         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1137         u32 temp_lo, temp_hi = 0;
1138         u64 mchbar_addr;
1139         int ret;
1140
1141         if (INTEL_INFO(dev)->gen >= 4)
1142                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1143         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1144         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1145
1146         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1147 #ifdef CONFIG_PNP
1148         if (mchbar_addr &&
1149             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1150                 return 0;
1151 #endif
1152
1153         /* Get some space for it */
1154         dev_priv->mch_res.name = "i915 MCHBAR";
1155         dev_priv->mch_res.flags = IORESOURCE_MEM;
1156         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1157                                      &dev_priv->mch_res,
1158                                      MCHBAR_SIZE, MCHBAR_SIZE,
1159                                      PCIBIOS_MIN_MEM,
1160                                      0, pcibios_align_resource,
1161                                      dev_priv->bridge_dev);
1162         if (ret) {
1163                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1164                 dev_priv->mch_res.start = 0;
1165                 return ret;
1166         }
1167
1168         if (INTEL_INFO(dev)->gen >= 4)
1169                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1170                                        upper_32_bits(dev_priv->mch_res.start));
1171
1172         pci_write_config_dword(dev_priv->bridge_dev, reg,
1173                                lower_32_bits(dev_priv->mch_res.start));
1174         return 0;
1175 }
1176
1177 /* Setup MCHBAR if possible, return true if we should disable it again */
1178 static void
1179 intel_setup_mchbar(struct drm_device *dev)
1180 {
1181         drm_i915_private_t *dev_priv = dev->dev_private;
1182         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1183         u32 temp;
1184         bool enabled;
1185
1186         dev_priv->mchbar_need_disable = false;
1187
1188         if (IS_I915G(dev) || IS_I915GM(dev)) {
1189                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1190                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1191         } else {
1192                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1193                 enabled = temp & 1;
1194         }
1195
1196         /* If it's already enabled, don't have to do anything */
1197         if (enabled)
1198                 return;
1199
1200         if (intel_alloc_mchbar_resource(dev))
1201                 return;
1202
1203         dev_priv->mchbar_need_disable = true;
1204
1205         /* Space is allocated or reserved, so enable it. */
1206         if (IS_I915G(dev) || IS_I915GM(dev)) {
1207                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1208                                        temp | DEVEN_MCHBAR_EN);
1209         } else {
1210                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1211                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1212         }
1213 }
1214
1215 static void
1216 intel_teardown_mchbar(struct drm_device *dev)
1217 {
1218         drm_i915_private_t *dev_priv = dev->dev_private;
1219         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1220         u32 temp;
1221
1222         if (dev_priv->mchbar_need_disable) {
1223                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1224                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1225                         temp &= ~DEVEN_MCHBAR_EN;
1226                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1227                 } else {
1228                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1229                         temp &= ~1;
1230                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1231                 }
1232         }
1233
1234         if (dev_priv->mch_res.start)
1235                 release_resource(&dev_priv->mch_res);
1236 }
1237
1238 /* true = enable decode, false = disable decoder */
1239 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1240 {
1241         struct drm_device *dev = cookie;
1242
1243         intel_modeset_vga_set_state(dev, state);
1244         if (state)
1245                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1246                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1247         else
1248                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1249 }
1250
1251 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1252 {
1253         struct drm_device *dev = pci_get_drvdata(pdev);
1254         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1255         if (state == VGA_SWITCHEROO_ON) {
1256                 pr_info("switched on\n");
1257                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1258                 /* i915 resume handler doesn't set to D0 */
1259                 pci_set_power_state(dev->pdev, PCI_D0);
1260                 i915_resume(dev);
1261                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1262         } else {
1263                 pr_err("switched off\n");
1264                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1265                 i915_suspend(dev, pmm);
1266                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1267         }
1268 }
1269
1270 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1271 {
1272         struct drm_device *dev = pci_get_drvdata(pdev);
1273         bool can_switch;
1274
1275         spin_lock(&dev->count_lock);
1276         can_switch = (dev->open_count == 0);
1277         spin_unlock(&dev->count_lock);
1278         return can_switch;
1279 }
1280
1281 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1282         .set_gpu_state = i915_switcheroo_set_state,
1283         .reprobe = NULL,
1284         .can_switch = i915_switcheroo_can_switch,
1285 };
1286
1287 static int i915_load_modeset_init(struct drm_device *dev)
1288 {
1289         struct drm_i915_private *dev_priv = dev->dev_private;
1290         int ret;
1291
1292         ret = intel_parse_bios(dev);
1293         if (ret)
1294                 DRM_INFO("failed to find VBIOS tables\n");
1295
1296         /* If we have > 1 VGA cards, then we need to arbitrate access
1297          * to the common VGA resources.
1298          *
1299          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1300          * then we do not take part in VGA arbitration and the
1301          * vga_client_register() fails with -ENODEV.
1302          */
1303         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1304         if (ret && ret != -ENODEV)
1305                 goto out;
1306
1307         intel_register_dsm_handler();
1308
1309         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1310         if (ret)
1311                 goto cleanup_vga_client;
1312
1313         /* Initialise stolen first so that we may reserve preallocated
1314          * objects for the BIOS to KMS transition.
1315          */
1316         ret = i915_gem_init_stolen(dev);
1317         if (ret)
1318                 goto cleanup_vga_switcheroo;
1319
1320         ret = drm_irq_install(dev);
1321         if (ret)
1322                 goto cleanup_gem_stolen;
1323
1324         intel_power_domains_init_hw(dev);
1325
1326         /* Important: The output setup functions called by modeset_init need
1327          * working irqs for e.g. gmbus and dp aux transfers. */
1328         intel_modeset_init(dev);
1329
1330         ret = i915_gem_init(dev);
1331         if (ret)
1332                 goto cleanup_power;
1333
1334         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1335
1336         intel_modeset_gem_init(dev);
1337
1338         /* Always safe in the mode setting case. */
1339         /* FIXME: do pre/post-mode set stuff in core KMS code */
1340         dev->vblank_disable_allowed = true;
1341         if (INTEL_INFO(dev)->num_pipes == 0) {
1342                 intel_display_power_put(dev, POWER_DOMAIN_VGA);
1343                 return 0;
1344         }
1345
1346         ret = intel_fbdev_init(dev);
1347         if (ret)
1348                 goto cleanup_gem;
1349
1350         /* Only enable hotplug handling once the fbdev is fully set up. */
1351         intel_hpd_init(dev);
1352
1353         /*
1354          * Some ports require correctly set-up hpd registers for detection to
1355          * work properly (leading to ghost connected connector status), e.g. VGA
1356          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1357          * irqs are fully enabled. Now we should scan for the initial config
1358          * only once hotplug handling is enabled, but due to screwed-up locking
1359          * around kms/fbdev init we can't protect the fdbev initial config
1360          * scanning against hotplug events. Hence do this first and ignore the
1361          * tiny window where we will loose hotplug notifactions.
1362          */
1363         intel_fbdev_initial_config(dev);
1364
1365         /* Only enable hotplug handling once the fbdev is fully set up. */
1366         dev_priv->enable_hotplug_processing = true;
1367
1368         drm_kms_helper_poll_init(dev);
1369
1370         return 0;
1371
1372 cleanup_gem:
1373         mutex_lock(&dev->struct_mutex);
1374         i915_gem_cleanup_ringbuffer(dev);
1375         i915_gem_context_fini(dev);
1376         mutex_unlock(&dev->struct_mutex);
1377         i915_gem_cleanup_aliasing_ppgtt(dev);
1378         drm_mm_takedown(&dev_priv->gtt.base.mm);
1379 cleanup_power:
1380         intel_display_power_put(dev, POWER_DOMAIN_VGA);
1381         drm_irq_uninstall(dev);
1382 cleanup_gem_stolen:
1383         i915_gem_cleanup_stolen(dev);
1384 cleanup_vga_switcheroo:
1385         vga_switcheroo_unregister_client(dev->pdev);
1386 cleanup_vga_client:
1387         vga_client_register(dev->pdev, NULL, NULL, NULL);
1388 out:
1389         return ret;
1390 }
1391
1392 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1393 {
1394         struct drm_i915_master_private *master_priv;
1395
1396         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1397         if (!master_priv)
1398                 return -ENOMEM;
1399
1400         master->driver_priv = master_priv;
1401         return 0;
1402 }
1403
1404 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1405 {
1406         struct drm_i915_master_private *master_priv = master->driver_priv;
1407
1408         if (!master_priv)
1409                 return;
1410
1411         kfree(master_priv);
1412
1413         master->driver_priv = NULL;
1414 }
1415
1416 #if IS_ENABLED(CONFIG_FB)
1417 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1418 {
1419         struct apertures_struct *ap;
1420         struct pci_dev *pdev = dev_priv->dev->pdev;
1421         bool primary;
1422
1423         ap = alloc_apertures(1);
1424         if (!ap)
1425                 return;
1426
1427         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1428         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1429
1430         primary =
1431                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1432
1433         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1434
1435         kfree(ap);
1436 }
1437 #else
1438 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1439 {
1440 }
1441 #endif
1442
1443 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1444 {
1445         const struct intel_device_info *info = dev_priv->info;
1446
1447 #define PRINT_S(name) "%s"
1448 #define SEP_EMPTY
1449 #define PRINT_FLAG(name) info->name ? #name "," : ""
1450 #define SEP_COMMA ,
1451         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1452                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1453                          info->gen,
1454                          dev_priv->dev->pdev->device,
1455                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1456 #undef PRINT_S
1457 #undef SEP_EMPTY
1458 #undef PRINT_FLAG
1459 #undef SEP_COMMA
1460 }
1461
1462 /**
1463  * i915_driver_load - setup chip and create an initial config
1464  * @dev: DRM device
1465  * @flags: startup flags
1466  *
1467  * The driver load routine has to do several things:
1468  *   - drive output discovery via intel_modeset_init()
1469  *   - initialize the memory manager
1470  *   - allocate initial config memory
1471  *   - setup the DRM framebuffer with the allocated memory
1472  */
1473 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1474 {
1475         struct drm_i915_private *dev_priv;
1476         struct intel_device_info *info;
1477         int ret = 0, mmio_bar, mmio_size;
1478         uint32_t aperture_size;
1479
1480         info = (struct intel_device_info *) flags;
1481
1482         /* Refuse to load on gen6+ without kms enabled. */
1483         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1484                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1485                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1486                 return -ENODEV;
1487         }
1488
1489         /* UMS needs agp support. */
1490         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1491                 return -EINVAL;
1492
1493         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1494         if (dev_priv == NULL)
1495                 return -ENOMEM;
1496
1497         dev->dev_private = (void *)dev_priv;
1498         dev_priv->dev = dev;
1499         dev_priv->info = info;
1500
1501         spin_lock_init(&dev_priv->irq_lock);
1502         spin_lock_init(&dev_priv->gpu_error.lock);
1503         spin_lock_init(&dev_priv->backlight_lock);
1504         spin_lock_init(&dev_priv->uncore.lock);
1505         spin_lock_init(&dev_priv->mm.object_stat_lock);
1506         mutex_init(&dev_priv->dpio_lock);
1507         mutex_init(&dev_priv->modeset_restore_lock);
1508
1509         intel_pm_setup(dev);
1510
1511         intel_display_crc_init(dev);
1512
1513         i915_dump_device_info(dev_priv);
1514
1515         /* Not all pre-production machines fall into this category, only the
1516          * very first ones. Almost everything should work, except for maybe
1517          * suspend/resume. And we don't implement workarounds that affect only
1518          * pre-production machines. */
1519         if (IS_HSW_EARLY_SDV(dev))
1520                 DRM_INFO("This is an early pre-production Haswell machine. "
1521                          "It may not be fully functional.\n");
1522
1523         if (i915_get_bridge_dev(dev)) {
1524                 ret = -EIO;
1525                 goto free_priv;
1526         }
1527
1528         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1529         /* Before gen4, the registers and the GTT are behind different BARs.
1530          * However, from gen4 onwards, the registers and the GTT are shared
1531          * in the same BAR, so we want to restrict this ioremap from
1532          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1533          * the register BAR remains the same size for all the earlier
1534          * generations up to Ironlake.
1535          */
1536         if (info->gen < 5)
1537                 mmio_size = 512*1024;
1538         else
1539                 mmio_size = 2*1024*1024;
1540
1541         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1542         if (!dev_priv->regs) {
1543                 DRM_ERROR("failed to map registers\n");
1544                 ret = -EIO;
1545                 goto put_bridge;
1546         }
1547
1548         intel_uncore_early_sanitize(dev);
1549
1550         /* This must be called before any calls to HAS_PCH_* */
1551         intel_detect_pch(dev);
1552
1553         intel_uncore_init(dev);
1554
1555         ret = i915_gem_gtt_init(dev);
1556         if (ret)
1557                 goto out_regs;
1558
1559         if (drm_core_check_feature(dev, DRIVER_MODESET))
1560                 i915_kick_out_firmware_fb(dev_priv);
1561
1562         pci_set_master(dev->pdev);
1563
1564         /* overlay on gen2 is broken and can't address above 1G */
1565         if (IS_GEN2(dev))
1566                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1567
1568         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1569          * using 32bit addressing, overwriting memory if HWS is located
1570          * above 4GB.
1571          *
1572          * The documentation also mentions an issue with undefined
1573          * behaviour if any general state is accessed within a page above 4GB,
1574          * which also needs to be handled carefully.
1575          */
1576         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1577                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1578
1579         aperture_size = dev_priv->gtt.mappable_end;
1580
1581         dev_priv->gtt.mappable =
1582                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1583                                      aperture_size);
1584         if (dev_priv->gtt.mappable == NULL) {
1585                 ret = -EIO;
1586                 goto out_gtt;
1587         }
1588
1589         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1590                                               aperture_size);
1591
1592         /* The i915 workqueue is primarily used for batched retirement of
1593          * requests (and thus managing bo) once the task has been completed
1594          * by the GPU. i915_gem_retire_requests() is called directly when we
1595          * need high-priority retirement, such as waiting for an explicit
1596          * bo.
1597          *
1598          * It is also used for periodic low-priority events, such as
1599          * idle-timers and recording error state.
1600          *
1601          * All tasks on the workqueue are expected to acquire the dev mutex
1602          * so there is no point in running more than one instance of the
1603          * workqueue at any time.  Use an ordered one.
1604          */
1605         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1606         if (dev_priv->wq == NULL) {
1607                 DRM_ERROR("Failed to create our workqueue.\n");
1608                 ret = -ENOMEM;
1609                 goto out_mtrrfree;
1610         }
1611
1612         intel_irq_init(dev);
1613         intel_uncore_sanitize(dev);
1614
1615         /* Try to make sure MCHBAR is enabled before poking at it */
1616         intel_setup_mchbar(dev);
1617         intel_setup_gmbus(dev);
1618         intel_opregion_setup(dev);
1619
1620         intel_setup_bios(dev);
1621
1622         i915_gem_load(dev);
1623
1624         /* On the 945G/GM, the chipset reports the MSI capability on the
1625          * integrated graphics even though the support isn't actually there
1626          * according to the published specs.  It doesn't appear to function
1627          * correctly in testing on 945G.
1628          * This may be a side effect of MSI having been made available for PEG
1629          * and the registers being closely associated.
1630          *
1631          * According to chipset errata, on the 965GM, MSI interrupts may
1632          * be lost or delayed, but we use them anyways to avoid
1633          * stuck interrupts on some machines.
1634          */
1635         if (!IS_I945G(dev) && !IS_I945GM(dev))
1636                 pci_enable_msi(dev->pdev);
1637
1638         dev_priv->num_plane = 1;
1639         if (IS_VALLEYVIEW(dev))
1640                 dev_priv->num_plane = 2;
1641
1642         if (INTEL_INFO(dev)->num_pipes) {
1643                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1644                 if (ret)
1645                         goto out_gem_unload;
1646         }
1647
1648         intel_power_domains_init(dev);
1649
1650         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1651                 ret = i915_load_modeset_init(dev);
1652                 if (ret < 0) {
1653                         DRM_ERROR("failed to init modeset\n");
1654                         goto out_power_well;
1655                 }
1656         } else {
1657                 /* Start out suspended in ums mode. */
1658                 dev_priv->ums.mm_suspended = 1;
1659         }
1660
1661         i915_setup_sysfs(dev);
1662
1663         if (INTEL_INFO(dev)->num_pipes) {
1664                 /* Must be done after probing outputs */
1665                 intel_opregion_init(dev);
1666                 acpi_video_register();
1667         }
1668
1669         if (IS_GEN5(dev))
1670                 intel_gpu_ips_init(dev_priv);
1671
1672         intel_init_runtime_pm(dev_priv);
1673
1674         return 0;
1675
1676 out_power_well:
1677         intel_power_domains_remove(dev);
1678         drm_vblank_cleanup(dev);
1679 out_gem_unload:
1680         if (dev_priv->mm.inactive_shrinker.scan_objects)
1681                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1682
1683         if (dev->pdev->msi_enabled)
1684                 pci_disable_msi(dev->pdev);
1685
1686         intel_teardown_gmbus(dev);
1687         intel_teardown_mchbar(dev);
1688         destroy_workqueue(dev_priv->wq);
1689 out_mtrrfree:
1690         arch_phys_wc_del(dev_priv->gtt.mtrr);
1691         io_mapping_free(dev_priv->gtt.mappable);
1692 out_gtt:
1693         list_del(&dev_priv->gtt.base.global_link);
1694         drm_mm_takedown(&dev_priv->gtt.base.mm);
1695         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1696 out_regs:
1697         intel_uncore_fini(dev);
1698         pci_iounmap(dev->pdev, dev_priv->regs);
1699 put_bridge:
1700         pci_dev_put(dev_priv->bridge_dev);
1701 free_priv:
1702         if (dev_priv->slab)
1703                 kmem_cache_destroy(dev_priv->slab);
1704         kfree(dev_priv);
1705         return ret;
1706 }
1707
1708 int i915_driver_unload(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         int ret;
1712
1713         ret = i915_gem_suspend(dev);
1714         if (ret) {
1715                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1716                 return ret;
1717         }
1718
1719         intel_fini_runtime_pm(dev_priv);
1720
1721         intel_gpu_ips_teardown();
1722
1723         /* The i915.ko module is still not prepared to be loaded when
1724          * the power well is not enabled, so just enable it in case
1725          * we're going to unload/reload. */
1726         intel_display_set_init_power(dev, true);
1727         intel_power_domains_remove(dev);
1728
1729         i915_teardown_sysfs(dev);
1730
1731         if (dev_priv->mm.inactive_shrinker.scan_objects)
1732                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1733
1734         io_mapping_free(dev_priv->gtt.mappable);
1735         arch_phys_wc_del(dev_priv->gtt.mtrr);
1736
1737         acpi_video_unregister();
1738
1739         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1740                 intel_fbdev_fini(dev);
1741                 intel_modeset_cleanup(dev);
1742                 cancel_work_sync(&dev_priv->console_resume_work);
1743
1744                 /*
1745                  * free the memory space allocated for the child device
1746                  * config parsed from VBT
1747                  */
1748                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1749                         kfree(dev_priv->vbt.child_dev);
1750                         dev_priv->vbt.child_dev = NULL;
1751                         dev_priv->vbt.child_dev_num = 0;
1752                 }
1753
1754                 vga_switcheroo_unregister_client(dev->pdev);
1755                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1756         }
1757
1758         /* Free error state after interrupts are fully disabled. */
1759         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1760         cancel_work_sync(&dev_priv->gpu_error.work);
1761         i915_destroy_error_state(dev);
1762
1763         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
1764
1765         if (dev->pdev->msi_enabled)
1766                 pci_disable_msi(dev->pdev);
1767
1768         intel_opregion_fini(dev);
1769
1770         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1771                 /* Flush any outstanding unpin_work. */
1772                 flush_workqueue(dev_priv->wq);
1773
1774                 mutex_lock(&dev->struct_mutex);
1775                 i915_gem_free_all_phys_object(dev);
1776                 i915_gem_cleanup_ringbuffer(dev);
1777                 i915_gem_context_fini(dev);
1778                 mutex_unlock(&dev->struct_mutex);
1779                 i915_gem_cleanup_aliasing_ppgtt(dev);
1780                 i915_gem_cleanup_stolen(dev);
1781
1782                 if (!I915_NEED_GFX_HWS(dev))
1783                         i915_free_hws(dev);
1784         }
1785
1786         list_del(&dev_priv->gtt.base.global_link);
1787         WARN_ON(!list_empty(&dev_priv->vm_list));
1788
1789         drm_vblank_cleanup(dev);
1790
1791         intel_teardown_gmbus(dev);
1792         intel_teardown_mchbar(dev);
1793
1794         destroy_workqueue(dev_priv->wq);
1795         pm_qos_remove_request(&dev_priv->pm_qos);
1796
1797         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1798
1799         intel_uncore_fini(dev);
1800         if (dev_priv->regs != NULL)
1801                 pci_iounmap(dev->pdev, dev_priv->regs);
1802
1803         if (dev_priv->slab)
1804                 kmem_cache_destroy(dev_priv->slab);
1805
1806         pci_dev_put(dev_priv->bridge_dev);
1807         kfree(dev->dev_private);
1808
1809         return 0;
1810 }
1811
1812 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1813 {
1814         int ret;
1815
1816         ret = i915_gem_open(dev, file);
1817         if (ret)
1818                 return ret;
1819
1820         return 0;
1821 }
1822
1823 /**
1824  * i915_driver_lastclose - clean up after all DRM clients have exited
1825  * @dev: DRM device
1826  *
1827  * Take care of cleaning up after all DRM clients have exited.  In the
1828  * mode setting case, we want to restore the kernel's initial mode (just
1829  * in case the last client left us in a bad state).
1830  *
1831  * Additionally, in the non-mode setting case, we'll tear down the GTT
1832  * and DMA structures, since the kernel won't be using them, and clea
1833  * up any GEM state.
1834  */
1835 void i915_driver_lastclose(struct drm_device * dev)
1836 {
1837         drm_i915_private_t *dev_priv = dev->dev_private;
1838
1839         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1840          * goes right around and calls lastclose. Check for this and don't clean
1841          * up anything. */
1842         if (!dev_priv)
1843                 return;
1844
1845         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1846                 intel_fbdev_restore_mode(dev);
1847                 vga_switcheroo_process_delayed_switch();
1848                 return;
1849         }
1850
1851         i915_gem_lastclose(dev);
1852
1853         i915_dma_cleanup(dev);
1854 }
1855
1856 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1857 {
1858         mutex_lock(&dev->struct_mutex);
1859         i915_gem_context_close(dev, file_priv);
1860         i915_gem_release(dev, file_priv);
1861         mutex_unlock(&dev->struct_mutex);
1862 }
1863
1864 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1865 {
1866         struct drm_i915_file_private *file_priv = file->driver_priv;
1867
1868         kfree(file_priv);
1869 }
1870
1871 const struct drm_ioctl_desc i915_ioctls[] = {
1872         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1873         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1874         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1875         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1876         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1877         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1878         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1879         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1880         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1881         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1882         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1883         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1884         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1885         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1886         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1887         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1888         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1889         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1890         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1891         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1892         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1893         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1894         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1895         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1896         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1897         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1898         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1899         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1900         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1901         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1902         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1903         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1904         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1905         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1906         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1907         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1908         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1909         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1910         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1911         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1912         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1913         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1914         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1915         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1916         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1917         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1918         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1919         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1920         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1921 };
1922
1923 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1924
1925 /*
1926  * This is really ugly: Because old userspace abused the linux agp interface to
1927  * manage the gtt, we need to claim that all intel devices are agp.  For
1928  * otherwise the drm core refuses to initialize the agp support code.
1929  */
1930 int i915_driver_device_is_agp(struct drm_device * dev)
1931 {
1932         return 1;
1933 }