drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 121                 if (i915_is_ggtt(vma->vm) &&
 122                     drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *ring;
 134         struct i915_vma *vma;
 135         int pin_count = 0;
 136         int i;
 137
 138         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 139                    &obj->base,
 140                    obj->active ? "*" : " ",
 141                    get_pin_flag(obj),
 142                    get_tiling_flag(obj),
 143                    get_global_flag(obj),
 144                    obj->base.size / 1024,
 145                    obj->base.read_domains,
 146                    obj->base.write_domain);
 147         for_each_ring(ring, dev_priv, i)
 148                 seq_printf(m, "%x ",
 149                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 150         seq_printf(m, "] %x %x%s%s%s",
 151                    i915_gem_request_get_seqno(obj->last_write_req),
 152                    i915_gem_request_get_seqno(obj->last_fenced_req),
 153                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 154                    obj->dirty ? " dirty" : "",
 155                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 156         if (obj->base.name)
 157                 seq_printf(m, " (name: %d)", obj->base.name);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (vma->pin_count > 0)
 160                         pin_count++;
 161         }
 162         seq_printf(m, " (pinned x %d)", pin_count);
 163         if (obj->pin_display)
 164                 seq_printf(m, " (display)");
 165         if (obj->fence_reg != I915_FENCE_REG_NONE)
 166                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 167         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_is_ggtt(vma->vm))
 172                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 173                 else
 174                         seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_ring(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         struct i915_address_space *vm = &dev_priv->gtt.base;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &vm->active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &vm->inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, mm_list) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         if (a->stolen->start < b->stolen->start)
 257                 return -1;
 258         if (a->stolen->start > b->stolen->start)
 259                 return 1;
 260         return 0;
 261 }
 262
 263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 264 {
 265         struct drm_info_node *node = m->private;
 266         struct drm_device *dev = node->minor->dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct drm_i915_gem_object *obj;
 269         u64 total_obj_size, total_gtt_size;
 270         LIST_HEAD(stolen);
 271         int count, ret;
 272
 273         ret = mutex_lock_interruptible(&dev->struct_mutex);
 274         if (ret)
 275                 return ret;
 276
 277         total_obj_size = total_gtt_size = count = 0;
 278         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 279                 if (obj->stolen == NULL)
 280                         continue;
 281
 282                 list_add(&obj->obj_exec_link, &stolen);
 283
 284                 total_obj_size += obj->base.size;
 285                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 286                 count++;
 287         }
 288         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 289                 if (obj->stolen == NULL)
 290                         continue;
 291
 292                 list_add(&obj->obj_exec_link, &stolen);
 293
 294                 total_obj_size += obj->base.size;
 295                 count++;
 296         }
 297         list_sort(NULL, &stolen, obj_rank_by_stolen);
 298         seq_puts(m, "Stolen:\n");
 299         while (!list_empty(&stolen)) {
 300                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 301                 seq_puts(m, "   ");
 302                 describe_obj(m, obj);
 303                 seq_putc(m, '\n');
 304                 list_del_init(&obj->obj_exec_link);
 305         }
 306         mutex_unlock(&dev->struct_mutex);
 307
 308         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 309                    count, total_obj_size, total_gtt_size);
 310         return 0;
 311 }
 312
 313 #define count_objects(list, member) do { \
 314         list_for_each_entry(obj, list, member) { \
 315                 size += i915_gem_obj_total_ggtt_size(obj); \
 316                 ++count; \
 317                 if (obj->map_and_fenceable) { \
 318                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 319                         ++mappable_count; \
 320                 } \
 321         } \
 322 } while (0)
 323
 324 struct file_stats {
 325         struct drm_i915_file_private *file_priv;
 326         unsigned long count;
 327         u64 total, unbound;
 328         u64 global, shared;
 329         u64 active, inactive;
 330 };
 331
 332 static int per_file_stats(int id, void *ptr, void *data)
 333 {
 334         struct drm_i915_gem_object *obj = ptr;
 335         struct file_stats *stats = data;
 336         struct i915_vma *vma;
 337
 338         stats->count++;
 339         stats->total += obj->base.size;
 340
 341         if (obj->base.name || obj->base.dma_buf)
 342                 stats->shared += obj->base.size;
 343
 344         if (USES_FULL_PPGTT(obj->base.dev)) {
 345                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 346                         struct i915_hw_ppgtt *ppgtt;
 347
 348                         if (!drm_mm_node_allocated(&vma->node))
 349                                 continue;
 350
 351                         if (i915_is_ggtt(vma->vm)) {
 352                                 stats->global += obj->base.size;
 353                                 continue;
 354                         }
 355
 356                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 357                         if (ppgtt->file_priv != stats->file_priv)
 358                                 continue;
 359
 360                         if (obj->active) /* XXX per-vma statistic */
 361                                 stats->active += obj->base.size;
 362                         else
 363                                 stats->inactive += obj->base.size;
 364
 365                         return 0;
 366                 }
 367         } else {
 368                 if (i915_gem_obj_ggtt_bound(obj)) {
 369                         stats->global += obj->base.size;
 370                         if (obj->active)
 371                                 stats->active += obj->base.size;
 372                         else
 373                                 stats->inactive += obj->base.size;
 374                         return 0;
 375                 }
 376         }
 377
 378         if (!list_empty(&obj->global_list))
 379                 stats->unbound += obj->base.size;
 380
 381         return 0;
 382 }
 383
 384 #define print_file_stats(m, name, stats) do { \
 385         if (stats.count) \
 386                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 387                            name, \
 388                            stats.count, \
 389                            stats.total, \
 390                            stats.active, \
 391                            stats.inactive, \
 392                            stats.global, \
 393                            stats.shared, \
 394                            stats.unbound); \
 395 } while (0)
 396
 397 static void print_batch_pool_stats(struct seq_file *m,
 398                                    struct drm_i915_private *dev_priv)
 399 {
 400         struct drm_i915_gem_object *obj;
 401         struct file_stats stats;
 402         struct intel_engine_cs *ring;
 403         int i, j;
 404
 405         memset(&stats, 0, sizeof(stats));
 406
 407         for_each_ring(ring, dev_priv, i) {
 408                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 409                         list_for_each_entry(obj,
 410                                             &ring->batch_pool.cache_list[j],
 411                                             batch_pool_link)
 412                                 per_file_stats(0, obj, &stats);
 413                 }
 414         }
 415
 416         print_file_stats(m, "[k]batch pool", stats);
 417 }
 418
 419 #define count_vmas(list, member) do { \
 420         list_for_each_entry(vma, list, member) { \
 421                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 422                 ++count; \
 423                 if (vma->obj->map_and_fenceable) { \
 424                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 425                         ++mappable_count; \
 426                 } \
 427         } \
 428 } while (0)
 429
 430 static int i915_gem_object_info(struct seq_file *m, void* data)
 431 {
 432         struct drm_info_node *node = m->private;
 433         struct drm_device *dev = node->minor->dev;
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         u32 count, mappable_count, purgeable_count;
 436         u64 size, mappable_size, purgeable_size;
 437         struct drm_i915_gem_object *obj;
 438         struct i915_address_space *vm = &dev_priv->gtt.base;
 439         struct drm_file *file;
 440         struct i915_vma *vma;
 441         int ret;
 442
 443         ret = mutex_lock_interruptible(&dev->struct_mutex);
 444         if (ret)
 445                 return ret;
 446
 447         seq_printf(m, "%u objects, %zu bytes\n",
 448                    dev_priv->mm.object_count,
 449                    dev_priv->mm.object_memory);
 450
 451         size = count = mappable_size = mappable_count = 0;
 452         count_objects(&dev_priv->mm.bound_list, global_list);
 453         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 454                    count, mappable_count, size, mappable_size);
 455
 456         size = count = mappable_size = mappable_count = 0;
 457         count_vmas(&vm->active_list, mm_list);
 458         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 459                    count, mappable_count, size, mappable_size);
 460
 461         size = count = mappable_size = mappable_count = 0;
 462         count_vmas(&vm->inactive_list, mm_list);
 463         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 464                    count, mappable_count, size, mappable_size);
 465
 466         size = count = purgeable_size = purgeable_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 468                 size += obj->base.size, ++count;
 469                 if (obj->madv == I915_MADV_DONTNEED)
 470                         purgeable_size += obj->base.size, ++purgeable_count;
 471         }
 472         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 473
 474         size = count = mappable_size = mappable_count = 0;
 475         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 476                 if (obj->fault_mappable) {
 477                         size += i915_gem_obj_ggtt_size(obj);
 478                         ++count;
 479                 }
 480                 if (obj->pin_display) {
 481                         mappable_size += i915_gem_obj_ggtt_size(obj);
 482                         ++mappable_count;
 483                 }
 484                 if (obj->madv == I915_MADV_DONTNEED) {
 485                         purgeable_size += obj->base.size;
 486                         ++purgeable_count;
 487                 }
 488         }
 489         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 490                    purgeable_count, purgeable_size);
 491         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 492                    mappable_count, mappable_size);
 493         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 494                    count, size);
 495
 496         seq_printf(m, "%llu [%llu] gtt total\n",
 497                    dev_priv->gtt.base.total,
 498                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 499
 500         seq_putc(m, '\n');
 501         print_batch_pool_stats(m, dev_priv);
 502         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 503                 struct file_stats stats;
 504                 struct task_struct *task;
 505
 506                 memset(&stats, 0, sizeof(stats));
 507                 stats.file_priv = file->driver_priv;
 508                 spin_lock(&file->table_lock);
 509                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 510                 spin_unlock(&file->table_lock);
 511                 /*
 512                  * Although we have a valid reference on file->pid, that does
 513                  * not guarantee that the task_struct who called get_pid() is
 514                  * still alive (e.g. get_pid(current) => fork() => exit()).
 515                  * Therefore, we need to protect this ->comm access using RCU.
 516                  */
 517                 rcu_read_lock();
 518                 task = pid_task(file->pid, PIDTYPE_PID);
 519                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 520                 rcu_read_unlock();
 521         }
 522
 523         mutex_unlock(&dev->struct_mutex);
 524
 525         return 0;
 526 }
 527
 528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 529 {
 530         struct drm_info_node *node = m->private;
 531         struct drm_device *dev = node->minor->dev;
 532         uintptr_t list = (uintptr_t) node->info_ent->data;
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534         struct drm_i915_gem_object *obj;
 535         u64 total_obj_size, total_gtt_size;
 536         int count, ret;
 537
 538         ret = mutex_lock_interruptible(&dev->struct_mutex);
 539         if (ret)
 540                 return ret;
 541
 542         total_obj_size = total_gtt_size = count = 0;
 543         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 544                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 545                         continue;
 546
 547                 seq_puts(m, "   ");
 548                 describe_obj(m, obj);
 549                 seq_putc(m, '\n');
 550                 total_obj_size += obj->base.size;
 551                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 552                 count++;
 553         }
 554
 555         mutex_unlock(&dev->struct_mutex);
 556
 557         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 558                    count, total_obj_size, total_gtt_size);
 559
 560         return 0;
 561 }
 562
 563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 564 {
 565         struct drm_info_node *node = m->private;
 566         struct drm_device *dev = node->minor->dev;
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct intel_crtc *crtc;
 569         int ret;
 570
 571         ret = mutex_lock_interruptible(&dev->struct_mutex);
 572         if (ret)
 573                 return ret;
 574
 575         for_each_intel_crtc(dev, crtc) {
 576                 const char pipe = pipe_name(crtc->pipe);
 577                 const char plane = plane_name(crtc->plane);
 578                 struct intel_unpin_work *work;
 579
 580                 spin_lock_irq(&dev->event_lock);
 581                 work = crtc->unpin_work;
 582                 if (work == NULL) {
 583                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 584                                    pipe, plane);
 585                 } else {
 586                         u32 addr;
 587
 588                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 589                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 590                                            pipe, plane);
 591                         } else {
 592                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 593                                            pipe, plane);
 594                         }
 595                         if (work->flip_queued_req) {
 596                                 struct intel_engine_cs *ring =
 597                                         i915_gem_request_get_ring(work->flip_queued_req);
 598
 599                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 600                                            ring->name,
 601                                            i915_gem_request_get_seqno(work->flip_queued_req),
 602                                            dev_priv->next_seqno,
 603                                            ring->get_seqno(ring, true),
 604                                            i915_gem_request_completed(work->flip_queued_req, true));
 605                         } else
 606                                 seq_printf(m, "Flip not associated with any ring\n");
 607                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 608                                    work->flip_queued_vblank,
 609                                    work->flip_ready_vblank,
 610                                    drm_crtc_vblank_count(&crtc->base));
 611                         if (work->enable_stall_check)
 612                                 seq_puts(m, "Stall check enabled, ");
 613                         else
 614                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 615                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 616
 617                         if (INTEL_INFO(dev)->gen >= 4)
 618                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 619                         else
 620                                 addr = I915_READ(DSPADDR(crtc->plane));
 621                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 622
 623                         if (work->pending_flip_obj) {
 624                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 625                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 626                         }
 627                 }
 628                 spin_unlock_irq(&dev->event_lock);
 629         }
 630
 631         mutex_unlock(&dev->struct_mutex);
 632
 633         return 0;
 634 }
 635
 636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 637 {
 638         struct drm_info_node *node = m->private;
 639         struct drm_device *dev = node->minor->dev;
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641         struct drm_i915_gem_object *obj;
 642         struct intel_engine_cs *ring;
 643         int total = 0;
 644         int ret, i, j;
 645
 646         ret = mutex_lock_interruptible(&dev->struct_mutex);
 647         if (ret)
 648                 return ret;
 649
 650         for_each_ring(ring, dev_priv, i) {
 651                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 652                         int count;
 653
 654                         count = 0;
 655                         list_for_each_entry(obj,
 656                                             &ring->batch_pool.cache_list[j],
 657                                             batch_pool_link)
 658                                 count++;
 659                         seq_printf(m, "%s cache[%d]: %d objects\n",
 660                                    ring->name, j, count);
 661
 662                         list_for_each_entry(obj,
 663                                             &ring->batch_pool.cache_list[j],
 664                                             batch_pool_link) {
 665                                 seq_puts(m, "   ");
 666                                 describe_obj(m, obj);
 667                                 seq_putc(m, '\n');
 668                         }
 669
 670                         total += count;
 671                 }
 672         }
 673
 674         seq_printf(m, "total: %d\n", total);
 675
 676         mutex_unlock(&dev->struct_mutex);
 677
 678         return 0;
 679 }
 680
 681 static int i915_gem_request_info(struct seq_file *m, void *data)
 682 {
 683         struct drm_info_node *node = m->private;
 684         struct drm_device *dev = node->minor->dev;
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct intel_engine_cs *ring;
 687         struct drm_i915_gem_request *req;
 688         int ret, any, i;
 689
 690         ret = mutex_lock_interruptible(&dev->struct_mutex);
 691         if (ret)
 692                 return ret;
 693
 694         any = 0;
 695         for_each_ring(ring, dev_priv, i) {
 696                 int count;
 697
 698                 count = 0;
 699                 list_for_each_entry(req, &ring->request_list, list)
 700                         count++;
 701                 if (count == 0)
 702                         continue;
 703
 704                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 705                 list_for_each_entry(req, &ring->request_list, list) {
 706                         struct task_struct *task;
 707
 708                         rcu_read_lock();
 709                         task = NULL;
 710                         if (req->pid)
 711                                 task = pid_task(req->pid, PIDTYPE_PID);
 712                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 713                                    req->seqno,
 714                                    (int) (jiffies - req->emitted_jiffies),
 715                                    task ? task->comm : "<unknown>",
 716                                    task ? task->pid : -1);
 717                         rcu_read_unlock();
 718                 }
 719
 720                 any++;
 721         }
 722         mutex_unlock(&dev->struct_mutex);
 723
 724         if (any == 0)
 725                 seq_puts(m, "No requests\n");
 726
 727         return 0;
 728 }
 729
 730 static void i915_ring_seqno_info(struct seq_file *m,
 731                                  struct intel_engine_cs *ring)
 732 {
 733         if (ring->get_seqno) {
 734                 seq_printf(m, "Current sequence (%s): %x\n",
 735                            ring->name, ring->get_seqno(ring, false));
 736         }
 737 }
 738
 739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 740 {
 741         struct drm_info_node *node = m->private;
 742         struct drm_device *dev = node->minor->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct intel_engine_cs *ring;
 745         int ret, i;
 746
 747         ret = mutex_lock_interruptible(&dev->struct_mutex);
 748         if (ret)
 749                 return ret;
 750         intel_runtime_pm_get(dev_priv);
 751
 752         for_each_ring(ring, dev_priv, i)
 753                 i915_ring_seqno_info(m, ring);
 754
 755         intel_runtime_pm_put(dev_priv);
 756         mutex_unlock(&dev->struct_mutex);
 757
 758         return 0;
 759 }
 760
 761
 762 static int i915_interrupt_info(struct seq_file *m, void *data)
 763 {
 764         struct drm_info_node *node = m->private;
 765         struct drm_device *dev = node->minor->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         struct intel_engine_cs *ring;
 768         int ret, i, pipe;
 769
 770         ret = mutex_lock_interruptible(&dev->struct_mutex);
 771         if (ret)
 772                 return ret;
 773         intel_runtime_pm_get(dev_priv);
 774
 775         if (IS_CHERRYVIEW(dev)) {
 776                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 777                            I915_READ(GEN8_MASTER_IRQ));
 778
 779                 seq_printf(m, "Display IER:\t%08x\n",
 780                            I915_READ(VLV_IER));
 781                 seq_printf(m, "Display IIR:\t%08x\n",
 782                            I915_READ(VLV_IIR));
 783                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 784                            I915_READ(VLV_IIR_RW));
 785                 seq_printf(m, "Display IMR:\t%08x\n",
 786                            I915_READ(VLV_IMR));
 787                 for_each_pipe(dev_priv, pipe)
 788                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 789                                    pipe_name(pipe),
 790                                    I915_READ(PIPESTAT(pipe)));
 791
 792                 seq_printf(m, "Port hotplug:\t%08x\n",
 793                            I915_READ(PORT_HOTPLUG_EN));
 794                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 795                            I915_READ(VLV_DPFLIPSTAT));
 796                 seq_printf(m, "DPINVGTT:\t%08x\n",
 797                            I915_READ(DPINVGTT));
 798
 799                 for (i = 0; i < 4; i++) {
 800                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IMR(i)));
 802                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 803                                    i, I915_READ(GEN8_GT_IIR(i)));
 804                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 805                                    i, I915_READ(GEN8_GT_IER(i)));
 806                 }
 807
 808                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IMR));
 810                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 811                            I915_READ(GEN8_PCU_IIR));
 812                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 813                            I915_READ(GEN8_PCU_IER));
 814         } else if (INTEL_INFO(dev)->gen >= 8) {
 815                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 816                            I915_READ(GEN8_MASTER_IRQ));
 817
 818                 for (i = 0; i < 4; i++) {
 819                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IMR(i)));
 821                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 822                                    i, I915_READ(GEN8_GT_IIR(i)));
 823                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 824                                    i, I915_READ(GEN8_GT_IER(i)));
 825                 }
 826
 827                 for_each_pipe(dev_priv, pipe) {
 828                         if (!intel_display_power_is_enabled(dev_priv,
 829                                                 POWER_DOMAIN_PIPE(pipe))) {
 830                                 seq_printf(m, "Pipe %c power disabled\n",
 831                                            pipe_name(pipe));
 832                                 continue;
 833                         }
 834                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 835                                    pipe_name(pipe),
 836                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 837                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 838                                    pipe_name(pipe),
 839                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 840                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 841                                    pipe_name(pipe),
 842                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 843                 }
 844
 845                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 846                            I915_READ(GEN8_DE_PORT_IMR));
 847                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 848                            I915_READ(GEN8_DE_PORT_IIR));
 849                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 850                            I915_READ(GEN8_DE_PORT_IER));
 851
 852                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 853                            I915_READ(GEN8_DE_MISC_IMR));
 854                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 855                            I915_READ(GEN8_DE_MISC_IIR));
 856                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 857                            I915_READ(GEN8_DE_MISC_IER));
 858
 859                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 860                            I915_READ(GEN8_PCU_IMR));
 861                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 862                            I915_READ(GEN8_PCU_IIR));
 863                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 864                            I915_READ(GEN8_PCU_IER));
 865         } else if (IS_VALLEYVIEW(dev)) {
 866                 seq_printf(m, "Display IER:\t%08x\n",
 867                            I915_READ(VLV_IER));
 868                 seq_printf(m, "Display IIR:\t%08x\n",
 869                            I915_READ(VLV_IIR));
 870                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 871                            I915_READ(VLV_IIR_RW));
 872                 seq_printf(m, "Display IMR:\t%08x\n",
 873                            I915_READ(VLV_IMR));
 874                 for_each_pipe(dev_priv, pipe)
 875                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 876                                    pipe_name(pipe),
 877                                    I915_READ(PIPESTAT(pipe)));
 878
 879                 seq_printf(m, "Master IER:\t%08x\n",
 880                            I915_READ(VLV_MASTER_IER));
 881
 882                 seq_printf(m, "Render IER:\t%08x\n",
 883                            I915_READ(GTIER));
 884                 seq_printf(m, "Render IIR:\t%08x\n",
 885                            I915_READ(GTIIR));
 886                 seq_printf(m, "Render IMR:\t%08x\n",
 887                            I915_READ(GTIMR));
 888
 889                 seq_printf(m, "PM IER:\t\t%08x\n",
 890                            I915_READ(GEN6_PMIER));
 891                 seq_printf(m, "PM IIR:\t\t%08x\n",
 892                            I915_READ(GEN6_PMIIR));
 893                 seq_printf(m, "PM IMR:\t\t%08x\n",
 894                            I915_READ(GEN6_PMIMR));
 895
 896                 seq_printf(m, "Port hotplug:\t%08x\n",
 897                            I915_READ(PORT_HOTPLUG_EN));
 898                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 899                            I915_READ(VLV_DPFLIPSTAT));
 900                 seq_printf(m, "DPINVGTT:\t%08x\n",
 901                            I915_READ(DPINVGTT));
 902
 903         } else if (!HAS_PCH_SPLIT(dev)) {
 904                 seq_printf(m, "Interrupt enable:    %08x\n",
 905                            I915_READ(IER));
 906                 seq_printf(m, "Interrupt identity:  %08x\n",
 907                            I915_READ(IIR));
 908                 seq_printf(m, "Interrupt mask:      %08x\n",
 909                            I915_READ(IMR));
 910                 for_each_pipe(dev_priv, pipe)
 911                         seq_printf(m, "Pipe %c stat:         %08x\n",
 912                                    pipe_name(pipe),
 913                                    I915_READ(PIPESTAT(pipe)));
 914         } else {
 915                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 916                            I915_READ(DEIER));
 917                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 918                            I915_READ(DEIIR));
 919                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 920                            I915_READ(DEIMR));
 921                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 922                            I915_READ(SDEIER));
 923                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 924                            I915_READ(SDEIIR));
 925                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 926                            I915_READ(SDEIMR));
 927                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 928                            I915_READ(GTIER));
 929                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 930                            I915_READ(GTIIR));
 931                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 932                            I915_READ(GTIMR));
 933         }
 934         for_each_ring(ring, dev_priv, i) {
 935                 if (INTEL_INFO(dev)->gen >= 6) {
 936                         seq_printf(m,
 937                                    "Graphics Interrupt mask (%s):       %08x\n",
 938                                    ring->name, I915_READ_IMR(ring));
 939                 }
 940                 i915_ring_seqno_info(m, ring);
 941         }
 942         intel_runtime_pm_put(dev_priv);
 943         mutex_unlock(&dev->struct_mutex);
 944
 945         return 0;
 946 }
 947
 948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 949 {
 950         struct drm_info_node *node = m->private;
 951         struct drm_device *dev = node->minor->dev;
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         int i, ret;
 954
 955         ret = mutex_lock_interruptible(&dev->struct_mutex);
 956         if (ret)
 957                 return ret;
 958
 959         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 960         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 961         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 962                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 963
 964                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 965                            i, dev_priv->fence_regs[i].pin_count);
 966                 if (obj == NULL)
 967                         seq_puts(m, "unused");
 968                 else
 969                         describe_obj(m, obj);
 970                 seq_putc(m, '\n');
 971         }
 972
 973         mutex_unlock(&dev->struct_mutex);
 974         return 0;
 975 }
 976
 977 static int i915_hws_info(struct seq_file *m, void *data)
 978 {
 979         struct drm_info_node *node = m->private;
 980         struct drm_device *dev = node->minor->dev;
 981         struct drm_i915_private *dev_priv = dev->dev_private;
 982         struct intel_engine_cs *ring;
 983         const u32 *hws;
 984         int i;
 985
 986         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 987         hws = ring->status_page.page_addr;
 988         if (hws == NULL)
 989                 return 0;
 990
 991         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 992                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 993                            i * 4,
 994                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 995         }
 996         return 0;
 997 }
 998
 999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001                        const char __user *ubuf,
1002                        size_t cnt,
1003                        loff_t *ppos)
1004 {
1005         struct i915_error_state_file_priv *error_priv = filp->private_data;
1006         struct drm_device *dev = error_priv->dev;
1007         int ret;
1008
1009         DRM_DEBUG_DRIVER("Resetting error state\n");
1010
1011         ret = mutex_lock_interruptible(&dev->struct_mutex);
1012         if (ret)
1013                 return ret;
1014
1015         i915_destroy_error_state(dev);
1016         mutex_unlock(&dev->struct_mutex);
1017
1018         return cnt;
1019 }
1020
1021 static int i915_error_state_open(struct inode *inode, struct file *file)
1022 {
1023         struct drm_device *dev = inode->i_private;
1024         struct i915_error_state_file_priv *error_priv;
1025
1026         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1027         if (!error_priv)
1028                 return -ENOMEM;
1029
1030         error_priv->dev = dev;
1031
1032         i915_error_state_get(dev, error_priv);
1033
1034         file->private_data = error_priv;
1035
1036         return 0;
1037 }
1038
1039 static int i915_error_state_release(struct inode *inode, struct file *file)
1040 {
1041         struct i915_error_state_file_priv *error_priv = file->private_data;
1042
1043         i915_error_state_put(error_priv);
1044         kfree(error_priv);
1045
1046         return 0;
1047 }
1048
1049 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1050                                      size_t count, loff_t *pos)
1051 {
1052         struct i915_error_state_file_priv *error_priv = file->private_data;
1053         struct drm_i915_error_state_buf error_str;
1054         loff_t tmp_pos = 0;
1055         ssize_t ret_count = 0;
1056         int ret;
1057
1058         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1059         if (ret)
1060                 return ret;
1061
1062         ret = i915_error_state_to_str(&error_str, error_priv);
1063         if (ret)
1064                 goto out;
1065
1066         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1067                                             error_str.buf,
1068                                             error_str.bytes);
1069
1070         if (ret_count < 0)
1071                 ret = ret_count;
1072         else
1073                 *pos = error_str.start + ret_count;
1074 out:
1075         i915_error_state_buf_release(&error_str);
1076         return ret ?: ret_count;
1077 }
1078
1079 static const struct file_operations i915_error_state_fops = {
1080         .owner = THIS_MODULE,
1081         .open = i915_error_state_open,
1082         .read = i915_error_state_read,
1083         .write = i915_error_state_write,
1084         .llseek = default_llseek,
1085         .release = i915_error_state_release,
1086 };
1087
1088 static int
1089 i915_next_seqno_get(void *data, u64 *val)
1090 {
1091         struct drm_device *dev = data;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         int ret;
1094
1095         ret = mutex_lock_interruptible(&dev->struct_mutex);
1096         if (ret)
1097                 return ret;
1098
1099         *val = dev_priv->next_seqno;
1100         mutex_unlock(&dev->struct_mutex);
1101
1102         return 0;
1103 }
1104
1105 static int
1106 i915_next_seqno_set(void *data, u64 val)
1107 {
1108         struct drm_device *dev = data;
1109         int ret;
1110
1111         ret = mutex_lock_interruptible(&dev->struct_mutex);
1112         if (ret)
1113                 return ret;
1114
1115         ret = i915_gem_set_seqno(dev, val);
1116         mutex_unlock(&dev->struct_mutex);
1117
1118         return ret;
1119 }
1120
1121 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1122                         i915_next_seqno_get, i915_next_seqno_set,
1123                         "0x%llx\n");
1124
1125 static int i915_frequency_info(struct seq_file *m, void *unused)
1126 {
1127         struct drm_info_node *node = m->private;
1128         struct drm_device *dev = node->minor->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         int ret = 0;
1131
1132         intel_runtime_pm_get(dev_priv);
1133
1134         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1135
1136         if (IS_GEN5(dev)) {
1137                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1138                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139
1140                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1141                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1142                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143                            MEMSTAT_VID_SHIFT);
1144                 seq_printf(m, "Current P-state: %d\n",
1145                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1146         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1147                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1148                 u32 rp_state_limits;
1149                 u32 gt_perf_status;
1150                 u32 rp_state_cap;
1151                 u32 rpmodectl, rpinclimit, rpdeclimit;
1152                 u32 rpstat, cagf, reqf;
1153                 u32 rpupei, rpcurup, rpprevup;
1154                 u32 rpdownei, rpcurdown, rpprevdown;
1155                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1156                 int max_freq;
1157
1158                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1159                 if (IS_BROXTON(dev)) {
1160                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1161                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162                 } else {
1163                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1164                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1165                 }
1166
1167                 /* RPSTAT1 is in the GT power well */
1168                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1169                 if (ret)
1170                         goto out;
1171
1172                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1173
1174                 reqf = I915_READ(GEN6_RPNSWREQ);
1175                 if (IS_GEN9(dev))
1176                         reqf >>= 23;
1177                 else {
1178                         reqf &= ~GEN6_TURBO_DISABLE;
1179                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1180                                 reqf >>= 24;
1181                         else
1182                                 reqf >>= 25;
1183                 }
1184                 reqf = intel_gpu_freq(dev_priv, reqf);
1185
1186                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1187                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1188                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189
1190                 rpstat = I915_READ(GEN6_RPSTAT1);
1191                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1192                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1193                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1194                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1195                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1196                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1197                 if (IS_GEN9(dev))
1198                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1199                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1200                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201                 else
1202                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1203                 cagf = intel_gpu_freq(dev_priv, cagf);
1204
1205                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1206                 mutex_unlock(&dev->struct_mutex);
1207
1208                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1209                         pm_ier = I915_READ(GEN6_PMIER);
1210                         pm_imr = I915_READ(GEN6_PMIMR);
1211                         pm_isr = I915_READ(GEN6_PMISR);
1212                         pm_iir = I915_READ(GEN6_PMIIR);
1213                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1214                 } else {
1215                         pm_ier = I915_READ(GEN8_GT_IER(2));
1216                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1217                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1218                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1219                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1220                 }
1221                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1222                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1223                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1224                 seq_printf(m, "Render p-state ratio: %d\n",
1225                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1226                 seq_printf(m, "Render p-state VID: %d\n",
1227                            gt_perf_status & 0xff);
1228                 seq_printf(m, "Render p-state limit: %d\n",
1229                            rp_state_limits & 0xff);
1230                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1234                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1235                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1236                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1237                            GEN6_CURICONT_MASK);
1238                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1239                            GEN6_CURBSYTAVG_MASK);
1240                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1241                            GEN6_CURBSYTAVG_MASK);
1242                 seq_printf(m, "Up threshold: %d%%\n",
1243                            dev_priv->rps.up_threshold);
1244
1245                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246                            GEN6_CURIAVG_MASK);
1247                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1248                            GEN6_CURBSYTAVG_MASK);
1249                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1250                            GEN6_CURBSYTAVG_MASK);
1251                 seq_printf(m, "Down threshold: %d%%\n",
1252                            dev_priv->rps.down_threshold);
1253
1254                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1255                             rp_state_cap >> 16) & 0xff;
1256                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1257                              GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (rp_state_cap & 0xff00) >> 8;
1262                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1263                              GEN9_FREQ_SCALER : 1);
1264                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1265                            intel_gpu_freq(dev_priv, max_freq));
1266
1267                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1268                             rp_state_cap >> 0) & 0xff;
1269                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1270                              GEN9_FREQ_SCALER : 1);
1271                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1272                            intel_gpu_freq(dev_priv, max_freq));
1273                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1275
1276                 seq_printf(m, "Current freq: %d MHz\n",
1277                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1278                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1279                 seq_printf(m, "Idle freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1281                 seq_printf(m, "Min freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1283                 seq_printf(m, "Max freq: %d MHz\n",
1284                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1285                 seq_printf(m,
1286                            "efficient (RPe) frequency: %d MHz\n",
1287                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1288         } else if (IS_VALLEYVIEW(dev)) {
1289                 u32 freq_sts;
1290
1291                 mutex_lock(&dev_priv->rps.hw_lock);
1292                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1293                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1294                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1295
1296                 seq_printf(m, "actual GPU freq: %d MHz\n",
1297                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1298
1299                 seq_printf(m, "current GPU freq: %d MHz\n",
1300                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1301
1302                 seq_printf(m, "max GPU freq: %d MHz\n",
1303                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1304
1305                 seq_printf(m, "min GPU freq: %d MHz\n",
1306                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1307
1308                 seq_printf(m, "idle GPU freq: %d MHz\n",
1309                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1310
1311                 seq_printf(m,
1312                            "efficient (RPe) frequency: %d MHz\n",
1313                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1314                 mutex_unlock(&dev_priv->rps.hw_lock);
1315         } else {
1316                 seq_puts(m, "no P-state info available\n");
1317         }
1318
1319         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
1323 out:
1324         intel_runtime_pm_put(dev_priv);
1325         return ret;
1326 }
1327
1328 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329 {
1330         struct drm_info_node *node = m->private;
1331         struct drm_device *dev = node->minor->dev;
1332         struct drm_i915_private *dev_priv = dev->dev_private;
1333         struct intel_engine_cs *ring;
1334         u64 acthd[I915_NUM_RINGS];
1335         u32 seqno[I915_NUM_RINGS];
1336         int i;
1337
1338         if (!i915.enable_hangcheck) {
1339                 seq_printf(m, "Hangcheck disabled\n");
1340                 return 0;
1341         }
1342
1343         intel_runtime_pm_get(dev_priv);
1344
1345         for_each_ring(ring, dev_priv, i) {
1346                 seqno[i] = ring->get_seqno(ring, false);
1347                 acthd[i] = intel_ring_get_active_head(ring);
1348         }
1349
1350         intel_runtime_pm_put(dev_priv);
1351
1352         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1353                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1354                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1355                                             jiffies));
1356         } else
1357                 seq_printf(m, "Hangcheck inactive\n");
1358
1359         for_each_ring(ring, dev_priv, i) {
1360                 seq_printf(m, "%s:\n", ring->name);
1361                 seq_printf(m, "\tseqno = %x [current %x]\n",
1362                            ring->hangcheck.seqno, seqno[i]);
1363                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1364                            (long long)ring->hangcheck.acthd,
1365                            (long long)acthd[i]);
1366                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1367                            (long long)ring->hangcheck.max_acthd);
1368                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1369                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1370         }
1371
1372         return 0;
1373 }
1374
1375 static int ironlake_drpc_info(struct seq_file *m)
1376 {
1377         struct drm_info_node *node = m->private;
1378         struct drm_device *dev = node->minor->dev;
1379         struct drm_i915_private *dev_priv = dev->dev_private;
1380         u32 rgvmodectl, rstdbyctl;
1381         u16 crstandvid;
1382         int ret;
1383
1384         ret = mutex_lock_interruptible(&dev->struct_mutex);
1385         if (ret)
1386                 return ret;
1387         intel_runtime_pm_get(dev_priv);
1388
1389         rgvmodectl = I915_READ(MEMMODECTL);
1390         rstdbyctl = I915_READ(RSTDBYCTL);
1391         crstandvid = I915_READ16(CRSTANDVID);
1392
1393         intel_runtime_pm_put(dev_priv);
1394         mutex_unlock(&dev->struct_mutex);
1395
1396         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1397         seq_printf(m, "Boost freq: %d\n",
1398                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1399                    MEMMODE_BOOST_FREQ_SHIFT);
1400         seq_printf(m, "HW control enabled: %s\n",
1401                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1402         seq_printf(m, "SW control enabled: %s\n",
1403                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1404         seq_printf(m, "Gated voltage change: %s\n",
1405                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1406         seq_printf(m, "Starting frequency: P%d\n",
1407                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1408         seq_printf(m, "Max P-state: P%d\n",
1409                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1410         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1411         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1412         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1413         seq_printf(m, "Render standby enabled: %s\n",
1414                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1415         seq_puts(m, "Current RS state: ");
1416         switch (rstdbyctl & RSX_STATUS_MASK) {
1417         case RSX_STATUS_ON:
1418                 seq_puts(m, "on\n");
1419                 break;
1420         case RSX_STATUS_RC1:
1421                 seq_puts(m, "RC1\n");
1422                 break;
1423         case RSX_STATUS_RC1E:
1424                 seq_puts(m, "RC1E\n");
1425                 break;
1426         case RSX_STATUS_RS1:
1427                 seq_puts(m, "RS1\n");
1428                 break;
1429         case RSX_STATUS_RS2:
1430                 seq_puts(m, "RS2 (RC6)\n");
1431                 break;
1432         case RSX_STATUS_RS3:
1433                 seq_puts(m, "RC3 (RC6+)\n");
1434                 break;
1435         default:
1436                 seq_puts(m, "unknown\n");
1437                 break;
1438         }
1439
1440         return 0;
1441 }
1442
1443 static int i915_forcewake_domains(struct seq_file *m, void *data)
1444 {
1445         struct drm_info_node *node = m->private;
1446         struct drm_device *dev = node->minor->dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         struct intel_uncore_forcewake_domain *fw_domain;
1449         int i;
1450
1451         spin_lock_irq(&dev_priv->uncore.lock);
1452         for_each_fw_domain(fw_domain, dev_priv, i) {
1453                 seq_printf(m, "%s.wake_count = %u\n",
1454                            intel_uncore_forcewake_domain_to_str(i),
1455                            fw_domain->wake_count);
1456         }
1457         spin_unlock_irq(&dev_priv->uncore.lock);
1458
1459         return 0;
1460 }
1461
1462 static int vlv_drpc_info(struct seq_file *m)
1463 {
1464         struct drm_info_node *node = m->private;
1465         struct drm_device *dev = node->minor->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         u32 rpmodectl1, rcctl1, pw_status;
1468
1469         intel_runtime_pm_get(dev_priv);
1470
1471         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1472         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1473         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1474
1475         intel_runtime_pm_put(dev_priv);
1476
1477         seq_printf(m, "Video Turbo Mode: %s\n",
1478                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1479         seq_printf(m, "Turbo enabled: %s\n",
1480                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1481         seq_printf(m, "HW control enabled: %s\n",
1482                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1483         seq_printf(m, "SW control enabled: %s\n",
1484                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1485                           GEN6_RP_MEDIA_SW_MODE));
1486         seq_printf(m, "RC6 Enabled: %s\n",
1487                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1488                                         GEN6_RC_CTL_EI_MODE(1))));
1489         seq_printf(m, "Render Power Well: %s\n",
1490                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1491         seq_printf(m, "Media Power Well: %s\n",
1492                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1493
1494         seq_printf(m, "Render RC6 residency since boot: %u\n",
1495                    I915_READ(VLV_GT_RENDER_RC6));
1496         seq_printf(m, "Media RC6 residency since boot: %u\n",
1497                    I915_READ(VLV_GT_MEDIA_RC6));
1498
1499         return i915_forcewake_domains(m, NULL);
1500 }
1501
1502 static int gen6_drpc_info(struct seq_file *m)
1503 {
1504         struct drm_info_node *node = m->private;
1505         struct drm_device *dev = node->minor->dev;
1506         struct drm_i915_private *dev_priv = dev->dev_private;
1507         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1508         unsigned forcewake_count;
1509         int count = 0, ret;
1510
1511         ret = mutex_lock_interruptible(&dev->struct_mutex);
1512         if (ret)
1513                 return ret;
1514         intel_runtime_pm_get(dev_priv);
1515
1516         spin_lock_irq(&dev_priv->uncore.lock);
1517         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1518         spin_unlock_irq(&dev_priv->uncore.lock);
1519
1520         if (forcewake_count) {
1521                 seq_puts(m, "RC information inaccurate because somebody "
1522                             "holds a forcewake reference \n");
1523         } else {
1524                 /* NB: we cannot use forcewake, else we read the wrong values */
1525                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1526                         udelay(10);
1527                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1528         }
1529
1530         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1531         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1532
1533         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1534         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535         mutex_unlock(&dev->struct_mutex);
1536         mutex_lock(&dev_priv->rps.hw_lock);
1537         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1538         mutex_unlock(&dev_priv->rps.hw_lock);
1539
1540         intel_runtime_pm_put(dev_priv);
1541
1542         seq_printf(m, "Video Turbo Mode: %s\n",
1543                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1544         seq_printf(m, "HW control enabled: %s\n",
1545                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1546         seq_printf(m, "SW control enabled: %s\n",
1547                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1548                           GEN6_RP_MEDIA_SW_MODE));
1549         seq_printf(m, "RC1e Enabled: %s\n",
1550                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1551         seq_printf(m, "RC6 Enabled: %s\n",
1552                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1553         seq_printf(m, "Deep RC6 Enabled: %s\n",
1554                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1555         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1556                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1557         seq_puts(m, "Current RC state: ");
1558         switch (gt_core_status & GEN6_RCn_MASK) {
1559         case GEN6_RC0:
1560                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1561                         seq_puts(m, "Core Power Down\n");
1562                 else
1563                         seq_puts(m, "on\n");
1564                 break;
1565         case GEN6_RC3:
1566                 seq_puts(m, "RC3\n");
1567                 break;
1568         case GEN6_RC6:
1569                 seq_puts(m, "RC6\n");
1570                 break;
1571         case GEN6_RC7:
1572                 seq_puts(m, "RC7\n");
1573                 break;
1574         default:
1575                 seq_puts(m, "Unknown\n");
1576                 break;
1577         }
1578
1579         seq_printf(m, "Core Power Down: %s\n",
1580                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1581
1582         /* Not exactly sure what this is */
1583         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1584                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1585         seq_printf(m, "RC6 residency since boot: %u\n",
1586                    I915_READ(GEN6_GT_GFX_RC6));
1587         seq_printf(m, "RC6+ residency since boot: %u\n",
1588                    I915_READ(GEN6_GT_GFX_RC6p));
1589         seq_printf(m, "RC6++ residency since boot: %u\n",
1590                    I915_READ(GEN6_GT_GFX_RC6pp));
1591
1592         seq_printf(m, "RC6   voltage: %dmV\n",
1593                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1594         seq_printf(m, "RC6+  voltage: %dmV\n",
1595                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1596         seq_printf(m, "RC6++ voltage: %dmV\n",
1597                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1598         return 0;
1599 }
1600
1601 static int i915_drpc_info(struct seq_file *m, void *unused)
1602 {
1603         struct drm_info_node *node = m->private;
1604         struct drm_device *dev = node->minor->dev;
1605
1606         if (IS_VALLEYVIEW(dev))
1607                 return vlv_drpc_info(m);
1608         else if (INTEL_INFO(dev)->gen >= 6)
1609                 return gen6_drpc_info(m);
1610         else
1611                 return ironlake_drpc_info(m);
1612 }
1613
1614 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1615 {
1616         struct drm_info_node *node = m->private;
1617         struct drm_device *dev = node->minor->dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1621                    dev_priv->fb_tracking.busy_bits);
1622
1623         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1624                    dev_priv->fb_tracking.flip_bits);
1625
1626         return 0;
1627 }
1628
1629 static int i915_fbc_status(struct seq_file *m, void *unused)
1630 {
1631         struct drm_info_node *node = m->private;
1632         struct drm_device *dev = node->minor->dev;
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634
1635         if (!HAS_FBC(dev)) {
1636                 seq_puts(m, "FBC unsupported on this chipset\n");
1637                 return 0;
1638         }
1639
1640         intel_runtime_pm_get(dev_priv);
1641         mutex_lock(&dev_priv->fbc.lock);
1642
1643         if (intel_fbc_enabled(dev_priv))
1644                 seq_puts(m, "FBC enabled\n");
1645         else
1646                 seq_printf(m, "FBC disabled: %s\n",
1647                            dev_priv->fbc.no_fbc_reason);
1648
1649         if (INTEL_INFO(dev_priv)->gen >= 7)
1650                 seq_printf(m, "Compressing: %s\n",
1651                            yesno(I915_READ(FBC_STATUS2) &
1652                                  FBC_COMPRESSION_MASK));
1653
1654         mutex_unlock(&dev_priv->fbc.lock);
1655         intel_runtime_pm_put(dev_priv);
1656
1657         return 0;
1658 }
1659
1660 static int i915_fbc_fc_get(void *data, u64 *val)
1661 {
1662         struct drm_device *dev = data;
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1666                 return -ENODEV;
1667
1668         *val = dev_priv->fbc.false_color;
1669
1670         return 0;
1671 }
1672
1673 static int i915_fbc_fc_set(void *data, u64 val)
1674 {
1675         struct drm_device *dev = data;
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677         u32 reg;
1678
1679         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1680                 return -ENODEV;
1681
1682         mutex_lock(&dev_priv->fbc.lock);
1683
1684         reg = I915_READ(ILK_DPFC_CONTROL);
1685         dev_priv->fbc.false_color = val;
1686
1687         I915_WRITE(ILK_DPFC_CONTROL, val ?
1688                    (reg | FBC_CTL_FALSE_COLOR) :
1689                    (reg & ~FBC_CTL_FALSE_COLOR));
1690
1691         mutex_unlock(&dev_priv->fbc.lock);
1692         return 0;
1693 }
1694
1695 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1696                         i915_fbc_fc_get, i915_fbc_fc_set,
1697                         "%llu\n");
1698
1699 static int i915_ips_status(struct seq_file *m, void *unused)
1700 {
1701         struct drm_info_node *node = m->private;
1702         struct drm_device *dev = node->minor->dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704
1705         if (!HAS_IPS(dev)) {
1706                 seq_puts(m, "not supported\n");
1707                 return 0;
1708         }
1709
1710         intel_runtime_pm_get(dev_priv);
1711
1712         seq_printf(m, "Enabled by kernel parameter: %s\n",
1713                    yesno(i915.enable_ips));
1714
1715         if (INTEL_INFO(dev)->gen >= 8) {
1716                 seq_puts(m, "Currently: unknown\n");
1717         } else {
1718                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1719                         seq_puts(m, "Currently: enabled\n");
1720                 else
1721                         seq_puts(m, "Currently: disabled\n");
1722         }
1723
1724         intel_runtime_pm_put(dev_priv);
1725
1726         return 0;
1727 }
1728
1729 static int i915_sr_status(struct seq_file *m, void *unused)
1730 {
1731         struct drm_info_node *node = m->private;
1732         struct drm_device *dev = node->minor->dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         bool sr_enabled = false;
1735
1736         intel_runtime_pm_get(dev_priv);
1737
1738         if (HAS_PCH_SPLIT(dev))
1739                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1740         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1741                  IS_I945G(dev) || IS_I945GM(dev))
1742                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1743         else if (IS_I915GM(dev))
1744                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1745         else if (IS_PINEVIEW(dev))
1746                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1747         else if (IS_VALLEYVIEW(dev))
1748                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1749
1750         intel_runtime_pm_put(dev_priv);
1751
1752         seq_printf(m, "self-refresh: %s\n",
1753                    sr_enabled ? "enabled" : "disabled");
1754
1755         return 0;
1756 }
1757
1758 static int i915_emon_status(struct seq_file *m, void *unused)
1759 {
1760         struct drm_info_node *node = m->private;
1761         struct drm_device *dev = node->minor->dev;
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         unsigned long temp, chipset, gfx;
1764         int ret;
1765
1766         if (!IS_GEN5(dev))
1767                 return -ENODEV;
1768
1769         ret = mutex_lock_interruptible(&dev->struct_mutex);
1770         if (ret)
1771                 return ret;
1772
1773         temp = i915_mch_val(dev_priv);
1774         chipset = i915_chipset_val(dev_priv);
1775         gfx = i915_gfx_val(dev_priv);
1776         mutex_unlock(&dev->struct_mutex);
1777
1778         seq_printf(m, "GMCH temp: %ld\n", temp);
1779         seq_printf(m, "Chipset power: %ld\n", chipset);
1780         seq_printf(m, "GFX power: %ld\n", gfx);
1781         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1782
1783         return 0;
1784 }
1785
1786 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1787 {
1788         struct drm_info_node *node = m->private;
1789         struct drm_device *dev = node->minor->dev;
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791         int ret = 0;
1792         int gpu_freq, ia_freq;
1793         unsigned int max_gpu_freq, min_gpu_freq;
1794
1795         if (!HAS_CORE_RING_FREQ(dev)) {
1796                 seq_puts(m, "unsupported on this chipset\n");
1797                 return 0;
1798         }
1799
1800         intel_runtime_pm_get(dev_priv);
1801
1802         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1803
1804         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1805         if (ret)
1806                 goto out;
1807
1808         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1809                 /* Convert GT frequency to 50 HZ units */
1810                 min_gpu_freq =
1811                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1812                 max_gpu_freq =
1813                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1814         } else {
1815                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1816                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1817         }
1818
1819         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1820
1821         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1822                 ia_freq = gpu_freq;
1823                 sandybridge_pcode_read(dev_priv,
1824                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1825                                        &ia_freq);
1826                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1827                            intel_gpu_freq(dev_priv, (gpu_freq *
1828                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1829                                  GEN9_FREQ_SCALER : 1))),
1830                            ((ia_freq >> 0) & 0xff) * 100,
1831                            ((ia_freq >> 8) & 0xff) * 100);
1832         }
1833
1834         mutex_unlock(&dev_priv->rps.hw_lock);
1835
1836 out:
1837         intel_runtime_pm_put(dev_priv);
1838         return ret;
1839 }
1840
1841 static int i915_opregion(struct seq_file *m, void *unused)
1842 {
1843         struct drm_info_node *node = m->private;
1844         struct drm_device *dev = node->minor->dev;
1845         struct drm_i915_private *dev_priv = dev->dev_private;
1846         struct intel_opregion *opregion = &dev_priv->opregion;
1847         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1848         int ret;
1849
1850         if (data == NULL)
1851                 return -ENOMEM;
1852
1853         ret = mutex_lock_interruptible(&dev->struct_mutex);
1854         if (ret)
1855                 goto out;
1856
1857         if (opregion->header) {
1858                 memcpy(data, opregion->header, OPREGION_SIZE);
1859                 seq_write(m, data, OPREGION_SIZE);
1860         }
1861
1862         mutex_unlock(&dev->struct_mutex);
1863
1864 out:
1865         kfree(data);
1866         return 0;
1867 }
1868
1869 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1870 {
1871         struct drm_info_node *node = m->private;
1872         struct drm_device *dev = node->minor->dev;
1873         struct intel_fbdev *ifbdev = NULL;
1874         struct intel_framebuffer *fb;
1875         struct drm_framebuffer *drm_fb;
1876
1877 #ifdef CONFIG_DRM_FBDEV_EMULATION
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879
1880         ifbdev = dev_priv->fbdev;
1881         fb = to_intel_framebuffer(ifbdev->helper.fb);
1882
1883         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1884                    fb->base.width,
1885                    fb->base.height,
1886                    fb->base.depth,
1887                    fb->base.bits_per_pixel,
1888                    fb->base.modifier[0],
1889                    atomic_read(&fb->base.refcount.refcount));
1890         describe_obj(m, fb->obj);
1891         seq_putc(m, '\n');
1892 #endif
1893
1894         mutex_lock(&dev->mode_config.fb_lock);
1895         drm_for_each_fb(drm_fb, dev) {
1896                 fb = to_intel_framebuffer(drm_fb);
1897                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1898                         continue;
1899
1900                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901                            fb->base.width,
1902                            fb->base.height,
1903                            fb->base.depth,
1904                            fb->base.bits_per_pixel,
1905                            fb->base.modifier[0],
1906                            atomic_read(&fb->base.refcount.refcount));
1907                 describe_obj(m, fb->obj);
1908                 seq_putc(m, '\n');
1909         }
1910         mutex_unlock(&dev->mode_config.fb_lock);
1911
1912         return 0;
1913 }
1914
1915 static void describe_ctx_ringbuf(struct seq_file *m,
1916                                  struct intel_ringbuffer *ringbuf)
1917 {
1918         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1919                    ringbuf->space, ringbuf->head, ringbuf->tail,
1920                    ringbuf->last_retired_head);
1921 }
1922
1923 static int i915_context_status(struct seq_file *m, void *unused)
1924 {
1925         struct drm_info_node *node = m->private;
1926         struct drm_device *dev = node->minor->dev;
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         struct intel_engine_cs *ring;
1929         struct intel_context *ctx;
1930         int ret, i;
1931
1932         ret = mutex_lock_interruptible(&dev->struct_mutex);
1933         if (ret)
1934                 return ret;
1935
1936         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1937                 if (!i915.enable_execlists &&
1938                     ctx->legacy_hw_ctx.rcs_state == NULL)
1939                         continue;
1940
1941                 seq_puts(m, "HW context ");
1942                 describe_ctx(m, ctx);
1943                 for_each_ring(ring, dev_priv, i) {
1944                         if (ring->default_context == ctx)
1945                                 seq_printf(m, "(default context %s) ",
1946                                            ring->name);
1947                 }
1948
1949                 if (i915.enable_execlists) {
1950                         seq_putc(m, '\n');
1951                         for_each_ring(ring, dev_priv, i) {
1952                                 struct drm_i915_gem_object *ctx_obj =
1953                                         ctx->engine[i].state;
1954                                 struct intel_ringbuffer *ringbuf =
1955                                         ctx->engine[i].ringbuf;
1956
1957                                 seq_printf(m, "%s: ", ring->name);
1958                                 if (ctx_obj)
1959                                         describe_obj(m, ctx_obj);
1960                                 if (ringbuf)
1961                                         describe_ctx_ringbuf(m, ringbuf);
1962                                 seq_putc(m, '\n');
1963                         }
1964                 } else {
1965                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1966                 }
1967
1968                 seq_putc(m, '\n');
1969         }
1970
1971         mutex_unlock(&dev->struct_mutex);
1972
1973         return 0;
1974 }
1975
1976 static void i915_dump_lrc_obj(struct seq_file *m,
1977                               struct intel_engine_cs *ring,
1978                               struct drm_i915_gem_object *ctx_obj)
1979 {
1980         struct page *page;
1981         uint32_t *reg_state;
1982         int j;
1983         unsigned long ggtt_offset = 0;
1984
1985         if (ctx_obj == NULL) {
1986                 seq_printf(m, "Context on %s with no gem object\n",
1987                            ring->name);
1988                 return;
1989         }
1990
1991         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1992                    intel_execlists_ctx_id(ctx_obj));
1993
1994         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1995                 seq_puts(m, "\tNot bound in GGTT\n");
1996         else
1997                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1998
1999         if (i915_gem_object_get_pages(ctx_obj)) {
2000                 seq_puts(m, "\tFailed to get pages for context object\n");
2001                 return;
2002         }
2003
2004         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2005         if (!WARN_ON(page == NULL)) {
2006                 reg_state = kmap_atomic(page);
2007
2008                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2009                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2010                                    ggtt_offset + 4096 + (j * 4),
2011                                    reg_state[j], reg_state[j + 1],
2012                                    reg_state[j + 2], reg_state[j + 3]);
2013                 }
2014                 kunmap_atomic(reg_state);
2015         }
2016
2017         seq_putc(m, '\n');
2018 }
2019
2020 static int i915_dump_lrc(struct seq_file *m, void *unused)
2021 {
2022         struct drm_info_node *node = (struct drm_info_node *) m->private;
2023         struct drm_device *dev = node->minor->dev;
2024         struct drm_i915_private *dev_priv = dev->dev_private;
2025         struct intel_engine_cs *ring;
2026         struct intel_context *ctx;
2027         int ret, i;
2028
2029         if (!i915.enable_execlists) {
2030                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2031                 return 0;
2032         }
2033
2034         ret = mutex_lock_interruptible(&dev->struct_mutex);
2035         if (ret)
2036                 return ret;
2037
2038         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2039                 for_each_ring(ring, dev_priv, i) {
2040                         if (ring->default_context != ctx)
2041                                 i915_dump_lrc_obj(m, ring,
2042                                                   ctx->engine[i].state);
2043                 }
2044         }
2045
2046         mutex_unlock(&dev->struct_mutex);
2047
2048         return 0;
2049 }
2050
2051 static int i915_execlists(struct seq_file *m, void *data)
2052 {
2053         struct drm_info_node *node = (struct drm_info_node *)m->private;
2054         struct drm_device *dev = node->minor->dev;
2055         struct drm_i915_private *dev_priv = dev->dev_private;
2056         struct intel_engine_cs *ring;
2057         u32 status_pointer;
2058         u8 read_pointer;
2059         u8 write_pointer;
2060         u32 status;
2061         u32 ctx_id;
2062         struct list_head *cursor;
2063         int ring_id, i;
2064         int ret;
2065
2066         if (!i915.enable_execlists) {
2067                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2068                 return 0;
2069         }
2070
2071         ret = mutex_lock_interruptible(&dev->struct_mutex);
2072         if (ret)
2073                 return ret;
2074
2075         intel_runtime_pm_get(dev_priv);
2076
2077         for_each_ring(ring, dev_priv, ring_id) {
2078                 struct drm_i915_gem_request *head_req = NULL;
2079                 int count = 0;
2080                 unsigned long flags;
2081
2082                 seq_printf(m, "%s\n", ring->name);
2083
2084                 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2085                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2086                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2087                            status, ctx_id);
2088
2089                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2090                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2091
2092                 read_pointer = ring->next_context_status_buffer;
2093                 write_pointer = status_pointer & 0x07;
2094                 if (read_pointer > write_pointer)
2095                         write_pointer += 6;
2096                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2097                            read_pointer, write_pointer);
2098
2099                 for (i = 0; i < 6; i++) {
2100                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2101                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2102
2103                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2104                                    i, status, ctx_id);
2105                 }
2106
2107                 spin_lock_irqsave(&ring->execlist_lock, flags);
2108                 list_for_each(cursor, &ring->execlist_queue)
2109                         count++;
2110                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2111                                 struct drm_i915_gem_request, execlist_link);
2112                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2113
2114                 seq_printf(m, "\t%d requests in queue\n", count);
2115                 if (head_req) {
2116                         struct drm_i915_gem_object *ctx_obj;
2117
2118                         ctx_obj = head_req->ctx->engine[ring_id].state;
2119                         seq_printf(m, "\tHead request id: %u\n",
2120                                    intel_execlists_ctx_id(ctx_obj));
2121                         seq_printf(m, "\tHead request tail: %u\n",
2122                                    head_req->tail);
2123                 }
2124
2125                 seq_putc(m, '\n');
2126         }
2127
2128         intel_runtime_pm_put(dev_priv);
2129         mutex_unlock(&dev->struct_mutex);
2130
2131         return 0;
2132 }
2133
2134 static const char *swizzle_string(unsigned swizzle)
2135 {
2136         switch (swizzle) {
2137         case I915_BIT_6_SWIZZLE_NONE:
2138                 return "none";
2139         case I915_BIT_6_SWIZZLE_9:
2140                 return "bit9";
2141         case I915_BIT_6_SWIZZLE_9_10:
2142                 return "bit9/bit10";
2143         case I915_BIT_6_SWIZZLE_9_11:
2144                 return "bit9/bit11";
2145         case I915_BIT_6_SWIZZLE_9_10_11:
2146                 return "bit9/bit10/bit11";
2147         case I915_BIT_6_SWIZZLE_9_17:
2148                 return "bit9/bit17";
2149         case I915_BIT_6_SWIZZLE_9_10_17:
2150                 return "bit9/bit10/bit17";
2151         case I915_BIT_6_SWIZZLE_UNKNOWN:
2152                 return "unknown";
2153         }
2154
2155         return "bug";
2156 }
2157
2158 static int i915_swizzle_info(struct seq_file *m, void *data)
2159 {
2160         struct drm_info_node *node = m->private;
2161         struct drm_device *dev = node->minor->dev;
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         int ret;
2164
2165         ret = mutex_lock_interruptible(&dev->struct_mutex);
2166         if (ret)
2167                 return ret;
2168         intel_runtime_pm_get(dev_priv);
2169
2170         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2171                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2172         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2173                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2174
2175         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2176                 seq_printf(m, "DDC = 0x%08x\n",
2177                            I915_READ(DCC));
2178                 seq_printf(m, "DDC2 = 0x%08x\n",
2179                            I915_READ(DCC2));
2180                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2181                            I915_READ16(C0DRB3));
2182                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2183                            I915_READ16(C1DRB3));
2184         } else if (INTEL_INFO(dev)->gen >= 6) {
2185                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2186                            I915_READ(MAD_DIMM_C0));
2187                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2188                            I915_READ(MAD_DIMM_C1));
2189                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2190                            I915_READ(MAD_DIMM_C2));
2191                 seq_printf(m, "TILECTL = 0x%08x\n",
2192                            I915_READ(TILECTL));
2193                 if (INTEL_INFO(dev)->gen >= 8)
2194                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2195                                    I915_READ(GAMTARBMODE));
2196                 else
2197                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2198                                    I915_READ(ARB_MODE));
2199                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2200                            I915_READ(DISP_ARB_CTL));
2201         }
2202
2203         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2204                 seq_puts(m, "L-shaped memory detected\n");
2205
2206         intel_runtime_pm_put(dev_priv);
2207         mutex_unlock(&dev->struct_mutex);
2208
2209         return 0;
2210 }
2211
2212 static int per_file_ctx(int id, void *ptr, void *data)
2213 {
2214         struct intel_context *ctx = ptr;
2215         struct seq_file *m = data;
2216         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2217
2218         if (!ppgtt) {
2219                 seq_printf(m, "  no ppgtt for context %d\n",
2220                            ctx->user_handle);
2221                 return 0;
2222         }
2223
2224         if (i915_gem_context_is_default(ctx))
2225                 seq_puts(m, "  default context:\n");
2226         else
2227                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2228         ppgtt->debug_dump(ppgtt, m);
2229
2230         return 0;
2231 }
2232
2233 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2234 {
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236         struct intel_engine_cs *ring;
2237         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2238         int unused, i;
2239
2240         if (!ppgtt)
2241                 return;
2242
2243         for_each_ring(ring, dev_priv, unused) {
2244                 seq_printf(m, "%s\n", ring->name);
2245                 for (i = 0; i < 4; i++) {
2246                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2247                         pdp <<= 32;
2248                         pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2249                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2250                 }
2251         }
2252 }
2253
2254 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2255 {
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         struct intel_engine_cs *ring;
2258         int i;
2259
2260         if (INTEL_INFO(dev)->gen == 6)
2261                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2262
2263         for_each_ring(ring, dev_priv, i) {
2264                 seq_printf(m, "%s\n", ring->name);
2265                 if (INTEL_INFO(dev)->gen == 7)
2266                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2267                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2268                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2269                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2270         }
2271         if (dev_priv->mm.aliasing_ppgtt) {
2272                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2273
2274                 seq_puts(m, "aliasing PPGTT:\n");
2275                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2276
2277                 ppgtt->debug_dump(ppgtt, m);
2278         }
2279
2280         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2281 }
2282
2283 static int i915_ppgtt_info(struct seq_file *m, void *data)
2284 {
2285         struct drm_info_node *node = m->private;
2286         struct drm_device *dev = node->minor->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct drm_file *file;
2289
2290         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2291         if (ret)
2292                 return ret;
2293         intel_runtime_pm_get(dev_priv);
2294
2295         if (INTEL_INFO(dev)->gen >= 8)
2296                 gen8_ppgtt_info(m, dev);
2297         else if (INTEL_INFO(dev)->gen >= 6)
2298                 gen6_ppgtt_info(m, dev);
2299
2300         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2301                 struct drm_i915_file_private *file_priv = file->driver_priv;
2302                 struct task_struct *task;
2303
2304                 task = get_pid_task(file->pid, PIDTYPE_PID);
2305                 if (!task) {
2306                         ret = -ESRCH;
2307                         goto out_put;
2308                 }
2309                 seq_printf(m, "\nproc: %s\n", task->comm);
2310                 put_task_struct(task);
2311                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2312                              (void *)(unsigned long)m);
2313         }
2314
2315 out_put:
2316         intel_runtime_pm_put(dev_priv);
2317         mutex_unlock(&dev->struct_mutex);
2318
2319         return ret;
2320 }
2321
2322 static int count_irq_waiters(struct drm_i915_private *i915)
2323 {
2324         struct intel_engine_cs *ring;
2325         int count = 0;
2326         int i;
2327
2328         for_each_ring(ring, i915, i)
2329                 count += ring->irq_refcount;
2330
2331         return count;
2332 }
2333
2334 static int i915_rps_boost_info(struct seq_file *m, void *data)
2335 {
2336         struct drm_info_node *node = m->private;
2337         struct drm_device *dev = node->minor->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct drm_file *file;
2340
2341         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2342         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2343         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2344         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2345                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2346                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2347                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2348                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2349                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2350         spin_lock(&dev_priv->rps.client_lock);
2351         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2352                 struct drm_i915_file_private *file_priv = file->driver_priv;
2353                 struct task_struct *task;
2354
2355                 rcu_read_lock();
2356                 task = pid_task(file->pid, PIDTYPE_PID);
2357                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2358                            task ? task->comm : "<unknown>",
2359                            task ? task->pid : -1,
2360                            file_priv->rps.boosts,
2361                            list_empty(&file_priv->rps.link) ? "" : ", active");
2362                 rcu_read_unlock();
2363         }
2364         seq_printf(m, "Semaphore boosts: %d%s\n",
2365                    dev_priv->rps.semaphores.boosts,
2366                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2367         seq_printf(m, "MMIO flip boosts: %d%s\n",
2368                    dev_priv->rps.mmioflips.boosts,
2369                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2370         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2371         spin_unlock(&dev_priv->rps.client_lock);
2372
2373         return 0;
2374 }
2375
2376 static int i915_llc(struct seq_file *m, void *data)
2377 {
2378         struct drm_info_node *node = m->private;
2379         struct drm_device *dev = node->minor->dev;
2380         struct drm_i915_private *dev_priv = dev->dev_private;
2381
2382         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2383         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2384         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2385
2386         return 0;
2387 }
2388
2389 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2390 {
2391         struct drm_info_node *node = m->private;
2392         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2393         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2394         u32 tmp, i;
2395
2396         if (!HAS_GUC_UCODE(dev_priv->dev))
2397                 return 0;
2398
2399         seq_printf(m, "GuC firmware status:\n");
2400         seq_printf(m, "\tpath: %s\n",
2401                 guc_fw->guc_fw_path);
2402         seq_printf(m, "\tfetch: %s\n",
2403                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2404         seq_printf(m, "\tload: %s\n",
2405                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2406         seq_printf(m, "\tversion wanted: %d.%d\n",
2407                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2408         seq_printf(m, "\tversion found: %d.%d\n",
2409                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2410         seq_printf(m, "\theader: offset is %d; size = %d\n",
2411                 guc_fw->header_offset, guc_fw->header_size);
2412         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2413                 guc_fw->ucode_offset, guc_fw->ucode_size);
2414         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2415                 guc_fw->rsa_offset, guc_fw->rsa_size);
2416
2417         tmp = I915_READ(GUC_STATUS);
2418
2419         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2420         seq_printf(m, "\tBootrom status = 0x%x\n",
2421                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2422         seq_printf(m, "\tuKernel status = 0x%x\n",
2423                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2424         seq_printf(m, "\tMIA Core status = 0x%x\n",
2425                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2426         seq_puts(m, "\nScratch registers:\n");
2427         for (i = 0; i < 16; i++)
2428                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2429
2430         return 0;
2431 }
2432
2433 static void i915_guc_client_info(struct seq_file *m,
2434                                  struct drm_i915_private *dev_priv,
2435                                  struct i915_guc_client *client)
2436 {
2437         struct intel_engine_cs *ring;
2438         uint64_t tot = 0;
2439         uint32_t i;
2440
2441         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2442                 client->priority, client->ctx_index, client->proc_desc_offset);
2443         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2444                 client->doorbell_id, client->doorbell_offset, client->cookie);
2445         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2446                 client->wq_size, client->wq_offset, client->wq_tail);
2447
2448         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2449         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2450         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2451
2452         for_each_ring(ring, dev_priv, i) {
2453                 seq_printf(m, "\tSubmissions: %llu %s\n",
2454                                 client->submissions[i],
2455                                 ring->name);
2456                 tot += client->submissions[i];
2457         }
2458         seq_printf(m, "\tTotal: %llu\n", tot);
2459 }
2460
2461 static int i915_guc_info(struct seq_file *m, void *data)
2462 {
2463         struct drm_info_node *node = m->private;
2464         struct drm_device *dev = node->minor->dev;
2465         struct drm_i915_private *dev_priv = dev->dev_private;
2466         struct intel_guc guc;
2467         struct i915_guc_client client = {};
2468         struct intel_engine_cs *ring;
2469         enum intel_ring_id i;
2470         u64 total = 0;
2471
2472         if (!HAS_GUC_SCHED(dev_priv->dev))
2473                 return 0;
2474
2475         /* Take a local copy of the GuC data, so we can dump it at leisure */
2476         spin_lock(&dev_priv->guc.host2guc_lock);
2477         guc = dev_priv->guc;
2478         if (guc.execbuf_client) {
2479                 spin_lock(&guc.execbuf_client->wq_lock);
2480                 client = *guc.execbuf_client;
2481                 spin_unlock(&guc.execbuf_client->wq_lock);
2482         }
2483         spin_unlock(&dev_priv->guc.host2guc_lock);
2484
2485         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2486         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2487         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2488         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2489         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2490
2491         seq_printf(m, "\nGuC submissions:\n");
2492         for_each_ring(ring, dev_priv, i) {
2493                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2494                         ring->name, guc.submissions[i],
2495                         guc.last_seqno[i], guc.last_seqno[i]);
2496                 total += guc.submissions[i];
2497         }
2498         seq_printf(m, "\t%s: %llu\n", "Total", total);
2499
2500         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2501         i915_guc_client_info(m, dev_priv, &client);
2502
2503         /* Add more as required ... */
2504
2505         return 0;
2506 }
2507
2508 static int i915_guc_log_dump(struct seq_file *m, void *data)
2509 {
2510         struct drm_info_node *node = m->private;
2511         struct drm_device *dev = node->minor->dev;
2512         struct drm_i915_private *dev_priv = dev->dev_private;
2513         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2514         u32 *log;
2515         int i = 0, pg;
2516
2517         if (!log_obj)
2518                 return 0;
2519
2520         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2521                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2522
2523                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2524                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2525                                    *(log + i), *(log + i + 1),
2526                                    *(log + i + 2), *(log + i + 3));
2527
2528                 kunmap_atomic(log);
2529         }
2530
2531         seq_putc(m, '\n');
2532
2533         return 0;
2534 }
2535
2536 static int i915_edp_psr_status(struct seq_file *m, void *data)
2537 {
2538         struct drm_info_node *node = m->private;
2539         struct drm_device *dev = node->minor->dev;
2540         struct drm_i915_private *dev_priv = dev->dev_private;
2541         u32 psrperf = 0;
2542         u32 stat[3];
2543         enum pipe pipe;
2544         bool enabled = false;
2545
2546         if (!HAS_PSR(dev)) {
2547                 seq_puts(m, "PSR not supported\n");
2548                 return 0;
2549         }
2550
2551         intel_runtime_pm_get(dev_priv);
2552
2553         mutex_lock(&dev_priv->psr.lock);
2554         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2555         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2556         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2557         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2558         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2559                    dev_priv->psr.busy_frontbuffer_bits);
2560         seq_printf(m, "Re-enable work scheduled: %s\n",
2561                    yesno(work_busy(&dev_priv->psr.work.work)));
2562
2563         if (HAS_DDI(dev))
2564                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2565         else {
2566                 for_each_pipe(dev_priv, pipe) {
2567                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2568                                 VLV_EDP_PSR_CURR_STATE_MASK;
2569                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2570                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2571                                 enabled = true;
2572                 }
2573         }
2574         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2575
2576         if (!HAS_DDI(dev))
2577                 for_each_pipe(dev_priv, pipe) {
2578                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2579                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2580                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2581                 }
2582         seq_puts(m, "\n");
2583
2584         /* CHV PSR has no kind of performance counter */
2585         if (HAS_DDI(dev)) {
2586                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2587                         EDP_PSR_PERF_CNT_MASK;
2588
2589                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2590         }
2591         mutex_unlock(&dev_priv->psr.lock);
2592
2593         intel_runtime_pm_put(dev_priv);
2594         return 0;
2595 }
2596
2597 static int i915_sink_crc(struct seq_file *m, void *data)
2598 {
2599         struct drm_info_node *node = m->private;
2600         struct drm_device *dev = node->minor->dev;
2601         struct intel_encoder *encoder;
2602         struct intel_connector *connector;
2603         struct intel_dp *intel_dp = NULL;
2604         int ret;
2605         u8 crc[6];
2606
2607         drm_modeset_lock_all(dev);
2608         for_each_intel_connector(dev, connector) {
2609
2610                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2611                         continue;
2612
2613                 if (!connector->base.encoder)
2614                         continue;
2615
2616                 encoder = to_intel_encoder(connector->base.encoder);
2617                 if (encoder->type != INTEL_OUTPUT_EDP)
2618                         continue;
2619
2620                 intel_dp = enc_to_intel_dp(&encoder->base);
2621
2622                 ret = intel_dp_sink_crc(intel_dp, crc);
2623                 if (ret)
2624                         goto out;
2625
2626                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2627                            crc[0], crc[1], crc[2],
2628                            crc[3], crc[4], crc[5]);
2629                 goto out;
2630         }
2631         ret = -ENODEV;
2632 out:
2633         drm_modeset_unlock_all(dev);
2634         return ret;
2635 }
2636
2637 static int i915_energy_uJ(struct seq_file *m, void *data)
2638 {
2639         struct drm_info_node *node = m->private;
2640         struct drm_device *dev = node->minor->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         u64 power;
2643         u32 units;
2644
2645         if (INTEL_INFO(dev)->gen < 6)
2646                 return -ENODEV;
2647
2648         intel_runtime_pm_get(dev_priv);
2649
2650         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2651         power = (power & 0x1f00) >> 8;
2652         units = 1000000 / (1 << power); /* convert to uJ */
2653         power = I915_READ(MCH_SECP_NRG_STTS);
2654         power *= units;
2655
2656         intel_runtime_pm_put(dev_priv);
2657
2658         seq_printf(m, "%llu", (long long unsigned)power);
2659
2660         return 0;
2661 }
2662
2663 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2664 {
2665         struct drm_info_node *node = m->private;
2666         struct drm_device *dev = node->minor->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668
2669         if (!HAS_RUNTIME_PM(dev)) {
2670                 seq_puts(m, "not supported\n");
2671                 return 0;
2672         }
2673
2674         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2675         seq_printf(m, "IRQs disabled: %s\n",
2676                    yesno(!intel_irqs_enabled(dev_priv)));
2677 #ifdef CONFIG_PM
2678         seq_printf(m, "Usage count: %d\n",
2679                    atomic_read(&dev->dev->power.usage_count));
2680 #else
2681         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2682 #endif
2683
2684         return 0;
2685 }
2686
2687 static const char *power_domain_str(enum intel_display_power_domain domain)
2688 {
2689         switch (domain) {
2690         case POWER_DOMAIN_PIPE_A:
2691                 return "PIPE_A";
2692         case POWER_DOMAIN_PIPE_B:
2693                 return "PIPE_B";
2694         case POWER_DOMAIN_PIPE_C:
2695                 return "PIPE_C";
2696         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2697                 return "PIPE_A_PANEL_FITTER";
2698         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2699                 return "PIPE_B_PANEL_FITTER";
2700         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2701                 return "PIPE_C_PANEL_FITTER";
2702         case POWER_DOMAIN_TRANSCODER_A:
2703                 return "TRANSCODER_A";
2704         case POWER_DOMAIN_TRANSCODER_B:
2705                 return "TRANSCODER_B";
2706         case POWER_DOMAIN_TRANSCODER_C:
2707                 return "TRANSCODER_C";
2708         case POWER_DOMAIN_TRANSCODER_EDP:
2709                 return "TRANSCODER_EDP";
2710         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2711                 return "PORT_DDI_A_2_LANES";
2712         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2713                 return "PORT_DDI_A_4_LANES";
2714         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2715                 return "PORT_DDI_B_2_LANES";
2716         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2717                 return "PORT_DDI_B_4_LANES";
2718         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2719                 return "PORT_DDI_C_2_LANES";
2720         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2721                 return "PORT_DDI_C_4_LANES";
2722         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2723                 return "PORT_DDI_D_2_LANES";
2724         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2725                 return "PORT_DDI_D_4_LANES";
2726         case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2727                 return "PORT_DDI_E_2_LANES";
2728         case POWER_DOMAIN_PORT_DSI:
2729                 return "PORT_DSI";
2730         case POWER_DOMAIN_PORT_CRT:
2731                 return "PORT_CRT";
2732         case POWER_DOMAIN_PORT_OTHER:
2733                 return "PORT_OTHER";
2734         case POWER_DOMAIN_VGA:
2735                 return "VGA";
2736         case POWER_DOMAIN_AUDIO:
2737                 return "AUDIO";
2738         case POWER_DOMAIN_PLLS:
2739                 return "PLLS";
2740         case POWER_DOMAIN_AUX_A:
2741                 return "AUX_A";
2742         case POWER_DOMAIN_AUX_B:
2743                 return "AUX_B";
2744         case POWER_DOMAIN_AUX_C:
2745                 return "AUX_C";
2746         case POWER_DOMAIN_AUX_D:
2747                 return "AUX_D";
2748         case POWER_DOMAIN_INIT:
2749                 return "INIT";
2750         default:
2751                 MISSING_CASE(domain);
2752                 return "?";
2753         }
2754 }
2755
2756 static int i915_power_domain_info(struct seq_file *m, void *unused)
2757 {
2758         struct drm_info_node *node = m->private;
2759         struct drm_device *dev = node->minor->dev;
2760         struct drm_i915_private *dev_priv = dev->dev_private;
2761         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2762         int i;
2763
2764         mutex_lock(&power_domains->lock);
2765
2766         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2767         for (i = 0; i < power_domains->power_well_count; i++) {
2768                 struct i915_power_well *power_well;
2769                 enum intel_display_power_domain power_domain;
2770
2771                 power_well = &power_domains->power_wells[i];
2772                 seq_printf(m, "%-25s %d\n", power_well->name,
2773                            power_well->count);
2774
2775                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2776                      power_domain++) {
2777                         if (!(BIT(power_domain) & power_well->domains))
2778                                 continue;
2779
2780                         seq_printf(m, "  %-23s %d\n",
2781                                  power_domain_str(power_domain),
2782                                  power_domains->domain_use_count[power_domain]);
2783                 }
2784         }
2785
2786         mutex_unlock(&power_domains->lock);
2787
2788         return 0;
2789 }
2790
2791 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792                                  struct drm_display_mode *mode)
2793 {
2794         int i;
2795
2796         for (i = 0; i < tabs; i++)
2797                 seq_putc(m, '\t');
2798
2799         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800                    mode->base.id, mode->name,
2801                    mode->vrefresh, mode->clock,
2802                    mode->hdisplay, mode->hsync_start,
2803                    mode->hsync_end, mode->htotal,
2804                    mode->vdisplay, mode->vsync_start,
2805                    mode->vsync_end, mode->vtotal,
2806                    mode->type, mode->flags);
2807 }
2808
2809 static void intel_encoder_info(struct seq_file *m,
2810                                struct intel_crtc *intel_crtc,
2811                                struct intel_encoder *intel_encoder)
2812 {
2813         struct drm_info_node *node = m->private;
2814         struct drm_device *dev = node->minor->dev;
2815         struct drm_crtc *crtc = &intel_crtc->base;
2816         struct intel_connector *intel_connector;
2817         struct drm_encoder *encoder;
2818
2819         encoder = &intel_encoder->base;
2820         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2821                    encoder->base.id, encoder->name);
2822         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823                 struct drm_connector *connector = &intel_connector->base;
2824                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2825                            connector->base.id,
2826                            connector->name,
2827                            drm_get_connector_status_name(connector->status));
2828                 if (connector->status == connector_status_connected) {
2829                         struct drm_display_mode *mode = &crtc->mode;
2830                         seq_printf(m, ", mode:\n");
2831                         intel_seq_print_mode(m, 2, mode);
2832                 } else {
2833                         seq_putc(m, '\n');
2834                 }
2835         }
2836 }
2837
2838 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2839 {
2840         struct drm_info_node *node = m->private;
2841         struct drm_device *dev = node->minor->dev;
2842         struct drm_crtc *crtc = &intel_crtc->base;
2843         struct intel_encoder *intel_encoder;
2844         struct drm_plane_state *plane_state = crtc->primary->state;
2845         struct drm_framebuffer *fb = plane_state->fb;
2846
2847         if (fb)
2848                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849                            fb->base.id, plane_state->src_x >> 16,
2850                            plane_state->src_y >> 16, fb->width, fb->height);
2851         else
2852                 seq_puts(m, "\tprimary plane disabled\n");
2853         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854                 intel_encoder_info(m, intel_crtc, intel_encoder);
2855 }
2856
2857 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2858 {
2859         struct drm_display_mode *mode = panel->fixed_mode;
2860
2861         seq_printf(m, "\tfixed mode:\n");
2862         intel_seq_print_mode(m, 2, mode);
2863 }
2864
2865 static void intel_dp_info(struct seq_file *m,
2866                           struct intel_connector *intel_connector)
2867 {
2868         struct intel_encoder *intel_encoder = intel_connector->encoder;
2869         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2870
2871         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2872         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2873         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2874                 intel_panel_info(m, &intel_connector->panel);
2875 }
2876
2877 static void intel_hdmi_info(struct seq_file *m,
2878                             struct intel_connector *intel_connector)
2879 {
2880         struct intel_encoder *intel_encoder = intel_connector->encoder;
2881         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2882
2883         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2884 }
2885
2886 static void intel_lvds_info(struct seq_file *m,
2887                             struct intel_connector *intel_connector)
2888 {
2889         intel_panel_info(m, &intel_connector->panel);
2890 }
2891
2892 static void intel_connector_info(struct seq_file *m,
2893                                  struct drm_connector *connector)
2894 {
2895         struct intel_connector *intel_connector = to_intel_connector(connector);
2896         struct intel_encoder *intel_encoder = intel_connector->encoder;
2897         struct drm_display_mode *mode;
2898
2899         seq_printf(m, "connector %d: type %s, status: %s\n",
2900                    connector->base.id, connector->name,
2901                    drm_get_connector_status_name(connector->status));
2902         if (connector->status == connector_status_connected) {
2903                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2904                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2905                            connector->display_info.width_mm,
2906                            connector->display_info.height_mm);
2907                 seq_printf(m, "\tsubpixel order: %s\n",
2908                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2909                 seq_printf(m, "\tCEA rev: %d\n",
2910                            connector->display_info.cea_rev);
2911         }
2912         if (intel_encoder) {
2913                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2914                     intel_encoder->type == INTEL_OUTPUT_EDP)
2915                         intel_dp_info(m, intel_connector);
2916                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2917                         intel_hdmi_info(m, intel_connector);
2918                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2919                         intel_lvds_info(m, intel_connector);
2920         }
2921
2922         seq_printf(m, "\tmodes:\n");
2923         list_for_each_entry(mode, &connector->modes, head)
2924                 intel_seq_print_mode(m, 2, mode);
2925 }
2926
2927 static bool cursor_active(struct drm_device *dev, int pipe)
2928 {
2929         struct drm_i915_private *dev_priv = dev->dev_private;
2930         u32 state;
2931
2932         if (IS_845G(dev) || IS_I865G(dev))
2933                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2934         else
2935                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2936
2937         return state;
2938 }
2939
2940 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2941 {
2942         struct drm_i915_private *dev_priv = dev->dev_private;
2943         u32 pos;
2944
2945         pos = I915_READ(CURPOS(pipe));
2946
2947         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2948         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2949                 *x = -*x;
2950
2951         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2952         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2953                 *y = -*y;
2954
2955         return cursor_active(dev, pipe);
2956 }
2957
2958 static const char *plane_type(enum drm_plane_type type)
2959 {
2960         switch (type) {
2961         case DRM_PLANE_TYPE_OVERLAY:
2962                 return "OVL";
2963         case DRM_PLANE_TYPE_PRIMARY:
2964                 return "PRI";
2965         case DRM_PLANE_TYPE_CURSOR:
2966                 return "CUR";
2967         /*
2968          * Deliberately omitting default: to generate compiler warnings
2969          * when a new drm_plane_type gets added.
2970          */
2971         }
2972
2973         return "unknown";
2974 }
2975
2976 static const char *plane_rotation(unsigned int rotation)
2977 {
2978         static char buf[48];
2979         /*
2980          * According to doc only one DRM_ROTATE_ is allowed but this
2981          * will print them all to visualize if the values are misused
2982          */
2983         snprintf(buf, sizeof(buf),
2984                  "%s%s%s%s%s%s(0x%08x)",
2985                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2986                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2987                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
2988                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
2989                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
2990                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
2991                  rotation);
2992
2993         return buf;
2994 }
2995
2996 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2997 {
2998         struct drm_info_node *node = m->private;
2999         struct drm_device *dev = node->minor->dev;
3000         struct intel_plane *intel_plane;
3001
3002         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3003                 struct drm_plane_state *state;
3004                 struct drm_plane *plane = &intel_plane->base;
3005
3006                 if (!plane->state) {
3007                         seq_puts(m, "plane->state is NULL!\n");
3008                         continue;
3009                 }
3010
3011                 state = plane->state;
3012
3013                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3014                            plane->base.id,
3015                            plane_type(intel_plane->base.type),
3016                            state->crtc_x, state->crtc_y,
3017                            state->crtc_w, state->crtc_h,
3018                            (state->src_x >> 16),
3019                            ((state->src_x & 0xffff) * 15625) >> 10,
3020                            (state->src_y >> 16),
3021                            ((state->src_y & 0xffff) * 15625) >> 10,
3022                            (state->src_w >> 16),
3023                            ((state->src_w & 0xffff) * 15625) >> 10,
3024                            (state->src_h >> 16),
3025                            ((state->src_h & 0xffff) * 15625) >> 10,
3026                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3027                            plane_rotation(state->rotation));
3028         }
3029 }
3030
3031 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3032 {
3033         struct intel_crtc_state *pipe_config;
3034         int num_scalers = intel_crtc->num_scalers;
3035         int i;
3036
3037         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3038
3039         /* Not all platformas have a scaler */
3040         if (num_scalers) {
3041                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3042                            num_scalers,
3043                            pipe_config->scaler_state.scaler_users,
3044                            pipe_config->scaler_state.scaler_id);
3045
3046                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3047                         struct intel_scaler *sc =
3048                                         &pipe_config->scaler_state.scalers[i];
3049
3050                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3051                                    i, yesno(sc->in_use), sc->mode);
3052                 }
3053                 seq_puts(m, "\n");
3054         } else {
3055                 seq_puts(m, "\tNo scalers available on this platform\n");
3056         }
3057 }
3058
3059 static int i915_display_info(struct seq_file *m, void *unused)
3060 {
3061         struct drm_info_node *node = m->private;
3062         struct drm_device *dev = node->minor->dev;
3063         struct drm_i915_private *dev_priv = dev->dev_private;
3064         struct intel_crtc *crtc;
3065         struct drm_connector *connector;
3066
3067         intel_runtime_pm_get(dev_priv);
3068         drm_modeset_lock_all(dev);
3069         seq_printf(m, "CRTC info\n");
3070         seq_printf(m, "---------\n");
3071         for_each_intel_crtc(dev, crtc) {
3072                 bool active;
3073                 struct intel_crtc_state *pipe_config;
3074                 int x, y;
3075
3076                 pipe_config = to_intel_crtc_state(crtc->base.state);
3077
3078                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3079                            crtc->base.base.id, pipe_name(crtc->pipe),
3080                            yesno(pipe_config->base.active),
3081                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3082                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3083
3084                 if (pipe_config->base.active) {
3085                         intel_crtc_info(m, crtc);
3086
3087                         active = cursor_position(dev, crtc->pipe, &x, &y);
3088                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3089                                    yesno(crtc->cursor_base),
3090                                    x, y, crtc->base.cursor->state->crtc_w,
3091                                    crtc->base.cursor->state->crtc_h,
3092                                    crtc->cursor_addr, yesno(active));
3093                         intel_scaler_info(m, crtc);
3094                         intel_plane_info(m, crtc);
3095                 }
3096
3097                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3098                            yesno(!crtc->cpu_fifo_underrun_disabled),
3099                            yesno(!crtc->pch_fifo_underrun_disabled));
3100         }
3101
3102         seq_printf(m, "\n");
3103         seq_printf(m, "Connector info\n");
3104         seq_printf(m, "--------------\n");
3105         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3106                 intel_connector_info(m, connector);
3107         }
3108         drm_modeset_unlock_all(dev);
3109         intel_runtime_pm_put(dev_priv);
3110
3111         return 0;
3112 }
3113
3114 static int i915_semaphore_status(struct seq_file *m, void *unused)
3115 {
3116         struct drm_info_node *node = (struct drm_info_node *) m->private;
3117         struct drm_device *dev = node->minor->dev;
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119         struct intel_engine_cs *ring;
3120         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3121         int i, j, ret;
3122
3123         if (!i915_semaphore_is_enabled(dev)) {
3124                 seq_puts(m, "Semaphores are disabled\n");
3125                 return 0;
3126         }
3127
3128         ret = mutex_lock_interruptible(&dev->struct_mutex);
3129         if (ret)
3130                 return ret;
3131         intel_runtime_pm_get(dev_priv);
3132
3133         if (IS_BROADWELL(dev)) {
3134                 struct page *page;
3135                 uint64_t *seqno;
3136
3137                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3138
3139                 seqno = (uint64_t *)kmap_atomic(page);
3140                 for_each_ring(ring, dev_priv, i) {
3141                         uint64_t offset;
3142
3143                         seq_printf(m, "%s\n", ring->name);
3144
3145                         seq_puts(m, "  Last signal:");
3146                         for (j = 0; j < num_rings; j++) {
3147                                 offset = i * I915_NUM_RINGS + j;
3148                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3149                                            seqno[offset], offset * 8);
3150                         }
3151                         seq_putc(m, '\n');
3152
3153                         seq_puts(m, "  Last wait:  ");
3154                         for (j = 0; j < num_rings; j++) {
3155                                 offset = i + (j * I915_NUM_RINGS);
3156                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3157                                            seqno[offset], offset * 8);
3158                         }
3159                         seq_putc(m, '\n');
3160
3161                 }
3162                 kunmap_atomic(seqno);
3163         } else {
3164                 seq_puts(m, "  Last signal:");
3165                 for_each_ring(ring, dev_priv, i)
3166                         for (j = 0; j < num_rings; j++)
3167                                 seq_printf(m, "0x%08x\n",
3168                                            I915_READ(ring->semaphore.mbox.signal[j]));
3169                 seq_putc(m, '\n');
3170         }
3171
3172         seq_puts(m, "\nSync seqno:\n");
3173         for_each_ring(ring, dev_priv, i) {
3174                 for (j = 0; j < num_rings; j++) {
3175                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3176                 }
3177                 seq_putc(m, '\n');
3178         }
3179         seq_putc(m, '\n');
3180
3181         intel_runtime_pm_put(dev_priv);
3182         mutex_unlock(&dev->struct_mutex);
3183         return 0;
3184 }
3185
3186 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3187 {
3188         struct drm_info_node *node = (struct drm_info_node *) m->private;
3189         struct drm_device *dev = node->minor->dev;
3190         struct drm_i915_private *dev_priv = dev->dev_private;
3191         int i;
3192
3193         drm_modeset_lock_all(dev);
3194         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3195                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3196
3197                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3198                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3199                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3200                 seq_printf(m, " tracked hardware state:\n");
3201                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3202                 seq_printf(m, " dpll_md: 0x%08x\n",
3203                            pll->config.hw_state.dpll_md);
3204                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3205                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3206                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3207         }
3208         drm_modeset_unlock_all(dev);
3209
3210         return 0;
3211 }
3212
3213 static int i915_wa_registers(struct seq_file *m, void *unused)
3214 {
3215         int i;
3216         int ret;
3217         struct drm_info_node *node = (struct drm_info_node *) m->private;
3218         struct drm_device *dev = node->minor->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220
3221         ret = mutex_lock_interruptible(&dev->struct_mutex);
3222         if (ret)
3223                 return ret;
3224
3225         intel_runtime_pm_get(dev_priv);
3226
3227         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3228         for (i = 0; i < dev_priv->workarounds.count; ++i) {
3229                 u32 addr, mask, value, read;
3230                 bool ok;
3231
3232                 addr = dev_priv->workarounds.reg[i].addr;
3233                 mask = dev_priv->workarounds.reg[i].mask;
3234                 value = dev_priv->workarounds.reg[i].value;
3235                 read = I915_READ(addr);
3236                 ok = (value & mask) == (read & mask);
3237                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3238                            addr, value, mask, read, ok ? "OK" : "FAIL");
3239         }
3240
3241         intel_runtime_pm_put(dev_priv);
3242         mutex_unlock(&dev->struct_mutex);
3243
3244         return 0;
3245 }
3246
3247 static int i915_ddb_info(struct seq_file *m, void *unused)
3248 {
3249         struct drm_info_node *node = m->private;
3250         struct drm_device *dev = node->minor->dev;
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252         struct skl_ddb_allocation *ddb;
3253         struct skl_ddb_entry *entry;
3254         enum pipe pipe;
3255         int plane;
3256
3257         if (INTEL_INFO(dev)->gen < 9)
3258                 return 0;
3259
3260         drm_modeset_lock_all(dev);
3261
3262         ddb = &dev_priv->wm.skl_hw.ddb;
3263
3264         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3265
3266         for_each_pipe(dev_priv, pipe) {
3267                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3268
3269                 for_each_plane(dev_priv, pipe, plane) {
3270                         entry = &ddb->plane[pipe][plane];
3271                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3272                                    entry->start, entry->end,
3273                                    skl_ddb_entry_size(entry));
3274                 }
3275
3276                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3277                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3278                            entry->end, skl_ddb_entry_size(entry));
3279         }
3280
3281         drm_modeset_unlock_all(dev);
3282
3283         return 0;
3284 }
3285
3286 static void drrs_status_per_crtc(struct seq_file *m,
3287                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3288 {
3289         struct intel_encoder *intel_encoder;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct i915_drrs *drrs = &dev_priv->drrs;
3292         int vrefresh = 0;
3293
3294         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3295                 /* Encoder connected on this CRTC */
3296                 switch (intel_encoder->type) {
3297                 case INTEL_OUTPUT_EDP:
3298                         seq_puts(m, "eDP:\n");
3299                         break;
3300                 case INTEL_OUTPUT_DSI:
3301                         seq_puts(m, "DSI:\n");
3302                         break;
3303                 case INTEL_OUTPUT_HDMI:
3304                         seq_puts(m, "HDMI:\n");
3305                         break;
3306                 case INTEL_OUTPUT_DISPLAYPORT:
3307                         seq_puts(m, "DP:\n");
3308                         break;
3309                 default:
3310                         seq_printf(m, "Other encoder (id=%d).\n",
3311                                                 intel_encoder->type);
3312                         return;
3313                 }
3314         }
3315
3316         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3317                 seq_puts(m, "\tVBT: DRRS_type: Static");
3318         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3319                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3320         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3321                 seq_puts(m, "\tVBT: DRRS_type: None");
3322         else
3323                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3324
3325         seq_puts(m, "\n\n");
3326
3327         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3328                 struct intel_panel *panel;
3329
3330                 mutex_lock(&drrs->mutex);
3331                 /* DRRS Supported */
3332                 seq_puts(m, "\tDRRS Supported: Yes\n");
3333
3334                 /* disable_drrs() will make drrs->dp NULL */
3335                 if (!drrs->dp) {
3336                         seq_puts(m, "Idleness DRRS: Disabled");
3337                         mutex_unlock(&drrs->mutex);
3338                         return;
3339                 }
3340
3341                 panel = &drrs->dp->attached_connector->panel;
3342                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3343                                         drrs->busy_frontbuffer_bits);
3344
3345                 seq_puts(m, "\n\t\t");
3346                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3347                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3348                         vrefresh = panel->fixed_mode->vrefresh;
3349                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3350                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3351                         vrefresh = panel->downclock_mode->vrefresh;
3352                 } else {
3353                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3354                                                 drrs->refresh_rate_type);
3355                         mutex_unlock(&drrs->mutex);
3356                         return;
3357                 }
3358                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3359
3360                 seq_puts(m, "\n\t\t");
3361                 mutex_unlock(&drrs->mutex);
3362         } else {
3363                 /* DRRS not supported. Print the VBT parameter*/
3364                 seq_puts(m, "\tDRRS Supported : No");
3365         }
3366         seq_puts(m, "\n");
3367 }
3368
3369 static int i915_drrs_status(struct seq_file *m, void *unused)
3370 {
3371         struct drm_info_node *node = m->private;
3372         struct drm_device *dev = node->minor->dev;
3373         struct intel_crtc *intel_crtc;
3374         int active_crtc_cnt = 0;
3375
3376         for_each_intel_crtc(dev, intel_crtc) {
3377                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3378
3379                 if (intel_crtc->base.state->active) {
3380                         active_crtc_cnt++;
3381                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3382
3383                         drrs_status_per_crtc(m, dev, intel_crtc);
3384                 }
3385
3386                 drm_modeset_unlock(&intel_crtc->base.mutex);
3387         }
3388
3389         if (!active_crtc_cnt)
3390                 seq_puts(m, "No active crtc found\n");
3391
3392         return 0;
3393 }
3394
3395 struct pipe_crc_info {
3396         const char *name;
3397         struct drm_device *dev;
3398         enum pipe pipe;
3399 };
3400
3401 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3402 {
3403         struct drm_info_node *node = (struct drm_info_node *) m->private;
3404         struct drm_device *dev = node->minor->dev;
3405         struct drm_encoder *encoder;
3406         struct intel_encoder *intel_encoder;
3407         struct intel_digital_port *intel_dig_port;
3408         drm_modeset_lock_all(dev);
3409         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3410                 intel_encoder = to_intel_encoder(encoder);
3411                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3412                         continue;
3413                 intel_dig_port = enc_to_dig_port(encoder);
3414                 if (!intel_dig_port->dp.can_mst)
3415                         continue;
3416
3417                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3418         }
3419         drm_modeset_unlock_all(dev);
3420         return 0;
3421 }
3422
3423 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3424 {
3425         struct pipe_crc_info *info = inode->i_private;
3426         struct drm_i915_private *dev_priv = info->dev->dev_private;
3427         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3428
3429         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3430                 return -ENODEV;
3431
3432         spin_lock_irq(&pipe_crc->lock);
3433
3434         if (pipe_crc->opened) {
3435                 spin_unlock_irq(&pipe_crc->lock);
3436                 return -EBUSY; /* already open */
3437         }
3438
3439         pipe_crc->opened = true;
3440         filep->private_data = inode->i_private;
3441
3442         spin_unlock_irq(&pipe_crc->lock);
3443
3444         return 0;
3445 }
3446
3447 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3448 {
3449         struct pipe_crc_info *info = inode->i_private;
3450         struct drm_i915_private *dev_priv = info->dev->dev_private;
3451         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3452
3453         spin_lock_irq(&pipe_crc->lock);
3454         pipe_crc->opened = false;
3455         spin_unlock_irq(&pipe_crc->lock);
3456
3457         return 0;
3458 }
3459
3460 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3461 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3462 /* account for \'0' */
3463 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3464
3465 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3466 {
3467         assert_spin_locked(&pipe_crc->lock);
3468         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3469                         INTEL_PIPE_CRC_ENTRIES_NR);
3470 }
3471
3472 static ssize_t
3473 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3474                    loff_t *pos)
3475 {
3476         struct pipe_crc_info *info = filep->private_data;
3477         struct drm_device *dev = info->dev;
3478         struct drm_i915_private *dev_priv = dev->dev_private;
3479         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3480         char buf[PIPE_CRC_BUFFER_LEN];
3481         int n_entries;
3482         ssize_t bytes_read;
3483
3484         /*
3485          * Don't allow user space to provide buffers not big enough to hold
3486          * a line of data.
3487          */
3488         if (count < PIPE_CRC_LINE_LEN)
3489                 return -EINVAL;
3490
3491         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3492                 return 0;
3493
3494         /* nothing to read */
3495         spin_lock_irq(&pipe_crc->lock);
3496         while (pipe_crc_data_count(pipe_crc) == 0) {
3497                 int ret;
3498
3499                 if (filep->f_flags & O_NONBLOCK) {
3500                         spin_unlock_irq(&pipe_crc->lock);
3501                         return -EAGAIN;
3502                 }
3503
3504                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3505                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3506                 if (ret) {
3507                         spin_unlock_irq(&pipe_crc->lock);
3508                         return ret;
3509                 }
3510         }
3511
3512         /* We now have one or more entries to read */
3513         n_entries = count / PIPE_CRC_LINE_LEN;
3514
3515         bytes_read = 0;
3516         while (n_entries > 0) {
3517                 struct intel_pipe_crc_entry *entry =
3518                         &pipe_crc->entries[pipe_crc->tail];
3519                 int ret;
3520
3521                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3522                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3523                         break;
3524
3525                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3526                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3527
3528                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3529                                        "%8u %8x %8x %8x %8x %8x\n",
3530                                        entry->frame, entry->crc[0],
3531                                        entry->crc[1], entry->crc[2],
3532                                        entry->crc[3], entry->crc[4]);
3533
3534                 spin_unlock_irq(&pipe_crc->lock);
3535
3536                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3537                 if (ret == PIPE_CRC_LINE_LEN)
3538                         return -EFAULT;
3539
3540                 user_buf += PIPE_CRC_LINE_LEN;
3541                 n_entries--;
3542
3543                 spin_lock_irq(&pipe_crc->lock);
3544         }
3545
3546         spin_unlock_irq(&pipe_crc->lock);
3547
3548         return bytes_read;
3549 }
3550
3551 static const struct file_operations i915_pipe_crc_fops = {
3552         .owner = THIS_MODULE,
3553         .open = i915_pipe_crc_open,
3554         .read = i915_pipe_crc_read,
3555         .release = i915_pipe_crc_release,
3556 };
3557
3558 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3559         {
3560                 .name = "i915_pipe_A_crc",
3561                 .pipe = PIPE_A,
3562         },
3563         {
3564                 .name = "i915_pipe_B_crc",
3565                 .pipe = PIPE_B,
3566         },
3567         {
3568                 .name = "i915_pipe_C_crc",
3569                 .pipe = PIPE_C,
3570         },
3571 };
3572
3573 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3574                                 enum pipe pipe)
3575 {
3576         struct drm_device *dev = minor->dev;
3577         struct dentry *ent;
3578         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3579
3580         info->dev = dev;
3581         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3582                                   &i915_pipe_crc_fops);
3583         if (!ent)
3584                 return -ENOMEM;
3585
3586         return drm_add_fake_info_node(minor, ent, info);
3587 }
3588
3589 static const char * const pipe_crc_sources[] = {
3590         "none",
3591         "plane1",
3592         "plane2",
3593         "pf",
3594         "pipe",
3595         "TV",
3596         "DP-B",
3597         "DP-C",
3598         "DP-D",
3599         "auto",
3600 };
3601
3602 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3603 {
3604         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3605         return pipe_crc_sources[source];
3606 }
3607
3608 static int display_crc_ctl_show(struct seq_file *m, void *data)
3609 {
3610         struct drm_device *dev = m->private;
3611         struct drm_i915_private *dev_priv = dev->dev_private;
3612         int i;
3613
3614         for (i = 0; i < I915_MAX_PIPES; i++)
3615                 seq_printf(m, "%c %s\n", pipe_name(i),
3616                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3617
3618         return 0;
3619 }
3620
3621 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3622 {
3623         struct drm_device *dev = inode->i_private;
3624
3625         return single_open(file, display_crc_ctl_show, dev);
3626 }
3627
3628 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3629                                  uint32_t *val)
3630 {
3631         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3632                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3633
3634         switch (*source) {
3635         case INTEL_PIPE_CRC_SOURCE_PIPE:
3636                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3637                 break;
3638         case INTEL_PIPE_CRC_SOURCE_NONE:
3639                 *val = 0;
3640                 break;
3641         default:
3642                 return -EINVAL;
3643         }
3644
3645         return 0;
3646 }
3647
3648 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3649                                      enum intel_pipe_crc_source *source)
3650 {
3651         struct intel_encoder *encoder;
3652         struct intel_crtc *crtc;
3653         struct intel_digital_port *dig_port;
3654         int ret = 0;
3655
3656         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3657
3658         drm_modeset_lock_all(dev);
3659         for_each_intel_encoder(dev, encoder) {
3660                 if (!encoder->base.crtc)
3661                         continue;
3662
3663                 crtc = to_intel_crtc(encoder->base.crtc);
3664
3665                 if (crtc->pipe != pipe)
3666                         continue;
3667
3668                 switch (encoder->type) {
3669                 case INTEL_OUTPUT_TVOUT:
3670                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3671                         break;
3672                 case INTEL_OUTPUT_DISPLAYPORT:
3673                 case INTEL_OUTPUT_EDP:
3674                         dig_port = enc_to_dig_port(&encoder->base);
3675                         switch (dig_port->port) {
3676                         case PORT_B:
3677                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3678                                 break;
3679                         case PORT_C:
3680                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3681                                 break;
3682                         case PORT_D:
3683                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3684                                 break;
3685                         default:
3686                                 WARN(1, "nonexisting DP port %c\n",
3687                                      port_name(dig_port->port));
3688                                 break;
3689                         }
3690                         break;
3691                 default:
3692                         break;
3693                 }
3694         }
3695         drm_modeset_unlock_all(dev);
3696
3697         return ret;
3698 }
3699
3700 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3701                                 enum pipe pipe,
3702                                 enum intel_pipe_crc_source *source,
3703                                 uint32_t *val)
3704 {
3705         struct drm_i915_private *dev_priv = dev->dev_private;
3706         bool need_stable_symbols = false;
3707
3708         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3709                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3710                 if (ret)
3711                         return ret;
3712         }
3713
3714         switch (*source) {
3715         case INTEL_PIPE_CRC_SOURCE_PIPE:
3716                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3717                 break;
3718         case INTEL_PIPE_CRC_SOURCE_DP_B:
3719                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3720                 need_stable_symbols = true;
3721                 break;
3722         case INTEL_PIPE_CRC_SOURCE_DP_C:
3723                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3724                 need_stable_symbols = true;
3725                 break;
3726         case INTEL_PIPE_CRC_SOURCE_DP_D:
3727                 if (!IS_CHERRYVIEW(dev))
3728                         return -EINVAL;
3729                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3730                 need_stable_symbols = true;
3731                 break;
3732         case INTEL_PIPE_CRC_SOURCE_NONE:
3733                 *val = 0;
3734                 break;
3735         default:
3736                 return -EINVAL;
3737         }
3738
3739         /*
3740          * When the pipe CRC tap point is after the transcoders we need
3741          * to tweak symbol-level features to produce a deterministic series of
3742          * symbols for a given frame. We need to reset those features only once
3743          * a frame (instead of every nth symbol):
3744          *   - DC-balance: used to ensure a better clock recovery from the data
3745          *     link (SDVO)
3746          *   - DisplayPort scrambling: used for EMI reduction
3747          */
3748         if (need_stable_symbols) {
3749                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3750
3751                 tmp |= DC_BALANCE_RESET_VLV;
3752                 switch (pipe) {
3753                 case PIPE_A:
3754                         tmp |= PIPE_A_SCRAMBLE_RESET;
3755                         break;
3756                 case PIPE_B:
3757                         tmp |= PIPE_B_SCRAMBLE_RESET;
3758                         break;
3759                 case PIPE_C:
3760                         tmp |= PIPE_C_SCRAMBLE_RESET;
3761                         break;
3762                 default:
3763                         return -EINVAL;
3764                 }
3765                 I915_WRITE(PORT_DFT2_G4X, tmp);
3766         }
3767
3768         return 0;
3769 }
3770
3771 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3772                                  enum pipe pipe,
3773                                  enum intel_pipe_crc_source *source,
3774                                  uint32_t *val)
3775 {
3776         struct drm_i915_private *dev_priv = dev->dev_private;
3777         bool need_stable_symbols = false;
3778
3779         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3780                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3781                 if (ret)
3782                         return ret;
3783         }
3784
3785         switch (*source) {
3786         case INTEL_PIPE_CRC_SOURCE_PIPE:
3787                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3788                 break;
3789         case INTEL_PIPE_CRC_SOURCE_TV:
3790                 if (!SUPPORTS_TV(dev))
3791                         return -EINVAL;
3792                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3793                 break;
3794         case INTEL_PIPE_CRC_SOURCE_DP_B:
3795                 if (!IS_G4X(dev))
3796                         return -EINVAL;
3797                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3798                 need_stable_symbols = true;
3799                 break;
3800         case INTEL_PIPE_CRC_SOURCE_DP_C:
3801                 if (!IS_G4X(dev))
3802                         return -EINVAL;
3803                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3804                 need_stable_symbols = true;
3805                 break;
3806         case INTEL_PIPE_CRC_SOURCE_DP_D:
3807                 if (!IS_G4X(dev))
3808                         return -EINVAL;
3809                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3810                 need_stable_symbols = true;
3811                 break;
3812         case INTEL_PIPE_CRC_SOURCE_NONE:
3813                 *val = 0;
3814                 break;
3815         default:
3816                 return -EINVAL;
3817         }
3818
3819         /*
3820          * When the pipe CRC tap point is after the transcoders we need
3821          * to tweak symbol-level features to produce a deterministic series of
3822          * symbols for a given frame. We need to reset those features only once
3823          * a frame (instead of every nth symbol):
3824          *   - DC-balance: used to ensure a better clock recovery from the data
3825          *     link (SDVO)
3826          *   - DisplayPort scrambling: used for EMI reduction
3827          */
3828         if (need_stable_symbols) {
3829                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3830
3831                 WARN_ON(!IS_G4X(dev));
3832
3833                 I915_WRITE(PORT_DFT_I9XX,
3834                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3835
3836                 if (pipe == PIPE_A)
3837                         tmp |= PIPE_A_SCRAMBLE_RESET;
3838                 else
3839                         tmp |= PIPE_B_SCRAMBLE_RESET;
3840
3841                 I915_WRITE(PORT_DFT2_G4X, tmp);
3842         }
3843
3844         return 0;
3845 }
3846
3847 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3848                                          enum pipe pipe)
3849 {
3850         struct drm_i915_private *dev_priv = dev->dev_private;
3851         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3852
3853         switch (pipe) {
3854         case PIPE_A:
3855                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3856                 break;
3857         case PIPE_B:
3858                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3859                 break;
3860         case PIPE_C:
3861                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3862                 break;
3863         default:
3864                 return;
3865         }
3866         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3867                 tmp &= ~DC_BALANCE_RESET_VLV;
3868         I915_WRITE(PORT_DFT2_G4X, tmp);
3869
3870 }
3871
3872 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3873                                          enum pipe pipe)
3874 {
3875         struct drm_i915_private *dev_priv = dev->dev_private;
3876         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3877
3878         if (pipe == PIPE_A)
3879                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3880         else
3881                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3882         I915_WRITE(PORT_DFT2_G4X, tmp);
3883
3884         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3885                 I915_WRITE(PORT_DFT_I9XX,
3886                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3887         }
3888 }
3889
3890 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3891                                 uint32_t *val)
3892 {
3893         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3894                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3895
3896         switch (*source) {
3897         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3898                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3899                 break;
3900         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3901                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3902                 break;
3903         case INTEL_PIPE_CRC_SOURCE_PIPE:
3904                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3905                 break;
3906         case INTEL_PIPE_CRC_SOURCE_NONE:
3907                 *val = 0;
3908                 break;
3909         default:
3910                 return -EINVAL;
3911         }
3912
3913         return 0;
3914 }
3915
3916 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3917 {
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         struct intel_crtc *crtc =
3920                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3921         struct intel_crtc_state *pipe_config;
3922         struct drm_atomic_state *state;
3923         int ret = 0;
3924
3925         drm_modeset_lock_all(dev);
3926         state = drm_atomic_state_alloc(dev);
3927         if (!state) {
3928                 ret = -ENOMEM;
3929                 goto out;
3930         }
3931
3932         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3933         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3934         if (IS_ERR(pipe_config)) {
3935                 ret = PTR_ERR(pipe_config);
3936                 goto out;
3937         }
3938
3939         pipe_config->pch_pfit.force_thru = enable;
3940         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3941             pipe_config->pch_pfit.enabled != enable)
3942                 pipe_config->base.connectors_changed = true;
3943
3944         ret = drm_atomic_commit(state);
3945 out:
3946         drm_modeset_unlock_all(dev);
3947         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3948         if (ret)
3949                 drm_atomic_state_free(state);
3950 }
3951
3952 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3953                                 enum pipe pipe,
3954                                 enum intel_pipe_crc_source *source,
3955                                 uint32_t *val)
3956 {
3957         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3958                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3959
3960         switch (*source) {
3961         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3962                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3963                 break;
3964         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3965                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3966                 break;
3967         case INTEL_PIPE_CRC_SOURCE_PF:
3968                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3969                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3970
3971                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3972                 break;
3973         case INTEL_PIPE_CRC_SOURCE_NONE:
3974                 *val = 0;
3975                 break;
3976         default:
3977                 return -EINVAL;
3978         }
3979
3980         return 0;
3981 }
3982
3983 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3984                                enum intel_pipe_crc_source source)
3985 {
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3988         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3989                                                                         pipe));
3990         u32 val = 0; /* shut up gcc */
3991         int ret;
3992
3993         if (pipe_crc->source == source)
3994                 return 0;
3995
3996         /* forbid changing the source without going back to 'none' */
3997         if (pipe_crc->source && source)
3998                 return -EINVAL;
3999
4000         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
4001                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4002                 return -EIO;
4003         }
4004
4005         if (IS_GEN2(dev))
4006                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4007         else if (INTEL_INFO(dev)->gen < 5)
4008                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4009         else if (IS_VALLEYVIEW(dev))
4010                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4011         else if (IS_GEN5(dev) || IS_GEN6(dev))
4012                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4013         else
4014                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4015
4016         if (ret != 0)
4017                 return ret;
4018
4019         /* none -> real source transition */
4020         if (source) {
4021                 struct intel_pipe_crc_entry *entries;
4022
4023                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4024                                  pipe_name(pipe), pipe_crc_source_name(source));
4025
4026                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4027                                   sizeof(pipe_crc->entries[0]),
4028                                   GFP_KERNEL);
4029                 if (!entries)
4030                         return -ENOMEM;
4031
4032                 /*
4033                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4034                  * enabled and disabled dynamically based on package C states,
4035                  * user space can't make reliable use of the CRCs, so let's just
4036                  * completely disable it.
4037                  */
4038                 hsw_disable_ips(crtc);
4039
4040                 spin_lock_irq(&pipe_crc->lock);
4041                 kfree(pipe_crc->entries);
4042                 pipe_crc->entries = entries;
4043                 pipe_crc->head = 0;
4044                 pipe_crc->tail = 0;
4045                 spin_unlock_irq(&pipe_crc->lock);
4046         }
4047
4048         pipe_crc->source = source;
4049
4050         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4051         POSTING_READ(PIPE_CRC_CTL(pipe));
4052
4053         /* real source -> none transition */
4054         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4055                 struct intel_pipe_crc_entry *entries;
4056                 struct intel_crtc *crtc =
4057                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4058
4059                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4060                                  pipe_name(pipe));
4061
4062                 drm_modeset_lock(&crtc->base.mutex, NULL);
4063                 if (crtc->base.state->active)
4064                         intel_wait_for_vblank(dev, pipe);
4065                 drm_modeset_unlock(&crtc->base.mutex);
4066
4067                 spin_lock_irq(&pipe_crc->lock);
4068                 entries = pipe_crc->entries;
4069                 pipe_crc->entries = NULL;
4070                 pipe_crc->head = 0;
4071                 pipe_crc->tail = 0;
4072                 spin_unlock_irq(&pipe_crc->lock);
4073
4074                 kfree(entries);
4075
4076                 if (IS_G4X(dev))
4077                         g4x_undo_pipe_scramble_reset(dev, pipe);
4078                 else if (IS_VALLEYVIEW(dev))
4079                         vlv_undo_pipe_scramble_reset(dev, pipe);
4080                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4081                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4082
4083                 hsw_enable_ips(crtc);
4084         }
4085
4086         return 0;
4087 }
4088
4089 /*
4090  * Parse pipe CRC command strings:
4091  *   command: wsp* object wsp+ name wsp+ source wsp*
4092  *   object: 'pipe'
4093  *   name: (A | B | C)
4094  *   source: (none | plane1 | plane2 | pf)
4095  *   wsp: (#0x20 | #0x9 | #0xA)+
4096  *
4097  * eg.:
4098  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4099  *  "pipe A none"    ->  Stop CRC
4100  */
4101 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4102 {
4103         int n_words = 0;
4104
4105         while (*buf) {
4106                 char *end;
4107
4108                 /* skip leading white space */
4109                 buf = skip_spaces(buf);
4110                 if (!*buf)
4111                         break;  /* end of buffer */
4112
4113                 /* find end of word */
4114                 for (end = buf; *end && !isspace(*end); end++)
4115                         ;
4116
4117                 if (n_words == max_words) {
4118                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4119                                          max_words);
4120                         return -EINVAL; /* ran out of words[] before bytes */
4121                 }
4122
4123                 if (*end)
4124                         *end++ = '\0';
4125                 words[n_words++] = buf;
4126                 buf = end;
4127         }
4128
4129         return n_words;
4130 }
4131
4132 enum intel_pipe_crc_object {
4133         PIPE_CRC_OBJECT_PIPE,
4134 };
4135
4136 static const char * const pipe_crc_objects[] = {
4137         "pipe",
4138 };
4139
4140 static int
4141 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4142 {
4143         int i;
4144
4145         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4146                 if (!strcmp(buf, pipe_crc_objects[i])) {
4147                         *o = i;
4148                         return 0;
4149                     }
4150
4151         return -EINVAL;
4152 }
4153
4154 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4155 {
4156         const char name = buf[0];
4157
4158         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4159                 return -EINVAL;
4160
4161         *pipe = name - 'A';
4162
4163         return 0;
4164 }
4165
4166 static int
4167 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4168 {
4169         int i;
4170
4171         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4172                 if (!strcmp(buf, pipe_crc_sources[i])) {
4173                         *s = i;
4174                         return 0;
4175                     }
4176
4177         return -EINVAL;
4178 }
4179
4180 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4181 {
4182 #define N_WORDS 3
4183         int n_words;
4184         char *words[N_WORDS];
4185         enum pipe pipe;
4186         enum intel_pipe_crc_object object;
4187         enum intel_pipe_crc_source source;
4188
4189         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4190         if (n_words != N_WORDS) {
4191                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4192                                  N_WORDS);
4193                 return -EINVAL;
4194         }
4195
4196         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4197                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4198                 return -EINVAL;
4199         }
4200
4201         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4202                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4203                 return -EINVAL;
4204         }
4205
4206         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4207                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4208                 return -EINVAL;
4209         }
4210
4211         return pipe_crc_set_source(dev, pipe, source);
4212 }
4213
4214 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4215                                      size_t len, loff_t *offp)
4216 {
4217         struct seq_file *m = file->private_data;
4218         struct drm_device *dev = m->private;
4219         char *tmpbuf;
4220         int ret;
4221
4222         if (len == 0)
4223                 return 0;
4224
4225         if (len > PAGE_SIZE - 1) {
4226                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4227                                  PAGE_SIZE);
4228                 return -E2BIG;
4229         }
4230
4231         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4232         if (!tmpbuf)
4233                 return -ENOMEM;
4234
4235         if (copy_from_user(tmpbuf, ubuf, len)) {
4236                 ret = -EFAULT;
4237                 goto out;
4238         }
4239         tmpbuf[len] = '\0';
4240
4241         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4242
4243 out:
4244         kfree(tmpbuf);
4245         if (ret < 0)
4246                 return ret;
4247
4248         *offp += len;
4249         return len;
4250 }
4251
4252 static const struct file_operations i915_display_crc_ctl_fops = {
4253         .owner = THIS_MODULE,
4254         .open = display_crc_ctl_open,
4255         .read = seq_read,
4256         .llseek = seq_lseek,
4257         .release = single_release,
4258         .write = display_crc_ctl_write
4259 };
4260
4261 static ssize_t i915_displayport_test_active_write(struct file *file,
4262                                             const char __user *ubuf,
4263                                             size_t len, loff_t *offp)
4264 {
4265         char *input_buffer;
4266         int status = 0;
4267         struct drm_device *dev;
4268         struct drm_connector *connector;
4269         struct list_head *connector_list;
4270         struct intel_dp *intel_dp;
4271         int val = 0;
4272
4273         dev = ((struct seq_file *)file->private_data)->private;
4274
4275         connector_list = &dev->mode_config.connector_list;
4276
4277         if (len == 0)
4278                 return 0;
4279
4280         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4281         if (!input_buffer)
4282                 return -ENOMEM;
4283
4284         if (copy_from_user(input_buffer, ubuf, len)) {
4285                 status = -EFAULT;
4286                 goto out;
4287         }
4288
4289         input_buffer[len] = '\0';
4290         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4291
4292         list_for_each_entry(connector, connector_list, head) {
4293
4294                 if (connector->connector_type !=
4295                     DRM_MODE_CONNECTOR_DisplayPort)
4296                         continue;
4297
4298                 if (connector->status == connector_status_connected &&
4299                     connector->encoder != NULL) {
4300                         intel_dp = enc_to_intel_dp(connector->encoder);
4301                         status = kstrtoint(input_buffer, 10, &val);
4302                         if (status < 0)
4303                                 goto out;
4304                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4305                         /* To prevent erroneous activation of the compliance
4306                          * testing code, only accept an actual value of 1 here
4307                          */
4308                         if (val == 1)
4309                                 intel_dp->compliance_test_active = 1;
4310                         else
4311                                 intel_dp->compliance_test_active = 0;
4312                 }
4313         }
4314 out:
4315         kfree(input_buffer);
4316         if (status < 0)
4317                 return status;
4318
4319         *offp += len;
4320         return len;
4321 }
4322
4323 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4324 {
4325         struct drm_device *dev = m->private;
4326         struct drm_connector *connector;
4327         struct list_head *connector_list = &dev->mode_config.connector_list;
4328         struct intel_dp *intel_dp;
4329
4330         list_for_each_entry(connector, connector_list, head) {
4331
4332                 if (connector->connector_type !=
4333                     DRM_MODE_CONNECTOR_DisplayPort)
4334                         continue;
4335
4336                 if (connector->status == connector_status_connected &&
4337                     connector->encoder != NULL) {
4338                         intel_dp = enc_to_intel_dp(connector->encoder);
4339                         if (intel_dp->compliance_test_active)
4340                                 seq_puts(m, "1");
4341                         else
4342                                 seq_puts(m, "0");
4343                 } else
4344                         seq_puts(m, "0");
4345         }
4346
4347         return 0;
4348 }
4349
4350 static int i915_displayport_test_active_open(struct inode *inode,
4351                                        struct file *file)
4352 {
4353         struct drm_device *dev = inode->i_private;
4354
4355         return single_open(file, i915_displayport_test_active_show, dev);
4356 }
4357
4358 static const struct file_operations i915_displayport_test_active_fops = {
4359         .owner = THIS_MODULE,
4360         .open = i915_displayport_test_active_open,
4361         .read = seq_read,
4362         .llseek = seq_lseek,
4363         .release = single_release,
4364         .write = i915_displayport_test_active_write
4365 };
4366
4367 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4368 {
4369         struct drm_device *dev = m->private;
4370         struct drm_connector *connector;
4371         struct list_head *connector_list = &dev->mode_config.connector_list;
4372         struct intel_dp *intel_dp;
4373
4374         list_for_each_entry(connector, connector_list, head) {
4375
4376                 if (connector->connector_type !=
4377                     DRM_MODE_CONNECTOR_DisplayPort)
4378                         continue;
4379
4380                 if (connector->status == connector_status_connected &&
4381                     connector->encoder != NULL) {
4382                         intel_dp = enc_to_intel_dp(connector->encoder);
4383                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4384                 } else
4385                         seq_puts(m, "0");
4386         }
4387
4388         return 0;
4389 }
4390 static int i915_displayport_test_data_open(struct inode *inode,
4391                                        struct file *file)
4392 {
4393         struct drm_device *dev = inode->i_private;
4394
4395         return single_open(file, i915_displayport_test_data_show, dev);
4396 }
4397
4398 static const struct file_operations i915_displayport_test_data_fops = {
4399         .owner = THIS_MODULE,
4400         .open = i915_displayport_test_data_open,
4401         .read = seq_read,
4402         .llseek = seq_lseek,
4403         .release = single_release
4404 };
4405
4406 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4407 {
4408         struct drm_device *dev = m->private;
4409         struct drm_connector *connector;
4410         struct list_head *connector_list = &dev->mode_config.connector_list;
4411         struct intel_dp *intel_dp;
4412
4413         list_for_each_entry(connector, connector_list, head) {
4414
4415                 if (connector->connector_type !=
4416                     DRM_MODE_CONNECTOR_DisplayPort)
4417                         continue;
4418
4419                 if (connector->status == connector_status_connected &&
4420                     connector->encoder != NULL) {
4421                         intel_dp = enc_to_intel_dp(connector->encoder);
4422                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4423                 } else
4424                         seq_puts(m, "0");
4425         }
4426
4427         return 0;
4428 }
4429
4430 static int i915_displayport_test_type_open(struct inode *inode,
4431                                        struct file *file)
4432 {
4433         struct drm_device *dev = inode->i_private;
4434
4435         return single_open(file, i915_displayport_test_type_show, dev);
4436 }
4437
4438 static const struct file_operations i915_displayport_test_type_fops = {
4439         .owner = THIS_MODULE,
4440         .open = i915_displayport_test_type_open,
4441         .read = seq_read,
4442         .llseek = seq_lseek,
4443         .release = single_release
4444 };
4445
4446 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4447 {
4448         struct drm_device *dev = m->private;
4449         int level;
4450         int num_levels;
4451
4452         if (IS_CHERRYVIEW(dev))
4453                 num_levels = 3;
4454         else if (IS_VALLEYVIEW(dev))
4455                 num_levels = 1;
4456         else
4457                 num_levels = ilk_wm_max_level(dev) + 1;
4458
4459         drm_modeset_lock_all(dev);
4460
4461         for (level = 0; level < num_levels; level++) {
4462                 unsigned int latency = wm[level];
4463
4464                 /*
4465                  * - WM1+ latency values in 0.5us units
4466                  * - latencies are in us on gen9/vlv/chv
4467                  */
4468                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4469                         latency *= 10;
4470                 else if (level > 0)
4471                         latency *= 5;
4472
4473                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4474                            level, wm[level], latency / 10, latency % 10);
4475         }
4476
4477         drm_modeset_unlock_all(dev);
4478 }
4479
4480 static int pri_wm_latency_show(struct seq_file *m, void *data)
4481 {
4482         struct drm_device *dev = m->private;
4483         struct drm_i915_private *dev_priv = dev->dev_private;
4484         const uint16_t *latencies;
4485
4486         if (INTEL_INFO(dev)->gen >= 9)
4487                 latencies = dev_priv->wm.skl_latency;
4488         else
4489                 latencies = to_i915(dev)->wm.pri_latency;
4490
4491         wm_latency_show(m, latencies);
4492
4493         return 0;
4494 }
4495
4496 static int spr_wm_latency_show(struct seq_file *m, void *data)
4497 {
4498         struct drm_device *dev = m->private;
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         const uint16_t *latencies;
4501
4502         if (INTEL_INFO(dev)->gen >= 9)
4503                 latencies = dev_priv->wm.skl_latency;
4504         else
4505                 latencies = to_i915(dev)->wm.spr_latency;
4506
4507         wm_latency_show(m, latencies);
4508
4509         return 0;
4510 }
4511
4512 static int cur_wm_latency_show(struct seq_file *m, void *data)
4513 {
4514         struct drm_device *dev = m->private;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516         const uint16_t *latencies;
4517
4518         if (INTEL_INFO(dev)->gen >= 9)
4519                 latencies = dev_priv->wm.skl_latency;
4520         else
4521                 latencies = to_i915(dev)->wm.cur_latency;
4522
4523         wm_latency_show(m, latencies);
4524
4525         return 0;
4526 }
4527
4528 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4529 {
4530         struct drm_device *dev = inode->i_private;
4531
4532         if (INTEL_INFO(dev)->gen < 5)
4533                 return -ENODEV;
4534
4535         return single_open(file, pri_wm_latency_show, dev);
4536 }
4537
4538 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4539 {
4540         struct drm_device *dev = inode->i_private;
4541
4542         if (HAS_GMCH_DISPLAY(dev))
4543                 return -ENODEV;
4544
4545         return single_open(file, spr_wm_latency_show, dev);
4546 }
4547
4548 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4549 {
4550         struct drm_device *dev = inode->i_private;
4551
4552         if (HAS_GMCH_DISPLAY(dev))
4553                 return -ENODEV;
4554
4555         return single_open(file, cur_wm_latency_show, dev);
4556 }
4557
4558 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4559                                 size_t len, loff_t *offp, uint16_t wm[8])
4560 {
4561         struct seq_file *m = file->private_data;
4562         struct drm_device *dev = m->private;
4563         uint16_t new[8] = { 0 };
4564         int num_levels;
4565         int level;
4566         int ret;
4567         char tmp[32];
4568
4569         if (IS_CHERRYVIEW(dev))
4570                 num_levels = 3;
4571         else if (IS_VALLEYVIEW(dev))
4572                 num_levels = 1;
4573         else
4574                 num_levels = ilk_wm_max_level(dev) + 1;
4575
4576         if (len >= sizeof(tmp))
4577                 return -EINVAL;
4578
4579         if (copy_from_user(tmp, ubuf, len))
4580                 return -EFAULT;
4581
4582         tmp[len] = '\0';
4583
4584         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4585                      &new[0], &new[1], &new[2], &new[3],
4586                      &new[4], &new[5], &new[6], &new[7]);
4587         if (ret != num_levels)
4588                 return -EINVAL;
4589
4590         drm_modeset_lock_all(dev);
4591
4592         for (level = 0; level < num_levels; level++)
4593                 wm[level] = new[level];
4594
4595         drm_modeset_unlock_all(dev);
4596
4597         return len;
4598 }
4599
4600
4601 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4602                                     size_t len, loff_t *offp)
4603 {
4604         struct seq_file *m = file->private_data;
4605         struct drm_device *dev = m->private;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         uint16_t *latencies;
4608
4609         if (INTEL_INFO(dev)->gen >= 9)
4610                 latencies = dev_priv->wm.skl_latency;
4611         else
4612                 latencies = to_i915(dev)->wm.pri_latency;
4613
4614         return wm_latency_write(file, ubuf, len, offp, latencies);
4615 }
4616
4617 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4618                                     size_t len, loff_t *offp)
4619 {
4620         struct seq_file *m = file->private_data;
4621         struct drm_device *dev = m->private;
4622         struct drm_i915_private *dev_priv = dev->dev_private;
4623         uint16_t *latencies;
4624
4625         if (INTEL_INFO(dev)->gen >= 9)
4626                 latencies = dev_priv->wm.skl_latency;
4627         else
4628                 latencies = to_i915(dev)->wm.spr_latency;
4629
4630         return wm_latency_write(file, ubuf, len, offp, latencies);
4631 }
4632
4633 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4634                                     size_t len, loff_t *offp)
4635 {
4636         struct seq_file *m = file->private_data;
4637         struct drm_device *dev = m->private;
4638         struct drm_i915_private *dev_priv = dev->dev_private;
4639         uint16_t *latencies;
4640
4641         if (INTEL_INFO(dev)->gen >= 9)
4642                 latencies = dev_priv->wm.skl_latency;
4643         else
4644                 latencies = to_i915(dev)->wm.cur_latency;
4645
4646         return wm_latency_write(file, ubuf, len, offp, latencies);
4647 }
4648
4649 static const struct file_operations i915_pri_wm_latency_fops = {
4650         .owner = THIS_MODULE,
4651         .open = pri_wm_latency_open,
4652         .read = seq_read,
4653         .llseek = seq_lseek,
4654         .release = single_release,
4655         .write = pri_wm_latency_write
4656 };
4657
4658 static const struct file_operations i915_spr_wm_latency_fops = {
4659         .owner = THIS_MODULE,
4660         .open = spr_wm_latency_open,
4661         .read = seq_read,
4662         .llseek = seq_lseek,
4663         .release = single_release,
4664         .write = spr_wm_latency_write
4665 };
4666
4667 static const struct file_operations i915_cur_wm_latency_fops = {
4668         .owner = THIS_MODULE,
4669         .open = cur_wm_latency_open,
4670         .read = seq_read,
4671         .llseek = seq_lseek,
4672         .release = single_release,
4673         .write = cur_wm_latency_write
4674 };
4675
4676 static int
4677 i915_wedged_get(void *data, u64 *val)
4678 {
4679         struct drm_device *dev = data;
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681
4682         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4683
4684         return 0;
4685 }
4686
4687 static int
4688 i915_wedged_set(void *data, u64 val)
4689 {
4690         struct drm_device *dev = data;
4691         struct drm_i915_private *dev_priv = dev->dev_private;
4692
4693         /*
4694          * There is no safeguard against this debugfs entry colliding
4695          * with the hangcheck calling same i915_handle_error() in
4696          * parallel, causing an explosion. For now we assume that the
4697          * test harness is responsible enough not to inject gpu hangs
4698          * while it is writing to 'i915_wedged'
4699          */
4700
4701         if (i915_reset_in_progress(&dev_priv->gpu_error))
4702                 return -EAGAIN;
4703
4704         intel_runtime_pm_get(dev_priv);
4705
4706         i915_handle_error(dev, val,
4707                           "Manually setting wedged to %llu", val);
4708
4709         intel_runtime_pm_put(dev_priv);
4710
4711         return 0;
4712 }
4713
4714 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4715                         i915_wedged_get, i915_wedged_set,
4716                         "%llu\n");
4717
4718 static int
4719 i915_ring_stop_get(void *data, u64 *val)
4720 {
4721         struct drm_device *dev = data;
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723
4724         *val = dev_priv->gpu_error.stop_rings;
4725
4726         return 0;
4727 }
4728
4729 static int
4730 i915_ring_stop_set(void *data, u64 val)
4731 {
4732         struct drm_device *dev = data;
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734         int ret;
4735
4736         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4737
4738         ret = mutex_lock_interruptible(&dev->struct_mutex);
4739         if (ret)
4740                 return ret;
4741
4742         dev_priv->gpu_error.stop_rings = val;
4743         mutex_unlock(&dev->struct_mutex);
4744
4745         return 0;
4746 }
4747
4748 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4749                         i915_ring_stop_get, i915_ring_stop_set,
4750                         "0x%08llx\n");
4751
4752 static int
4753 i915_ring_missed_irq_get(void *data, u64 *val)
4754 {
4755         struct drm_device *dev = data;
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757
4758         *val = dev_priv->gpu_error.missed_irq_rings;
4759         return 0;
4760 }
4761
4762 static int
4763 i915_ring_missed_irq_set(void *data, u64 val)
4764 {
4765         struct drm_device *dev = data;
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         int ret;
4768
4769         /* Lock against concurrent debugfs callers */
4770         ret = mutex_lock_interruptible(&dev->struct_mutex);
4771         if (ret)
4772                 return ret;
4773         dev_priv->gpu_error.missed_irq_rings = val;
4774         mutex_unlock(&dev->struct_mutex);
4775
4776         return 0;
4777 }
4778
4779 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4780                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4781                         "0x%08llx\n");
4782
4783 static int
4784 i915_ring_test_irq_get(void *data, u64 *val)
4785 {
4786         struct drm_device *dev = data;
4787         struct drm_i915_private *dev_priv = dev->dev_private;
4788
4789         *val = dev_priv->gpu_error.test_irq_rings;
4790
4791         return 0;
4792 }
4793
4794 static int
4795 i915_ring_test_irq_set(void *data, u64 val)
4796 {
4797         struct drm_device *dev = data;
4798         struct drm_i915_private *dev_priv = dev->dev_private;
4799         int ret;
4800
4801         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4802
4803         /* Lock against concurrent debugfs callers */
4804         ret = mutex_lock_interruptible(&dev->struct_mutex);
4805         if (ret)
4806                 return ret;
4807
4808         dev_priv->gpu_error.test_irq_rings = val;
4809         mutex_unlock(&dev->struct_mutex);
4810
4811         return 0;
4812 }
4813
4814 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4815                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4816                         "0x%08llx\n");
4817
4818 #define DROP_UNBOUND 0x1
4819 #define DROP_BOUND 0x2
4820 #define DROP_RETIRE 0x4
4821 #define DROP_ACTIVE 0x8
4822 #define DROP_ALL (DROP_UNBOUND | \
4823                   DROP_BOUND | \
4824                   DROP_RETIRE | \
4825                   DROP_ACTIVE)
4826 static int
4827 i915_drop_caches_get(void *data, u64 *val)
4828 {
4829         *val = DROP_ALL;
4830
4831         return 0;
4832 }
4833
4834 static int
4835 i915_drop_caches_set(void *data, u64 val)
4836 {
4837         struct drm_device *dev = data;
4838         struct drm_i915_private *dev_priv = dev->dev_private;
4839         int ret;
4840
4841         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4842
4843         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4844          * on ioctls on -EAGAIN. */
4845         ret = mutex_lock_interruptible(&dev->struct_mutex);
4846         if (ret)
4847                 return ret;
4848
4849         if (val & DROP_ACTIVE) {
4850                 ret = i915_gpu_idle(dev);
4851                 if (ret)
4852                         goto unlock;
4853         }
4854
4855         if (val & (DROP_RETIRE | DROP_ACTIVE))
4856                 i915_gem_retire_requests(dev);
4857
4858         if (val & DROP_BOUND)
4859                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4860
4861         if (val & DROP_UNBOUND)
4862                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4863
4864 unlock:
4865         mutex_unlock(&dev->struct_mutex);
4866
4867         return ret;
4868 }
4869
4870 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4871                         i915_drop_caches_get, i915_drop_caches_set,
4872                         "0x%08llx\n");
4873
4874 static int
4875 i915_max_freq_get(void *data, u64 *val)
4876 {
4877         struct drm_device *dev = data;
4878         struct drm_i915_private *dev_priv = dev->dev_private;
4879         int ret;
4880
4881         if (INTEL_INFO(dev)->gen < 6)
4882                 return -ENODEV;
4883
4884         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4885
4886         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4887         if (ret)
4888                 return ret;
4889
4890         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4891         mutex_unlock(&dev_priv->rps.hw_lock);
4892
4893         return 0;
4894 }
4895
4896 static int
4897 i915_max_freq_set(void *data, u64 val)
4898 {
4899         struct drm_device *dev = data;
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901         u32 hw_max, hw_min;
4902         int ret;
4903
4904         if (INTEL_INFO(dev)->gen < 6)
4905                 return -ENODEV;
4906
4907         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4908
4909         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4910
4911         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4912         if (ret)
4913                 return ret;
4914
4915         /*
4916          * Turbo will still be enabled, but won't go above the set value.
4917          */
4918         val = intel_freq_opcode(dev_priv, val);
4919
4920         hw_max = dev_priv->rps.max_freq;
4921         hw_min = dev_priv->rps.min_freq;
4922
4923         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4924                 mutex_unlock(&dev_priv->rps.hw_lock);
4925                 return -EINVAL;
4926         }
4927
4928         dev_priv->rps.max_freq_softlimit = val;
4929
4930         intel_set_rps(dev, val);
4931
4932         mutex_unlock(&dev_priv->rps.hw_lock);
4933
4934         return 0;
4935 }
4936
4937 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4938                         i915_max_freq_get, i915_max_freq_set,
4939                         "%llu\n");
4940
4941 static int
4942 i915_min_freq_get(void *data, u64 *val)
4943 {
4944         struct drm_device *dev = data;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         int ret;
4947
4948         if (INTEL_INFO(dev)->gen < 6)
4949                 return -ENODEV;
4950
4951         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4952
4953         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4954         if (ret)
4955                 return ret;
4956
4957         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4958         mutex_unlock(&dev_priv->rps.hw_lock);
4959
4960         return 0;
4961 }
4962
4963 static int
4964 i915_min_freq_set(void *data, u64 val)
4965 {
4966         struct drm_device *dev = data;
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         u32 hw_max, hw_min;
4969         int ret;
4970
4971         if (INTEL_INFO(dev)->gen < 6)
4972                 return -ENODEV;
4973
4974         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4975
4976         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4977
4978         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4979         if (ret)
4980                 return ret;
4981
4982         /*
4983          * Turbo will still be enabled, but won't go below the set value.
4984          */
4985         val = intel_freq_opcode(dev_priv, val);
4986
4987         hw_max = dev_priv->rps.max_freq;
4988         hw_min = dev_priv->rps.min_freq;
4989
4990         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4991                 mutex_unlock(&dev_priv->rps.hw_lock);
4992                 return -EINVAL;
4993         }
4994
4995         dev_priv->rps.min_freq_softlimit = val;
4996
4997         intel_set_rps(dev, val);
4998
4999         mutex_unlock(&dev_priv->rps.hw_lock);
5000
5001         return 0;
5002 }
5003
5004 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5005                         i915_min_freq_get, i915_min_freq_set,
5006                         "%llu\n");
5007
5008 static int
5009 i915_cache_sharing_get(void *data, u64 *val)
5010 {
5011         struct drm_device *dev = data;
5012         struct drm_i915_private *dev_priv = dev->dev_private;
5013         u32 snpcr;
5014         int ret;
5015
5016         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5017                 return -ENODEV;
5018
5019         ret = mutex_lock_interruptible(&dev->struct_mutex);
5020         if (ret)
5021                 return ret;
5022         intel_runtime_pm_get(dev_priv);
5023
5024         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5025
5026         intel_runtime_pm_put(dev_priv);
5027         mutex_unlock(&dev_priv->dev->struct_mutex);
5028
5029         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5030
5031         return 0;
5032 }
5033
5034 static int
5035 i915_cache_sharing_set(void *data, u64 val)
5036 {
5037         struct drm_device *dev = data;
5038         struct drm_i915_private *dev_priv = dev->dev_private;
5039         u32 snpcr;
5040
5041         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5042                 return -ENODEV;
5043
5044         if (val > 3)
5045                 return -EINVAL;
5046
5047         intel_runtime_pm_get(dev_priv);
5048         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5049
5050         /* Update the cache sharing policy here as well */
5051         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5052         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5053         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5054         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5055
5056         intel_runtime_pm_put(dev_priv);
5057         return 0;
5058 }
5059
5060 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5061                         i915_cache_sharing_get, i915_cache_sharing_set,
5062                         "%llu\n");
5063
5064 struct sseu_dev_status {
5065         unsigned int slice_total;
5066         unsigned int subslice_total;
5067         unsigned int subslice_per_slice;
5068         unsigned int eu_total;
5069         unsigned int eu_per_subslice;
5070 };
5071
5072 static void cherryview_sseu_device_status(struct drm_device *dev,
5073                                           struct sseu_dev_status *stat)
5074 {
5075         struct drm_i915_private *dev_priv = dev->dev_private;
5076         int ss_max = 2;
5077         int ss;
5078         u32 sig1[ss_max], sig2[ss_max];
5079
5080         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5081         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5082         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5083         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5084
5085         for (ss = 0; ss < ss_max; ss++) {
5086                 unsigned int eu_cnt;
5087
5088                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5089                         /* skip disabled subslice */
5090                         continue;
5091
5092                 stat->slice_total = 1;
5093                 stat->subslice_per_slice++;
5094                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5095                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5096                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5097                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5098                 stat->eu_total += eu_cnt;
5099                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5100         }
5101         stat->subslice_total = stat->subslice_per_slice;
5102 }
5103
5104 static void gen9_sseu_device_status(struct drm_device *dev,
5105                                     struct sseu_dev_status *stat)
5106 {
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108         int s_max = 3, ss_max = 4;
5109         int s, ss;
5110         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5111
5112         /* BXT has a single slice and at most 3 subslices. */
5113         if (IS_BROXTON(dev)) {
5114                 s_max = 1;
5115                 ss_max = 3;
5116         }
5117
5118         for (s = 0; s < s_max; s++) {
5119                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5120                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5121                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5122         }
5123
5124         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5125                      GEN9_PGCTL_SSA_EU19_ACK |
5126                      GEN9_PGCTL_SSA_EU210_ACK |
5127                      GEN9_PGCTL_SSA_EU311_ACK;
5128         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5129                      GEN9_PGCTL_SSB_EU19_ACK |
5130                      GEN9_PGCTL_SSB_EU210_ACK |
5131                      GEN9_PGCTL_SSB_EU311_ACK;
5132
5133         for (s = 0; s < s_max; s++) {
5134                 unsigned int ss_cnt = 0;
5135
5136                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5137                         /* skip disabled slice */
5138                         continue;
5139
5140                 stat->slice_total++;
5141
5142                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5143                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5144
5145                 for (ss = 0; ss < ss_max; ss++) {
5146                         unsigned int eu_cnt;
5147
5148                         if (IS_BROXTON(dev) &&
5149                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5150                                 /* skip disabled subslice */
5151                                 continue;
5152
5153                         if (IS_BROXTON(dev))
5154                                 ss_cnt++;
5155
5156                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5157                                                eu_mask[ss%2]);
5158                         stat->eu_total += eu_cnt;
5159                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5160                                                     eu_cnt);
5161                 }
5162
5163                 stat->subslice_total += ss_cnt;
5164                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5165                                                ss_cnt);
5166         }
5167 }
5168
5169 static void broadwell_sseu_device_status(struct drm_device *dev,
5170                                          struct sseu_dev_status *stat)
5171 {
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         int s;
5174         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5175
5176         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5177
5178         if (stat->slice_total) {
5179                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5180                 stat->subslice_total = stat->slice_total *
5181                                        stat->subslice_per_slice;
5182                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5183                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5184
5185                 /* subtract fused off EU(s) from enabled slice(s) */
5186                 for (s = 0; s < stat->slice_total; s++) {
5187                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5188
5189                         stat->eu_total -= hweight8(subslice_7eu);
5190                 }
5191         }
5192 }
5193
5194 static int i915_sseu_status(struct seq_file *m, void *unused)
5195 {
5196         struct drm_info_node *node = (struct drm_info_node *) m->private;
5197         struct drm_device *dev = node->minor->dev;
5198         struct sseu_dev_status stat;
5199
5200         if (INTEL_INFO(dev)->gen < 8)
5201                 return -ENODEV;
5202
5203         seq_puts(m, "SSEU Device Info\n");
5204         seq_printf(m, "  Available Slice Total: %u\n",
5205                    INTEL_INFO(dev)->slice_total);
5206         seq_printf(m, "  Available Subslice Total: %u\n",
5207                    INTEL_INFO(dev)->subslice_total);
5208         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5209                    INTEL_INFO(dev)->subslice_per_slice);
5210         seq_printf(m, "  Available EU Total: %u\n",
5211                    INTEL_INFO(dev)->eu_total);
5212         seq_printf(m, "  Available EU Per Subslice: %u\n",
5213                    INTEL_INFO(dev)->eu_per_subslice);
5214         seq_printf(m, "  Has Slice Power Gating: %s\n",
5215                    yesno(INTEL_INFO(dev)->has_slice_pg));
5216         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5217                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5218         seq_printf(m, "  Has EU Power Gating: %s\n",
5219                    yesno(INTEL_INFO(dev)->has_eu_pg));
5220
5221         seq_puts(m, "SSEU Device Status\n");
5222         memset(&stat, 0, sizeof(stat));
5223         if (IS_CHERRYVIEW(dev)) {
5224                 cherryview_sseu_device_status(dev, &stat);
5225         } else if (IS_BROADWELL(dev)) {
5226                 broadwell_sseu_device_status(dev, &stat);
5227         } else if (INTEL_INFO(dev)->gen >= 9) {
5228                 gen9_sseu_device_status(dev, &stat);
5229         }
5230         seq_printf(m, "  Enabled Slice Total: %u\n",
5231                    stat.slice_total);
5232         seq_printf(m, "  Enabled Subslice Total: %u\n",
5233                    stat.subslice_total);
5234         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5235                    stat.subslice_per_slice);
5236         seq_printf(m, "  Enabled EU Total: %u\n",
5237                    stat.eu_total);
5238         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5239                    stat.eu_per_subslice);
5240
5241         return 0;
5242 }
5243
5244 static int i915_forcewake_open(struct inode *inode, struct file *file)
5245 {
5246         struct drm_device *dev = inode->i_private;
5247         struct drm_i915_private *dev_priv = dev->dev_private;
5248
5249         if (INTEL_INFO(dev)->gen < 6)
5250                 return 0;
5251
5252         intel_runtime_pm_get(dev_priv);
5253         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5254
5255         return 0;
5256 }
5257
5258 static int i915_forcewake_release(struct inode *inode, struct file *file)
5259 {
5260         struct drm_device *dev = inode->i_private;
5261         struct drm_i915_private *dev_priv = dev->dev_private;
5262
5263         if (INTEL_INFO(dev)->gen < 6)
5264                 return 0;
5265
5266         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5267         intel_runtime_pm_put(dev_priv);
5268
5269         return 0;
5270 }
5271
5272 static const struct file_operations i915_forcewake_fops = {
5273         .owner = THIS_MODULE,
5274         .open = i915_forcewake_open,
5275         .release = i915_forcewake_release,
5276 };
5277
5278 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5279 {
5280         struct drm_device *dev = minor->dev;
5281         struct dentry *ent;
5282
5283         ent = debugfs_create_file("i915_forcewake_user",
5284                                   S_IRUSR,
5285                                   root, dev,
5286                                   &i915_forcewake_fops);
5287         if (!ent)
5288                 return -ENOMEM;
5289
5290         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5291 }
5292
5293 static int i915_debugfs_create(struct dentry *root,
5294                                struct drm_minor *minor,
5295                                const char *name,
5296                                const struct file_operations *fops)
5297 {
5298         struct drm_device *dev = minor->dev;
5299         struct dentry *ent;
5300
5301         ent = debugfs_create_file(name,
5302                                   S_IRUGO | S_IWUSR,
5303                                   root, dev,
5304                                   fops);
5305         if (!ent)
5306                 return -ENOMEM;
5307
5308         return drm_add_fake_info_node(minor, ent, fops);
5309 }
5310
5311 static const struct drm_info_list i915_debugfs_list[] = {
5312         {"i915_capabilities", i915_capabilities, 0},
5313         {"i915_gem_objects", i915_gem_object_info, 0},
5314         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5315         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5316         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5317         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5318         {"i915_gem_stolen", i915_gem_stolen_list_info },
5319         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5320         {"i915_gem_request", i915_gem_request_info, 0},
5321         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5322         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5323         {"i915_gem_interrupt", i915_interrupt_info, 0},
5324         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5325         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5326         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5327         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5328         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5329         {"i915_guc_info", i915_guc_info, 0},
5330         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5331         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5332         {"i915_frequency_info", i915_frequency_info, 0},
5333         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5334         {"i915_drpc_info", i915_drpc_info, 0},
5335         {"i915_emon_status", i915_emon_status, 0},
5336         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5337         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5338         {"i915_fbc_status", i915_fbc_status, 0},
5339         {"i915_ips_status", i915_ips_status, 0},
5340         {"i915_sr_status", i915_sr_status, 0},
5341         {"i915_opregion", i915_opregion, 0},
5342         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5343         {"i915_context_status", i915_context_status, 0},
5344         {"i915_dump_lrc", i915_dump_lrc, 0},
5345         {"i915_execlists", i915_execlists, 0},
5346         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5347         {"i915_swizzle_info", i915_swizzle_info, 0},
5348         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5349         {"i915_llc", i915_llc, 0},
5350         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5351         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5352         {"i915_energy_uJ", i915_energy_uJ, 0},
5353         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5354         {"i915_power_domain_info", i915_power_domain_info, 0},
5355         {"i915_display_info", i915_display_info, 0},
5356         {"i915_semaphore_status", i915_semaphore_status, 0},
5357         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5358         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5359         {"i915_wa_registers", i915_wa_registers, 0},
5360         {"i915_ddb_info", i915_ddb_info, 0},
5361         {"i915_sseu_status", i915_sseu_status, 0},
5362         {"i915_drrs_status", i915_drrs_status, 0},
5363         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5364 };
5365 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5366
5367 static const struct i915_debugfs_files {
5368         const char *name;
5369         const struct file_operations *fops;
5370 } i915_debugfs_files[] = {
5371         {"i915_wedged", &i915_wedged_fops},
5372         {"i915_max_freq", &i915_max_freq_fops},
5373         {"i915_min_freq", &i915_min_freq_fops},
5374         {"i915_cache_sharing", &i915_cache_sharing_fops},
5375         {"i915_ring_stop", &i915_ring_stop_fops},
5376         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5377         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5378         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5379         {"i915_error_state", &i915_error_state_fops},
5380         {"i915_next_seqno", &i915_next_seqno_fops},
5381         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5382         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5383         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5384         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5385         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5386         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5387         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5388         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5389 };
5390
5391 void intel_display_crc_init(struct drm_device *dev)
5392 {
5393         struct drm_i915_private *dev_priv = dev->dev_private;
5394         enum pipe pipe;
5395
5396         for_each_pipe(dev_priv, pipe) {
5397                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5398
5399                 pipe_crc->opened = false;
5400                 spin_lock_init(&pipe_crc->lock);
5401                 init_waitqueue_head(&pipe_crc->wq);
5402         }
5403 }
5404
5405 int i915_debugfs_init(struct drm_minor *minor)
5406 {
5407         int ret, i;
5408
5409         ret = i915_forcewake_create(minor->debugfs_root, minor);
5410         if (ret)
5411                 return ret;
5412
5413         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5414                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5415                 if (ret)
5416                         return ret;
5417         }
5418
5419         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5420                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5421                                           i915_debugfs_files[i].name,
5422                                           i915_debugfs_files[i].fops);
5423                 if (ret)
5424                         return ret;
5425         }
5426
5427         return drm_debugfs_create_files(i915_debugfs_list,
5428                                         I915_DEBUGFS_ENTRIES,
5429                                         minor->debugfs_root, minor);
5430 }
5431
5432 void i915_debugfs_cleanup(struct drm_minor *minor)
5433 {
5434         int i;
5435
5436         drm_debugfs_remove_files(i915_debugfs_list,
5437                                  I915_DEBUGFS_ENTRIES, minor);
5438
5439         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5440                                  1, minor);
5441
5442         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5443                 struct drm_info_list *info_list =
5444                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5445
5446                 drm_debugfs_remove_files(info_list, 1, minor);
5447         }
5448
5449         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5450                 struct drm_info_list *info_list =
5451                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5452
5453                 drm_debugfs_remove_files(info_list, 1, minor);
5454         }
5455 }
5456
5457 struct dpcd_block {
5458         /* DPCD dump start address. */
5459         unsigned int offset;
5460         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5461         unsigned int end;
5462         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5463         size_t size;
5464         /* Only valid for eDP. */
5465         bool edp;
5466 };
5467
5468 static const struct dpcd_block i915_dpcd_debug[] = {
5469         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5470         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5471         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5472         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5473         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5474         { .offset = DP_SET_POWER },
5475         { .offset = DP_EDP_DPCD_REV },
5476         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5477         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5478         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5479 };
5480
5481 static int i915_dpcd_show(struct seq_file *m, void *data)
5482 {
5483         struct drm_connector *connector = m->private;
5484         struct intel_dp *intel_dp =
5485                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5486         uint8_t buf[16];
5487         ssize_t err;
5488         int i;
5489
5490         if (connector->status != connector_status_connected)
5491                 return -ENODEV;
5492
5493         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5494                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5495                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5496
5497                 if (b->edp &&
5498                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5499                         continue;
5500
5501                 /* low tech for now */
5502                 if (WARN_ON(size > sizeof(buf)))
5503                         continue;
5504
5505                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5506                 if (err <= 0) {
5507                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5508                                   size, b->offset, err);
5509                         continue;
5510                 }
5511
5512                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5513         }
5514
5515         return 0;
5516 }
5517
5518 static int i915_dpcd_open(struct inode *inode, struct file *file)
5519 {
5520         return single_open(file, i915_dpcd_show, inode->i_private);
5521 }
5522
5523 static const struct file_operations i915_dpcd_fops = {
5524         .owner = THIS_MODULE,
5525         .open = i915_dpcd_open,
5526         .read = seq_read,
5527         .llseek = seq_lseek,
5528         .release = single_release,
5529 };
5530
5531 /**
5532  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5533  * @connector: pointer to a registered drm_connector
5534  *
5535  * Cleanup will be done by drm_connector_unregister() through a call to
5536  * drm_debugfs_connector_remove().
5537  *
5538  * Returns 0 on success, negative error codes on error.
5539  */
5540 int i915_debugfs_connector_add(struct drm_connector *connector)
5541 {
5542         struct dentry *root = connector->debugfs_entry;
5543
5544         /* The connector must have been registered beforehands. */
5545         if (!root)
5546                 return -ENODEV;
5547
5548         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5549             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5550                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5551                                     &i915_dpcd_fops);
5552
5553         return 0;
5554 }