drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/list_sort.h>
  31 #include "intel_drv.h"
  32
  33 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  34 {
  35         return to_i915(node->minor->dev);
  36 }
  37
  38 static __always_inline void seq_print_param(struct seq_file *m,
  39                                             const char *name,
  40                                             const char *type,
  41                                             const void *x)
  42 {
  43         if (!__builtin_strcmp(type, "bool"))
  44                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  45         else if (!__builtin_strcmp(type, "int"))
  46                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  47         else if (!__builtin_strcmp(type, "unsigned int"))
  48                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  49         else if (!__builtin_strcmp(type, "char *"))
  50                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  51         else
  52                 BUILD_BUG();
  53 }
  54
  55 static int i915_capabilities(struct seq_file *m, void *data)
  56 {
  57         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  58         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  59
  60         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  61         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  63
  64 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  65         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  66 #undef PRINT_FLAG
  67
  68         kernel_param_lock(THIS_MODULE);
  69 #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x);
  70         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  71 #undef PRINT_PARAM
  72         kernel_param_unlock(THIS_MODULE);
  73
  74         return 0;
  75 }
  76
  77 static char get_active_flag(struct drm_i915_gem_object *obj)
  78 {
  79         return i915_gem_object_is_active(obj) ? '*' : ' ';
  80 }
  81
  82 static char get_pin_flag(struct drm_i915_gem_object *obj)
  83 {
  84         return obj->pin_display ? 'p' : ' ';
  85 }
  86
  87 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  88 {
  89         switch (i915_gem_object_get_tiling(obj)) {
  90         default:
  91         case I915_TILING_NONE: return ' ';
  92         case I915_TILING_X: return 'X';
  93         case I915_TILING_Y: return 'Y';
  94         }
  95 }
  96
  97 static char get_global_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 100 }
 101
 102 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 103 {
 104         return obj->mm.mapping ? 'M' : ' ';
 105 }
 106
 107 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 108 {
 109         u64 size = 0;
 110         struct i915_vma *vma;
 111
 112         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 113                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 114                         size += vma->node.size;
 115         }
 116
 117         return size;
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 124         struct intel_engine_cs *engine;
 125         struct i915_vma *vma;
 126         unsigned int frontbuffer_bits;
 127         int pin_count = 0;
 128
 129         lockdep_assert_held(&obj->base.dev->struct_mutex);
 130
 131         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 132                    &obj->base,
 133                    get_active_flag(obj),
 134                    get_pin_flag(obj),
 135                    get_tiling_flag(obj),
 136                    get_global_flag(obj),
 137                    get_pin_mapped_flag(obj),
 138                    obj->base.size / 1024,
 139                    obj->base.read_domains,
 140                    obj->base.write_domain,
 141                    i915_cache_level_str(dev_priv, obj->cache_level),
 142                    obj->mm.dirty ? " dirty" : "",
 143                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 144         if (obj->base.name)
 145                 seq_printf(m, " (name: %d)", obj->base.name);
 146         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 147                 if (i915_vma_is_pinned(vma))
 148                         pin_count++;
 149         }
 150         seq_printf(m, " (pinned x %d)", pin_count);
 151         if (obj->pin_display)
 152                 seq_printf(m, " (display)");
 153         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 154                 if (!drm_mm_node_allocated(&vma->node))
 155                         continue;
 156
 157                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 158                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 159                            vma->node.start, vma->node.size);
 160                 if (i915_vma_is_ggtt(vma)) {
 161                         switch (vma->ggtt_view.type) {
 162                         case I915_GGTT_VIEW_NORMAL:
 163                                 seq_puts(m, ", normal");
 164                                 break;
 165
 166                         case I915_GGTT_VIEW_PARTIAL:
 167                                 seq_printf(m, ", partial [%08llx+%x]",
 168                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 169                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 170                                 break;
 171
 172                         case I915_GGTT_VIEW_ROTATED:
 173                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 174                                            vma->ggtt_view.rotated.plane[0].width,
 175                                            vma->ggtt_view.rotated.plane[0].height,
 176                                            vma->ggtt_view.rotated.plane[0].stride,
 177                                            vma->ggtt_view.rotated.plane[0].offset,
 178                                            vma->ggtt_view.rotated.plane[1].width,
 179                                            vma->ggtt_view.rotated.plane[1].height,
 180                                            vma->ggtt_view.rotated.plane[1].stride,
 181                                            vma->ggtt_view.rotated.plane[1].offset);
 182                                 break;
 183
 184                         default:
 185                                 MISSING_CASE(vma->ggtt_view.type);
 186                                 break;
 187                         }
 188                 }
 189                 if (vma->fence)
 190                         seq_printf(m, " , fence: %d%s",
 191                                    vma->fence->id,
 192                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 193                 seq_puts(m, ")");
 194         }
 195         if (obj->stolen)
 196                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 197
 198         engine = i915_gem_object_last_write_engine(obj);
 199         if (engine)
 200                 seq_printf(m, " (%s)", engine->name);
 201
 202         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 203         if (frontbuffer_bits)
 204                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 205 }
 206
 207 static int obj_rank_by_stolen(void *priv,
 208                               struct list_head *A, struct list_head *B)
 209 {
 210         struct drm_i915_gem_object *a =
 211                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 212         struct drm_i915_gem_object *b =
 213                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 214
 215         if (a->stolen->start < b->stolen->start)
 216                 return -1;
 217         if (a->stolen->start > b->stolen->start)
 218                 return 1;
 219         return 0;
 220 }
 221
 222 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 223 {
 224         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 225         struct drm_device *dev = &dev_priv->drm;
 226         struct drm_i915_gem_object *obj;
 227         u64 total_obj_size, total_gtt_size;
 228         LIST_HEAD(stolen);
 229         int count, ret;
 230
 231         ret = mutex_lock_interruptible(&dev->struct_mutex);
 232         if (ret)
 233                 return ret;
 234
 235         total_obj_size = total_gtt_size = count = 0;
 236         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 237                 if (obj->stolen == NULL)
 238                         continue;
 239
 240                 list_add(&obj->obj_exec_link, &stolen);
 241
 242                 total_obj_size += obj->base.size;
 243                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 244                 count++;
 245         }
 246         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 247                 if (obj->stolen == NULL)
 248                         continue;
 249
 250                 list_add(&obj->obj_exec_link, &stolen);
 251
 252                 total_obj_size += obj->base.size;
 253                 count++;
 254         }
 255         list_sort(NULL, &stolen, obj_rank_by_stolen);
 256         seq_puts(m, "Stolen:\n");
 257         while (!list_empty(&stolen)) {
 258                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 259                 seq_puts(m, "   ");
 260                 describe_obj(m, obj);
 261                 seq_putc(m, '\n');
 262                 list_del_init(&obj->obj_exec_link);
 263         }
 264         mutex_unlock(&dev->struct_mutex);
 265
 266         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 267                    count, total_obj_size, total_gtt_size);
 268         return 0;
 269 }
 270
 271 struct file_stats {
 272         struct drm_i915_file_private *file_priv;
 273         unsigned long count;
 274         u64 total, unbound;
 275         u64 global, shared;
 276         u64 active, inactive;
 277 };
 278
 279 static int per_file_stats(int id, void *ptr, void *data)
 280 {
 281         struct drm_i915_gem_object *obj = ptr;
 282         struct file_stats *stats = data;
 283         struct i915_vma *vma;
 284
 285         stats->count++;
 286         stats->total += obj->base.size;
 287         if (!obj->bind_count)
 288                 stats->unbound += obj->base.size;
 289         if (obj->base.name || obj->base.dma_buf)
 290                 stats->shared += obj->base.size;
 291
 292         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 293                 if (!drm_mm_node_allocated(&vma->node))
 294                         continue;
 295
 296                 if (i915_vma_is_ggtt(vma)) {
 297                         stats->global += vma->node.size;
 298                 } else {
 299                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 300
 301                         if (ppgtt->base.file != stats->file_priv)
 302                                 continue;
 303                 }
 304
 305                 if (i915_vma_is_active(vma))
 306                         stats->active += vma->node.size;
 307                 else
 308                         stats->inactive += vma->node.size;
 309         }
 310
 311         return 0;
 312 }
 313
 314 #define print_file_stats(m, name, stats) do { \
 315         if (stats.count) \
 316                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 317                            name, \
 318                            stats.count, \
 319                            stats.total, \
 320                            stats.active, \
 321                            stats.inactive, \
 322                            stats.global, \
 323                            stats.shared, \
 324                            stats.unbound); \
 325 } while (0)
 326
 327 static void print_batch_pool_stats(struct seq_file *m,
 328                                    struct drm_i915_private *dev_priv)
 329 {
 330         struct drm_i915_gem_object *obj;
 331         struct file_stats stats;
 332         struct intel_engine_cs *engine;
 333         enum intel_engine_id id;
 334         int j;
 335
 336         memset(&stats, 0, sizeof(stats));
 337
 338         for_each_engine(engine, dev_priv, id) {
 339                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 340                         list_for_each_entry(obj,
 341                                             &engine->batch_pool.cache_list[j],
 342                                             batch_pool_link)
 343                                 per_file_stats(0, obj, &stats);
 344                 }
 345         }
 346
 347         print_file_stats(m, "[k]batch pool", stats);
 348 }
 349
 350 static int per_file_ctx_stats(int id, void *ptr, void *data)
 351 {
 352         struct i915_gem_context *ctx = ptr;
 353         int n;
 354
 355         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 356                 if (ctx->engine[n].state)
 357                         per_file_stats(0, ctx->engine[n].state->obj, data);
 358                 if (ctx->engine[n].ring)
 359                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 360         }
 361
 362         return 0;
 363 }
 364
 365 static void print_context_stats(struct seq_file *m,
 366                                 struct drm_i915_private *dev_priv)
 367 {
 368         struct drm_device *dev = &dev_priv->drm;
 369         struct file_stats stats;
 370         struct drm_file *file;
 371
 372         memset(&stats, 0, sizeof(stats));
 373
 374         mutex_lock(&dev->struct_mutex);
 375         if (dev_priv->kernel_context)
 376                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 377
 378         list_for_each_entry(file, &dev->filelist, lhead) {
 379                 struct drm_i915_file_private *fpriv = file->driver_priv;
 380                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 381         }
 382         mutex_unlock(&dev->struct_mutex);
 383
 384         print_file_stats(m, "[k]contexts", stats);
 385 }
 386
 387 static int i915_gem_object_info(struct seq_file *m, void *data)
 388 {
 389         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 390         struct drm_device *dev = &dev_priv->drm;
 391         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 392         u32 count, mapped_count, purgeable_count, dpy_count;
 393         u64 size, mapped_size, purgeable_size, dpy_size;
 394         struct drm_i915_gem_object *obj;
 395         struct drm_file *file;
 396         int ret;
 397
 398         ret = mutex_lock_interruptible(&dev->struct_mutex);
 399         if (ret)
 400                 return ret;
 401
 402         seq_printf(m, "%u objects, %llu bytes\n",
 403                    dev_priv->mm.object_count,
 404                    dev_priv->mm.object_memory);
 405
 406         size = count = 0;
 407         mapped_size = mapped_count = 0;
 408         purgeable_size = purgeable_count = 0;
 409         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 410                 size += obj->base.size;
 411                 ++count;
 412
 413                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 414                         purgeable_size += obj->base.size;
 415                         ++purgeable_count;
 416                 }
 417
 418                 if (obj->mm.mapping) {
 419                         mapped_count++;
 420                         mapped_size += obj->base.size;
 421                 }
 422         }
 423         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 424
 425         size = count = dpy_size = dpy_count = 0;
 426         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 427                 size += obj->base.size;
 428                 ++count;
 429
 430                 if (obj->pin_display) {
 431                         dpy_size += obj->base.size;
 432                         ++dpy_count;
 433                 }
 434
 435                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 436                         purgeable_size += obj->base.size;
 437                         ++purgeable_count;
 438                 }
 439
 440                 if (obj->mm.mapping) {
 441                         mapped_count++;
 442                         mapped_size += obj->base.size;
 443                 }
 444         }
 445         seq_printf(m, "%u bound objects, %llu bytes\n",
 446                    count, size);
 447         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 448                    purgeable_count, purgeable_size);
 449         seq_printf(m, "%u mapped objects, %llu bytes\n",
 450                    mapped_count, mapped_size);
 451         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 452                    dpy_count, dpy_size);
 453
 454         seq_printf(m, "%llu [%llu] gtt total\n",
 455                    ggtt->base.total, ggtt->mappable_end);
 456
 457         seq_putc(m, '\n');
 458         print_batch_pool_stats(m, dev_priv);
 459         mutex_unlock(&dev->struct_mutex);
 460
 461         mutex_lock(&dev->filelist_mutex);
 462         print_context_stats(m, dev_priv);
 463         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 464                 struct file_stats stats;
 465                 struct drm_i915_file_private *file_priv = file->driver_priv;
 466                 struct drm_i915_gem_request *request;
 467                 struct task_struct *task;
 468
 469                 memset(&stats, 0, sizeof(stats));
 470                 stats.file_priv = file->driver_priv;
 471                 spin_lock(&file->table_lock);
 472                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 473                 spin_unlock(&file->table_lock);
 474                 /*
 475                  * Although we have a valid reference on file->pid, that does
 476                  * not guarantee that the task_struct who called get_pid() is
 477                  * still alive (e.g. get_pid(current) => fork() => exit()).
 478                  * Therefore, we need to protect this ->comm access using RCU.
 479                  */
 480                 mutex_lock(&dev->struct_mutex);
 481                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 482                                                    struct drm_i915_gem_request,
 483                                                    client_link);
 484                 rcu_read_lock();
 485                 task = pid_task(request && request->ctx->pid ?
 486                                 request->ctx->pid : file->pid,
 487                                 PIDTYPE_PID);
 488                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 489                 rcu_read_unlock();
 490                 mutex_unlock(&dev->struct_mutex);
 491         }
 492         mutex_unlock(&dev->filelist_mutex);
 493
 494         return 0;
 495 }
 496
 497 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 498 {
 499         struct drm_info_node *node = m->private;
 500         struct drm_i915_private *dev_priv = node_to_i915(node);
 501         struct drm_device *dev = &dev_priv->drm;
 502         bool show_pin_display_only = !!node->info_ent->data;
 503         struct drm_i915_gem_object *obj;
 504         u64 total_obj_size, total_gtt_size;
 505         int count, ret;
 506
 507         ret = mutex_lock_interruptible(&dev->struct_mutex);
 508         if (ret)
 509                 return ret;
 510
 511         total_obj_size = total_gtt_size = count = 0;
 512         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 513                 if (show_pin_display_only && !obj->pin_display)
 514                         continue;
 515
 516                 seq_puts(m, "   ");
 517                 describe_obj(m, obj);
 518                 seq_putc(m, '\n');
 519                 total_obj_size += obj->base.size;
 520                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 521                 count++;
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 527                    count, total_obj_size, total_gtt_size);
 528
 529         return 0;
 530 }
 531
 532 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 533 {
 534         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 535         struct drm_device *dev = &dev_priv->drm;
 536         struct intel_crtc *crtc;
 537         int ret;
 538
 539         ret = mutex_lock_interruptible(&dev->struct_mutex);
 540         if (ret)
 541                 return ret;
 542
 543         for_each_intel_crtc(dev, crtc) {
 544                 const char pipe = pipe_name(crtc->pipe);
 545                 const char plane = plane_name(crtc->plane);
 546                 struct intel_flip_work *work;
 547
 548                 spin_lock_irq(&dev->event_lock);
 549                 work = crtc->flip_work;
 550                 if (work == NULL) {
 551                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 552                                    pipe, plane);
 553                 } else {
 554                         u32 pending;
 555                         u32 addr;
 556
 557                         pending = atomic_read(&work->pending);
 558                         if (pending) {
 559                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 560                                            pipe, plane);
 561                         } else {
 562                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         }
 565                         if (work->flip_queued_req) {
 566                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 567
 568                                 seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n",
 569                                            engine->name,
 570                                            work->flip_queued_req->global_seqno,
 571                                            intel_engine_last_submit(engine),
 572                                            intel_engine_get_seqno(engine),
 573                                            i915_gem_request_completed(work->flip_queued_req));
 574                         } else
 575                                 seq_printf(m, "Flip not associated with any ring\n");
 576                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 577                                    work->flip_queued_vblank,
 578                                    work->flip_ready_vblank,
 579                                    intel_crtc_get_vblank_counter(crtc));
 580                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 581
 582                         if (INTEL_GEN(dev_priv) >= 4)
 583                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 584                         else
 585                                 addr = I915_READ(DSPADDR(crtc->plane));
 586                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 587
 588                         if (work->pending_flip_obj) {
 589                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 590                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 591                         }
 592                 }
 593                 spin_unlock_irq(&dev->event_lock);
 594         }
 595
 596         mutex_unlock(&dev->struct_mutex);
 597
 598         return 0;
 599 }
 600
 601 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 602 {
 603         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 604         struct drm_device *dev = &dev_priv->drm;
 605         struct drm_i915_gem_object *obj;
 606         struct intel_engine_cs *engine;
 607         enum intel_engine_id id;
 608         int total = 0;
 609         int ret, j;
 610
 611         ret = mutex_lock_interruptible(&dev->struct_mutex);
 612         if (ret)
 613                 return ret;
 614
 615         for_each_engine(engine, dev_priv, id) {
 616                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 617                         int count;
 618
 619                         count = 0;
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link)
 623                                 count++;
 624                         seq_printf(m, "%s cache[%d]: %d objects\n",
 625                                    engine->name, j, count);
 626
 627                         list_for_each_entry(obj,
 628                                             &engine->batch_pool.cache_list[j],
 629                                             batch_pool_link) {
 630                                 seq_puts(m, "   ");
 631                                 describe_obj(m, obj);
 632                                 seq_putc(m, '\n');
 633                         }
 634
 635                         total += count;
 636                 }
 637         }
 638
 639         seq_printf(m, "total: %d\n", total);
 640
 641         mutex_unlock(&dev->struct_mutex);
 642
 643         return 0;
 644 }
 645
 646 static void print_request(struct seq_file *m,
 647                           struct drm_i915_gem_request *rq,
 648                           const char *prefix)
 649 {
 650         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 651                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 652                    rq->priotree.priority,
 653                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 654                    rq->timeline->common->name);
 655 }
 656
 657 static int i915_gem_request_info(struct seq_file *m, void *data)
 658 {
 659         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 660         struct drm_device *dev = &dev_priv->drm;
 661         struct drm_i915_gem_request *req;
 662         struct intel_engine_cs *engine;
 663         enum intel_engine_id id;
 664         int ret, any;
 665
 666         ret = mutex_lock_interruptible(&dev->struct_mutex);
 667         if (ret)
 668                 return ret;
 669
 670         any = 0;
 671         for_each_engine(engine, dev_priv, id) {
 672                 int count;
 673
 674                 count = 0;
 675                 list_for_each_entry(req, &engine->timeline->requests, link)
 676                         count++;
 677                 if (count == 0)
 678                         continue;
 679
 680                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 681                 list_for_each_entry(req, &engine->timeline->requests, link)
 682                         print_request(m, req, "    ");
 683
 684                 any++;
 685         }
 686         mutex_unlock(&dev->struct_mutex);
 687
 688         if (any == 0)
 689                 seq_puts(m, "No requests\n");
 690
 691         return 0;
 692 }
 693
 694 static void i915_ring_seqno_info(struct seq_file *m,
 695                                  struct intel_engine_cs *engine)
 696 {
 697         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 698         struct rb_node *rb;
 699
 700         seq_printf(m, "Current sequence (%s): %x\n",
 701                    engine->name, intel_engine_get_seqno(engine));
 702
 703         spin_lock_irq(&b->rb_lock);
 704         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 705                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 706
 707                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 708                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 709         }
 710         spin_unlock_irq(&b->rb_lock);
 711 }
 712
 713 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 714 {
 715         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 716         struct intel_engine_cs *engine;
 717         enum intel_engine_id id;
 718
 719         for_each_engine(engine, dev_priv, id)
 720                 i915_ring_seqno_info(m, engine);
 721
 722         return 0;
 723 }
 724
 725
 726 static int i915_interrupt_info(struct seq_file *m, void *data)
 727 {
 728         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 729         struct intel_engine_cs *engine;
 730         enum intel_engine_id id;
 731         int i, pipe;
 732
 733         intel_runtime_pm_get(dev_priv);
 734
 735         if (IS_CHERRYVIEW(dev_priv)) {
 736                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 737                            I915_READ(GEN8_MASTER_IRQ));
 738
 739                 seq_printf(m, "Display IER:\t%08x\n",
 740                            I915_READ(VLV_IER));
 741                 seq_printf(m, "Display IIR:\t%08x\n",
 742                            I915_READ(VLV_IIR));
 743                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 744                            I915_READ(VLV_IIR_RW));
 745                 seq_printf(m, "Display IMR:\t%08x\n",
 746                            I915_READ(VLV_IMR));
 747                 for_each_pipe(dev_priv, pipe) {
 748                         enum intel_display_power_domain power_domain;
 749
 750                         power_domain = POWER_DOMAIN_PIPE(pipe);
 751                         if (!intel_display_power_get_if_enabled(dev_priv,
 752                                                                 power_domain)) {
 753                                 seq_printf(m, "Pipe %c power disabled\n",
 754                                            pipe_name(pipe));
 755                                 continue;
 756                         }
 757
 758                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 759                                    pipe_name(pipe),
 760                                    I915_READ(PIPESTAT(pipe)));
 761
 762                         intel_display_power_put(dev_priv, power_domain);
 763                 }
 764
 765                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 766                 seq_printf(m, "Port hotplug:\t%08x\n",
 767                            I915_READ(PORT_HOTPLUG_EN));
 768                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 769                            I915_READ(VLV_DPFLIPSTAT));
 770                 seq_printf(m, "DPINVGTT:\t%08x\n",
 771                            I915_READ(DPINVGTT));
 772                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 773
 774                 for (i = 0; i < 4; i++) {
 775                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 776                                    i, I915_READ(GEN8_GT_IMR(i)));
 777                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 778                                    i, I915_READ(GEN8_GT_IIR(i)));
 779                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 780                                    i, I915_READ(GEN8_GT_IER(i)));
 781                 }
 782
 783                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 784                            I915_READ(GEN8_PCU_IMR));
 785                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 786                            I915_READ(GEN8_PCU_IIR));
 787                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 788                            I915_READ(GEN8_PCU_IER));
 789         } else if (INTEL_GEN(dev_priv) >= 8) {
 790                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 791                            I915_READ(GEN8_MASTER_IRQ));
 792
 793                 for (i = 0; i < 4; i++) {
 794                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 795                                    i, I915_READ(GEN8_GT_IMR(i)));
 796                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IIR(i)));
 798                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IER(i)));
 800                 }
 801
 802                 for_each_pipe(dev_priv, pipe) {
 803                         enum intel_display_power_domain power_domain;
 804
 805                         power_domain = POWER_DOMAIN_PIPE(pipe);
 806                         if (!intel_display_power_get_if_enabled(dev_priv,
 807                                                                 power_domain)) {
 808                                 seq_printf(m, "Pipe %c power disabled\n",
 809                                            pipe_name(pipe));
 810                                 continue;
 811                         }
 812                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 813                                    pipe_name(pipe),
 814                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 815                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 816                                    pipe_name(pipe),
 817                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 818                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 819                                    pipe_name(pipe),
 820                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 821
 822                         intel_display_power_put(dev_priv, power_domain);
 823                 }
 824
 825                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 826                            I915_READ(GEN8_DE_PORT_IMR));
 827                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 828                            I915_READ(GEN8_DE_PORT_IIR));
 829                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 830                            I915_READ(GEN8_DE_PORT_IER));
 831
 832                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 833                            I915_READ(GEN8_DE_MISC_IMR));
 834                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 835                            I915_READ(GEN8_DE_MISC_IIR));
 836                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 837                            I915_READ(GEN8_DE_MISC_IER));
 838
 839                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 840                            I915_READ(GEN8_PCU_IMR));
 841                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 842                            I915_READ(GEN8_PCU_IIR));
 843                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 844                            I915_READ(GEN8_PCU_IER));
 845         } else if (IS_VALLEYVIEW(dev_priv)) {
 846                 seq_printf(m, "Display IER:\t%08x\n",
 847                            I915_READ(VLV_IER));
 848                 seq_printf(m, "Display IIR:\t%08x\n",
 849                            I915_READ(VLV_IIR));
 850                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 851                            I915_READ(VLV_IIR_RW));
 852                 seq_printf(m, "Display IMR:\t%08x\n",
 853                            I915_READ(VLV_IMR));
 854                 for_each_pipe(dev_priv, pipe) {
 855                         enum intel_display_power_domain power_domain;
 856
 857                         power_domain = POWER_DOMAIN_PIPE(pipe);
 858                         if (!intel_display_power_get_if_enabled(dev_priv,
 859                                                                 power_domain)) {
 860                                 seq_printf(m, "Pipe %c power disabled\n",
 861                                            pipe_name(pipe));
 862                                 continue;
 863                         }
 864
 865                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 866                                    pipe_name(pipe),
 867                                    I915_READ(PIPESTAT(pipe)));
 868                         intel_display_power_put(dev_priv, power_domain);
 869                 }
 870
 871                 seq_printf(m, "Master IER:\t%08x\n",
 872                            I915_READ(VLV_MASTER_IER));
 873
 874                 seq_printf(m, "Render IER:\t%08x\n",
 875                            I915_READ(GTIER));
 876                 seq_printf(m, "Render IIR:\t%08x\n",
 877                            I915_READ(GTIIR));
 878                 seq_printf(m, "Render IMR:\t%08x\n",
 879                            I915_READ(GTIMR));
 880
 881                 seq_printf(m, "PM IER:\t\t%08x\n",
 882                            I915_READ(GEN6_PMIER));
 883                 seq_printf(m, "PM IIR:\t\t%08x\n",
 884                            I915_READ(GEN6_PMIIR));
 885                 seq_printf(m, "PM IMR:\t\t%08x\n",
 886                            I915_READ(GEN6_PMIMR));
 887
 888                 seq_printf(m, "Port hotplug:\t%08x\n",
 889                            I915_READ(PORT_HOTPLUG_EN));
 890                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 891                            I915_READ(VLV_DPFLIPSTAT));
 892                 seq_printf(m, "DPINVGTT:\t%08x\n",
 893                            I915_READ(DPINVGTT));
 894
 895         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 896                 seq_printf(m, "Interrupt enable:    %08x\n",
 897                            I915_READ(IER));
 898                 seq_printf(m, "Interrupt identity:  %08x\n",
 899                            I915_READ(IIR));
 900                 seq_printf(m, "Interrupt mask:      %08x\n",
 901                            I915_READ(IMR));
 902                 for_each_pipe(dev_priv, pipe)
 903                         seq_printf(m, "Pipe %c stat:         %08x\n",
 904                                    pipe_name(pipe),
 905                                    I915_READ(PIPESTAT(pipe)));
 906         } else {
 907                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 908                            I915_READ(DEIER));
 909                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 910                            I915_READ(DEIIR));
 911                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 912                            I915_READ(DEIMR));
 913                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 914                            I915_READ(SDEIER));
 915                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 916                            I915_READ(SDEIIR));
 917                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 918                            I915_READ(SDEIMR));
 919                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 920                            I915_READ(GTIER));
 921                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 922                            I915_READ(GTIIR));
 923                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 924                            I915_READ(GTIMR));
 925         }
 926         for_each_engine(engine, dev_priv, id) {
 927                 if (INTEL_GEN(dev_priv) >= 6) {
 928                         seq_printf(m,
 929                                    "Graphics Interrupt mask (%s):       %08x\n",
 930                                    engine->name, I915_READ_IMR(engine));
 931                 }
 932                 i915_ring_seqno_info(m, engine);
 933         }
 934         intel_runtime_pm_put(dev_priv);
 935
 936         return 0;
 937 }
 938
 939 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 940 {
 941         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 942         struct drm_device *dev = &dev_priv->drm;
 943         int i, ret;
 944
 945         ret = mutex_lock_interruptible(&dev->struct_mutex);
 946         if (ret)
 947                 return ret;
 948
 949         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 950         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 951                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 952
 953                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 954                            i, dev_priv->fence_regs[i].pin_count);
 955                 if (!vma)
 956                         seq_puts(m, "unused");
 957                 else
 958                         describe_obj(m, vma->obj);
 959                 seq_putc(m, '\n');
 960         }
 961
 962         mutex_unlock(&dev->struct_mutex);
 963         return 0;
 964 }
 965
 966 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 967 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 968                               size_t count, loff_t *pos)
 969 {
 970         struct i915_gpu_state *error = file->private_data;
 971         struct drm_i915_error_state_buf str;
 972         ssize_t ret;
 973         loff_t tmp;
 974
 975         if (!error)
 976                 return 0;
 977
 978         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 979         if (ret)
 980                 return ret;
 981
 982         ret = i915_error_state_to_str(&str, error);
 983         if (ret)
 984                 goto out;
 985
 986         tmp = 0;
 987         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 988         if (ret < 0)
 989                 goto out;
 990
 991         *pos = str.start + ret;
 992 out:
 993         i915_error_state_buf_release(&str);
 994         return ret;
 995 }
 996
 997 static int gpu_state_release(struct inode *inode, struct file *file)
 998 {
 999         i915_gpu_state_put(file->private_data);
1000         return 0;
1001 }
1002
1003 static int i915_gpu_info_open(struct inode *inode, struct file *file)
1004 {
1005         struct i915_gpu_state *gpu;
1006
1007         gpu = i915_capture_gpu_state(inode->i_private);
1008         if (!gpu)
1009                 return -ENOMEM;
1010
1011         file->private_data = gpu;
1012         return 0;
1013 }
1014
1015 static const struct file_operations i915_gpu_info_fops = {
1016         .owner = THIS_MODULE,
1017         .open = i915_gpu_info_open,
1018         .read = gpu_state_read,
1019         .llseek = default_llseek,
1020         .release = gpu_state_release,
1021 };
1022
1023 static ssize_t
1024 i915_error_state_write(struct file *filp,
1025                        const char __user *ubuf,
1026                        size_t cnt,
1027                        loff_t *ppos)
1028 {
1029         struct i915_gpu_state *error = filp->private_data;
1030
1031         if (!error)
1032                 return 0;
1033
1034         DRM_DEBUG_DRIVER("Resetting error state\n");
1035         i915_reset_error_state(error->i915);
1036
1037         return cnt;
1038 }
1039
1040 static int i915_error_state_open(struct inode *inode, struct file *file)
1041 {
1042         file->private_data = i915_first_error_state(inode->i_private);
1043         return 0;
1044 }
1045
1046 static const struct file_operations i915_error_state_fops = {
1047         .owner = THIS_MODULE,
1048         .open = i915_error_state_open,
1049         .read = gpu_state_read,
1050         .write = i915_error_state_write,
1051         .llseek = default_llseek,
1052         .release = gpu_state_release,
1053 };
1054 #endif
1055
1056 static int
1057 i915_next_seqno_set(void *data, u64 val)
1058 {
1059         struct drm_i915_private *dev_priv = data;
1060         struct drm_device *dev = &dev_priv->drm;
1061         int ret;
1062
1063         ret = mutex_lock_interruptible(&dev->struct_mutex);
1064         if (ret)
1065                 return ret;
1066
1067         ret = i915_gem_set_global_seqno(dev, val);
1068         mutex_unlock(&dev->struct_mutex);
1069
1070         return ret;
1071 }
1072
1073 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1074                         NULL, i915_next_seqno_set,
1075                         "0x%llx\n");
1076
1077 static int i915_frequency_info(struct seq_file *m, void *unused)
1078 {
1079         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1080         int ret = 0;
1081
1082         intel_runtime_pm_get(dev_priv);
1083
1084         if (IS_GEN5(dev_priv)) {
1085                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1086                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1087
1088                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1089                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1090                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1091                            MEMSTAT_VID_SHIFT);
1092                 seq_printf(m, "Current P-state: %d\n",
1093                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1094         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1095                 u32 freq_sts;
1096
1097                 mutex_lock(&dev_priv->rps.hw_lock);
1098                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1099                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1100                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1101
1102                 seq_printf(m, "actual GPU freq: %d MHz\n",
1103                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1104
1105                 seq_printf(m, "current GPU freq: %d MHz\n",
1106                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1107
1108                 seq_printf(m, "max GPU freq: %d MHz\n",
1109                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1110
1111                 seq_printf(m, "min GPU freq: %d MHz\n",
1112                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1113
1114                 seq_printf(m, "idle GPU freq: %d MHz\n",
1115                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1116
1117                 seq_printf(m,
1118                            "efficient (RPe) frequency: %d MHz\n",
1119                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1120                 mutex_unlock(&dev_priv->rps.hw_lock);
1121         } else if (INTEL_GEN(dev_priv) >= 6) {
1122                 u32 rp_state_limits;
1123                 u32 gt_perf_status;
1124                 u32 rp_state_cap;
1125                 u32 rpmodectl, rpinclimit, rpdeclimit;
1126                 u32 rpstat, cagf, reqf;
1127                 u32 rpupei, rpcurup, rpprevup;
1128                 u32 rpdownei, rpcurdown, rpprevdown;
1129                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1130                 int max_freq;
1131
1132                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1133                 if (IS_GEN9_LP(dev_priv)) {
1134                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1135                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1136                 } else {
1137                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1138                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1139                 }
1140
1141                 /* RPSTAT1 is in the GT power well */
1142                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1143
1144                 reqf = I915_READ(GEN6_RPNSWREQ);
1145                 if (IS_GEN9(dev_priv))
1146                         reqf >>= 23;
1147                 else {
1148                         reqf &= ~GEN6_TURBO_DISABLE;
1149                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1150                                 reqf >>= 24;
1151                         else
1152                                 reqf >>= 25;
1153                 }
1154                 reqf = intel_gpu_freq(dev_priv, reqf);
1155
1156                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1157                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1158                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1159
1160                 rpstat = I915_READ(GEN6_RPSTAT1);
1161                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1162                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1163                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1164                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1165                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1166                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1167                 if (IS_GEN9(dev_priv))
1168                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1169                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1170                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1171                 else
1172                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1173                 cagf = intel_gpu_freq(dev_priv, cagf);
1174
1175                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1176
1177                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1178                         pm_ier = I915_READ(GEN6_PMIER);
1179                         pm_imr = I915_READ(GEN6_PMIMR);
1180                         pm_isr = I915_READ(GEN6_PMISR);
1181                         pm_iir = I915_READ(GEN6_PMIIR);
1182                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1183                 } else {
1184                         pm_ier = I915_READ(GEN8_GT_IER(2));
1185                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1186                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1187                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1188                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1189                 }
1190                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1191                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1192                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1193                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1194                 seq_printf(m, "Render p-state ratio: %d\n",
1195                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1196                 seq_printf(m, "Render p-state VID: %d\n",
1197                            gt_perf_status & 0xff);
1198                 seq_printf(m, "Render p-state limit: %d\n",
1199                            rp_state_limits & 0xff);
1200                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1201                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1202                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1203                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1204                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1205                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1206                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1207                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1208                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1209                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1210                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1211                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1212                 seq_printf(m, "Up threshold: %d%%\n",
1213                            dev_priv->rps.up_threshold);
1214
1215                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1216                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1217                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1218                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1219                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1220                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1221                 seq_printf(m, "Down threshold: %d%%\n",
1222                            dev_priv->rps.down_threshold);
1223
1224                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1225                             rp_state_cap >> 16) & 0xff;
1226                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1227                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1228                            intel_gpu_freq(dev_priv, max_freq));
1229
1230                 max_freq = (rp_state_cap & 0xff00) >> 8;
1231                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1232                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1233                            intel_gpu_freq(dev_priv, max_freq));
1234
1235                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1236                             rp_state_cap >> 0) & 0xff;
1237                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1238                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1239                            intel_gpu_freq(dev_priv, max_freq));
1240                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1241                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1242
1243                 seq_printf(m, "Current freq: %d MHz\n",
1244                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1245                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1246                 seq_printf(m, "Idle freq: %d MHz\n",
1247                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1248                 seq_printf(m, "Min freq: %d MHz\n",
1249                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1250                 seq_printf(m, "Boost freq: %d MHz\n",
1251                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1252                 seq_printf(m, "Max freq: %d MHz\n",
1253                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1254                 seq_printf(m,
1255                            "efficient (RPe) frequency: %d MHz\n",
1256                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1257         } else {
1258                 seq_puts(m, "no P-state info available\n");
1259         }
1260
1261         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1262         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1263         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1264
1265         intel_runtime_pm_put(dev_priv);
1266         return ret;
1267 }
1268
1269 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1270                                struct seq_file *m,
1271                                struct intel_instdone *instdone)
1272 {
1273         int slice;
1274         int subslice;
1275
1276         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1277                    instdone->instdone);
1278
1279         if (INTEL_GEN(dev_priv) <= 3)
1280                 return;
1281
1282         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1283                    instdone->slice_common);
1284
1285         if (INTEL_GEN(dev_priv) <= 6)
1286                 return;
1287
1288         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1289                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1290                            slice, subslice, instdone->sampler[slice][subslice]);
1291
1292         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1293                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1294                            slice, subslice, instdone->row[slice][subslice]);
1295 }
1296
1297 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298 {
1299         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1300         struct intel_engine_cs *engine;
1301         u64 acthd[I915_NUM_ENGINES];
1302         u32 seqno[I915_NUM_ENGINES];
1303         struct intel_instdone instdone;
1304         enum intel_engine_id id;
1305
1306         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1307                 seq_printf(m, "Wedged\n");
1308         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1309                 seq_printf(m, "Reset in progress\n");
1310         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1311                 seq_printf(m, "Waiter holding struct mutex\n");
1312         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1313                 seq_printf(m, "struct_mutex blocked for reset\n");
1314
1315         if (!i915.enable_hangcheck) {
1316                 seq_printf(m, "Hangcheck disabled\n");
1317                 return 0;
1318         }
1319
1320         intel_runtime_pm_get(dev_priv);
1321
1322         for_each_engine(engine, dev_priv, id) {
1323                 acthd[id] = intel_engine_get_active_head(engine);
1324                 seqno[id] = intel_engine_get_seqno(engine);
1325         }
1326
1327         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1328
1329         intel_runtime_pm_put(dev_priv);
1330
1331         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1332                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1333                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1334                                             jiffies));
1335         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1336                 seq_puts(m, "Hangcheck active, work pending\n");
1337         else
1338                 seq_puts(m, "Hangcheck inactive\n");
1339
1340         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1341
1342         for_each_engine(engine, dev_priv, id) {
1343                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1344                 struct rb_node *rb;
1345
1346                 seq_printf(m, "%s:\n", engine->name);
1347                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1348                            engine->hangcheck.seqno, seqno[id],
1349                            intel_engine_last_submit(engine),
1350                            engine->timeline->inflight_seqnos);
1351                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1352                            yesno(intel_engine_has_waiter(engine)),
1353                            yesno(test_bit(engine->id,
1354                                           &dev_priv->gpu_error.missed_irq_rings)),
1355                            yesno(engine->hangcheck.stalled));
1356
1357                 spin_lock_irq(&b->rb_lock);
1358                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1359                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1360
1361                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1362                                    w->tsk->comm, w->tsk->pid, w->seqno);
1363                 }
1364                 spin_unlock_irq(&b->rb_lock);
1365
1366                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1367                            (long long)engine->hangcheck.acthd,
1368                            (long long)acthd[id]);
1369                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1370                            hangcheck_action_to_str(engine->hangcheck.action),
1371                            engine->hangcheck.action,
1372                            jiffies_to_msecs(jiffies -
1373                                             engine->hangcheck.action_timestamp));
1374
1375                 if (engine->id == RCS) {
1376                         seq_puts(m, "\tinstdone read =\n");
1377
1378                         i915_instdone_info(dev_priv, m, &instdone);
1379
1380                         seq_puts(m, "\tinstdone accu =\n");
1381
1382                         i915_instdone_info(dev_priv, m,
1383                                            &engine->hangcheck.instdone);
1384                 }
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int ironlake_drpc_info(struct seq_file *m)
1391 {
1392         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1393         u32 rgvmodectl, rstdbyctl;
1394         u16 crstandvid;
1395
1396         intel_runtime_pm_get(dev_priv);
1397
1398         rgvmodectl = I915_READ(MEMMODECTL);
1399         rstdbyctl = I915_READ(RSTDBYCTL);
1400         crstandvid = I915_READ16(CRSTANDVID);
1401
1402         intel_runtime_pm_put(dev_priv);
1403
1404         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1405         seq_printf(m, "Boost freq: %d\n",
1406                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1407                    MEMMODE_BOOST_FREQ_SHIFT);
1408         seq_printf(m, "HW control enabled: %s\n",
1409                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1410         seq_printf(m, "SW control enabled: %s\n",
1411                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1412         seq_printf(m, "Gated voltage change: %s\n",
1413                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1414         seq_printf(m, "Starting frequency: P%d\n",
1415                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1416         seq_printf(m, "Max P-state: P%d\n",
1417                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1418         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1419         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1420         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1421         seq_printf(m, "Render standby enabled: %s\n",
1422                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1423         seq_puts(m, "Current RS state: ");
1424         switch (rstdbyctl & RSX_STATUS_MASK) {
1425         case RSX_STATUS_ON:
1426                 seq_puts(m, "on\n");
1427                 break;
1428         case RSX_STATUS_RC1:
1429                 seq_puts(m, "RC1\n");
1430                 break;
1431         case RSX_STATUS_RC1E:
1432                 seq_puts(m, "RC1E\n");
1433                 break;
1434         case RSX_STATUS_RS1:
1435                 seq_puts(m, "RS1\n");
1436                 break;
1437         case RSX_STATUS_RS2:
1438                 seq_puts(m, "RS2 (RC6)\n");
1439                 break;
1440         case RSX_STATUS_RS3:
1441                 seq_puts(m, "RC3 (RC6+)\n");
1442                 break;
1443         default:
1444                 seq_puts(m, "unknown\n");
1445                 break;
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int i915_forcewake_domains(struct seq_file *m, void *data)
1452 {
1453         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1454         struct intel_uncore_forcewake_domain *fw_domain;
1455
1456         spin_lock_irq(&dev_priv->uncore.lock);
1457         for_each_fw_domain(fw_domain, dev_priv) {
1458                 seq_printf(m, "%s.wake_count = %u\n",
1459                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1460                            fw_domain->wake_count);
1461         }
1462         spin_unlock_irq(&dev_priv->uncore.lock);
1463
1464         return 0;
1465 }
1466
1467 static int vlv_drpc_info(struct seq_file *m)
1468 {
1469         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1470         u32 rpmodectl1, rcctl1, pw_status;
1471
1472         intel_runtime_pm_get(dev_priv);
1473
1474         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1475         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1476         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1477
1478         intel_runtime_pm_put(dev_priv);
1479
1480         seq_printf(m, "Video Turbo Mode: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1482         seq_printf(m, "Turbo enabled: %s\n",
1483                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1484         seq_printf(m, "HW control enabled: %s\n",
1485                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1486         seq_printf(m, "SW control enabled: %s\n",
1487                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1488                           GEN6_RP_MEDIA_SW_MODE));
1489         seq_printf(m, "RC6 Enabled: %s\n",
1490                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1491                                         GEN6_RC_CTL_EI_MODE(1))));
1492         seq_printf(m, "Render Power Well: %s\n",
1493                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1494         seq_printf(m, "Media Power Well: %s\n",
1495                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1496
1497         seq_printf(m, "Render RC6 residency since boot: %u\n",
1498                    I915_READ(VLV_GT_RENDER_RC6));
1499         seq_printf(m, "Media RC6 residency since boot: %u\n",
1500                    I915_READ(VLV_GT_MEDIA_RC6));
1501
1502         return i915_forcewake_domains(m, NULL);
1503 }
1504
1505 static int gen6_drpc_info(struct seq_file *m)
1506 {
1507         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1508         struct drm_device *dev = &dev_priv->drm;
1509         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1510         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1511         unsigned forcewake_count;
1512         int count = 0, ret;
1513
1514         ret = mutex_lock_interruptible(&dev->struct_mutex);
1515         if (ret)
1516                 return ret;
1517         intel_runtime_pm_get(dev_priv);
1518
1519         spin_lock_irq(&dev_priv->uncore.lock);
1520         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1521         spin_unlock_irq(&dev_priv->uncore.lock);
1522
1523         if (forcewake_count) {
1524                 seq_puts(m, "RC information inaccurate because somebody "
1525                             "holds a forcewake reference \n");
1526         } else {
1527                 /* NB: we cannot use forcewake, else we read the wrong values */
1528                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1529                         udelay(10);
1530                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1531         }
1532
1533         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1534         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1535
1536         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1537         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1538         if (INTEL_GEN(dev_priv) >= 9) {
1539                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1540                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1541         }
1542         mutex_unlock(&dev->struct_mutex);
1543         mutex_lock(&dev_priv->rps.hw_lock);
1544         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1545         mutex_unlock(&dev_priv->rps.hw_lock);
1546
1547         intel_runtime_pm_put(dev_priv);
1548
1549         seq_printf(m, "Video Turbo Mode: %s\n",
1550                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1551         seq_printf(m, "HW control enabled: %s\n",
1552                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1553         seq_printf(m, "SW control enabled: %s\n",
1554                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1555                           GEN6_RP_MEDIA_SW_MODE));
1556         seq_printf(m, "RC1e Enabled: %s\n",
1557                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1558         seq_printf(m, "RC6 Enabled: %s\n",
1559                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1560         if (INTEL_GEN(dev_priv) >= 9) {
1561                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1562                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1563                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1564                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1565         }
1566         seq_printf(m, "Deep RC6 Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1568         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1570         seq_puts(m, "Current RC state: ");
1571         switch (gt_core_status & GEN6_RCn_MASK) {
1572         case GEN6_RC0:
1573                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1574                         seq_puts(m, "Core Power Down\n");
1575                 else
1576                         seq_puts(m, "on\n");
1577                 break;
1578         case GEN6_RC3:
1579                 seq_puts(m, "RC3\n");
1580                 break;
1581         case GEN6_RC6:
1582                 seq_puts(m, "RC6\n");
1583                 break;
1584         case GEN6_RC7:
1585                 seq_puts(m, "RC7\n");
1586                 break;
1587         default:
1588                 seq_puts(m, "Unknown\n");
1589                 break;
1590         }
1591
1592         seq_printf(m, "Core Power Down: %s\n",
1593                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1594         if (INTEL_GEN(dev_priv) >= 9) {
1595                 seq_printf(m, "Render Power Well: %s\n",
1596                         (gen9_powergate_status &
1597                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1598                 seq_printf(m, "Media Power Well: %s\n",
1599                         (gen9_powergate_status &
1600                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1601         }
1602
1603         /* Not exactly sure what this is */
1604         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1605                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1606         seq_printf(m, "RC6 residency since boot: %u\n",
1607                    I915_READ(GEN6_GT_GFX_RC6));
1608         seq_printf(m, "RC6+ residency since boot: %u\n",
1609                    I915_READ(GEN6_GT_GFX_RC6p));
1610         seq_printf(m, "RC6++ residency since boot: %u\n",
1611                    I915_READ(GEN6_GT_GFX_RC6pp));
1612
1613         seq_printf(m, "RC6   voltage: %dmV\n",
1614                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1615         seq_printf(m, "RC6+  voltage: %dmV\n",
1616                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1617         seq_printf(m, "RC6++ voltage: %dmV\n",
1618                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1619         return i915_forcewake_domains(m, NULL);
1620 }
1621
1622 static int i915_drpc_info(struct seq_file *m, void *unused)
1623 {
1624         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1625
1626         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1627                 return vlv_drpc_info(m);
1628         else if (INTEL_GEN(dev_priv) >= 6)
1629                 return gen6_drpc_info(m);
1630         else
1631                 return ironlake_drpc_info(m);
1632 }
1633
1634 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1635 {
1636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639                    dev_priv->fb_tracking.busy_bits);
1640
1641         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642                    dev_priv->fb_tracking.flip_bits);
1643
1644         return 0;
1645 }
1646
1647 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 {
1649         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1650
1651         if (!HAS_FBC(dev_priv)) {
1652                 seq_puts(m, "FBC unsupported on this chipset\n");
1653                 return 0;
1654         }
1655
1656         intel_runtime_pm_get(dev_priv);
1657         mutex_lock(&dev_priv->fbc.lock);
1658
1659         if (intel_fbc_is_active(dev_priv))
1660                 seq_puts(m, "FBC enabled\n");
1661         else
1662                 seq_printf(m, "FBC disabled: %s\n",
1663                            dev_priv->fbc.no_fbc_reason);
1664
1665         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1666                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1667                                 BDW_FBC_COMPRESSION_MASK :
1668                                 IVB_FBC_COMPRESSION_MASK;
1669                 seq_printf(m, "Compressing: %s\n",
1670                            yesno(I915_READ(FBC_STATUS2) & mask));
1671         }
1672
1673         mutex_unlock(&dev_priv->fbc.lock);
1674         intel_runtime_pm_put(dev_priv);
1675
1676         return 0;
1677 }
1678
1679 static int i915_fbc_fc_get(void *data, u64 *val)
1680 {
1681         struct drm_i915_private *dev_priv = data;
1682
1683         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1684                 return -ENODEV;
1685
1686         *val = dev_priv->fbc.false_color;
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_set(void *data, u64 val)
1692 {
1693         struct drm_i915_private *dev_priv = data;
1694         u32 reg;
1695
1696         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1697                 return -ENODEV;
1698
1699         mutex_lock(&dev_priv->fbc.lock);
1700
1701         reg = I915_READ(ILK_DPFC_CONTROL);
1702         dev_priv->fbc.false_color = val;
1703
1704         I915_WRITE(ILK_DPFC_CONTROL, val ?
1705                    (reg | FBC_CTL_FALSE_COLOR) :
1706                    (reg & ~FBC_CTL_FALSE_COLOR));
1707
1708         mutex_unlock(&dev_priv->fbc.lock);
1709         return 0;
1710 }
1711
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713                         i915_fbc_fc_get, i915_fbc_fc_set,
1714                         "%llu\n");
1715
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1717 {
1718         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1719
1720         if (!HAS_IPS(dev_priv)) {
1721                 seq_puts(m, "not supported\n");
1722                 return 0;
1723         }
1724
1725         intel_runtime_pm_get(dev_priv);
1726
1727         seq_printf(m, "Enabled by kernel parameter: %s\n",
1728                    yesno(i915.enable_ips));
1729
1730         if (INTEL_GEN(dev_priv) >= 8) {
1731                 seq_puts(m, "Currently: unknown\n");
1732         } else {
1733                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1734                         seq_puts(m, "Currently: enabled\n");
1735                 else
1736                         seq_puts(m, "Currently: disabled\n");
1737         }
1738
1739         intel_runtime_pm_put(dev_priv);
1740
1741         return 0;
1742 }
1743
1744 static int i915_sr_status(struct seq_file *m, void *unused)
1745 {
1746         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1747         bool sr_enabled = false;
1748
1749         intel_runtime_pm_get(dev_priv);
1750         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1751
1752         if (HAS_PCH_SPLIT(dev_priv))
1753                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1754         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1755                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1756                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1757         else if (IS_I915GM(dev_priv))
1758                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1759         else if (IS_PINEVIEW(dev_priv))
1760                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1761         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1762                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1763
1764         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1765         intel_runtime_pm_put(dev_priv);
1766
1767         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1768
1769         return 0;
1770 }
1771
1772 static int i915_emon_status(struct seq_file *m, void *unused)
1773 {
1774         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1775         struct drm_device *dev = &dev_priv->drm;
1776         unsigned long temp, chipset, gfx;
1777         int ret;
1778
1779         if (!IS_GEN5(dev_priv))
1780                 return -ENODEV;
1781
1782         ret = mutex_lock_interruptible(&dev->struct_mutex);
1783         if (ret)
1784                 return ret;
1785
1786         temp = i915_mch_val(dev_priv);
1787         chipset = i915_chipset_val(dev_priv);
1788         gfx = i915_gfx_val(dev_priv);
1789         mutex_unlock(&dev->struct_mutex);
1790
1791         seq_printf(m, "GMCH temp: %ld\n", temp);
1792         seq_printf(m, "Chipset power: %ld\n", chipset);
1793         seq_printf(m, "GFX power: %ld\n", gfx);
1794         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1795
1796         return 0;
1797 }
1798
1799 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1800 {
1801         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1802         int ret = 0;
1803         int gpu_freq, ia_freq;
1804         unsigned int max_gpu_freq, min_gpu_freq;
1805
1806         if (!HAS_LLC(dev_priv)) {
1807                 seq_puts(m, "unsupported on this chipset\n");
1808                 return 0;
1809         }
1810
1811         intel_runtime_pm_get(dev_priv);
1812
1813         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1814         if (ret)
1815                 goto out;
1816
1817         if (IS_GEN9_BC(dev_priv)) {
1818                 /* Convert GT frequency to 50 HZ units */
1819                 min_gpu_freq =
1820                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1821                 max_gpu_freq =
1822                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1823         } else {
1824                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1825                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1826         }
1827
1828         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1829
1830         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1831                 ia_freq = gpu_freq;
1832                 sandybridge_pcode_read(dev_priv,
1833                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1834                                        &ia_freq);
1835                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1836                            intel_gpu_freq(dev_priv, (gpu_freq *
1837                                                      (IS_GEN9_BC(dev_priv) ?
1838                                                       GEN9_FREQ_SCALER : 1))),
1839                            ((ia_freq >> 0) & 0xff) * 100,
1840                            ((ia_freq >> 8) & 0xff) * 100);
1841         }
1842
1843         mutex_unlock(&dev_priv->rps.hw_lock);
1844
1845 out:
1846         intel_runtime_pm_put(dev_priv);
1847         return ret;
1848 }
1849
1850 static int i915_opregion(struct seq_file *m, void *unused)
1851 {
1852         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1853         struct drm_device *dev = &dev_priv->drm;
1854         struct intel_opregion *opregion = &dev_priv->opregion;
1855         int ret;
1856
1857         ret = mutex_lock_interruptible(&dev->struct_mutex);
1858         if (ret)
1859                 goto out;
1860
1861         if (opregion->header)
1862                 seq_write(m, opregion->header, OPREGION_SIZE);
1863
1864         mutex_unlock(&dev->struct_mutex);
1865
1866 out:
1867         return 0;
1868 }
1869
1870 static int i915_vbt(struct seq_file *m, void *unused)
1871 {
1872         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1873
1874         if (opregion->vbt)
1875                 seq_write(m, opregion->vbt, opregion->vbt_size);
1876
1877         return 0;
1878 }
1879
1880 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1881 {
1882         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1883         struct drm_device *dev = &dev_priv->drm;
1884         struct intel_framebuffer *fbdev_fb = NULL;
1885         struct drm_framebuffer *drm_fb;
1886         int ret;
1887
1888         ret = mutex_lock_interruptible(&dev->struct_mutex);
1889         if (ret)
1890                 return ret;
1891
1892 #ifdef CONFIG_DRM_FBDEV_EMULATION
1893         if (dev_priv->fbdev) {
1894                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1895
1896                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1897                            fbdev_fb->base.width,
1898                            fbdev_fb->base.height,
1899                            fbdev_fb->base.format->depth,
1900                            fbdev_fb->base.format->cpp[0] * 8,
1901                            fbdev_fb->base.modifier,
1902                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1903                 describe_obj(m, fbdev_fb->obj);
1904                 seq_putc(m, '\n');
1905         }
1906 #endif
1907
1908         mutex_lock(&dev->mode_config.fb_lock);
1909         drm_for_each_fb(drm_fb, dev) {
1910                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1911                 if (fb == fbdev_fb)
1912                         continue;
1913
1914                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1915                            fb->base.width,
1916                            fb->base.height,
1917                            fb->base.format->depth,
1918                            fb->base.format->cpp[0] * 8,
1919                            fb->base.modifier,
1920                            drm_framebuffer_read_refcount(&fb->base));
1921                 describe_obj(m, fb->obj);
1922                 seq_putc(m, '\n');
1923         }
1924         mutex_unlock(&dev->mode_config.fb_lock);
1925         mutex_unlock(&dev->struct_mutex);
1926
1927         return 0;
1928 }
1929
1930 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1931 {
1932         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1933                    ring->space, ring->head, ring->tail,
1934                    ring->last_retired_head);
1935 }
1936
1937 static int i915_context_status(struct seq_file *m, void *unused)
1938 {
1939         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1940         struct drm_device *dev = &dev_priv->drm;
1941         struct intel_engine_cs *engine;
1942         struct i915_gem_context *ctx;
1943         enum intel_engine_id id;
1944         int ret;
1945
1946         ret = mutex_lock_interruptible(&dev->struct_mutex);
1947         if (ret)
1948                 return ret;
1949
1950         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1951                 seq_printf(m, "HW context %u ", ctx->hw_id);
1952                 if (ctx->pid) {
1953                         struct task_struct *task;
1954
1955                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1956                         if (task) {
1957                                 seq_printf(m, "(%s [%d]) ",
1958                                            task->comm, task->pid);
1959                                 put_task_struct(task);
1960                         }
1961                 } else if (IS_ERR(ctx->file_priv)) {
1962                         seq_puts(m, "(deleted) ");
1963                 } else {
1964                         seq_puts(m, "(kernel) ");
1965                 }
1966
1967                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1968                 seq_putc(m, '\n');
1969
1970                 for_each_engine(engine, dev_priv, id) {
1971                         struct intel_context *ce = &ctx->engine[engine->id];
1972
1973                         seq_printf(m, "%s: ", engine->name);
1974                         seq_putc(m, ce->initialised ? 'I' : 'i');
1975                         if (ce->state)
1976                                 describe_obj(m, ce->state->obj);
1977                         if (ce->ring)
1978                                 describe_ctx_ring(m, ce->ring);
1979                         seq_putc(m, '\n');
1980                 }
1981
1982                 seq_putc(m, '\n');
1983         }
1984
1985         mutex_unlock(&dev->struct_mutex);
1986
1987         return 0;
1988 }
1989
1990 static void i915_dump_lrc_obj(struct seq_file *m,
1991                               struct i915_gem_context *ctx,
1992                               struct intel_engine_cs *engine)
1993 {
1994         struct i915_vma *vma = ctx->engine[engine->id].state;
1995         struct page *page;
1996         int j;
1997
1998         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1999
2000         if (!vma) {
2001                 seq_puts(m, "\tFake context\n");
2002                 return;
2003         }
2004
2005         if (vma->flags & I915_VMA_GLOBAL_BIND)
2006                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2007                            i915_ggtt_offset(vma));
2008
2009         if (i915_gem_object_pin_pages(vma->obj)) {
2010                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2011                 return;
2012         }
2013
2014         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2015         if (page) {
2016                 u32 *reg_state = kmap_atomic(page);
2017
2018                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2019                         seq_printf(m,
2020                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2021                                    j * 4,
2022                                    reg_state[j], reg_state[j + 1],
2023                                    reg_state[j + 2], reg_state[j + 3]);
2024                 }
2025                 kunmap_atomic(reg_state);
2026         }
2027
2028         i915_gem_object_unpin_pages(vma->obj);
2029         seq_putc(m, '\n');
2030 }
2031
2032 static int i915_dump_lrc(struct seq_file *m, void *unused)
2033 {
2034         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2035         struct drm_device *dev = &dev_priv->drm;
2036         struct intel_engine_cs *engine;
2037         struct i915_gem_context *ctx;
2038         enum intel_engine_id id;
2039         int ret;
2040
2041         if (!i915.enable_execlists) {
2042                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2043                 return 0;
2044         }
2045
2046         ret = mutex_lock_interruptible(&dev->struct_mutex);
2047         if (ret)
2048                 return ret;
2049
2050         list_for_each_entry(ctx, &dev_priv->context_list, link)
2051                 for_each_engine(engine, dev_priv, id)
2052                         i915_dump_lrc_obj(m, ctx, engine);
2053
2054         mutex_unlock(&dev->struct_mutex);
2055
2056         return 0;
2057 }
2058
2059 static const char *swizzle_string(unsigned swizzle)
2060 {
2061         switch (swizzle) {
2062         case I915_BIT_6_SWIZZLE_NONE:
2063                 return "none";
2064         case I915_BIT_6_SWIZZLE_9:
2065                 return "bit9";
2066         case I915_BIT_6_SWIZZLE_9_10:
2067                 return "bit9/bit10";
2068         case I915_BIT_6_SWIZZLE_9_11:
2069                 return "bit9/bit11";
2070         case I915_BIT_6_SWIZZLE_9_10_11:
2071                 return "bit9/bit10/bit11";
2072         case I915_BIT_6_SWIZZLE_9_17:
2073                 return "bit9/bit17";
2074         case I915_BIT_6_SWIZZLE_9_10_17:
2075                 return "bit9/bit10/bit17";
2076         case I915_BIT_6_SWIZZLE_UNKNOWN:
2077                 return "unknown";
2078         }
2079
2080         return "bug";
2081 }
2082
2083 static int i915_swizzle_info(struct seq_file *m, void *data)
2084 {
2085         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2086
2087         intel_runtime_pm_get(dev_priv);
2088
2089         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2090                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2091         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2092                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2093
2094         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2095                 seq_printf(m, "DDC = 0x%08x\n",
2096                            I915_READ(DCC));
2097                 seq_printf(m, "DDC2 = 0x%08x\n",
2098                            I915_READ(DCC2));
2099                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2100                            I915_READ16(C0DRB3));
2101                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2102                            I915_READ16(C1DRB3));
2103         } else if (INTEL_GEN(dev_priv) >= 6) {
2104                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2105                            I915_READ(MAD_DIMM_C0));
2106                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2107                            I915_READ(MAD_DIMM_C1));
2108                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2109                            I915_READ(MAD_DIMM_C2));
2110                 seq_printf(m, "TILECTL = 0x%08x\n",
2111                            I915_READ(TILECTL));
2112                 if (INTEL_GEN(dev_priv) >= 8)
2113                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2114                                    I915_READ(GAMTARBMODE));
2115                 else
2116                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2117                                    I915_READ(ARB_MODE));
2118                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2119                            I915_READ(DISP_ARB_CTL));
2120         }
2121
2122         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2123                 seq_puts(m, "L-shaped memory detected\n");
2124
2125         intel_runtime_pm_put(dev_priv);
2126
2127         return 0;
2128 }
2129
2130 static int per_file_ctx(int id, void *ptr, void *data)
2131 {
2132         struct i915_gem_context *ctx = ptr;
2133         struct seq_file *m = data;
2134         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2135
2136         if (!ppgtt) {
2137                 seq_printf(m, "  no ppgtt for context %d\n",
2138                            ctx->user_handle);
2139                 return 0;
2140         }
2141
2142         if (i915_gem_context_is_default(ctx))
2143                 seq_puts(m, "  default context:\n");
2144         else
2145                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2146         ppgtt->debug_dump(ppgtt, m);
2147
2148         return 0;
2149 }
2150
2151 static void gen8_ppgtt_info(struct seq_file *m,
2152                             struct drm_i915_private *dev_priv)
2153 {
2154         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2155         struct intel_engine_cs *engine;
2156         enum intel_engine_id id;
2157         int i;
2158
2159         if (!ppgtt)
2160                 return;
2161
2162         for_each_engine(engine, dev_priv, id) {
2163                 seq_printf(m, "%s\n", engine->name);
2164                 for (i = 0; i < 4; i++) {
2165                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2166                         pdp <<= 32;
2167                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2168                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2169                 }
2170         }
2171 }
2172
2173 static void gen6_ppgtt_info(struct seq_file *m,
2174                             struct drm_i915_private *dev_priv)
2175 {
2176         struct intel_engine_cs *engine;
2177         enum intel_engine_id id;
2178
2179         if (IS_GEN6(dev_priv))
2180                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2181
2182         for_each_engine(engine, dev_priv, id) {
2183                 seq_printf(m, "%s\n", engine->name);
2184                 if (IS_GEN7(dev_priv))
2185                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2186                                    I915_READ(RING_MODE_GEN7(engine)));
2187                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2188                            I915_READ(RING_PP_DIR_BASE(engine)));
2189                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2190                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2191                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2192                            I915_READ(RING_PP_DIR_DCLV(engine)));
2193         }
2194         if (dev_priv->mm.aliasing_ppgtt) {
2195                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2196
2197                 seq_puts(m, "aliasing PPGTT:\n");
2198                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2199
2200                 ppgtt->debug_dump(ppgtt, m);
2201         }
2202
2203         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2204 }
2205
2206 static int i915_ppgtt_info(struct seq_file *m, void *data)
2207 {
2208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2209         struct drm_device *dev = &dev_priv->drm;
2210         struct drm_file *file;
2211         int ret;
2212
2213         mutex_lock(&dev->filelist_mutex);
2214         ret = mutex_lock_interruptible(&dev->struct_mutex);
2215         if (ret)
2216                 goto out_unlock;
2217
2218         intel_runtime_pm_get(dev_priv);
2219
2220         if (INTEL_GEN(dev_priv) >= 8)
2221                 gen8_ppgtt_info(m, dev_priv);
2222         else if (INTEL_GEN(dev_priv) >= 6)
2223                 gen6_ppgtt_info(m, dev_priv);
2224
2225         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2226                 struct drm_i915_file_private *file_priv = file->driver_priv;
2227                 struct task_struct *task;
2228
2229                 task = get_pid_task(file->pid, PIDTYPE_PID);
2230                 if (!task) {
2231                         ret = -ESRCH;
2232                         goto out_rpm;
2233                 }
2234                 seq_printf(m, "\nproc: %s\n", task->comm);
2235                 put_task_struct(task);
2236                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2237                              (void *)(unsigned long)m);
2238         }
2239
2240 out_rpm:
2241         intel_runtime_pm_put(dev_priv);
2242         mutex_unlock(&dev->struct_mutex);
2243 out_unlock:
2244         mutex_unlock(&dev->filelist_mutex);
2245         return ret;
2246 }
2247
2248 static int count_irq_waiters(struct drm_i915_private *i915)
2249 {
2250         struct intel_engine_cs *engine;
2251         enum intel_engine_id id;
2252         int count = 0;
2253
2254         for_each_engine(engine, i915, id)
2255                 count += intel_engine_has_waiter(engine);
2256
2257         return count;
2258 }
2259
2260 static const char *rps_power_to_str(unsigned int power)
2261 {
2262         static const char * const strings[] = {
2263                 [LOW_POWER] = "low power",
2264                 [BETWEEN] = "mixed",
2265                 [HIGH_POWER] = "high power",
2266         };
2267
2268         if (power >= ARRAY_SIZE(strings) || !strings[power])
2269                 return "unknown";
2270
2271         return strings[power];
2272 }
2273
2274 static int i915_rps_boost_info(struct seq_file *m, void *data)
2275 {
2276         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2277         struct drm_device *dev = &dev_priv->drm;
2278         struct drm_file *file;
2279
2280         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2281         seq_printf(m, "GPU busy? %s [%d requests]\n",
2282                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2283         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2284         seq_printf(m, "Frequency requested %d\n",
2285                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2286         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2287                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2288                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2289                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2290                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2291         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2292                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2293                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2295
2296         mutex_lock(&dev->filelist_mutex);
2297         spin_lock(&dev_priv->rps.client_lock);
2298         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2299                 struct drm_i915_file_private *file_priv = file->driver_priv;
2300                 struct task_struct *task;
2301
2302                 rcu_read_lock();
2303                 task = pid_task(file->pid, PIDTYPE_PID);
2304                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2305                            task ? task->comm : "<unknown>",
2306                            task ? task->pid : -1,
2307                            file_priv->rps.boosts,
2308                            list_empty(&file_priv->rps.link) ? "" : ", active");
2309                 rcu_read_unlock();
2310         }
2311         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2312         spin_unlock(&dev_priv->rps.client_lock);
2313         mutex_unlock(&dev->filelist_mutex);
2314
2315         if (INTEL_GEN(dev_priv) >= 6 &&
2316             dev_priv->rps.enabled &&
2317             dev_priv->gt.active_requests) {
2318                 u32 rpup, rpupei;
2319                 u32 rpdown, rpdownei;
2320
2321                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2322                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2323                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2324                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2325                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2326                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2327
2328                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2329                            rps_power_to_str(dev_priv->rps.power));
2330                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2331                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2332                            dev_priv->rps.up_threshold);
2333                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2334                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2335                            dev_priv->rps.down_threshold);
2336         } else {
2337                 seq_puts(m, "\nRPS Autotuning inactive\n");
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int i915_llc(struct seq_file *m, void *data)
2344 {
2345         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2346         const bool edram = INTEL_GEN(dev_priv) > 8;
2347
2348         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2349         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2350                    intel_uncore_edram_size(dev_priv)/1024/1024);
2351
2352         return 0;
2353 }
2354
2355 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2356 {
2357         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2358         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2359
2360         if (!HAS_HUC_UCODE(dev_priv))
2361                 return 0;
2362
2363         seq_puts(m, "HuC firmware status:\n");
2364         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2365         seq_printf(m, "\tfetch: %s\n",
2366                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2367         seq_printf(m, "\tload: %s\n",
2368                 intel_uc_fw_status_repr(huc_fw->load_status));
2369         seq_printf(m, "\tversion wanted: %d.%d\n",
2370                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2371         seq_printf(m, "\tversion found: %d.%d\n",
2372                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2373         seq_printf(m, "\theader: offset is %d; size = %d\n",
2374                 huc_fw->header_offset, huc_fw->header_size);
2375         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2376                 huc_fw->ucode_offset, huc_fw->ucode_size);
2377         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2378                 huc_fw->rsa_offset, huc_fw->rsa_size);
2379
2380         intel_runtime_pm_get(dev_priv);
2381         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2382         intel_runtime_pm_put(dev_priv);
2383
2384         return 0;
2385 }
2386
2387 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2388 {
2389         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2390         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2391         u32 tmp, i;
2392
2393         if (!HAS_GUC_UCODE(dev_priv))
2394                 return 0;
2395
2396         seq_printf(m, "GuC firmware status:\n");
2397         seq_printf(m, "\tpath: %s\n",
2398                 guc_fw->path);
2399         seq_printf(m, "\tfetch: %s\n",
2400                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2401         seq_printf(m, "\tload: %s\n",
2402                 intel_uc_fw_status_repr(guc_fw->load_status));
2403         seq_printf(m, "\tversion wanted: %d.%d\n",
2404                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2405         seq_printf(m, "\tversion found: %d.%d\n",
2406                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2407         seq_printf(m, "\theader: offset is %d; size = %d\n",
2408                 guc_fw->header_offset, guc_fw->header_size);
2409         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2410                 guc_fw->ucode_offset, guc_fw->ucode_size);
2411         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2412                 guc_fw->rsa_offset, guc_fw->rsa_size);
2413
2414         intel_runtime_pm_get(dev_priv);
2415
2416         tmp = I915_READ(GUC_STATUS);
2417
2418         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2419         seq_printf(m, "\tBootrom status = 0x%x\n",
2420                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2421         seq_printf(m, "\tuKernel status = 0x%x\n",
2422                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2423         seq_printf(m, "\tMIA Core status = 0x%x\n",
2424                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2425         seq_puts(m, "\nScratch registers:\n");
2426         for (i = 0; i < 16; i++)
2427                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2428
2429         intel_runtime_pm_put(dev_priv);
2430
2431         return 0;
2432 }
2433
2434 static void i915_guc_log_info(struct seq_file *m,
2435                               struct drm_i915_private *dev_priv)
2436 {
2437         struct intel_guc *guc = &dev_priv->guc;
2438
2439         seq_puts(m, "\nGuC logging stats:\n");
2440
2441         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2442                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2443                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2444
2445         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2446                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2447                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2448
2449         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2450                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2451                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2452
2453         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2454                    guc->log.flush_interrupt_count);
2455
2456         seq_printf(m, "\tCapture miss count: %u\n",
2457                    guc->log.capture_miss_count);
2458 }
2459
2460 static void i915_guc_client_info(struct seq_file *m,
2461                                  struct drm_i915_private *dev_priv,
2462                                  struct i915_guc_client *client)
2463 {
2464         struct intel_engine_cs *engine;
2465         enum intel_engine_id id;
2466         uint64_t tot = 0;
2467
2468         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2469                 client->priority, client->ctx_index, client->proc_desc_offset);
2470         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2471                 client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
2472         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2473                 client->wq_size, client->wq_offset, client->wq_tail);
2474
2475         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2476         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2477         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2478
2479         for_each_engine(engine, dev_priv, id) {
2480                 u64 submissions = client->submissions[id];
2481                 tot += submissions;
2482                 seq_printf(m, "\tSubmissions: %llu %s\n",
2483                                 submissions, engine->name);
2484         }
2485         seq_printf(m, "\tTotal: %llu\n", tot);
2486 }
2487
2488 static int i915_guc_info(struct seq_file *m, void *data)
2489 {
2490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2491         const struct intel_guc *guc = &dev_priv->guc;
2492         struct intel_engine_cs *engine;
2493         enum intel_engine_id id;
2494         u64 total;
2495
2496         if (!guc->execbuf_client) {
2497                 seq_printf(m, "GuC submission %s\n",
2498                            HAS_GUC_SCHED(dev_priv) ?
2499                            "disabled" :
2500                            "not supported");
2501                 return 0;
2502         }
2503
2504         seq_printf(m, "Doorbell map:\n");
2505         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap);
2506         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2507
2508         seq_printf(m, "GuC total action count: %llu\n", guc->action_count);
2509         seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);
2510         seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);
2511         seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);
2512         seq_printf(m, "GuC last action error code: %d\n", guc->action_err);
2513
2514         total = 0;
2515         seq_printf(m, "\nGuC submissions:\n");
2516         for_each_engine(engine, dev_priv, id) {
2517                 u64 submissions = guc->submissions[id];
2518                 total += submissions;
2519                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2520                         engine->name, submissions, guc->last_seqno[id]);
2521         }
2522         seq_printf(m, "\t%s: %llu\n", "Total", total);
2523
2524         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2525         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2526
2527         i915_guc_log_info(m, dev_priv);
2528
2529         /* Add more as required ... */
2530
2531         return 0;
2532 }
2533
2534 static int i915_guc_log_dump(struct seq_file *m, void *data)
2535 {
2536         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2537         struct drm_i915_gem_object *obj;
2538         int i = 0, pg;
2539
2540         if (!dev_priv->guc.log.vma)
2541                 return 0;
2542
2543         obj = dev_priv->guc.log.vma->obj;
2544         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2545                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2546
2547                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2548                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2549                                    *(log + i), *(log + i + 1),
2550                                    *(log + i + 2), *(log + i + 3));
2551
2552                 kunmap_atomic(log);
2553         }
2554
2555         seq_putc(m, '\n');
2556
2557         return 0;
2558 }
2559
2560 static int i915_guc_log_control_get(void *data, u64 *val)
2561 {
2562         struct drm_device *dev = data;
2563         struct drm_i915_private *dev_priv = to_i915(dev);
2564
2565         if (!dev_priv->guc.log.vma)
2566                 return -EINVAL;
2567
2568         *val = i915.guc_log_level;
2569
2570         return 0;
2571 }
2572
2573 static int i915_guc_log_control_set(void *data, u64 val)
2574 {
2575         struct drm_device *dev = data;
2576         struct drm_i915_private *dev_priv = to_i915(dev);
2577         int ret;
2578
2579         if (!dev_priv->guc.log.vma)
2580                 return -EINVAL;
2581
2582         ret = mutex_lock_interruptible(&dev->struct_mutex);
2583         if (ret)
2584                 return ret;
2585
2586         intel_runtime_pm_get(dev_priv);
2587         ret = i915_guc_log_control(dev_priv, val);
2588         intel_runtime_pm_put(dev_priv);
2589
2590         mutex_unlock(&dev->struct_mutex);
2591         return ret;
2592 }
2593
2594 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2595                         i915_guc_log_control_get, i915_guc_log_control_set,
2596                         "%lld\n");
2597
2598 static const char *psr2_live_status(u32 val)
2599 {
2600         static const char * const live_status[] = {
2601                 "IDLE",
2602                 "CAPTURE",
2603                 "CAPTURE_FS",
2604                 "SLEEP",
2605                 "BUFON_FW",
2606                 "ML_UP",
2607                 "SU_STANDBY",
2608                 "FAST_SLEEP",
2609                 "DEEP_SLEEP",
2610                 "BUF_ON",
2611                 "TG_ON"
2612         };
2613
2614         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2615         if (val < ARRAY_SIZE(live_status))
2616                 return live_status[val];
2617
2618         return "unknown";
2619 }
2620
2621 static int i915_edp_psr_status(struct seq_file *m, void *data)
2622 {
2623         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2624         u32 psrperf = 0;
2625         u32 stat[3];
2626         enum pipe pipe;
2627         bool enabled = false;
2628
2629         if (!HAS_PSR(dev_priv)) {
2630                 seq_puts(m, "PSR not supported\n");
2631                 return 0;
2632         }
2633
2634         intel_runtime_pm_get(dev_priv);
2635
2636         mutex_lock(&dev_priv->psr.lock);
2637         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2638         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2639         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2640         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2641         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2642                    dev_priv->psr.busy_frontbuffer_bits);
2643         seq_printf(m, "Re-enable work scheduled: %s\n",
2644                    yesno(work_busy(&dev_priv->psr.work.work)));
2645
2646         if (HAS_DDI(dev_priv)) {
2647                 if (dev_priv->psr.psr2_support)
2648                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2649                 else
2650                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2651         } else {
2652                 for_each_pipe(dev_priv, pipe) {
2653                         enum transcoder cpu_transcoder =
2654                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2655                         enum intel_display_power_domain power_domain;
2656
2657                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2658                         if (!intel_display_power_get_if_enabled(dev_priv,
2659                                                                 power_domain))
2660                                 continue;
2661
2662                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2663                                 VLV_EDP_PSR_CURR_STATE_MASK;
2664                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2665                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2666                                 enabled = true;
2667
2668                         intel_display_power_put(dev_priv, power_domain);
2669                 }
2670         }
2671
2672         seq_printf(m, "Main link in standby mode: %s\n",
2673                    yesno(dev_priv->psr.link_standby));
2674
2675         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2676
2677         if (!HAS_DDI(dev_priv))
2678                 for_each_pipe(dev_priv, pipe) {
2679                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2680                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2681                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2682                 }
2683         seq_puts(m, "\n");
2684
2685         /*
2686          * VLV/CHV PSR has no kind of performance counter
2687          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2688          */
2689         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2690                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2691                         EDP_PSR_PERF_CNT_MASK;
2692
2693                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2694         }
2695         if (dev_priv->psr.psr2_support) {
2696                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2697
2698                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2699                            psr2, psr2_live_status(psr2));
2700         }
2701         mutex_unlock(&dev_priv->psr.lock);
2702
2703         intel_runtime_pm_put(dev_priv);
2704         return 0;
2705 }
2706
2707 static int i915_sink_crc(struct seq_file *m, void *data)
2708 {
2709         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2710         struct drm_device *dev = &dev_priv->drm;
2711         struct intel_connector *connector;
2712         struct intel_dp *intel_dp = NULL;
2713         int ret;
2714         u8 crc[6];
2715
2716         drm_modeset_lock_all(dev);
2717         for_each_intel_connector(dev, connector) {
2718                 struct drm_crtc *crtc;
2719
2720                 if (!connector->base.state->best_encoder)
2721                         continue;
2722
2723                 crtc = connector->base.state->crtc;
2724                 if (!crtc->state->active)
2725                         continue;
2726
2727                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2728                         continue;
2729
2730                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2731
2732                 ret = intel_dp_sink_crc(intel_dp, crc);
2733                 if (ret)
2734                         goto out;
2735
2736                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2737                            crc[0], crc[1], crc[2],
2738                            crc[3], crc[4], crc[5]);
2739                 goto out;
2740         }
2741         ret = -ENODEV;
2742 out:
2743         drm_modeset_unlock_all(dev);
2744         return ret;
2745 }
2746
2747 static int i915_energy_uJ(struct seq_file *m, void *data)
2748 {
2749         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2750         u64 power;
2751         u32 units;
2752
2753         if (INTEL_GEN(dev_priv) < 6)
2754                 return -ENODEV;
2755
2756         intel_runtime_pm_get(dev_priv);
2757
2758         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2759         power = (power & 0x1f00) >> 8;
2760         units = 1000000 / (1 << power); /* convert to uJ */
2761         power = I915_READ(MCH_SECP_NRG_STTS);
2762         power *= units;
2763
2764         intel_runtime_pm_put(dev_priv);
2765
2766         seq_printf(m, "%llu", (long long unsigned)power);
2767
2768         return 0;
2769 }
2770
2771 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2772 {
2773         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2774         struct pci_dev *pdev = dev_priv->drm.pdev;
2775
2776         if (!HAS_RUNTIME_PM(dev_priv))
2777                 seq_puts(m, "Runtime power management not supported\n");
2778
2779         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2780         seq_printf(m, "IRQs disabled: %s\n",
2781                    yesno(!intel_irqs_enabled(dev_priv)));
2782 #ifdef CONFIG_PM
2783         seq_printf(m, "Usage count: %d\n",
2784                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2785 #else
2786         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2787 #endif
2788         seq_printf(m, "PCI device power state: %s [%d]\n",
2789                    pci_power_name(pdev->current_state),
2790                    pdev->current_state);
2791
2792         return 0;
2793 }
2794
2795 static int i915_power_domain_info(struct seq_file *m, void *unused)
2796 {
2797         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2798         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2799         int i;
2800
2801         mutex_lock(&power_domains->lock);
2802
2803         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2804         for (i = 0; i < power_domains->power_well_count; i++) {
2805                 struct i915_power_well *power_well;
2806                 enum intel_display_power_domain power_domain;
2807
2808                 power_well = &power_domains->power_wells[i];
2809                 seq_printf(m, "%-25s %d\n", power_well->name,
2810                            power_well->count);
2811
2812                 for_each_power_domain(power_domain, power_well->domains)
2813                         seq_printf(m, "  %-23s %d\n",
2814                                  intel_display_power_domain_str(power_domain),
2815                                  power_domains->domain_use_count[power_domain]);
2816         }
2817
2818         mutex_unlock(&power_domains->lock);
2819
2820         return 0;
2821 }
2822
2823 static int i915_dmc_info(struct seq_file *m, void *unused)
2824 {
2825         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2826         struct intel_csr *csr;
2827
2828         if (!HAS_CSR(dev_priv)) {
2829                 seq_puts(m, "not supported\n");
2830                 return 0;
2831         }
2832
2833         csr = &dev_priv->csr;
2834
2835         intel_runtime_pm_get(dev_priv);
2836
2837         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2838         seq_printf(m, "path: %s\n", csr->fw_path);
2839
2840         if (!csr->dmc_payload)
2841                 goto out;
2842
2843         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2844                    CSR_VERSION_MINOR(csr->version));
2845
2846         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2847                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2848                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2849                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2850                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2851         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2852                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2853                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2854         }
2855
2856 out:
2857         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2858         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2859         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2860
2861         intel_runtime_pm_put(dev_priv);
2862
2863         return 0;
2864 }
2865
2866 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2867                                  struct drm_display_mode *mode)
2868 {
2869         int i;
2870
2871         for (i = 0; i < tabs; i++)
2872                 seq_putc(m, '\t');
2873
2874         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2875                    mode->base.id, mode->name,
2876                    mode->vrefresh, mode->clock,
2877                    mode->hdisplay, mode->hsync_start,
2878                    mode->hsync_end, mode->htotal,
2879                    mode->vdisplay, mode->vsync_start,
2880                    mode->vsync_end, mode->vtotal,
2881                    mode->type, mode->flags);
2882 }
2883
2884 static void intel_encoder_info(struct seq_file *m,
2885                                struct intel_crtc *intel_crtc,
2886                                struct intel_encoder *intel_encoder)
2887 {
2888         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2889         struct drm_device *dev = &dev_priv->drm;
2890         struct drm_crtc *crtc = &intel_crtc->base;
2891         struct intel_connector *intel_connector;
2892         struct drm_encoder *encoder;
2893
2894         encoder = &intel_encoder->base;
2895         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2896                    encoder->base.id, encoder->name);
2897         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2898                 struct drm_connector *connector = &intel_connector->base;
2899                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2900                            connector->base.id,
2901                            connector->name,
2902                            drm_get_connector_status_name(connector->status));
2903                 if (connector->status == connector_status_connected) {
2904                         struct drm_display_mode *mode = &crtc->mode;
2905                         seq_printf(m, ", mode:\n");
2906                         intel_seq_print_mode(m, 2, mode);
2907                 } else {
2908                         seq_putc(m, '\n');
2909                 }
2910         }
2911 }
2912
2913 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2914 {
2915         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2916         struct drm_device *dev = &dev_priv->drm;
2917         struct drm_crtc *crtc = &intel_crtc->base;
2918         struct intel_encoder *intel_encoder;
2919         struct drm_plane_state *plane_state = crtc->primary->state;
2920         struct drm_framebuffer *fb = plane_state->fb;
2921
2922         if (fb)
2923                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2924                            fb->base.id, plane_state->src_x >> 16,
2925                            plane_state->src_y >> 16, fb->width, fb->height);
2926         else
2927                 seq_puts(m, "\tprimary plane disabled\n");
2928         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2929                 intel_encoder_info(m, intel_crtc, intel_encoder);
2930 }
2931
2932 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2933 {
2934         struct drm_display_mode *mode = panel->fixed_mode;
2935
2936         seq_printf(m, "\tfixed mode:\n");
2937         intel_seq_print_mode(m, 2, mode);
2938 }
2939
2940 static void intel_dp_info(struct seq_file *m,
2941                           struct intel_connector *intel_connector)
2942 {
2943         struct intel_encoder *intel_encoder = intel_connector->encoder;
2944         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2945
2946         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2947         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2948         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2949                 intel_panel_info(m, &intel_connector->panel);
2950
2951         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2952                                 &intel_dp->aux);
2953 }
2954
2955 static void intel_dp_mst_info(struct seq_file *m,
2956                           struct intel_connector *intel_connector)
2957 {
2958         struct intel_encoder *intel_encoder = intel_connector->encoder;
2959         struct intel_dp_mst_encoder *intel_mst =
2960                 enc_to_mst(&intel_encoder->base);
2961         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2962         struct intel_dp *intel_dp = &intel_dig_port->dp;
2963         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2964                                         intel_connector->port);
2965
2966         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2967 }
2968
2969 static void intel_hdmi_info(struct seq_file *m,
2970                             struct intel_connector *intel_connector)
2971 {
2972         struct intel_encoder *intel_encoder = intel_connector->encoder;
2973         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2974
2975         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2976 }
2977
2978 static void intel_lvds_info(struct seq_file *m,
2979                             struct intel_connector *intel_connector)
2980 {
2981         intel_panel_info(m, &intel_connector->panel);
2982 }
2983
2984 static void intel_connector_info(struct seq_file *m,
2985                                  struct drm_connector *connector)
2986 {
2987         struct intel_connector *intel_connector = to_intel_connector(connector);
2988         struct intel_encoder *intel_encoder = intel_connector->encoder;
2989         struct drm_display_mode *mode;
2990
2991         seq_printf(m, "connector %d: type %s, status: %s\n",
2992                    connector->base.id, connector->name,
2993                    drm_get_connector_status_name(connector->status));
2994         if (connector->status == connector_status_connected) {
2995                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2996                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2997                            connector->display_info.width_mm,
2998                            connector->display_info.height_mm);
2999                 seq_printf(m, "\tsubpixel order: %s\n",
3000                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3001                 seq_printf(m, "\tCEA rev: %d\n",
3002                            connector->display_info.cea_rev);
3003         }
3004
3005         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3006                 return;
3007
3008         switch (connector->connector_type) {
3009         case DRM_MODE_CONNECTOR_DisplayPort:
3010         case DRM_MODE_CONNECTOR_eDP:
3011                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3012                         intel_dp_mst_info(m, intel_connector);
3013                 else
3014                         intel_dp_info(m, intel_connector);
3015                 break;
3016         case DRM_MODE_CONNECTOR_LVDS:
3017                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3018                         intel_lvds_info(m, intel_connector);
3019                 break;
3020         case DRM_MODE_CONNECTOR_HDMIA:
3021                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3022                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3023                         intel_hdmi_info(m, intel_connector);
3024                 break;
3025         default:
3026                 break;
3027         }
3028
3029         seq_printf(m, "\tmodes:\n");
3030         list_for_each_entry(mode, &connector->modes, head)
3031                 intel_seq_print_mode(m, 2, mode);
3032 }
3033
3034 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
3035 {
3036         u32 state;
3037
3038         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
3039                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3040         else
3041                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3042
3043         return state;
3044 }
3045
3046 static bool cursor_position(struct drm_i915_private *dev_priv,
3047                             int pipe, int *x, int *y)
3048 {
3049         u32 pos;
3050
3051         pos = I915_READ(CURPOS(pipe));
3052
3053         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3054         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3055                 *x = -*x;
3056
3057         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3058         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3059                 *y = -*y;
3060
3061         return cursor_active(dev_priv, pipe);
3062 }
3063
3064 static const char *plane_type(enum drm_plane_type type)
3065 {
3066         switch (type) {
3067         case DRM_PLANE_TYPE_OVERLAY:
3068                 return "OVL";
3069         case DRM_PLANE_TYPE_PRIMARY:
3070                 return "PRI";
3071         case DRM_PLANE_TYPE_CURSOR:
3072                 return "CUR";
3073         /*
3074          * Deliberately omitting default: to generate compiler warnings
3075          * when a new drm_plane_type gets added.
3076          */
3077         }
3078
3079         return "unknown";
3080 }
3081
3082 static const char *plane_rotation(unsigned int rotation)
3083 {
3084         static char buf[48];
3085         /*
3086          * According to doc only one DRM_ROTATE_ is allowed but this
3087          * will print them all to visualize if the values are misused
3088          */
3089         snprintf(buf, sizeof(buf),
3090                  "%s%s%s%s%s%s(0x%08x)",
3091                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3092                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3093                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3094                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3095                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3096                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3097                  rotation);
3098
3099         return buf;
3100 }
3101
3102 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3103 {
3104         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3105         struct drm_device *dev = &dev_priv->drm;
3106         struct intel_plane *intel_plane;
3107
3108         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3109                 struct drm_plane_state *state;
3110                 struct drm_plane *plane = &intel_plane->base;
3111                 struct drm_format_name_buf format_name;
3112
3113                 if (!plane->state) {
3114                         seq_puts(m, "plane->state is NULL!\n");
3115                         continue;
3116                 }
3117
3118                 state = plane->state;
3119
3120                 if (state->fb) {
3121                         drm_get_format_name(state->fb->format->format,
3122                                             &format_name);
3123                 } else {
3124                         sprintf(format_name.str, "N/A");
3125                 }
3126
3127                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3128                            plane->base.id,
3129                            plane_type(intel_plane->base.type),
3130                            state->crtc_x, state->crtc_y,
3131                            state->crtc_w, state->crtc_h,
3132                            (state->src_x >> 16),
3133                            ((state->src_x & 0xffff) * 15625) >> 10,
3134                            (state->src_y >> 16),
3135                            ((state->src_y & 0xffff) * 15625) >> 10,
3136                            (state->src_w >> 16),
3137                            ((state->src_w & 0xffff) * 15625) >> 10,
3138                            (state->src_h >> 16),
3139                            ((state->src_h & 0xffff) * 15625) >> 10,
3140                            format_name.str,
3141                            plane_rotation(state->rotation));
3142         }
3143 }
3144
3145 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3146 {
3147         struct intel_crtc_state *pipe_config;
3148         int num_scalers = intel_crtc->num_scalers;
3149         int i;
3150
3151         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3152
3153         /* Not all platformas have a scaler */
3154         if (num_scalers) {
3155                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3156                            num_scalers,
3157                            pipe_config->scaler_state.scaler_users,
3158                            pipe_config->scaler_state.scaler_id);
3159
3160                 for (i = 0; i < num_scalers; i++) {
3161                         struct intel_scaler *sc =
3162                                         &pipe_config->scaler_state.scalers[i];
3163
3164                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3165                                    i, yesno(sc->in_use), sc->mode);
3166                 }
3167                 seq_puts(m, "\n");
3168         } else {
3169                 seq_puts(m, "\tNo scalers available on this platform\n");
3170         }
3171 }
3172
3173 static int i915_display_info(struct seq_file *m, void *unused)
3174 {
3175         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3176         struct drm_device *dev = &dev_priv->drm;
3177         struct intel_crtc *crtc;
3178         struct drm_connector *connector;
3179
3180         intel_runtime_pm_get(dev_priv);
3181         drm_modeset_lock_all(dev);
3182         seq_printf(m, "CRTC info\n");
3183         seq_printf(m, "---------\n");
3184         for_each_intel_crtc(dev, crtc) {
3185                 bool active;
3186                 struct intel_crtc_state *pipe_config;
3187                 int x, y;
3188
3189                 pipe_config = to_intel_crtc_state(crtc->base.state);
3190
3191                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3192                            crtc->base.base.id, pipe_name(crtc->pipe),
3193                            yesno(pipe_config->base.active),
3194                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3195                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3196
3197                 if (pipe_config->base.active) {
3198                         intel_crtc_info(m, crtc);
3199
3200                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3201                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3202                                    yesno(crtc->cursor_base),
3203                                    x, y, crtc->base.cursor->state->crtc_w,
3204                                    crtc->base.cursor->state->crtc_h,
3205                                    crtc->cursor_addr, yesno(active));
3206                         intel_scaler_info(m, crtc);
3207                         intel_plane_info(m, crtc);
3208                 }
3209
3210                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3211                            yesno(!crtc->cpu_fifo_underrun_disabled),
3212                            yesno(!crtc->pch_fifo_underrun_disabled));
3213         }
3214
3215         seq_printf(m, "\n");
3216         seq_printf(m, "Connector info\n");
3217         seq_printf(m, "--------------\n");
3218         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3219                 intel_connector_info(m, connector);
3220         }
3221         drm_modeset_unlock_all(dev);
3222         intel_runtime_pm_put(dev_priv);
3223
3224         return 0;
3225 }
3226
3227 static int i915_engine_info(struct seq_file *m, void *unused)
3228 {
3229         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3230         struct intel_engine_cs *engine;
3231         enum intel_engine_id id;
3232
3233         intel_runtime_pm_get(dev_priv);
3234
3235         seq_printf(m, "GT awake? %s\n",
3236                    yesno(dev_priv->gt.awake));
3237         seq_printf(m, "Global active requests: %d\n",
3238                    dev_priv->gt.active_requests);
3239
3240         for_each_engine(engine, dev_priv, id) {
3241                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3242                 struct drm_i915_gem_request *rq;
3243                 struct rb_node *rb;
3244                 u64 addr;
3245
3246                 seq_printf(m, "%s\n", engine->name);
3247                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
3248                            intel_engine_get_seqno(engine),
3249                            intel_engine_last_submit(engine),
3250                            engine->hangcheck.seqno,
3251                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
3252                            engine->timeline->inflight_seqnos);
3253
3254                 rcu_read_lock();
3255
3256                 seq_printf(m, "\tRequests:\n");
3257
3258                 rq = list_first_entry(&engine->timeline->requests,
3259                                       struct drm_i915_gem_request, link);
3260                 if (&rq->link != &engine->timeline->requests)
3261                         print_request(m, rq, "\t\tfirst  ");
3262
3263                 rq = list_last_entry(&engine->timeline->requests,
3264                                      struct drm_i915_gem_request, link);
3265                 if (&rq->link != &engine->timeline->requests)
3266                         print_request(m, rq, "\t\tlast   ");
3267
3268                 rq = i915_gem_find_active_request(engine);
3269                 if (rq) {
3270                         print_request(m, rq, "\t\tactive ");
3271                         seq_printf(m,
3272                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3273                                    rq->head, rq->postfix, rq->tail,
3274                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3275                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3276                 }
3277
3278                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3279                            I915_READ(RING_START(engine->mmio_base)),
3280                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3281                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3282                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3283                            rq ? rq->ring->head : 0);
3284                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3285                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3286                            rq ? rq->ring->tail : 0);
3287                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3288                            I915_READ(RING_CTL(engine->mmio_base)),
3289                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3290
3291                 rcu_read_unlock();
3292
3293                 addr = intel_engine_get_active_head(engine);
3294                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3295                            upper_32_bits(addr), lower_32_bits(addr));
3296                 addr = intel_engine_get_last_batch_head(engine);
3297                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3298                            upper_32_bits(addr), lower_32_bits(addr));
3299
3300                 if (i915.enable_execlists) {
3301                         u32 ptr, read, write;
3302                         struct rb_node *rb;
3303
3304                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3305                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3306                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3307
3308                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3309                         read = GEN8_CSB_READ_PTR(ptr);
3310                         write = GEN8_CSB_WRITE_PTR(ptr);
3311                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3312                                    read, write);
3313                         if (read >= GEN8_CSB_ENTRIES)
3314                                 read = 0;
3315                         if (write >= GEN8_CSB_ENTRIES)
3316                                 write = 0;
3317                         if (read > write)
3318                                 write += GEN8_CSB_ENTRIES;
3319                         while (read < write) {
3320                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3321
3322                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3323                                            idx,
3324                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3325                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3326                         }
3327
3328                         rcu_read_lock();
3329                         rq = READ_ONCE(engine->execlist_port[0].request);
3330                         if (rq) {
3331                                 seq_printf(m, "\t\tELSP[0] count=%d, ",
3332                                            engine->execlist_port[0].count);
3333                                 print_request(m, rq, "rq: ");
3334                         } else {
3335                                 seq_printf(m, "\t\tELSP[0] idle\n");
3336                         }
3337                         rq = READ_ONCE(engine->execlist_port[1].request);
3338                         if (rq) {
3339                                 seq_printf(m, "\t\tELSP[1] count=%d, ",
3340                                            engine->execlist_port[1].count);
3341                                 print_request(m, rq, "rq: ");
3342                         } else {
3343                                 seq_printf(m, "\t\tELSP[1] idle\n");
3344                         }
3345                         rcu_read_unlock();
3346
3347                         spin_lock_irq(&engine->timeline->lock);
3348                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3349                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3350                                 print_request(m, rq, "\t\tQ ");
3351                         }
3352                         spin_unlock_irq(&engine->timeline->lock);
3353                 } else if (INTEL_GEN(dev_priv) > 6) {
3354                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3355                                    I915_READ(RING_PP_DIR_BASE(engine)));
3356                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3357                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3358                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3359                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3360                 }
3361
3362                 spin_lock_irq(&b->rb_lock);
3363                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3364                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
3365
3366                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3367                                    w->tsk->comm, w->tsk->pid, w->seqno);
3368                 }
3369                 spin_unlock_irq(&b->rb_lock);
3370
3371                 seq_puts(m, "\n");
3372         }
3373
3374         intel_runtime_pm_put(dev_priv);
3375
3376         return 0;
3377 }
3378
3379 static int i915_semaphore_status(struct seq_file *m, void *unused)
3380 {
3381         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3382         struct drm_device *dev = &dev_priv->drm;
3383         struct intel_engine_cs *engine;
3384         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3385         enum intel_engine_id id;
3386         int j, ret;
3387
3388         if (!i915.semaphores) {
3389                 seq_puts(m, "Semaphores are disabled\n");
3390                 return 0;
3391         }
3392
3393         ret = mutex_lock_interruptible(&dev->struct_mutex);
3394         if (ret)
3395                 return ret;
3396         intel_runtime_pm_get(dev_priv);
3397
3398         if (IS_BROADWELL(dev_priv)) {
3399                 struct page *page;
3400                 uint64_t *seqno;
3401
3402                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3403
3404                 seqno = (uint64_t *)kmap_atomic(page);
3405                 for_each_engine(engine, dev_priv, id) {
3406                         uint64_t offset;
3407
3408                         seq_printf(m, "%s\n", engine->name);
3409
3410                         seq_puts(m, "  Last signal:");
3411                         for (j = 0; j < num_rings; j++) {
3412                                 offset = id * I915_NUM_ENGINES + j;
3413                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3414                                            seqno[offset], offset * 8);
3415                         }
3416                         seq_putc(m, '\n');
3417
3418                         seq_puts(m, "  Last wait:  ");
3419                         for (j = 0; j < num_rings; j++) {
3420                                 offset = id + (j * I915_NUM_ENGINES);
3421                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3422                                            seqno[offset], offset * 8);
3423                         }
3424                         seq_putc(m, '\n');
3425
3426                 }
3427                 kunmap_atomic(seqno);
3428         } else {
3429                 seq_puts(m, "  Last signal:");
3430                 for_each_engine(engine, dev_priv, id)
3431                         for (j = 0; j < num_rings; j++)
3432                                 seq_printf(m, "0x%08x\n",
3433                                            I915_READ(engine->semaphore.mbox.signal[j]));
3434                 seq_putc(m, '\n');
3435         }
3436
3437         intel_runtime_pm_put(dev_priv);
3438         mutex_unlock(&dev->struct_mutex);
3439         return 0;
3440 }
3441
3442 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3443 {
3444         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3445         struct drm_device *dev = &dev_priv->drm;
3446         int i;
3447
3448         drm_modeset_lock_all(dev);
3449         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3450                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3451
3452                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3453                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3454                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3455                 seq_printf(m, " tracked hardware state:\n");
3456                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3457                 seq_printf(m, " dpll_md: 0x%08x\n",
3458                            pll->state.hw_state.dpll_md);
3459                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3460                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3461                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3462         }
3463         drm_modeset_unlock_all(dev);
3464
3465         return 0;
3466 }
3467
3468 static int i915_wa_registers(struct seq_file *m, void *unused)
3469 {
3470         int i;
3471         int ret;
3472         struct intel_engine_cs *engine;
3473         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3474         struct drm_device *dev = &dev_priv->drm;
3475         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3476         enum intel_engine_id id;
3477
3478         ret = mutex_lock_interruptible(&dev->struct_mutex);
3479         if (ret)
3480                 return ret;
3481
3482         intel_runtime_pm_get(dev_priv);
3483
3484         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3485         for_each_engine(engine, dev_priv, id)
3486                 seq_printf(m, "HW whitelist count for %s: %d\n",
3487                            engine->name, workarounds->hw_whitelist_count[id]);
3488         for (i = 0; i < workarounds->count; ++i) {
3489                 i915_reg_t addr;
3490                 u32 mask, value, read;
3491                 bool ok;
3492
3493                 addr = workarounds->reg[i].addr;
3494                 mask = workarounds->reg[i].mask;
3495                 value = workarounds->reg[i].value;
3496                 read = I915_READ(addr);
3497                 ok = (value & mask) == (read & mask);
3498                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3499                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3500         }
3501
3502         intel_runtime_pm_put(dev_priv);
3503         mutex_unlock(&dev->struct_mutex);
3504
3505         return 0;
3506 }
3507
3508 static int i915_ddb_info(struct seq_file *m, void *unused)
3509 {
3510         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3511         struct drm_device *dev = &dev_priv->drm;
3512         struct skl_ddb_allocation *ddb;
3513         struct skl_ddb_entry *entry;
3514         enum pipe pipe;
3515         int plane;
3516
3517         if (INTEL_GEN(dev_priv) < 9)
3518                 return 0;
3519
3520         drm_modeset_lock_all(dev);
3521
3522         ddb = &dev_priv->wm.skl_hw.ddb;
3523
3524         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3525
3526         for_each_pipe(dev_priv, pipe) {
3527                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3528
3529                 for_each_universal_plane(dev_priv, pipe, plane) {
3530                         entry = &ddb->plane[pipe][plane];
3531                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3532                                    entry->start, entry->end,
3533                                    skl_ddb_entry_size(entry));
3534                 }
3535
3536                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3537                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3538                            entry->end, skl_ddb_entry_size(entry));
3539         }
3540
3541         drm_modeset_unlock_all(dev);
3542
3543         return 0;
3544 }
3545
3546 static void drrs_status_per_crtc(struct seq_file *m,
3547                                  struct drm_device *dev,
3548                                  struct intel_crtc *intel_crtc)
3549 {
3550         struct drm_i915_private *dev_priv = to_i915(dev);
3551         struct i915_drrs *drrs = &dev_priv->drrs;
3552         int vrefresh = 0;
3553         struct drm_connector *connector;
3554
3555         drm_for_each_connector(connector, dev) {
3556                 if (connector->state->crtc != &intel_crtc->base)
3557                         continue;
3558
3559                 seq_printf(m, "%s:\n", connector->name);
3560         }
3561
3562         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3563                 seq_puts(m, "\tVBT: DRRS_type: Static");
3564         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3565                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3566         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3567                 seq_puts(m, "\tVBT: DRRS_type: None");
3568         else
3569                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3570
3571         seq_puts(m, "\n\n");
3572
3573         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3574                 struct intel_panel *panel;
3575
3576                 mutex_lock(&drrs->mutex);
3577                 /* DRRS Supported */
3578                 seq_puts(m, "\tDRRS Supported: Yes\n");
3579
3580                 /* disable_drrs() will make drrs->dp NULL */
3581                 if (!drrs->dp) {
3582                         seq_puts(m, "Idleness DRRS: Disabled");
3583                         mutex_unlock(&drrs->mutex);
3584                         return;
3585                 }
3586
3587                 panel = &drrs->dp->attached_connector->panel;
3588                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3589                                         drrs->busy_frontbuffer_bits);
3590
3591                 seq_puts(m, "\n\t\t");
3592                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3593                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3594                         vrefresh = panel->fixed_mode->vrefresh;
3595                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3596                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3597                         vrefresh = panel->downclock_mode->vrefresh;
3598                 } else {
3599                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3600                                                 drrs->refresh_rate_type);
3601                         mutex_unlock(&drrs->mutex);
3602                         return;
3603                 }
3604                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3605
3606                 seq_puts(m, "\n\t\t");
3607                 mutex_unlock(&drrs->mutex);
3608         } else {
3609                 /* DRRS not supported. Print the VBT parameter*/
3610                 seq_puts(m, "\tDRRS Supported : No");
3611         }
3612         seq_puts(m, "\n");
3613 }
3614
3615 static int i915_drrs_status(struct seq_file *m, void *unused)
3616 {
3617         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3618         struct drm_device *dev = &dev_priv->drm;
3619         struct intel_crtc *intel_crtc;
3620         int active_crtc_cnt = 0;
3621
3622         drm_modeset_lock_all(dev);
3623         for_each_intel_crtc(dev, intel_crtc) {
3624                 if (intel_crtc->base.state->active) {
3625                         active_crtc_cnt++;
3626                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3627
3628                         drrs_status_per_crtc(m, dev, intel_crtc);
3629                 }
3630         }
3631         drm_modeset_unlock_all(dev);
3632
3633         if (!active_crtc_cnt)
3634                 seq_puts(m, "No active crtc found\n");
3635
3636         return 0;
3637 }
3638
3639 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3640 {
3641         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3642         struct drm_device *dev = &dev_priv->drm;
3643         struct intel_encoder *intel_encoder;
3644         struct intel_digital_port *intel_dig_port;
3645         struct drm_connector *connector;
3646
3647         drm_modeset_lock_all(dev);
3648         drm_for_each_connector(connector, dev) {
3649                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3650                         continue;
3651
3652                 intel_encoder = intel_attached_encoder(connector);
3653                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3654                         continue;
3655
3656                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3657                 if (!intel_dig_port->dp.can_mst)
3658                         continue;
3659
3660                 seq_printf(m, "MST Source Port %c\n",
3661                            port_name(intel_dig_port->port));
3662                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3663         }
3664         drm_modeset_unlock_all(dev);
3665         return 0;
3666 }
3667
3668 static ssize_t i915_displayport_test_active_write(struct file *file,
3669                                                   const char __user *ubuf,
3670                                                   size_t len, loff_t *offp)
3671 {
3672         char *input_buffer;
3673         int status = 0;
3674         struct drm_device *dev;
3675         struct drm_connector *connector;
3676         struct list_head *connector_list;
3677         struct intel_dp *intel_dp;
3678         int val = 0;
3679
3680         dev = ((struct seq_file *)file->private_data)->private;
3681
3682         connector_list = &dev->mode_config.connector_list;
3683
3684         if (len == 0)
3685                 return 0;
3686
3687         input_buffer = kmalloc(len + 1, GFP_KERNEL);
3688         if (!input_buffer)
3689                 return -ENOMEM;
3690
3691         if (copy_from_user(input_buffer, ubuf, len)) {
3692                 status = -EFAULT;
3693                 goto out;
3694         }
3695
3696         input_buffer[len] = '\0';
3697         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3698
3699         list_for_each_entry(connector, connector_list, head) {
3700                 if (connector->connector_type !=
3701                     DRM_MODE_CONNECTOR_DisplayPort)
3702                         continue;
3703
3704                 if (connector->status == connector_status_connected &&
3705                     connector->encoder != NULL) {
3706                         intel_dp = enc_to_intel_dp(connector->encoder);
3707                         status = kstrtoint(input_buffer, 10, &val);
3708                         if (status < 0)
3709                                 goto out;
3710                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3711                         /* To prevent erroneous activation of the compliance
3712                          * testing code, only accept an actual value of 1 here
3713                          */
3714                         if (val == 1)
3715                                 intel_dp->compliance.test_active = 1;
3716                         else
3717                                 intel_dp->compliance.test_active = 0;
3718                 }
3719         }
3720 out:
3721         kfree(input_buffer);
3722         if (status < 0)
3723                 return status;
3724
3725         *offp += len;
3726         return len;
3727 }
3728
3729 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3730 {
3731         struct drm_device *dev = m->private;
3732         struct drm_connector *connector;
3733         struct list_head *connector_list = &dev->mode_config.connector_list;
3734         struct intel_dp *intel_dp;
3735
3736         list_for_each_entry(connector, connector_list, head) {
3737                 if (connector->connector_type !=
3738                     DRM_MODE_CONNECTOR_DisplayPort)
3739                         continue;
3740
3741                 if (connector->status == connector_status_connected &&
3742                     connector->encoder != NULL) {
3743                         intel_dp = enc_to_intel_dp(connector->encoder);
3744                         if (intel_dp->compliance.test_active)
3745                                 seq_puts(m, "1");
3746                         else
3747                                 seq_puts(m, "0");
3748                 } else
3749                         seq_puts(m, "0");
3750         }
3751
3752         return 0;
3753 }
3754
3755 static int i915_displayport_test_active_open(struct inode *inode,
3756                                              struct file *file)
3757 {
3758         struct drm_i915_private *dev_priv = inode->i_private;
3759
3760         return single_open(file, i915_displayport_test_active_show,
3761                            &dev_priv->drm);
3762 }
3763
3764 static const struct file_operations i915_displayport_test_active_fops = {
3765         .owner = THIS_MODULE,
3766         .open = i915_displayport_test_active_open,
3767         .read = seq_read,
3768         .llseek = seq_lseek,
3769         .release = single_release,
3770         .write = i915_displayport_test_active_write
3771 };
3772
3773 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3774 {
3775         struct drm_device *dev = m->private;
3776         struct drm_connector *connector;
3777         struct list_head *connector_list = &dev->mode_config.connector_list;
3778         struct intel_dp *intel_dp;
3779
3780         list_for_each_entry(connector, connector_list, head) {
3781                 if (connector->connector_type !=
3782                     DRM_MODE_CONNECTOR_DisplayPort)
3783                         continue;
3784
3785                 if (connector->status == connector_status_connected &&
3786                     connector->encoder != NULL) {
3787                         intel_dp = enc_to_intel_dp(connector->encoder);
3788                         if (intel_dp->compliance.test_type ==
3789                             DP_TEST_LINK_EDID_READ)
3790                                 seq_printf(m, "%lx",
3791                                            intel_dp->compliance.test_data.edid);
3792                         else if (intel_dp->compliance.test_type ==
3793                                  DP_TEST_LINK_VIDEO_PATTERN) {
3794                                 seq_printf(m, "hdisplay: %d\n",
3795                                            intel_dp->compliance.test_data.hdisplay);
3796                                 seq_printf(m, "vdisplay: %d\n",
3797                                            intel_dp->compliance.test_data.vdisplay);
3798                                 seq_printf(m, "bpc: %u\n",
3799                                            intel_dp->compliance.test_data.bpc);
3800                         }
3801                 } else
3802                         seq_puts(m, "0");
3803         }
3804
3805         return 0;
3806 }
3807 static int i915_displayport_test_data_open(struct inode *inode,
3808                                            struct file *file)
3809 {
3810         struct drm_i915_private *dev_priv = inode->i_private;
3811
3812         return single_open(file, i915_displayport_test_data_show,
3813                            &dev_priv->drm);
3814 }
3815
3816 static const struct file_operations i915_displayport_test_data_fops = {
3817         .owner = THIS_MODULE,
3818         .open = i915_displayport_test_data_open,
3819         .read = seq_read,
3820         .llseek = seq_lseek,
3821         .release = single_release
3822 };
3823
3824 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3825 {
3826         struct drm_device *dev = m->private;
3827         struct drm_connector *connector;
3828         struct list_head *connector_list = &dev->mode_config.connector_list;
3829         struct intel_dp *intel_dp;
3830
3831         list_for_each_entry(connector, connector_list, head) {
3832                 if (connector->connector_type !=
3833                     DRM_MODE_CONNECTOR_DisplayPort)
3834                         continue;
3835
3836                 if (connector->status == connector_status_connected &&
3837                     connector->encoder != NULL) {
3838                         intel_dp = enc_to_intel_dp(connector->encoder);
3839                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3840                 } else
3841                         seq_puts(m, "0");
3842         }
3843
3844         return 0;
3845 }
3846
3847 static int i915_displayport_test_type_open(struct inode *inode,
3848                                        struct file *file)
3849 {
3850         struct drm_i915_private *dev_priv = inode->i_private;
3851
3852         return single_open(file, i915_displayport_test_type_show,
3853                            &dev_priv->drm);
3854 }
3855
3856 static const struct file_operations i915_displayport_test_type_fops = {
3857         .owner = THIS_MODULE,
3858         .open = i915_displayport_test_type_open,
3859         .read = seq_read,
3860         .llseek = seq_lseek,
3861         .release = single_release
3862 };
3863
3864 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3865 {
3866         struct drm_i915_private *dev_priv = m->private;
3867         struct drm_device *dev = &dev_priv->drm;
3868         int level;
3869         int num_levels;
3870
3871         if (IS_CHERRYVIEW(dev_priv))
3872                 num_levels = 3;
3873         else if (IS_VALLEYVIEW(dev_priv))
3874                 num_levels = 1;
3875         else
3876                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3877
3878         drm_modeset_lock_all(dev);
3879
3880         for (level = 0; level < num_levels; level++) {
3881                 unsigned int latency = wm[level];
3882
3883                 /*
3884                  * - WM1+ latency values in 0.5us units
3885                  * - latencies are in us on gen9/vlv/chv
3886                  */
3887                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
3888                     IS_CHERRYVIEW(dev_priv))
3889                         latency *= 10;
3890                 else if (level > 0)
3891                         latency *= 5;
3892
3893                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3894                            level, wm[level], latency / 10, latency % 10);
3895         }
3896
3897         drm_modeset_unlock_all(dev);
3898 }
3899
3900 static int pri_wm_latency_show(struct seq_file *m, void *data)
3901 {
3902         struct drm_i915_private *dev_priv = m->private;
3903         const uint16_t *latencies;
3904
3905         if (INTEL_GEN(dev_priv) >= 9)
3906                 latencies = dev_priv->wm.skl_latency;
3907         else
3908                 latencies = dev_priv->wm.pri_latency;
3909
3910         wm_latency_show(m, latencies);
3911
3912         return 0;
3913 }
3914
3915 static int spr_wm_latency_show(struct seq_file *m, void *data)
3916 {
3917         struct drm_i915_private *dev_priv = m->private;
3918         const uint16_t *latencies;
3919
3920         if (INTEL_GEN(dev_priv) >= 9)
3921                 latencies = dev_priv->wm.skl_latency;
3922         else
3923                 latencies = dev_priv->wm.spr_latency;
3924
3925         wm_latency_show(m, latencies);
3926
3927         return 0;
3928 }
3929
3930 static int cur_wm_latency_show(struct seq_file *m, void *data)
3931 {
3932         struct drm_i915_private *dev_priv = m->private;
3933         const uint16_t *latencies;
3934
3935         if (INTEL_GEN(dev_priv) >= 9)
3936                 latencies = dev_priv->wm.skl_latency;
3937         else
3938                 latencies = dev_priv->wm.cur_latency;
3939
3940         wm_latency_show(m, latencies);
3941
3942         return 0;
3943 }
3944
3945 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3946 {
3947         struct drm_i915_private *dev_priv = inode->i_private;
3948
3949         if (INTEL_GEN(dev_priv) < 5)
3950                 return -ENODEV;
3951
3952         return single_open(file, pri_wm_latency_show, dev_priv);
3953 }
3954
3955 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3956 {
3957         struct drm_i915_private *dev_priv = inode->i_private;
3958
3959         if (HAS_GMCH_DISPLAY(dev_priv))
3960                 return -ENODEV;
3961
3962         return single_open(file, spr_wm_latency_show, dev_priv);
3963 }
3964
3965 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3966 {
3967         struct drm_i915_private *dev_priv = inode->i_private;
3968
3969         if (HAS_GMCH_DISPLAY(dev_priv))
3970                 return -ENODEV;
3971
3972         return single_open(file, cur_wm_latency_show, dev_priv);
3973 }
3974
3975 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3976                                 size_t len, loff_t *offp, uint16_t wm[8])
3977 {
3978         struct seq_file *m = file->private_data;
3979         struct drm_i915_private *dev_priv = m->private;
3980         struct drm_device *dev = &dev_priv->drm;
3981         uint16_t new[8] = { 0 };
3982         int num_levels;
3983         int level;
3984         int ret;
3985         char tmp[32];
3986
3987         if (IS_CHERRYVIEW(dev_priv))
3988                 num_levels = 3;
3989         else if (IS_VALLEYVIEW(dev_priv))
3990                 num_levels = 1;
3991         else
3992                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3993
3994         if (len >= sizeof(tmp))
3995                 return -EINVAL;
3996
3997         if (copy_from_user(tmp, ubuf, len))
3998                 return -EFAULT;
3999
4000         tmp[len] = '\0';
4001
4002         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4003                      &new[0], &new[1], &new[2], &new[3],
4004                      &new[4], &new[5], &new[6], &new[7]);
4005         if (ret != num_levels)
4006                 return -EINVAL;
4007
4008         drm_modeset_lock_all(dev);
4009
4010         for (level = 0; level < num_levels; level++)
4011                 wm[level] = new[level];
4012
4013         drm_modeset_unlock_all(dev);
4014
4015         return len;
4016 }
4017
4018
4019 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4020                                     size_t len, loff_t *offp)
4021 {
4022         struct seq_file *m = file->private_data;
4023         struct drm_i915_private *dev_priv = m->private;
4024         uint16_t *latencies;
4025
4026         if (INTEL_GEN(dev_priv) >= 9)
4027                 latencies = dev_priv->wm.skl_latency;
4028         else
4029                 latencies = dev_priv->wm.pri_latency;
4030
4031         return wm_latency_write(file, ubuf, len, offp, latencies);
4032 }
4033
4034 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4035                                     size_t len, loff_t *offp)
4036 {
4037         struct seq_file *m = file->private_data;
4038         struct drm_i915_private *dev_priv = m->private;
4039         uint16_t *latencies;
4040
4041         if (INTEL_GEN(dev_priv) >= 9)
4042                 latencies = dev_priv->wm.skl_latency;
4043         else
4044                 latencies = dev_priv->wm.spr_latency;
4045
4046         return wm_latency_write(file, ubuf, len, offp, latencies);
4047 }
4048
4049 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4050                                     size_t len, loff_t *offp)
4051 {
4052         struct seq_file *m = file->private_data;
4053         struct drm_i915_private *dev_priv = m->private;
4054         uint16_t *latencies;
4055
4056         if (INTEL_GEN(dev_priv) >= 9)
4057                 latencies = dev_priv->wm.skl_latency;
4058         else
4059                 latencies = dev_priv->wm.cur_latency;
4060
4061         return wm_latency_write(file, ubuf, len, offp, latencies);
4062 }
4063
4064 static const struct file_operations i915_pri_wm_latency_fops = {
4065         .owner = THIS_MODULE,
4066         .open = pri_wm_latency_open,
4067         .read = seq_read,
4068         .llseek = seq_lseek,
4069         .release = single_release,
4070         .write = pri_wm_latency_write
4071 };
4072
4073 static const struct file_operations i915_spr_wm_latency_fops = {
4074         .owner = THIS_MODULE,
4075         .open = spr_wm_latency_open,
4076         .read = seq_read,
4077         .llseek = seq_lseek,
4078         .release = single_release,
4079         .write = spr_wm_latency_write
4080 };
4081
4082 static const struct file_operations i915_cur_wm_latency_fops = {
4083         .owner = THIS_MODULE,
4084         .open = cur_wm_latency_open,
4085         .read = seq_read,
4086         .llseek = seq_lseek,
4087         .release = single_release,
4088         .write = cur_wm_latency_write
4089 };
4090
4091 static int
4092 i915_wedged_get(void *data, u64 *val)
4093 {
4094         struct drm_i915_private *dev_priv = data;
4095
4096         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4097
4098         return 0;
4099 }
4100
4101 static int
4102 i915_wedged_set(void *data, u64 val)
4103 {
4104         struct drm_i915_private *dev_priv = data;
4105
4106         /*
4107          * There is no safeguard against this debugfs entry colliding
4108          * with the hangcheck calling same i915_handle_error() in
4109          * parallel, causing an explosion. For now we assume that the
4110          * test harness is responsible enough not to inject gpu hangs
4111          * while it is writing to 'i915_wedged'
4112          */
4113
4114         if (i915_reset_in_progress(&dev_priv->gpu_error))
4115                 return -EAGAIN;
4116
4117         i915_handle_error(dev_priv, val,
4118                           "Manually setting wedged to %llu", val);
4119
4120         return 0;
4121 }
4122
4123 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4124                         i915_wedged_get, i915_wedged_set,
4125                         "%llu\n");
4126
4127 static int
4128 i915_ring_missed_irq_get(void *data, u64 *val)
4129 {
4130         struct drm_i915_private *dev_priv = data;
4131
4132         *val = dev_priv->gpu_error.missed_irq_rings;
4133         return 0;
4134 }
4135
4136 static int
4137 i915_ring_missed_irq_set(void *data, u64 val)
4138 {
4139         struct drm_i915_private *dev_priv = data;
4140         struct drm_device *dev = &dev_priv->drm;
4141         int ret;
4142
4143         /* Lock against concurrent debugfs callers */
4144         ret = mutex_lock_interruptible(&dev->struct_mutex);
4145         if (ret)
4146                 return ret;
4147         dev_priv->gpu_error.missed_irq_rings = val;
4148         mutex_unlock(&dev->struct_mutex);
4149
4150         return 0;
4151 }
4152
4153 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4154                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4155                         "0x%08llx\n");
4156
4157 static int
4158 i915_ring_test_irq_get(void *data, u64 *val)
4159 {
4160         struct drm_i915_private *dev_priv = data;
4161
4162         *val = dev_priv->gpu_error.test_irq_rings;
4163
4164         return 0;
4165 }
4166
4167 static int
4168 i915_ring_test_irq_set(void *data, u64 val)
4169 {
4170         struct drm_i915_private *dev_priv = data;
4171
4172         val &= INTEL_INFO(dev_priv)->ring_mask;
4173         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4174         dev_priv->gpu_error.test_irq_rings = val;
4175
4176         return 0;
4177 }
4178
4179 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4180                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4181                         "0x%08llx\n");
4182
4183 #define DROP_UNBOUND 0x1
4184 #define DROP_BOUND 0x2
4185 #define DROP_RETIRE 0x4
4186 #define DROP_ACTIVE 0x8
4187 #define DROP_FREED 0x10
4188 #define DROP_ALL (DROP_UNBOUND  | \
4189                   DROP_BOUND    | \
4190                   DROP_RETIRE   | \
4191                   DROP_ACTIVE   | \
4192                   DROP_FREED)
4193 static int
4194 i915_drop_caches_get(void *data, u64 *val)
4195 {
4196         *val = DROP_ALL;
4197
4198         return 0;
4199 }
4200
4201 static int
4202 i915_drop_caches_set(void *data, u64 val)
4203 {
4204         struct drm_i915_private *dev_priv = data;
4205         struct drm_device *dev = &dev_priv->drm;
4206         int ret;
4207
4208         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4209
4210         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4211          * on ioctls on -EAGAIN. */
4212         ret = mutex_lock_interruptible(&dev->struct_mutex);
4213         if (ret)
4214                 return ret;
4215
4216         if (val & DROP_ACTIVE) {
4217                 ret = i915_gem_wait_for_idle(dev_priv,
4218                                              I915_WAIT_INTERRUPTIBLE |
4219                                              I915_WAIT_LOCKED);
4220                 if (ret)
4221                         goto unlock;
4222         }
4223
4224         if (val & (DROP_RETIRE | DROP_ACTIVE))
4225                 i915_gem_retire_requests(dev_priv);
4226
4227         if (val & DROP_BOUND)
4228                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4229
4230         if (val & DROP_UNBOUND)
4231                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4232
4233 unlock:
4234         mutex_unlock(&dev->struct_mutex);
4235
4236         if (val & DROP_FREED) {
4237                 synchronize_rcu();
4238                 i915_gem_drain_freed_objects(dev_priv);
4239         }
4240
4241         return ret;
4242 }
4243
4244 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4245                         i915_drop_caches_get, i915_drop_caches_set,
4246                         "0x%08llx\n");
4247
4248 static int
4249 i915_max_freq_get(void *data, u64 *val)
4250 {
4251         struct drm_i915_private *dev_priv = data;
4252
4253         if (INTEL_GEN(dev_priv) < 6)
4254                 return -ENODEV;
4255
4256         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4257         return 0;
4258 }
4259
4260 static int
4261 i915_max_freq_set(void *data, u64 val)
4262 {
4263         struct drm_i915_private *dev_priv = data;
4264         u32 hw_max, hw_min;
4265         int ret;
4266
4267         if (INTEL_GEN(dev_priv) < 6)
4268                 return -ENODEV;
4269
4270         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4271
4272         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4273         if (ret)
4274                 return ret;
4275
4276         /*
4277          * Turbo will still be enabled, but won't go above the set value.
4278          */
4279         val = intel_freq_opcode(dev_priv, val);
4280
4281         hw_max = dev_priv->rps.max_freq;
4282         hw_min = dev_priv->rps.min_freq;
4283
4284         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4285                 mutex_unlock(&dev_priv->rps.hw_lock);
4286                 return -EINVAL;
4287         }
4288
4289         dev_priv->rps.max_freq_softlimit = val;
4290
4291         if (intel_set_rps(dev_priv, val))
4292                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4293
4294         mutex_unlock(&dev_priv->rps.hw_lock);
4295
4296         return 0;
4297 }
4298
4299 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4300                         i915_max_freq_get, i915_max_freq_set,
4301                         "%llu\n");
4302
4303 static int
4304 i915_min_freq_get(void *data, u64 *val)
4305 {
4306         struct drm_i915_private *dev_priv = data;
4307
4308         if (INTEL_GEN(dev_priv) < 6)
4309                 return -ENODEV;
4310
4311         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4312         return 0;
4313 }
4314
4315 static int
4316 i915_min_freq_set(void *data, u64 val)
4317 {
4318         struct drm_i915_private *dev_priv = data;
4319         u32 hw_max, hw_min;
4320         int ret;
4321
4322         if (INTEL_GEN(dev_priv) < 6)
4323                 return -ENODEV;
4324
4325         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4326
4327         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4328         if (ret)
4329                 return ret;
4330
4331         /*
4332          * Turbo will still be enabled, but won't go below the set value.
4333          */
4334         val = intel_freq_opcode(dev_priv, val);
4335
4336         hw_max = dev_priv->rps.max_freq;
4337         hw_min = dev_priv->rps.min_freq;
4338
4339         if (val < hw_min ||
4340             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4341                 mutex_unlock(&dev_priv->rps.hw_lock);
4342                 return -EINVAL;
4343         }
4344
4345         dev_priv->rps.min_freq_softlimit = val;
4346
4347         if (intel_set_rps(dev_priv, val))
4348                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4349
4350         mutex_unlock(&dev_priv->rps.hw_lock);
4351
4352         return 0;
4353 }
4354
4355 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4356                         i915_min_freq_get, i915_min_freq_set,
4357                         "%llu\n");
4358
4359 static int
4360 i915_cache_sharing_get(void *data, u64 *val)
4361 {
4362         struct drm_i915_private *dev_priv = data;
4363         u32 snpcr;
4364
4365         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4366                 return -ENODEV;
4367
4368         intel_runtime_pm_get(dev_priv);
4369
4370         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4371
4372         intel_runtime_pm_put(dev_priv);
4373
4374         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4375
4376         return 0;
4377 }
4378
4379 static int
4380 i915_cache_sharing_set(void *data, u64 val)
4381 {
4382         struct drm_i915_private *dev_priv = data;
4383         u32 snpcr;
4384
4385         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4386                 return -ENODEV;
4387
4388         if (val > 3)
4389                 return -EINVAL;
4390
4391         intel_runtime_pm_get(dev_priv);
4392         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4393
4394         /* Update the cache sharing policy here as well */
4395         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4396         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4397         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4398         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4399
4400         intel_runtime_pm_put(dev_priv);
4401         return 0;
4402 }
4403
4404 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4405                         i915_cache_sharing_get, i915_cache_sharing_set,
4406                         "%llu\n");
4407
4408 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4409                                           struct sseu_dev_info *sseu)
4410 {
4411         int ss_max = 2;
4412         int ss;
4413         u32 sig1[ss_max], sig2[ss_max];
4414
4415         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4416         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4417         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4418         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4419
4420         for (ss = 0; ss < ss_max; ss++) {
4421                 unsigned int eu_cnt;
4422
4423                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4424                         /* skip disabled subslice */
4425                         continue;
4426
4427                 sseu->slice_mask = BIT(0);
4428                 sseu->subslice_mask |= BIT(ss);
4429                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4430                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4431                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4432                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4433                 sseu->eu_total += eu_cnt;
4434                 sseu->eu_per_subslice = max_t(unsigned int,
4435                                               sseu->eu_per_subslice, eu_cnt);
4436         }
4437 }
4438
4439 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4440                                     struct sseu_dev_info *sseu)
4441 {
4442         int s_max = 3, ss_max = 4;
4443         int s, ss;
4444         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4445
4446         /* BXT has a single slice and at most 3 subslices. */
4447         if (IS_GEN9_LP(dev_priv)) {
4448                 s_max = 1;
4449                 ss_max = 3;
4450         }
4451
4452         for (s = 0; s < s_max; s++) {
4453                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4454                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4455                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4456         }
4457
4458         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4459                      GEN9_PGCTL_SSA_EU19_ACK |
4460                      GEN9_PGCTL_SSA_EU210_ACK |
4461                      GEN9_PGCTL_SSA_EU311_ACK;
4462         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4463                      GEN9_PGCTL_SSB_EU19_ACK |
4464                      GEN9_PGCTL_SSB_EU210_ACK |
4465                      GEN9_PGCTL_SSB_EU311_ACK;
4466
4467         for (s = 0; s < s_max; s++) {
4468                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4469                         /* skip disabled slice */
4470                         continue;
4471
4472                 sseu->slice_mask |= BIT(s);
4473
4474                 if (IS_GEN9_BC(dev_priv))
4475                         sseu->subslice_mask =
4476                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4477
4478                 for (ss = 0; ss < ss_max; ss++) {
4479                         unsigned int eu_cnt;
4480
4481                         if (IS_GEN9_LP(dev_priv)) {
4482                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4483                                         /* skip disabled subslice */
4484                                         continue;
4485
4486                                 sseu->subslice_mask |= BIT(ss);
4487                         }
4488
4489                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4490                                                eu_mask[ss%2]);
4491                         sseu->eu_total += eu_cnt;
4492                         sseu->eu_per_subslice = max_t(unsigned int,
4493                                                       sseu->eu_per_subslice,
4494                                                       eu_cnt);
4495                 }
4496         }
4497 }
4498
4499 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4500                                          struct sseu_dev_info *sseu)
4501 {
4502         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4503         int s;
4504
4505         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4506
4507         if (sseu->slice_mask) {
4508                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4509                 sseu->eu_per_subslice =
4510                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4511                 sseu->eu_total = sseu->eu_per_subslice *
4512                                  sseu_subslice_total(sseu);
4513
4514                 /* subtract fused off EU(s) from enabled slice(s) */
4515                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4516                         u8 subslice_7eu =
4517                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4518
4519                         sseu->eu_total -= hweight8(subslice_7eu);
4520                 }
4521         }
4522 }
4523
4524 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4525                                  const struct sseu_dev_info *sseu)
4526 {
4527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4528         const char *type = is_available_info ? "Available" : "Enabled";
4529
4530         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4531                    sseu->slice_mask);
4532         seq_printf(m, "  %s Slice Total: %u\n", type,
4533                    hweight8(sseu->slice_mask));
4534         seq_printf(m, "  %s Subslice Total: %u\n", type,
4535                    sseu_subslice_total(sseu));
4536         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4537                    sseu->subslice_mask);
4538         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4539                    hweight8(sseu->subslice_mask));
4540         seq_printf(m, "  %s EU Total: %u\n", type,
4541                    sseu->eu_total);
4542         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4543                    sseu->eu_per_subslice);
4544
4545         if (!is_available_info)
4546                 return;
4547
4548         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4549         if (HAS_POOLED_EU(dev_priv))
4550                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4551
4552         seq_printf(m, "  Has Slice Power Gating: %s\n",
4553                    yesno(sseu->has_slice_pg));
4554         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4555                    yesno(sseu->has_subslice_pg));
4556         seq_printf(m, "  Has EU Power Gating: %s\n",
4557                    yesno(sseu->has_eu_pg));
4558 }
4559
4560 static int i915_sseu_status(struct seq_file *m, void *unused)
4561 {
4562         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4563         struct sseu_dev_info sseu;
4564
4565         if (INTEL_GEN(dev_priv) < 8)
4566                 return -ENODEV;
4567
4568         seq_puts(m, "SSEU Device Info\n");
4569         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4570
4571         seq_puts(m, "SSEU Device Status\n");
4572         memset(&sseu, 0, sizeof(sseu));
4573
4574         intel_runtime_pm_get(dev_priv);
4575
4576         if (IS_CHERRYVIEW(dev_priv)) {
4577                 cherryview_sseu_device_status(dev_priv, &sseu);
4578         } else if (IS_BROADWELL(dev_priv)) {
4579                 broadwell_sseu_device_status(dev_priv, &sseu);
4580         } else if (INTEL_GEN(dev_priv) >= 9) {
4581                 gen9_sseu_device_status(dev_priv, &sseu);
4582         }
4583
4584         intel_runtime_pm_put(dev_priv);
4585
4586         i915_print_sseu_info(m, false, &sseu);
4587
4588         return 0;
4589 }
4590
4591 static int i915_forcewake_open(struct inode *inode, struct file *file)
4592 {
4593         struct drm_i915_private *dev_priv = inode->i_private;
4594
4595         if (INTEL_GEN(dev_priv) < 6)
4596                 return 0;
4597
4598         intel_runtime_pm_get(dev_priv);
4599         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4600
4601         return 0;
4602 }
4603
4604 static int i915_forcewake_release(struct inode *inode, struct file *file)
4605 {
4606         struct drm_i915_private *dev_priv = inode->i_private;
4607
4608         if (INTEL_GEN(dev_priv) < 6)
4609                 return 0;
4610
4611         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4612         intel_runtime_pm_put(dev_priv);
4613
4614         return 0;
4615 }
4616
4617 static const struct file_operations i915_forcewake_fops = {
4618         .owner = THIS_MODULE,
4619         .open = i915_forcewake_open,
4620         .release = i915_forcewake_release,
4621 };
4622
4623 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4624 {
4625         struct drm_i915_private *dev_priv = m->private;
4626         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4627
4628         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4629         seq_printf(m, "Detected: %s\n",
4630                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4631
4632         return 0;
4633 }
4634
4635 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4636                                         const char __user *ubuf, size_t len,
4637                                         loff_t *offp)
4638 {
4639         struct seq_file *m = file->private_data;
4640         struct drm_i915_private *dev_priv = m->private;
4641         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4642         unsigned int new_threshold;
4643         int i;
4644         char *newline;
4645         char tmp[16];
4646
4647         if (len >= sizeof(tmp))
4648                 return -EINVAL;
4649
4650         if (copy_from_user(tmp, ubuf, len))
4651                 return -EFAULT;
4652
4653         tmp[len] = '\0';
4654
4655         /* Strip newline, if any */
4656         newline = strchr(tmp, '\n');
4657         if (newline)
4658                 *newline = '\0';
4659
4660         if (strcmp(tmp, "reset") == 0)
4661                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4662         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4663                 return -EINVAL;
4664
4665         if (new_threshold > 0)
4666                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4667                               new_threshold);
4668         else
4669                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4670
4671         spin_lock_irq(&dev_priv->irq_lock);
4672         hotplug->hpd_storm_threshold = new_threshold;
4673         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4674         for_each_hpd_pin(i)
4675                 hotplug->stats[i].count = 0;
4676         spin_unlock_irq(&dev_priv->irq_lock);
4677
4678         /* Re-enable hpd immediately if we were in an irq storm */
4679         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4680
4681         return len;
4682 }
4683
4684 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4685 {
4686         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4687 }
4688
4689 static const struct file_operations i915_hpd_storm_ctl_fops = {
4690         .owner = THIS_MODULE,
4691         .open = i915_hpd_storm_ctl_open,
4692         .read = seq_read,
4693         .llseek = seq_lseek,
4694         .release = single_release,
4695         .write = i915_hpd_storm_ctl_write
4696 };
4697
4698 static const struct drm_info_list i915_debugfs_list[] = {
4699         {"i915_capabilities", i915_capabilities, 0},
4700         {"i915_gem_objects", i915_gem_object_info, 0},
4701         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4702         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4703         {"i915_gem_stolen", i915_gem_stolen_list_info },
4704         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4705         {"i915_gem_request", i915_gem_request_info, 0},
4706         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4707         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4708         {"i915_gem_interrupt", i915_interrupt_info, 0},
4709         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4710         {"i915_guc_info", i915_guc_info, 0},
4711         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4712         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4713         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4714         {"i915_frequency_info", i915_frequency_info, 0},
4715         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4716         {"i915_drpc_info", i915_drpc_info, 0},
4717         {"i915_emon_status", i915_emon_status, 0},
4718         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4719         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4720         {"i915_fbc_status", i915_fbc_status, 0},
4721         {"i915_ips_status", i915_ips_status, 0},
4722         {"i915_sr_status", i915_sr_status, 0},
4723         {"i915_opregion", i915_opregion, 0},
4724         {"i915_vbt", i915_vbt, 0},
4725         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4726         {"i915_context_status", i915_context_status, 0},
4727         {"i915_dump_lrc", i915_dump_lrc, 0},
4728         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4729         {"i915_swizzle_info", i915_swizzle_info, 0},
4730         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4731         {"i915_llc", i915_llc, 0},
4732         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4733         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4734         {"i915_energy_uJ", i915_energy_uJ, 0},
4735         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4736         {"i915_power_domain_info", i915_power_domain_info, 0},
4737         {"i915_dmc_info", i915_dmc_info, 0},
4738         {"i915_display_info", i915_display_info, 0},
4739         {"i915_engine_info", i915_engine_info, 0},
4740         {"i915_semaphore_status", i915_semaphore_status, 0},
4741         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4742         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4743         {"i915_wa_registers", i915_wa_registers, 0},
4744         {"i915_ddb_info", i915_ddb_info, 0},
4745         {"i915_sseu_status", i915_sseu_status, 0},
4746         {"i915_drrs_status", i915_drrs_status, 0},
4747         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4748 };
4749 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4750
4751 static const struct i915_debugfs_files {
4752         const char *name;
4753         const struct file_operations *fops;
4754 } i915_debugfs_files[] = {
4755         {"i915_wedged", &i915_wedged_fops},
4756         {"i915_max_freq", &i915_max_freq_fops},
4757         {"i915_min_freq", &i915_min_freq_fops},
4758         {"i915_cache_sharing", &i915_cache_sharing_fops},
4759         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4760         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4761         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4762 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4763         {"i915_error_state", &i915_error_state_fops},
4764         {"i915_gpu_info", &i915_gpu_info_fops},
4765 #endif
4766         {"i915_next_seqno", &i915_next_seqno_fops},
4767         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4768         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4769         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4770         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4771         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4772         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4773         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4774         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4775         {"i915_guc_log_control", &i915_guc_log_control_fops},
4776         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
4777 };
4778
4779 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4780 {
4781         struct drm_minor *minor = dev_priv->drm.primary;
4782         struct dentry *ent;
4783         int ret, i;
4784
4785         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4786                                   minor->debugfs_root, to_i915(minor->dev),
4787                                   &i915_forcewake_fops);
4788         if (!ent)
4789                 return -ENOMEM;
4790
4791         ret = intel_pipe_crc_create(minor);
4792         if (ret)
4793                 return ret;
4794
4795         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4796                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4797                                           S_IRUGO | S_IWUSR,
4798                                           minor->debugfs_root,
4799                                           to_i915(minor->dev),
4800                                           i915_debugfs_files[i].fops);
4801                 if (!ent)
4802                         return -ENOMEM;
4803         }
4804
4805         return drm_debugfs_create_files(i915_debugfs_list,
4806                                         I915_DEBUGFS_ENTRIES,
4807                                         minor->debugfs_root, minor);
4808 }
4809
4810 struct dpcd_block {
4811         /* DPCD dump start address. */
4812         unsigned int offset;
4813         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4814         unsigned int end;
4815         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4816         size_t size;
4817         /* Only valid for eDP. */
4818         bool edp;
4819 };
4820
4821 static const struct dpcd_block i915_dpcd_debug[] = {
4822         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4823         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4824         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4825         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4826         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4827         { .offset = DP_SET_POWER },
4828         { .offset = DP_EDP_DPCD_REV },
4829         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4830         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4831         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4832 };
4833
4834 static int i915_dpcd_show(struct seq_file *m, void *data)
4835 {
4836         struct drm_connector *connector = m->private;
4837         struct intel_dp *intel_dp =
4838                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4839         uint8_t buf[16];
4840         ssize_t err;
4841         int i;
4842
4843         if (connector->status != connector_status_connected)
4844                 return -ENODEV;
4845
4846         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4847                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4848                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4849
4850                 if (b->edp &&
4851                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4852                         continue;
4853
4854                 /* low tech for now */
4855                 if (WARN_ON(size > sizeof(buf)))
4856                         continue;
4857
4858                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4859                 if (err <= 0) {
4860                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4861                                   size, b->offset, err);
4862                         continue;
4863                 }
4864
4865                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4866         }
4867
4868         return 0;
4869 }
4870
4871 static int i915_dpcd_open(struct inode *inode, struct file *file)
4872 {
4873         return single_open(file, i915_dpcd_show, inode->i_private);
4874 }
4875
4876 static const struct file_operations i915_dpcd_fops = {
4877         .owner = THIS_MODULE,
4878         .open = i915_dpcd_open,
4879         .read = seq_read,
4880         .llseek = seq_lseek,
4881         .release = single_release,
4882 };
4883
4884 static int i915_panel_show(struct seq_file *m, void *data)
4885 {
4886         struct drm_connector *connector = m->private;
4887         struct intel_dp *intel_dp =
4888                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4889
4890         if (connector->status != connector_status_connected)
4891                 return -ENODEV;
4892
4893         seq_printf(m, "Panel power up delay: %d\n",
4894                    intel_dp->panel_power_up_delay);
4895         seq_printf(m, "Panel power down delay: %d\n",
4896                    intel_dp->panel_power_down_delay);
4897         seq_printf(m, "Backlight on delay: %d\n",
4898                    intel_dp->backlight_on_delay);
4899         seq_printf(m, "Backlight off delay: %d\n",
4900                    intel_dp->backlight_off_delay);
4901
4902         return 0;
4903 }
4904
4905 static int i915_panel_open(struct inode *inode, struct file *file)
4906 {
4907         return single_open(file, i915_panel_show, inode->i_private);
4908 }
4909
4910 static const struct file_operations i915_panel_fops = {
4911         .owner = THIS_MODULE,
4912         .open = i915_panel_open,
4913         .read = seq_read,
4914         .llseek = seq_lseek,
4915         .release = single_release,
4916 };
4917
4918 /**
4919  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4920  * @connector: pointer to a registered drm_connector
4921  *
4922  * Cleanup will be done by drm_connector_unregister() through a call to
4923  * drm_debugfs_connector_remove().
4924  *
4925  * Returns 0 on success, negative error codes on error.
4926  */
4927 int i915_debugfs_connector_add(struct drm_connector *connector)
4928 {
4929         struct dentry *root = connector->debugfs_entry;
4930
4931         /* The connector must have been registered beforehands. */
4932         if (!root)
4933                 return -ENODEV;
4934
4935         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4936             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4937                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4938                                     connector, &i915_dpcd_fops);
4939
4940         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4941                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4942                                     connector, &i915_panel_fops);
4943
4944         return 0;
4945 }