drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/sched/mm.h>
  30 #include <linux/sort.h>
  31
  32 #include <drm/drm_debugfs.h>
  33
  34 #include "gem/i915_gem_context.h"
  35 #include "gt/intel_gt_buffer_pool.h"
  36 #include "gt/intel_gt_clock_utils.h"
  37 #include "gt/intel_gt.h"
  38 #include "gt/intel_gt_pm.h"
  39 #include "gt/intel_gt_requests.h"
  40 #include "gt/intel_reset.h"
  41 #include "gt/intel_rc6.h"
  42 #include "gt/intel_rps.h"
  43 #include "gt/intel_sseu_debugfs.h"
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_debugfs_params.h"
  47 #include "i915_irq.h"
  48 #include "i915_trace.h"
  49 #include "intel_pm.h"
  50 #include "intel_sideband.h"
  51
  52 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  53 {
  54         return to_i915(node->minor->dev);
  55 }
  56
  57 static int i915_capabilities(struct seq_file *m, void *data)
  58 {
  59         struct drm_i915_private *i915 = node_to_i915(m->private);
  60         struct drm_printer p = drm_seq_file_printer(m);
  61
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
  63
  64         intel_device_info_print_static(INTEL_INFO(i915), &p);
  65         intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
  66         intel_gt_info_print(&i915->gt.info, &p);
  67         intel_driver_caps_print(&i915->caps, &p);
  68
  69         kernel_param_lock(THIS_MODULE);
  70         i915_params_dump(&i915->params, &p);
  71         kernel_param_unlock(THIS_MODULE);
  72
  73         return 0;
  74 }
  75
  76 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  77 {
  78         switch (i915_gem_object_get_tiling(obj)) {
  79         default:
  80         case I915_TILING_NONE: return ' ';
  81         case I915_TILING_X: return 'X';
  82         case I915_TILING_Y: return 'Y';
  83         }
  84 }
  85
  86 static char get_global_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
  89 }
  90
  91 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  92 {
  93         return obj->mm.mapping ? 'M' : ' ';
  94 }
  95
  96 static const char *
  97 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
  98 {
  99         size_t x = 0;
 100
 101         switch (page_sizes) {
 102         case 0:
 103                 return "";
 104         case I915_GTT_PAGE_SIZE_4K:
 105                 return "4K";
 106         case I915_GTT_PAGE_SIZE_64K:
 107                 return "64K";
 108         case I915_GTT_PAGE_SIZE_2M:
 109                 return "2M";
 110         default:
 111                 if (!buf)
 112                         return "M";
 113
 114                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 115                         x += snprintf(buf + x, len - x, "2M, ");
 116                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 117                         x += snprintf(buf + x, len - x, "64K, ");
 118                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 119                         x += snprintf(buf + x, len - x, "4K, ");
 120                 buf[x-2] = '\0';
 121
 122                 return buf;
 123         }
 124 }
 125
 126 void
 127 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 128 {
 129         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 130         struct intel_engine_cs *engine;
 131         struct i915_vma *vma;
 132         int pin_count = 0;
 133
 134         seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
 135                    &obj->base,
 136                    get_tiling_flag(obj),
 137                    get_global_flag(obj),
 138                    get_pin_mapped_flag(obj),
 139                    obj->base.size / 1024,
 140                    obj->read_domains,
 141                    obj->write_domain,
 142                    i915_cache_level_str(dev_priv, obj->cache_level),
 143                    obj->mm.dirty ? " dirty" : "",
 144                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 145         if (obj->base.name)
 146                 seq_printf(m, " (name: %d)", obj->base.name);
 147
 148         spin_lock(&obj->vma.lock);
 149         list_for_each_entry(vma, &obj->vma.list, obj_link) {
 150                 if (!drm_mm_node_allocated(&vma->node))
 151                         continue;
 152
 153                 spin_unlock(&obj->vma.lock);
 154
 155                 if (i915_vma_is_pinned(vma))
 156                         pin_count++;
 157
 158                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 159                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 160                            vma->node.start, vma->node.size,
 161                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 162                 if (i915_vma_is_ggtt(vma)) {
 163                         switch (vma->ggtt_view.type) {
 164                         case I915_GGTT_VIEW_NORMAL:
 165                                 seq_puts(m, ", normal");
 166                                 break;
 167
 168                         case I915_GGTT_VIEW_PARTIAL:
 169                                 seq_printf(m, ", partial [%08llx+%x]",
 170                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 171                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 172                                 break;
 173
 174                         case I915_GGTT_VIEW_ROTATED:
 175                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 176                                            vma->ggtt_view.rotated.plane[0].width,
 177                                            vma->ggtt_view.rotated.plane[0].height,
 178                                            vma->ggtt_view.rotated.plane[0].stride,
 179                                            vma->ggtt_view.rotated.plane[0].offset,
 180                                            vma->ggtt_view.rotated.plane[1].width,
 181                                            vma->ggtt_view.rotated.plane[1].height,
 182                                            vma->ggtt_view.rotated.plane[1].stride,
 183                                            vma->ggtt_view.rotated.plane[1].offset);
 184                                 break;
 185
 186                         case I915_GGTT_VIEW_REMAPPED:
 187                                 seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 188                                            vma->ggtt_view.remapped.plane[0].width,
 189                                            vma->ggtt_view.remapped.plane[0].height,
 190                                            vma->ggtt_view.remapped.plane[0].stride,
 191                                            vma->ggtt_view.remapped.plane[0].offset,
 192                                            vma->ggtt_view.remapped.plane[1].width,
 193                                            vma->ggtt_view.remapped.plane[1].height,
 194                                            vma->ggtt_view.remapped.plane[1].stride,
 195                                            vma->ggtt_view.remapped.plane[1].offset);
 196                                 break;
 197
 198                         default:
 199                                 MISSING_CASE(vma->ggtt_view.type);
 200                                 break;
 201                         }
 202                 }
 203                 if (vma->fence)
 204                         seq_printf(m, " , fence: %d", vma->fence->id);
 205                 seq_puts(m, ")");
 206
 207                 spin_lock(&obj->vma.lock);
 208         }
 209         spin_unlock(&obj->vma.lock);
 210
 211         seq_printf(m, " (pinned x %d)", pin_count);
 212         if (obj->stolen)
 213                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 214         if (i915_gem_object_is_framebuffer(obj))
 215                 seq_printf(m, " (fb)");
 216
 217         engine = i915_gem_object_last_write_engine(obj);
 218         if (engine)
 219                 seq_printf(m, " (%s)", engine->name);
 220 }
 221
 222 struct file_stats {
 223         struct i915_address_space *vm;
 224         unsigned long count;
 225         u64 total;
 226         u64 active, inactive;
 227         u64 closed;
 228 };
 229
 230 static int per_file_stats(int id, void *ptr, void *data)
 231 {
 232         struct drm_i915_gem_object *obj = ptr;
 233         struct file_stats *stats = data;
 234         struct i915_vma *vma;
 235
 236         if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount))
 237                 return 0;
 238
 239         stats->count++;
 240         stats->total += obj->base.size;
 241
 242         spin_lock(&obj->vma.lock);
 243         if (!stats->vm) {
 244                 for_each_ggtt_vma(vma, obj) {
 245                         if (!drm_mm_node_allocated(&vma->node))
 246                                 continue;
 247
 248                         if (i915_vma_is_active(vma))
 249                                 stats->active += vma->node.size;
 250                         else
 251                                 stats->inactive += vma->node.size;
 252
 253                         if (i915_vma_is_closed(vma))
 254                                 stats->closed += vma->node.size;
 255                 }
 256         } else {
 257                 struct rb_node *p = obj->vma.tree.rb_node;
 258
 259                 while (p) {
 260                         long cmp;
 261
 262                         vma = rb_entry(p, typeof(*vma), obj_node);
 263                         cmp = i915_vma_compare(vma, stats->vm, NULL);
 264                         if (cmp == 0) {
 265                                 if (drm_mm_node_allocated(&vma->node)) {
 266                                         if (i915_vma_is_active(vma))
 267                                                 stats->active += vma->node.size;
 268                                         else
 269                                                 stats->inactive += vma->node.size;
 270
 271                                         if (i915_vma_is_closed(vma))
 272                                                 stats->closed += vma->node.size;
 273                                 }
 274                                 break;
 275                         }
 276                         if (cmp < 0)
 277                                 p = p->rb_right;
 278                         else
 279                                 p = p->rb_left;
 280                 }
 281         }
 282         spin_unlock(&obj->vma.lock);
 283
 284         i915_gem_object_put(obj);
 285         return 0;
 286 }
 287
 288 #define print_file_stats(m, name, stats) do { \
 289         if (stats.count) \
 290                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu closed)\n", \
 291                            name, \
 292                            stats.count, \
 293                            stats.total, \
 294                            stats.active, \
 295                            stats.inactive, \
 296                            stats.closed); \
 297 } while (0)
 298
 299 static void print_context_stats(struct seq_file *m,
 300                                 struct drm_i915_private *i915)
 301 {
 302         struct file_stats kstats = {};
 303         struct i915_gem_context *ctx, *cn;
 304
 305         spin_lock(&i915->gem.contexts.lock);
 306         list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
 307                 struct i915_gem_engines_iter it;
 308                 struct intel_context *ce;
 309
 310                 if (!kref_get_unless_zero(&ctx->ref))
 311                         continue;
 312
 313                 spin_unlock(&i915->gem.contexts.lock);
 314
 315                 for_each_gem_engine(ce,
 316                                     i915_gem_context_lock_engines(ctx), it) {
 317                         if (intel_context_pin_if_active(ce)) {
 318                                 rcu_read_lock();
 319                                 if (ce->state)
 320                                         per_file_stats(0,
 321                                                        ce->state->obj, &kstats);
 322                                 per_file_stats(0, ce->ring->vma->obj, &kstats);
 323                                 rcu_read_unlock();
 324                                 intel_context_unpin(ce);
 325                         }
 326                 }
 327                 i915_gem_context_unlock_engines(ctx);
 328
 329                 mutex_lock(&ctx->mutex);
 330                 if (!IS_ERR_OR_NULL(ctx->file_priv)) {
 331                         struct file_stats stats = {
 332                                 .vm = rcu_access_pointer(ctx->vm),
 333                         };
 334                         struct drm_file *file = ctx->file_priv->file;
 335                         struct task_struct *task;
 336                         char name[80];
 337
 338                         rcu_read_lock();
 339                         idr_for_each(&file->object_idr, per_file_stats, &stats);
 340                         rcu_read_unlock();
 341
 342                         rcu_read_lock();
 343                         task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
 344                         snprintf(name, sizeof(name), "%s",
 345                                  task ? task->comm : "<unknown>");
 346                         rcu_read_unlock();
 347
 348                         print_file_stats(m, name, stats);
 349                 }
 350                 mutex_unlock(&ctx->mutex);
 351
 352                 spin_lock(&i915->gem.contexts.lock);
 353                 list_safe_reset_next(ctx, cn, link);
 354                 i915_gem_context_put(ctx);
 355         }
 356         spin_unlock(&i915->gem.contexts.lock);
 357
 358         print_file_stats(m, "[k]contexts", kstats);
 359 }
 360
 361 static int i915_gem_object_info(struct seq_file *m, void *data)
 362 {
 363         struct drm_i915_private *i915 = node_to_i915(m->private);
 364         struct intel_memory_region *mr;
 365         enum intel_region_id id;
 366
 367         seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
 368                    i915->mm.shrink_count,
 369                    atomic_read(&i915->mm.free_count),
 370                    i915->mm.shrink_memory);
 371         for_each_memory_region(mr, i915, id)
 372                 seq_printf(m, "%s: total:%pa, available:%pa bytes\n",
 373                            mr->name, &mr->total, &mr->avail);
 374         seq_putc(m, '\n');
 375
 376         print_context_stats(m, i915);
 377
 378         return 0;
 379 }
 380
 381 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 382 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 383                               size_t count, loff_t *pos)
 384 {
 385         struct i915_gpu_coredump *error;
 386         ssize_t ret;
 387         void *buf;
 388
 389         error = file->private_data;
 390         if (!error)
 391                 return 0;
 392
 393         /* Bounce buffer required because of kernfs __user API convenience. */
 394         buf = kmalloc(count, GFP_KERNEL);
 395         if (!buf)
 396                 return -ENOMEM;
 397
 398         ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
 399         if (ret <= 0)
 400                 goto out;
 401
 402         if (!copy_to_user(ubuf, buf, ret))
 403                 *pos += ret;
 404         else
 405                 ret = -EFAULT;
 406
 407 out:
 408         kfree(buf);
 409         return ret;
 410 }
 411
 412 static int gpu_state_release(struct inode *inode, struct file *file)
 413 {
 414         i915_gpu_coredump_put(file->private_data);
 415         return 0;
 416 }
 417
 418 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 419 {
 420         struct drm_i915_private *i915 = inode->i_private;
 421         struct i915_gpu_coredump *gpu;
 422         intel_wakeref_t wakeref;
 423
 424         gpu = NULL;
 425         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
 426                 gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
 427         if (IS_ERR(gpu))
 428                 return PTR_ERR(gpu);
 429
 430         file->private_data = gpu;
 431         return 0;
 432 }
 433
 434 static const struct file_operations i915_gpu_info_fops = {
 435         .owner = THIS_MODULE,
 436         .open = i915_gpu_info_open,
 437         .read = gpu_state_read,
 438         .llseek = default_llseek,
 439         .release = gpu_state_release,
 440 };
 441
 442 static ssize_t
 443 i915_error_state_write(struct file *filp,
 444                        const char __user *ubuf,
 445                        size_t cnt,
 446                        loff_t *ppos)
 447 {
 448         struct i915_gpu_coredump *error = filp->private_data;
 449
 450         if (!error)
 451                 return 0;
 452
 453         drm_dbg(&error->i915->drm, "Resetting error state\n");
 454         i915_reset_error_state(error->i915);
 455
 456         return cnt;
 457 }
 458
 459 static int i915_error_state_open(struct inode *inode, struct file *file)
 460 {
 461         struct i915_gpu_coredump *error;
 462
 463         error = i915_first_error_state(inode->i_private);
 464         if (IS_ERR(error))
 465                 return PTR_ERR(error);
 466
 467         file->private_data  = error;
 468         return 0;
 469 }
 470
 471 static const struct file_operations i915_error_state_fops = {
 472         .owner = THIS_MODULE,
 473         .open = i915_error_state_open,
 474         .read = gpu_state_read,
 475         .write = i915_error_state_write,
 476         .llseek = default_llseek,
 477         .release = gpu_state_release,
 478 };
 479 #endif
 480
 481 static int i915_frequency_info(struct seq_file *m, void *unused)
 482 {
 483         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 484         struct intel_uncore *uncore = &dev_priv->uncore;
 485         struct intel_rps *rps = &dev_priv->gt.rps;
 486         intel_wakeref_t wakeref;
 487
 488         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 489
 490         if (IS_GEN(dev_priv, 5)) {
 491                 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 492                 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
 493
 494                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 495                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 496                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 497                            MEMSTAT_VID_SHIFT);
 498                 seq_printf(m, "Current P-state: %d\n",
 499                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 500         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 501                 u32 rpmodectl, freq_sts;
 502
 503                 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
 504                 seq_printf(m, "Video Turbo Mode: %s\n",
 505                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 506                 seq_printf(m, "HW control enabled: %s\n",
 507                            yesno(rpmodectl & GEN6_RP_ENABLE));
 508                 seq_printf(m, "SW control enabled: %s\n",
 509                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 510                                   GEN6_RP_MEDIA_SW_MODE));
 511
 512                 vlv_punit_get(dev_priv);
 513                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 514                 vlv_punit_put(dev_priv);
 515
 516                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 517                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 518
 519                 seq_printf(m, "actual GPU freq: %d MHz\n",
 520                            intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
 521
 522                 seq_printf(m, "current GPU freq: %d MHz\n",
 523                            intel_gpu_freq(rps, rps->cur_freq));
 524
 525                 seq_printf(m, "max GPU freq: %d MHz\n",
 526                            intel_gpu_freq(rps, rps->max_freq));
 527
 528                 seq_printf(m, "min GPU freq: %d MHz\n",
 529                            intel_gpu_freq(rps, rps->min_freq));
 530
 531                 seq_printf(m, "idle GPU freq: %d MHz\n",
 532                            intel_gpu_freq(rps, rps->idle_freq));
 533
 534                 seq_printf(m,
 535                            "efficient (RPe) frequency: %d MHz\n",
 536                            intel_gpu_freq(rps, rps->efficient_freq));
 537         } else if (INTEL_GEN(dev_priv) >= 6) {
 538                 u32 rp_state_limits;
 539                 u32 gt_perf_status;
 540                 u32 rp_state_cap;
 541                 u32 rpmodectl, rpinclimit, rpdeclimit;
 542                 u32 rpstat, cagf, reqf;
 543                 u32 rpupei, rpcurup, rpprevup;
 544                 u32 rpdownei, rpcurdown, rpprevdown;
 545                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 546                 int max_freq;
 547
 548                 rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
 549                 if (IS_GEN9_LP(dev_priv)) {
 550                         rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
 551                         gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
 552                 } else {
 553                         rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
 554                         gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
 555                 }
 556
 557                 /* RPSTAT1 is in the GT power well */
 558                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 559
 560                 reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
 561                 if (INTEL_GEN(dev_priv) >= 9)
 562                         reqf >>= 23;
 563                 else {
 564                         reqf &= ~GEN6_TURBO_DISABLE;
 565                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 566                                 reqf >>= 24;
 567                         else
 568                                 reqf >>= 25;
 569                 }
 570                 reqf = intel_gpu_freq(rps, reqf);
 571
 572                 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
 573                 rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD);
 574                 rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD);
 575
 576                 rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1);
 577                 rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
 578                 rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
 579                 rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
 580                 rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 581                 rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 582                 rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
 583                 cagf = intel_rps_read_actual_frequency(rps);
 584
 585                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 586
 587                 if (INTEL_GEN(dev_priv) >= 11) {
 588                         pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
 589                         pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
 590                         /*
 591                          * The equivalent to the PM ISR & IIR cannot be read
 592                          * without affecting the current state of the system
 593                          */
 594                         pm_isr = 0;
 595                         pm_iir = 0;
 596                 } else if (INTEL_GEN(dev_priv) >= 8) {
 597                         pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
 598                         pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
 599                         pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
 600                         pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2));
 601                 } else {
 602                         pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER);
 603                         pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR);
 604                         pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR);
 605                         pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
 606                 }
 607                 pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK);
 608
 609                 seq_printf(m, "Video Turbo Mode: %s\n",
 610                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 611                 seq_printf(m, "HW control enabled: %s\n",
 612                            yesno(rpmodectl & GEN6_RP_ENABLE));
 613                 seq_printf(m, "SW control enabled: %s\n",
 614                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 615                                   GEN6_RP_MEDIA_SW_MODE));
 616
 617                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
 618                            pm_ier, pm_imr, pm_mask);
 619                 if (INTEL_GEN(dev_priv) <= 10)
 620                         seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
 621                                    pm_isr, pm_iir);
 622                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 623                            rps->pm_intrmsk_mbz);
 624                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 625                 seq_printf(m, "Render p-state ratio: %d\n",
 626                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
 627                 seq_printf(m, "Render p-state VID: %d\n",
 628                            gt_perf_status & 0xff);
 629                 seq_printf(m, "Render p-state limit: %d\n",
 630                            rp_state_limits & 0xff);
 631                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 632                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 633                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
 634                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
 635                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
 636                 seq_printf(m, "CAGF: %dMHz\n", cagf);
 637                 seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
 638                            rpupei,
 639                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
 640                 seq_printf(m, "RP CUR UP: %d (%dun)\n",
 641                            rpcurup,
 642                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
 643                 seq_printf(m, "RP PREV UP: %d (%dns)\n",
 644                            rpprevup,
 645                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
 646                 seq_printf(m, "Up threshold: %d%%\n",
 647                            rps->power.up_threshold);
 648
 649                 seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
 650                            rpdownei,
 651                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 652                                                       rpdownei));
 653                 seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
 654                            rpcurdown,
 655                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 656                                                       rpcurdown));
 657                 seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
 658                            rpprevdown,
 659                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 660                                                       rpprevdown));
 661                 seq_printf(m, "Down threshold: %d%%\n",
 662                            rps->power.down_threshold);
 663
 664                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 665                             rp_state_cap >> 16) & 0xff;
 666                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 667                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 668                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 669                            intel_gpu_freq(rps, max_freq));
 670
 671                 max_freq = (rp_state_cap & 0xff00) >> 8;
 672                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 673                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 674                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 675                            intel_gpu_freq(rps, max_freq));
 676
 677                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 678                             rp_state_cap >> 0) & 0xff;
 679                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 680                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 681                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 682                            intel_gpu_freq(rps, max_freq));
 683                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
 684                            intel_gpu_freq(rps, rps->max_freq));
 685
 686                 seq_printf(m, "Current freq: %d MHz\n",
 687                            intel_gpu_freq(rps, rps->cur_freq));
 688                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
 689                 seq_printf(m, "Idle freq: %d MHz\n",
 690                            intel_gpu_freq(rps, rps->idle_freq));
 691                 seq_printf(m, "Min freq: %d MHz\n",
 692                            intel_gpu_freq(rps, rps->min_freq));
 693                 seq_printf(m, "Boost freq: %d MHz\n",
 694                            intel_gpu_freq(rps, rps->boost_freq));
 695                 seq_printf(m, "Max freq: %d MHz\n",
 696                            intel_gpu_freq(rps, rps->max_freq));
 697                 seq_printf(m,
 698                            "efficient (RPe) frequency: %d MHz\n",
 699                            intel_gpu_freq(rps, rps->efficient_freq));
 700         } else {
 701                 seq_puts(m, "no P-state info available\n");
 702         }
 703
 704         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
 705         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
 706         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
 707
 708         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 709         return 0;
 710 }
 711
 712 static const char *swizzle_string(unsigned swizzle)
 713 {
 714         switch (swizzle) {
 715         case I915_BIT_6_SWIZZLE_NONE:
 716                 return "none";
 717         case I915_BIT_6_SWIZZLE_9:
 718                 return "bit9";
 719         case I915_BIT_6_SWIZZLE_9_10:
 720                 return "bit9/bit10";
 721         case I915_BIT_6_SWIZZLE_9_11:
 722                 return "bit9/bit11";
 723         case I915_BIT_6_SWIZZLE_9_10_11:
 724                 return "bit9/bit10/bit11";
 725         case I915_BIT_6_SWIZZLE_9_17:
 726                 return "bit9/bit17";
 727         case I915_BIT_6_SWIZZLE_9_10_17:
 728                 return "bit9/bit10/bit17";
 729         case I915_BIT_6_SWIZZLE_UNKNOWN:
 730                 return "unknown";
 731         }
 732
 733         return "bug";
 734 }
 735
 736 static int i915_swizzle_info(struct seq_file *m, void *data)
 737 {
 738         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 739         struct intel_uncore *uncore = &dev_priv->uncore;
 740         intel_wakeref_t wakeref;
 741
 742         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
 743                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
 744         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
 745                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
 746
 747         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
 748                 seq_puts(m, "L-shaped memory detected\n");
 749
 750         /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
 751         if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
 752                 return 0;
 753
 754         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 755
 756         if (IS_GEN_RANGE(dev_priv, 3, 4)) {
 757                 seq_printf(m, "DDC = 0x%08x\n",
 758                            intel_uncore_read(uncore, DCC));
 759                 seq_printf(m, "DDC2 = 0x%08x\n",
 760                            intel_uncore_read(uncore, DCC2));
 761                 seq_printf(m, "C0DRB3 = 0x%04x\n",
 762                            intel_uncore_read16(uncore, C0DRB3));
 763                 seq_printf(m, "C1DRB3 = 0x%04x\n",
 764                            intel_uncore_read16(uncore, C1DRB3));
 765         } else if (INTEL_GEN(dev_priv) >= 6) {
 766                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 767                            intel_uncore_read(uncore, MAD_DIMM_C0));
 768                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
 769                            intel_uncore_read(uncore, MAD_DIMM_C1));
 770                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
 771                            intel_uncore_read(uncore, MAD_DIMM_C2));
 772                 seq_printf(m, "TILECTL = 0x%08x\n",
 773                            intel_uncore_read(uncore, TILECTL));
 774                 if (INTEL_GEN(dev_priv) >= 8)
 775                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
 776                                    intel_uncore_read(uncore, GAMTARBMODE));
 777                 else
 778                         seq_printf(m, "ARB_MODE = 0x%08x\n",
 779                                    intel_uncore_read(uncore, ARB_MODE));
 780                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
 781                            intel_uncore_read(uncore, DISP_ARB_CTL));
 782         }
 783
 784         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 785
 786         return 0;
 787 }
 788
 789 static int i915_rps_boost_info(struct seq_file *m, void *data)
 790 {
 791         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 792         struct intel_rps *rps = &dev_priv->gt.rps;
 793
 794         seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
 795         seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
 796         seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
 797         seq_printf(m, "Boosts outstanding? %d\n",
 798                    atomic_read(&rps->num_waiters));
 799         seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
 800         seq_printf(m, "Frequency requested %d, actual %d\n",
 801                    intel_gpu_freq(rps, rps->cur_freq),
 802                    intel_rps_read_actual_frequency(rps));
 803         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
 804                    intel_gpu_freq(rps, rps->min_freq),
 805                    intel_gpu_freq(rps, rps->min_freq_softlimit),
 806                    intel_gpu_freq(rps, rps->max_freq_softlimit),
 807                    intel_gpu_freq(rps, rps->max_freq));
 808         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
 809                    intel_gpu_freq(rps, rps->idle_freq),
 810                    intel_gpu_freq(rps, rps->efficient_freq),
 811                    intel_gpu_freq(rps, rps->boost_freq));
 812
 813         seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
 814
 815         return 0;
 816 }
 817
 818 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
 819 {
 820         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 821         struct pci_dev *pdev = dev_priv->drm.pdev;
 822
 823         if (!HAS_RUNTIME_PM(dev_priv))
 824                 seq_puts(m, "Runtime power management not supported\n");
 825
 826         seq_printf(m, "Runtime power status: %s\n",
 827                    enableddisabled(!dev_priv->power_domains.init_wakeref));
 828
 829         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
 830         seq_printf(m, "IRQs disabled: %s\n",
 831                    yesno(!intel_irqs_enabled(dev_priv)));
 832 #ifdef CONFIG_PM
 833         seq_printf(m, "Usage count: %d\n",
 834                    atomic_read(&dev_priv->drm.dev->power.usage_count));
 835 #else
 836         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
 837 #endif
 838         seq_printf(m, "PCI device power state: %s [%d]\n",
 839                    pci_power_name(pdev->current_state),
 840                    pdev->current_state);
 841
 842         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
 843                 struct drm_printer p = drm_seq_file_printer(m);
 844
 845                 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
 846         }
 847
 848         return 0;
 849 }
 850
 851 static int i915_engine_info(struct seq_file *m, void *unused)
 852 {
 853         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 854         struct intel_engine_cs *engine;
 855         intel_wakeref_t wakeref;
 856         struct drm_printer p;
 857
 858         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 859
 860         seq_printf(m, "GT awake? %s [%d]\n",
 861                    yesno(dev_priv->gt.awake),
 862                    atomic_read(&dev_priv->gt.wakeref.count));
 863         seq_printf(m, "CS timestamp frequency: %u Hz\n",
 864                    RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
 865
 866         p = drm_seq_file_printer(m);
 867         for_each_uabi_engine(engine, dev_priv)
 868                 intel_engine_dump(engine, &p, "%s\n", engine->name);
 869
 870         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 871
 872         return 0;
 873 }
 874
 875 static int i915_wa_registers(struct seq_file *m, void *unused)
 876 {
 877         struct drm_i915_private *i915 = node_to_i915(m->private);
 878         struct intel_engine_cs *engine;
 879
 880         for_each_uabi_engine(engine, i915) {
 881                 const struct i915_wa_list *wal = &engine->ctx_wa_list;
 882                 const struct i915_wa *wa;
 883                 unsigned int count;
 884
 885                 count = wal->count;
 886                 if (!count)
 887                         continue;
 888
 889                 seq_printf(m, "%s: Workarounds applied: %u\n",
 890                            engine->name, count);
 891
 892                 for (wa = wal->list; count--; wa++)
 893                         seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
 894                                    i915_mmio_reg_offset(wa->reg),
 895                                    wa->set, wa->clr);
 896
 897                 seq_printf(m, "\n");
 898         }
 899
 900         return 0;
 901 }
 902
 903 static int
 904 i915_wedged_get(void *data, u64 *val)
 905 {
 906         struct drm_i915_private *i915 = data;
 907         int ret = intel_gt_terminally_wedged(&i915->gt);
 908
 909         switch (ret) {
 910         case -EIO:
 911                 *val = 1;
 912                 return 0;
 913         case 0:
 914                 *val = 0;
 915                 return 0;
 916         default:
 917                 return ret;
 918         }
 919 }
 920
 921 static int
 922 i915_wedged_set(void *data, u64 val)
 923 {
 924         struct drm_i915_private *i915 = data;
 925
 926         /* Flush any previous reset before applying for a new one */
 927         wait_event(i915->gt.reset.queue,
 928                    !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
 929
 930         intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
 931                               "Manually set wedged engine mask = %llx", val);
 932         return 0;
 933 }
 934
 935 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
 936                         i915_wedged_get, i915_wedged_set,
 937                         "%llu\n");
 938
 939 static int
 940 i915_perf_noa_delay_set(void *data, u64 val)
 941 {
 942         struct drm_i915_private *i915 = data;
 943
 944         /*
 945          * This would lead to infinite waits as we're doing timestamp
 946          * difference on the CS with only 32bits.
 947          */
 948         if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)
 949                 return -EINVAL;
 950
 951         atomic64_set(&i915->perf.noa_programming_delay, val);
 952         return 0;
 953 }
 954
 955 static int
 956 i915_perf_noa_delay_get(void *data, u64 *val)
 957 {
 958         struct drm_i915_private *i915 = data;
 959
 960         *val = atomic64_read(&i915->perf.noa_programming_delay);
 961         return 0;
 962 }
 963
 964 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
 965                         i915_perf_noa_delay_get,
 966                         i915_perf_noa_delay_set,
 967                         "%llu\n");
 968
 969 #define DROP_UNBOUND    BIT(0)
 970 #define DROP_BOUND      BIT(1)
 971 #define DROP_RETIRE     BIT(2)
 972 #define DROP_ACTIVE     BIT(3)
 973 #define DROP_FREED      BIT(4)
 974 #define DROP_SHRINK_ALL BIT(5)
 975 #define DROP_IDLE       BIT(6)
 976 #define DROP_RESET_ACTIVE       BIT(7)
 977 #define DROP_RESET_SEQNO        BIT(8)
 978 #define DROP_RCU        BIT(9)
 979 #define DROP_ALL (DROP_UNBOUND  | \
 980                   DROP_BOUND    | \
 981                   DROP_RETIRE   | \
 982                   DROP_ACTIVE   | \
 983                   DROP_FREED    | \
 984                   DROP_SHRINK_ALL |\
 985                   DROP_IDLE     | \
 986                   DROP_RESET_ACTIVE | \
 987                   DROP_RESET_SEQNO | \
 988                   DROP_RCU)
 989 static int
 990 i915_drop_caches_get(void *data, u64 *val)
 991 {
 992         *val = DROP_ALL;
 993
 994         return 0;
 995 }
 996 static int
 997 gt_drop_caches(struct intel_gt *gt, u64 val)
 998 {
 999         int ret;
1000
1001         if (val & DROP_RESET_ACTIVE &&
1002             wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
1003                 intel_gt_set_wedged(gt);
1004
1005         if (val & DROP_RETIRE)
1006                 intel_gt_retire_requests(gt);
1007
1008         if (val & (DROP_IDLE | DROP_ACTIVE)) {
1009                 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
1010                 if (ret)
1011                         return ret;
1012         }
1013
1014         if (val & DROP_IDLE) {
1015                 ret = intel_gt_pm_wait_for_idle(gt);
1016                 if (ret)
1017                         return ret;
1018         }
1019
1020         if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
1021                 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
1022
1023         if (val & DROP_FREED)
1024                 intel_gt_flush_buffer_pool(gt);
1025
1026         return 0;
1027 }
1028
1029 static int
1030 i915_drop_caches_set(void *data, u64 val)
1031 {
1032         struct drm_i915_private *i915 = data;
1033         int ret;
1034
1035         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
1036                   val, val & DROP_ALL);
1037
1038         ret = gt_drop_caches(&i915->gt, val);
1039         if (ret)
1040                 return ret;
1041
1042         fs_reclaim_acquire(GFP_KERNEL);
1043         if (val & DROP_BOUND)
1044                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
1045
1046         if (val & DROP_UNBOUND)
1047                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
1048
1049         if (val & DROP_SHRINK_ALL)
1050                 i915_gem_shrink_all(i915);
1051         fs_reclaim_release(GFP_KERNEL);
1052
1053         if (val & DROP_RCU)
1054                 rcu_barrier();
1055
1056         if (val & DROP_FREED)
1057                 i915_gem_drain_freed_objects(i915);
1058
1059         return 0;
1060 }
1061
1062 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1063                         i915_drop_caches_get, i915_drop_caches_set,
1064                         "0x%08llx\n");
1065
1066 static int i915_sseu_status(struct seq_file *m, void *unused)
1067 {
1068         struct drm_i915_private *i915 = node_to_i915(m->private);
1069         struct intel_gt *gt = &i915->gt;
1070
1071         return intel_sseu_status(m, gt);
1072 }
1073
1074 static int i915_forcewake_open(struct inode *inode, struct file *file)
1075 {
1076         struct drm_i915_private *i915 = inode->i_private;
1077         struct intel_gt *gt = &i915->gt;
1078
1079         atomic_inc(&gt->user_wakeref);
1080         intel_gt_pm_get(gt);
1081         if (INTEL_GEN(i915) >= 6)
1082                 intel_uncore_forcewake_user_get(gt->uncore);
1083
1084         return 0;
1085 }
1086
1087 static int i915_forcewake_release(struct inode *inode, struct file *file)
1088 {
1089         struct drm_i915_private *i915 = inode->i_private;
1090         struct intel_gt *gt = &i915->gt;
1091
1092         if (INTEL_GEN(i915) >= 6)
1093                 intel_uncore_forcewake_user_put(&i915->uncore);
1094         intel_gt_pm_put(gt);
1095         atomic_dec(&gt->user_wakeref);
1096
1097         return 0;
1098 }
1099
1100 static const struct file_operations i915_forcewake_fops = {
1101         .owner = THIS_MODULE,
1102         .open = i915_forcewake_open,
1103         .release = i915_forcewake_release,
1104 };
1105
1106 static const struct drm_info_list i915_debugfs_list[] = {
1107         {"i915_capabilities", i915_capabilities, 0},
1108         {"i915_gem_objects", i915_gem_object_info, 0},
1109         {"i915_frequency_info", i915_frequency_info, 0},
1110         {"i915_swizzle_info", i915_swizzle_info, 0},
1111         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1112         {"i915_engine_info", i915_engine_info, 0},
1113         {"i915_wa_registers", i915_wa_registers, 0},
1114         {"i915_sseu_status", i915_sseu_status, 0},
1115         {"i915_rps_boost_info", i915_rps_boost_info, 0},
1116 };
1117 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1118
1119 static const struct i915_debugfs_files {
1120         const char *name;
1121         const struct file_operations *fops;
1122 } i915_debugfs_files[] = {
1123         {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
1124         {"i915_wedged", &i915_wedged_fops},
1125         {"i915_gem_drop_caches", &i915_drop_caches_fops},
1126 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1127         {"i915_error_state", &i915_error_state_fops},
1128         {"i915_gpu_info", &i915_gpu_info_fops},
1129 #endif
1130 };
1131
1132 void i915_debugfs_register(struct drm_i915_private *dev_priv)
1133 {
1134         struct drm_minor *minor = dev_priv->drm.primary;
1135         int i;
1136
1137         i915_debugfs_params(dev_priv);
1138
1139         debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
1140                             to_i915(minor->dev), &i915_forcewake_fops);
1141         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
1142                 debugfs_create_file(i915_debugfs_files[i].name,
1143                                     S_IRUGO | S_IWUSR,
1144                                     minor->debugfs_root,
1145                                     to_i915(minor->dev),
1146                                     i915_debugfs_files[i].fops);
1147         }
1148
1149         drm_debugfs_create_files(i915_debugfs_list,
1150                                  I915_DEBUGFS_ENTRIES,
1151                                  minor->debugfs_root, minor);
1152 }