drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82 #define SEP_SEMICOLON ;
  83         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  84 #undef PRINT_FLAG
  85 #undef SEP_SEMICOLON
  86
  87         return 0;
  88 }
  89
  90 static char get_active_flag(struct drm_i915_gem_object *obj)
  91 {
  92         return i915_gem_object_is_active(obj) ? '*' : ' ';
  93 }
  94
  95 static char get_pin_flag(struct drm_i915_gem_object *obj)
  96 {
  97         return obj->pin_display ? 'p' : ' ';
  98 }
  99
 100 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (i915_gem_object_get_tiling(obj)) {
 103         default:
 104         case I915_TILING_NONE: return ' ';
 105         case I915_TILING_X: return 'X';
 106         case I915_TILING_Y: return 'Y';
 107         }
 108 }
 109
 110 static char get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
 113 }
 114
 115 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return obj->mapping ? 'M' : ' ';
 118 }
 119
 120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 121 {
 122         u64 size = 0;
 123         struct i915_vma *vma;
 124
 125         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 126                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 127                         size += vma->node.size;
 128         }
 129
 130         return size;
 131 }
 132
 133 static void
 134 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 135 {
 136         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 137         struct intel_engine_cs *engine;
 138         struct i915_vma *vma;
 139         unsigned int frontbuffer_bits;
 140         int pin_count = 0;
 141         enum intel_engine_id id;
 142
 143         lockdep_assert_held(&obj->base.dev->struct_mutex);
 144
 145         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 146                    &obj->base,
 147                    get_active_flag(obj),
 148                    get_pin_flag(obj),
 149                    get_tiling_flag(obj),
 150                    get_global_flag(obj),
 151                    get_pin_mapped_flag(obj),
 152                    obj->base.size / 1024,
 153                    obj->base.read_domains,
 154                    obj->base.write_domain);
 155         for_each_engine_id(engine, dev_priv, id)
 156                 seq_printf(m, "%x ",
 157                            i915_gem_active_get_seqno(&obj->last_read[id],
 158                                                      &obj->base.dev->struct_mutex));
 159         seq_printf(m, "] %x %s%s%s",
 160                    i915_gem_active_get_seqno(&obj->last_write,
 161                                              &obj->base.dev->struct_mutex),
 162                    i915_cache_level_str(dev_priv, obj->cache_level),
 163                    obj->dirty ? " dirty" : "",
 164                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 165         if (obj->base.name)
 166                 seq_printf(m, " (name: %d)", obj->base.name);
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (i915_vma_is_pinned(vma))
 169                         pin_count++;
 170         }
 171         seq_printf(m, " (pinned x %d)", pin_count);
 172         if (obj->pin_display)
 173                 seq_printf(m, " (display)");
 174         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 175                 if (!drm_mm_node_allocated(&vma->node))
 176                         continue;
 177
 178                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 179                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 180                            vma->node.start, vma->node.size);
 181                 if (i915_vma_is_ggtt(vma))
 182                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 183                 if (vma->fence)
 184                         seq_printf(m, " , fence: %d%s",
 185                                    vma->fence->id,
 186                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 187                 seq_puts(m, ")");
 188         }
 189         if (obj->stolen)
 190                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 191         if (obj->pin_display || obj->fault_mappable) {
 192                 char s[3], *t = s;
 193                 if (obj->pin_display)
 194                         *t++ = 'p';
 195                 if (obj->fault_mappable)
 196                         *t++ = 'f';
 197                 *t = '\0';
 198                 seq_printf(m, " (%s mappable)", s);
 199         }
 200
 201         engine = i915_gem_active_get_engine(&obj->last_write,
 202                                             &dev_priv->drm.struct_mutex);
 203         if (engine)
 204                 seq_printf(m, " (%s)", engine->name);
 205
 206         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 207         if (frontbuffer_bits)
 208                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 209 }
 210
 211 static int obj_rank_by_stolen(void *priv,
 212                               struct list_head *A, struct list_head *B)
 213 {
 214         struct drm_i915_gem_object *a =
 215                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 216         struct drm_i915_gem_object *b =
 217                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 218
 219         if (a->stolen->start < b->stolen->start)
 220                 return -1;
 221         if (a->stolen->start > b->stolen->start)
 222                 return 1;
 223         return 0;
 224 }
 225
 226 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 227 {
 228         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 229         struct drm_device *dev = &dev_priv->drm;
 230         struct drm_i915_gem_object *obj;
 231         u64 total_obj_size, total_gtt_size;
 232         LIST_HEAD(stolen);
 233         int count, ret;
 234
 235         ret = mutex_lock_interruptible(&dev->struct_mutex);
 236         if (ret)
 237                 return ret;
 238
 239         total_obj_size = total_gtt_size = count = 0;
 240         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 241                 if (obj->stolen == NULL)
 242                         continue;
 243
 244                 list_add(&obj->obj_exec_link, &stolen);
 245
 246                 total_obj_size += obj->base.size;
 247                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 248                 count++;
 249         }
 250         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 251                 if (obj->stolen == NULL)
 252                         continue;
 253
 254                 list_add(&obj->obj_exec_link, &stolen);
 255
 256                 total_obj_size += obj->base.size;
 257                 count++;
 258         }
 259         list_sort(NULL, &stolen, obj_rank_by_stolen);
 260         seq_puts(m, "Stolen:\n");
 261         while (!list_empty(&stolen)) {
 262                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 263                 seq_puts(m, "   ");
 264                 describe_obj(m, obj);
 265                 seq_putc(m, '\n');
 266                 list_del_init(&obj->obj_exec_link);
 267         }
 268         mutex_unlock(&dev->struct_mutex);
 269
 270         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 271                    count, total_obj_size, total_gtt_size);
 272         return 0;
 273 }
 274
 275 struct file_stats {
 276         struct drm_i915_file_private *file_priv;
 277         unsigned long count;
 278         u64 total, unbound;
 279         u64 global, shared;
 280         u64 active, inactive;
 281 };
 282
 283 static int per_file_stats(int id, void *ptr, void *data)
 284 {
 285         struct drm_i915_gem_object *obj = ptr;
 286         struct file_stats *stats = data;
 287         struct i915_vma *vma;
 288
 289         stats->count++;
 290         stats->total += obj->base.size;
 291         if (!obj->bind_count)
 292                 stats->unbound += obj->base.size;
 293         if (obj->base.name || obj->base.dma_buf)
 294                 stats->shared += obj->base.size;
 295
 296         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 297                 if (!drm_mm_node_allocated(&vma->node))
 298                         continue;
 299
 300                 if (i915_vma_is_ggtt(vma)) {
 301                         stats->global += vma->node.size;
 302                 } else {
 303                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 304
 305                         if (ppgtt->base.file != stats->file_priv)
 306                                 continue;
 307                 }
 308
 309                 if (i915_vma_is_active(vma))
 310                         stats->active += vma->node.size;
 311                 else
 312                         stats->inactive += vma->node.size;
 313         }
 314
 315         return 0;
 316 }
 317
 318 #define print_file_stats(m, name, stats) do { \
 319         if (stats.count) \
 320                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 321                            name, \
 322                            stats.count, \
 323                            stats.total, \
 324                            stats.active, \
 325                            stats.inactive, \
 326                            stats.global, \
 327                            stats.shared, \
 328                            stats.unbound); \
 329 } while (0)
 330
 331 static void print_batch_pool_stats(struct seq_file *m,
 332                                    struct drm_i915_private *dev_priv)
 333 {
 334         struct drm_i915_gem_object *obj;
 335         struct file_stats stats;
 336         struct intel_engine_cs *engine;
 337         int j;
 338
 339         memset(&stats, 0, sizeof(stats));
 340
 341         for_each_engine(engine, dev_priv) {
 342                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 343                         list_for_each_entry(obj,
 344                                             &engine->batch_pool.cache_list[j],
 345                                             batch_pool_link)
 346                                 per_file_stats(0, obj, &stats);
 347                 }
 348         }
 349
 350         print_file_stats(m, "[k]batch pool", stats);
 351 }
 352
 353 static int per_file_ctx_stats(int id, void *ptr, void *data)
 354 {
 355         struct i915_gem_context *ctx = ptr;
 356         int n;
 357
 358         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 359                 if (ctx->engine[n].state)
 360                         per_file_stats(0, ctx->engine[n].state->obj, data);
 361                 if (ctx->engine[n].ring)
 362                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void print_context_stats(struct seq_file *m,
 369                                 struct drm_i915_private *dev_priv)
 370 {
 371         struct drm_device *dev = &dev_priv->drm;
 372         struct file_stats stats;
 373         struct drm_file *file;
 374
 375         memset(&stats, 0, sizeof(stats));
 376
 377         mutex_lock(&dev->struct_mutex);
 378         if (dev_priv->kernel_context)
 379                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 380
 381         list_for_each_entry(file, &dev->filelist, lhead) {
 382                 struct drm_i915_file_private *fpriv = file->driver_priv;
 383                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 384         }
 385         mutex_unlock(&dev->struct_mutex);
 386
 387         print_file_stats(m, "[k]contexts", stats);
 388 }
 389
 390 static int i915_gem_object_info(struct seq_file *m, void *data)
 391 {
 392         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 393         struct drm_device *dev = &dev_priv->drm;
 394         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 395         u32 count, mapped_count, purgeable_count, dpy_count;
 396         u64 size, mapped_size, purgeable_size, dpy_size;
 397         struct drm_i915_gem_object *obj;
 398         struct drm_file *file;
 399         int ret;
 400
 401         ret = mutex_lock_interruptible(&dev->struct_mutex);
 402         if (ret)
 403                 return ret;
 404
 405         seq_printf(m, "%u objects, %zu bytes\n",
 406                    dev_priv->mm.object_count,
 407                    dev_priv->mm.object_memory);
 408
 409         size = count = 0;
 410         mapped_size = mapped_count = 0;
 411         purgeable_size = purgeable_count = 0;
 412         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 413                 size += obj->base.size;
 414                 ++count;
 415
 416                 if (obj->madv == I915_MADV_DONTNEED) {
 417                         purgeable_size += obj->base.size;
 418                         ++purgeable_count;
 419                 }
 420
 421                 if (obj->mapping) {
 422                         mapped_count++;
 423                         mapped_size += obj->base.size;
 424                 }
 425         }
 426         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 427
 428         size = count = dpy_size = dpy_count = 0;
 429         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 430                 size += obj->base.size;
 431                 ++count;
 432
 433                 if (obj->pin_display) {
 434                         dpy_size += obj->base.size;
 435                         ++dpy_count;
 436                 }
 437
 438                 if (obj->madv == I915_MADV_DONTNEED) {
 439                         purgeable_size += obj->base.size;
 440                         ++purgeable_count;
 441                 }
 442
 443                 if (obj->mapping) {
 444                         mapped_count++;
 445                         mapped_size += obj->base.size;
 446                 }
 447         }
 448         seq_printf(m, "%u bound objects, %llu bytes\n",
 449                    count, size);
 450         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 451                    purgeable_count, purgeable_size);
 452         seq_printf(m, "%u mapped objects, %llu bytes\n",
 453                    mapped_count, mapped_size);
 454         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 455                    dpy_count, dpy_size);
 456
 457         seq_printf(m, "%llu [%llu] gtt total\n",
 458                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 459
 460         seq_putc(m, '\n');
 461         print_batch_pool_stats(m, dev_priv);
 462         mutex_unlock(&dev->struct_mutex);
 463
 464         mutex_lock(&dev->filelist_mutex);
 465         print_context_stats(m, dev_priv);
 466         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 467                 struct file_stats stats;
 468                 struct drm_i915_file_private *file_priv = file->driver_priv;
 469                 struct drm_i915_gem_request *request;
 470                 struct task_struct *task;
 471
 472                 memset(&stats, 0, sizeof(stats));
 473                 stats.file_priv = file->driver_priv;
 474                 spin_lock(&file->table_lock);
 475                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 476                 spin_unlock(&file->table_lock);
 477                 /*
 478                  * Although we have a valid reference on file->pid, that does
 479                  * not guarantee that the task_struct who called get_pid() is
 480                  * still alive (e.g. get_pid(current) => fork() => exit()).
 481                  * Therefore, we need to protect this ->comm access using RCU.
 482                  */
 483                 mutex_lock(&dev->struct_mutex);
 484                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 485                                                    struct drm_i915_gem_request,
 486                                                    client_list);
 487                 rcu_read_lock();
 488                 task = pid_task(request && request->ctx->pid ?
 489                                 request->ctx->pid : file->pid,
 490                                 PIDTYPE_PID);
 491                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 492                 rcu_read_unlock();
 493                 mutex_unlock(&dev->struct_mutex);
 494         }
 495         mutex_unlock(&dev->filelist_mutex);
 496
 497         return 0;
 498 }
 499
 500 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 501 {
 502         struct drm_info_node *node = m->private;
 503         struct drm_i915_private *dev_priv = node_to_i915(node);
 504         struct drm_device *dev = &dev_priv->drm;
 505         bool show_pin_display_only = !!node->info_ent->data;
 506         struct drm_i915_gem_object *obj;
 507         u64 total_obj_size, total_gtt_size;
 508         int count, ret;
 509
 510         ret = mutex_lock_interruptible(&dev->struct_mutex);
 511         if (ret)
 512                 return ret;
 513
 514         total_obj_size = total_gtt_size = count = 0;
 515         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 516                 if (show_pin_display_only && !obj->pin_display)
 517                         continue;
 518
 519                 seq_puts(m, "   ");
 520                 describe_obj(m, obj);
 521                 seq_putc(m, '\n');
 522                 total_obj_size += obj->base.size;
 523                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 524                 count++;
 525         }
 526
 527         mutex_unlock(&dev->struct_mutex);
 528
 529         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 530                    count, total_obj_size, total_gtt_size);
 531
 532         return 0;
 533 }
 534
 535 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 536 {
 537         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 538         struct drm_device *dev = &dev_priv->drm;
 539         struct intel_crtc *crtc;
 540         int ret;
 541
 542         ret = mutex_lock_interruptible(&dev->struct_mutex);
 543         if (ret)
 544                 return ret;
 545
 546         for_each_intel_crtc(dev, crtc) {
 547                 const char pipe = pipe_name(crtc->pipe);
 548                 const char plane = plane_name(crtc->plane);
 549                 struct intel_flip_work *work;
 550
 551                 spin_lock_irq(&dev->event_lock);
 552                 work = crtc->flip_work;
 553                 if (work == NULL) {
 554                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 555                                    pipe, plane);
 556                 } else {
 557                         u32 pending;
 558                         u32 addr;
 559
 560                         pending = atomic_read(&work->pending);
 561                         if (pending) {
 562                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 570
 571                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 572                                            engine->name,
 573                                            i915_gem_request_get_seqno(work->flip_queued_req),
 574                                            dev_priv->next_seqno,
 575                                            intel_engine_get_seqno(engine),
 576                                            i915_gem_request_completed(work->flip_queued_req));
 577                         } else
 578                                 seq_printf(m, "Flip not associated with any ring\n");
 579                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 580                                    work->flip_queued_vblank,
 581                                    work->flip_ready_vblank,
 582                                    intel_crtc_get_vblank_counter(crtc));
 583                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 584
 585                         if (INTEL_GEN(dev_priv) >= 4)
 586                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 587                         else
 588                                 addr = I915_READ(DSPADDR(crtc->plane));
 589                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 590
 591                         if (work->pending_flip_obj) {
 592                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 593                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 594                         }
 595                 }
 596                 spin_unlock_irq(&dev->event_lock);
 597         }
 598
 599         mutex_unlock(&dev->struct_mutex);
 600
 601         return 0;
 602 }
 603
 604 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 605 {
 606         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 607         struct drm_device *dev = &dev_priv->drm;
 608         struct drm_i915_gem_object *obj;
 609         struct intel_engine_cs *engine;
 610         int total = 0;
 611         int ret, j;
 612
 613         ret = mutex_lock_interruptible(&dev->struct_mutex);
 614         if (ret)
 615                 return ret;
 616
 617         for_each_engine(engine, dev_priv) {
 618                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 619                         int count;
 620
 621                         count = 0;
 622                         list_for_each_entry(obj,
 623                                             &engine->batch_pool.cache_list[j],
 624                                             batch_pool_link)
 625                                 count++;
 626                         seq_printf(m, "%s cache[%d]: %d objects\n",
 627                                    engine->name, j, count);
 628
 629                         list_for_each_entry(obj,
 630                                             &engine->batch_pool.cache_list[j],
 631                                             batch_pool_link) {
 632                                 seq_puts(m, "   ");
 633                                 describe_obj(m, obj);
 634                                 seq_putc(m, '\n');
 635                         }
 636
 637                         total += count;
 638                 }
 639         }
 640
 641         seq_printf(m, "total: %d\n", total);
 642
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         return 0;
 646 }
 647
 648 static void print_request(struct seq_file *m,
 649                           struct drm_i915_gem_request *rq,
 650                           const char *prefix)
 651 {
 652         struct pid *pid = rq->ctx->pid;
 653         struct task_struct *task;
 654
 655         rcu_read_lock();
 656         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 657         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 658                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 659                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 660                    task ? task->comm : "<unknown>",
 661                    task ? task->pid : -1);
 662         rcu_read_unlock();
 663 }
 664
 665 static int i915_gem_request_info(struct seq_file *m, void *data)
 666 {
 667         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 668         struct drm_device *dev = &dev_priv->drm;
 669         struct intel_engine_cs *engine;
 670         struct drm_i915_gem_request *req;
 671         int ret, any;
 672
 673         ret = mutex_lock_interruptible(&dev->struct_mutex);
 674         if (ret)
 675                 return ret;
 676
 677         any = 0;
 678         for_each_engine(engine, dev_priv) {
 679                 int count;
 680
 681                 count = 0;
 682                 list_for_each_entry(req, &engine->request_list, link)
 683                         count++;
 684                 if (count == 0)
 685                         continue;
 686
 687                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 688                 list_for_each_entry(req, &engine->request_list, link)
 689                         print_request(m, req, "    ");
 690
 691                 any++;
 692         }
 693         mutex_unlock(&dev->struct_mutex);
 694
 695         if (any == 0)
 696                 seq_puts(m, "No requests\n");
 697
 698         return 0;
 699 }
 700
 701 static void i915_ring_seqno_info(struct seq_file *m,
 702                                  struct intel_engine_cs *engine)
 703 {
 704         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 705         struct rb_node *rb;
 706
 707         seq_printf(m, "Current sequence (%s): %x\n",
 708                    engine->name, intel_engine_get_seqno(engine));
 709
 710         spin_lock(&b->lock);
 711         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 712                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 713
 714                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 715                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 716         }
 717         spin_unlock(&b->lock);
 718 }
 719
 720 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 721 {
 722         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 723         struct intel_engine_cs *engine;
 724
 725         for_each_engine(engine, dev_priv)
 726                 i915_ring_seqno_info(m, engine);
 727
 728         return 0;
 729 }
 730
 731
 732 static int i915_interrupt_info(struct seq_file *m, void *data)
 733 {
 734         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 735         struct intel_engine_cs *engine;
 736         int i, pipe;
 737
 738         intel_runtime_pm_get(dev_priv);
 739
 740         if (IS_CHERRYVIEW(dev_priv)) {
 741                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 742                            I915_READ(GEN8_MASTER_IRQ));
 743
 744                 seq_printf(m, "Display IER:\t%08x\n",
 745                            I915_READ(VLV_IER));
 746                 seq_printf(m, "Display IIR:\t%08x\n",
 747                            I915_READ(VLV_IIR));
 748                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 749                            I915_READ(VLV_IIR_RW));
 750                 seq_printf(m, "Display IMR:\t%08x\n",
 751                            I915_READ(VLV_IMR));
 752                 for_each_pipe(dev_priv, pipe)
 753                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 754                                    pipe_name(pipe),
 755                                    I915_READ(PIPESTAT(pipe)));
 756
 757                 seq_printf(m, "Port hotplug:\t%08x\n",
 758                            I915_READ(PORT_HOTPLUG_EN));
 759                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 760                            I915_READ(VLV_DPFLIPSTAT));
 761                 seq_printf(m, "DPINVGTT:\t%08x\n",
 762                            I915_READ(DPINVGTT));
 763
 764                 for (i = 0; i < 4; i++) {
 765                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IMR(i)));
 767                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IIR(i)));
 769                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 770                                    i, I915_READ(GEN8_GT_IER(i)));
 771                 }
 772
 773                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 774                            I915_READ(GEN8_PCU_IMR));
 775                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 776                            I915_READ(GEN8_PCU_IIR));
 777                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 778                            I915_READ(GEN8_PCU_IER));
 779         } else if (INTEL_GEN(dev_priv) >= 8) {
 780                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 781                            I915_READ(GEN8_MASTER_IRQ));
 782
 783                 for (i = 0; i < 4; i++) {
 784                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 785                                    i, I915_READ(GEN8_GT_IMR(i)));
 786                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 787                                    i, I915_READ(GEN8_GT_IIR(i)));
 788                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 789                                    i, I915_READ(GEN8_GT_IER(i)));
 790                 }
 791
 792                 for_each_pipe(dev_priv, pipe) {
 793                         enum intel_display_power_domain power_domain;
 794
 795                         power_domain = POWER_DOMAIN_PIPE(pipe);
 796                         if (!intel_display_power_get_if_enabled(dev_priv,
 797                                                                 power_domain)) {
 798                                 seq_printf(m, "Pipe %c power disabled\n",
 799                                            pipe_name(pipe));
 800                                 continue;
 801                         }
 802                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 803                                    pipe_name(pipe),
 804                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 805                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 806                                    pipe_name(pipe),
 807                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 808                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 809                                    pipe_name(pipe),
 810                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 811
 812                         intel_display_power_put(dev_priv, power_domain);
 813                 }
 814
 815                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 816                            I915_READ(GEN8_DE_PORT_IMR));
 817                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 818                            I915_READ(GEN8_DE_PORT_IIR));
 819                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 820                            I915_READ(GEN8_DE_PORT_IER));
 821
 822                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 823                            I915_READ(GEN8_DE_MISC_IMR));
 824                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 825                            I915_READ(GEN8_DE_MISC_IIR));
 826                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 827                            I915_READ(GEN8_DE_MISC_IER));
 828
 829                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 830                            I915_READ(GEN8_PCU_IMR));
 831                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 832                            I915_READ(GEN8_PCU_IIR));
 833                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 834                            I915_READ(GEN8_PCU_IER));
 835         } else if (IS_VALLEYVIEW(dev_priv)) {
 836                 seq_printf(m, "Display IER:\t%08x\n",
 837                            I915_READ(VLV_IER));
 838                 seq_printf(m, "Display IIR:\t%08x\n",
 839                            I915_READ(VLV_IIR));
 840                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 841                            I915_READ(VLV_IIR_RW));
 842                 seq_printf(m, "Display IMR:\t%08x\n",
 843                            I915_READ(VLV_IMR));
 844                 for_each_pipe(dev_priv, pipe)
 845                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 846                                    pipe_name(pipe),
 847                                    I915_READ(PIPESTAT(pipe)));
 848
 849                 seq_printf(m, "Master IER:\t%08x\n",
 850                            I915_READ(VLV_MASTER_IER));
 851
 852                 seq_printf(m, "Render IER:\t%08x\n",
 853                            I915_READ(GTIER));
 854                 seq_printf(m, "Render IIR:\t%08x\n",
 855                            I915_READ(GTIIR));
 856                 seq_printf(m, "Render IMR:\t%08x\n",
 857                            I915_READ(GTIMR));
 858
 859                 seq_printf(m, "PM IER:\t\t%08x\n",
 860                            I915_READ(GEN6_PMIER));
 861                 seq_printf(m, "PM IIR:\t\t%08x\n",
 862                            I915_READ(GEN6_PMIIR));
 863                 seq_printf(m, "PM IMR:\t\t%08x\n",
 864                            I915_READ(GEN6_PMIMR));
 865
 866                 seq_printf(m, "Port hotplug:\t%08x\n",
 867                            I915_READ(PORT_HOTPLUG_EN));
 868                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 869                            I915_READ(VLV_DPFLIPSTAT));
 870                 seq_printf(m, "DPINVGTT:\t%08x\n",
 871                            I915_READ(DPINVGTT));
 872
 873         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 874                 seq_printf(m, "Interrupt enable:    %08x\n",
 875                            I915_READ(IER));
 876                 seq_printf(m, "Interrupt identity:  %08x\n",
 877                            I915_READ(IIR));
 878                 seq_printf(m, "Interrupt mask:      %08x\n",
 879                            I915_READ(IMR));
 880                 for_each_pipe(dev_priv, pipe)
 881                         seq_printf(m, "Pipe %c stat:         %08x\n",
 882                                    pipe_name(pipe),
 883                                    I915_READ(PIPESTAT(pipe)));
 884         } else {
 885                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 886                            I915_READ(DEIER));
 887                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 888                            I915_READ(DEIIR));
 889                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 890                            I915_READ(DEIMR));
 891                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 892                            I915_READ(SDEIER));
 893                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 894                            I915_READ(SDEIIR));
 895                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 896                            I915_READ(SDEIMR));
 897                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 898                            I915_READ(GTIER));
 899                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 900                            I915_READ(GTIIR));
 901                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 902                            I915_READ(GTIMR));
 903         }
 904         for_each_engine(engine, dev_priv) {
 905                 if (INTEL_GEN(dev_priv) >= 6) {
 906                         seq_printf(m,
 907                                    "Graphics Interrupt mask (%s):       %08x\n",
 908                                    engine->name, I915_READ_IMR(engine));
 909                 }
 910                 i915_ring_seqno_info(m, engine);
 911         }
 912         intel_runtime_pm_put(dev_priv);
 913
 914         return 0;
 915 }
 916
 917 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 918 {
 919         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 920         struct drm_device *dev = &dev_priv->drm;
 921         int i, ret;
 922
 923         ret = mutex_lock_interruptible(&dev->struct_mutex);
 924         if (ret)
 925                 return ret;
 926
 927         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 928         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 929                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 930
 931                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 932                            i, dev_priv->fence_regs[i].pin_count);
 933                 if (!vma)
 934                         seq_puts(m, "unused");
 935                 else
 936                         describe_obj(m, vma->obj);
 937                 seq_putc(m, '\n');
 938         }
 939
 940         mutex_unlock(&dev->struct_mutex);
 941         return 0;
 942 }
 943
 944 static int i915_hws_info(struct seq_file *m, void *data)
 945 {
 946         struct drm_info_node *node = m->private;
 947         struct drm_i915_private *dev_priv = node_to_i915(node);
 948         struct intel_engine_cs *engine;
 949         const u32 *hws;
 950         int i;
 951
 952         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 953         hws = engine->status_page.page_addr;
 954         if (hws == NULL)
 955                 return 0;
 956
 957         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 958                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 959                            i * 4,
 960                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 961         }
 962         return 0;
 963 }
 964
 965 static ssize_t
 966 i915_error_state_write(struct file *filp,
 967                        const char __user *ubuf,
 968                        size_t cnt,
 969                        loff_t *ppos)
 970 {
 971         struct i915_error_state_file_priv *error_priv = filp->private_data;
 972
 973         DRM_DEBUG_DRIVER("Resetting error state\n");
 974         i915_destroy_error_state(error_priv->dev);
 975
 976         return cnt;
 977 }
 978
 979 static int i915_error_state_open(struct inode *inode, struct file *file)
 980 {
 981         struct drm_i915_private *dev_priv = inode->i_private;
 982         struct i915_error_state_file_priv *error_priv;
 983
 984         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 985         if (!error_priv)
 986                 return -ENOMEM;
 987
 988         error_priv->dev = &dev_priv->drm;
 989
 990         i915_error_state_get(&dev_priv->drm, error_priv);
 991
 992         file->private_data = error_priv;
 993
 994         return 0;
 995 }
 996
 997 static int i915_error_state_release(struct inode *inode, struct file *file)
 998 {
 999         struct i915_error_state_file_priv *error_priv = file->private_data;
1000
1001         i915_error_state_put(error_priv);
1002         kfree(error_priv);
1003
1004         return 0;
1005 }
1006
1007 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1008                                      size_t count, loff_t *pos)
1009 {
1010         struct i915_error_state_file_priv *error_priv = file->private_data;
1011         struct drm_i915_error_state_buf error_str;
1012         loff_t tmp_pos = 0;
1013         ssize_t ret_count = 0;
1014         int ret;
1015
1016         ret = i915_error_state_buf_init(&error_str,
1017                                         to_i915(error_priv->dev), count, *pos);
1018         if (ret)
1019                 return ret;
1020
1021         ret = i915_error_state_to_str(&error_str, error_priv);
1022         if (ret)
1023                 goto out;
1024
1025         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1026                                             error_str.buf,
1027                                             error_str.bytes);
1028
1029         if (ret_count < 0)
1030                 ret = ret_count;
1031         else
1032                 *pos = error_str.start + ret_count;
1033 out:
1034         i915_error_state_buf_release(&error_str);
1035         return ret ?: ret_count;
1036 }
1037
1038 static const struct file_operations i915_error_state_fops = {
1039         .owner = THIS_MODULE,
1040         .open = i915_error_state_open,
1041         .read = i915_error_state_read,
1042         .write = i915_error_state_write,
1043         .llseek = default_llseek,
1044         .release = i915_error_state_release,
1045 };
1046
1047 static int
1048 i915_next_seqno_get(void *data, u64 *val)
1049 {
1050         struct drm_i915_private *dev_priv = data;
1051         int ret;
1052
1053         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1054         if (ret)
1055                 return ret;
1056
1057         *val = dev_priv->next_seqno;
1058         mutex_unlock(&dev_priv->drm.struct_mutex);
1059
1060         return 0;
1061 }
1062
1063 static int
1064 i915_next_seqno_set(void *data, u64 val)
1065 {
1066         struct drm_i915_private *dev_priv = data;
1067         struct drm_device *dev = &dev_priv->drm;
1068         int ret;
1069
1070         ret = mutex_lock_interruptible(&dev->struct_mutex);
1071         if (ret)
1072                 return ret;
1073
1074         ret = i915_gem_set_seqno(dev, val);
1075         mutex_unlock(&dev->struct_mutex);
1076
1077         return ret;
1078 }
1079
1080 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1081                         i915_next_seqno_get, i915_next_seqno_set,
1082                         "0x%llx\n");
1083
1084 static int i915_frequency_info(struct seq_file *m, void *unused)
1085 {
1086         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1087         struct drm_device *dev = &dev_priv->drm;
1088         int ret = 0;
1089
1090         intel_runtime_pm_get(dev_priv);
1091
1092         if (IS_GEN5(dev_priv)) {
1093                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1094                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1095
1096                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1097                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1098                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1099                            MEMSTAT_VID_SHIFT);
1100                 seq_printf(m, "Current P-state: %d\n",
1101                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1102         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1103                 u32 freq_sts;
1104
1105                 mutex_lock(&dev_priv->rps.hw_lock);
1106                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1107                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1108                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1109
1110                 seq_printf(m, "actual GPU freq: %d MHz\n",
1111                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1112
1113                 seq_printf(m, "current GPU freq: %d MHz\n",
1114                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1115
1116                 seq_printf(m, "max GPU freq: %d MHz\n",
1117                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1118
1119                 seq_printf(m, "min GPU freq: %d MHz\n",
1120                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1121
1122                 seq_printf(m, "idle GPU freq: %d MHz\n",
1123                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1124
1125                 seq_printf(m,
1126                            "efficient (RPe) frequency: %d MHz\n",
1127                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1128                 mutex_unlock(&dev_priv->rps.hw_lock);
1129         } else if (INTEL_GEN(dev_priv) >= 6) {
1130                 u32 rp_state_limits;
1131                 u32 gt_perf_status;
1132                 u32 rp_state_cap;
1133                 u32 rpmodectl, rpinclimit, rpdeclimit;
1134                 u32 rpstat, cagf, reqf;
1135                 u32 rpupei, rpcurup, rpprevup;
1136                 u32 rpdownei, rpcurdown, rpprevdown;
1137                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1138                 int max_freq;
1139
1140                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1141                 if (IS_BROXTON(dev_priv)) {
1142                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1143                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1144                 } else {
1145                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1146                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1147                 }
1148
1149                 /* RPSTAT1 is in the GT power well */
1150                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1151                 if (ret)
1152                         goto out;
1153
1154                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1155
1156                 reqf = I915_READ(GEN6_RPNSWREQ);
1157                 if (IS_GEN9(dev_priv))
1158                         reqf >>= 23;
1159                 else {
1160                         reqf &= ~GEN6_TURBO_DISABLE;
1161                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1162                                 reqf >>= 24;
1163                         else
1164                                 reqf >>= 25;
1165                 }
1166                 reqf = intel_gpu_freq(dev_priv, reqf);
1167
1168                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1169                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1170                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1171
1172                 rpstat = I915_READ(GEN6_RPSTAT1);
1173                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1174                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1175                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1176                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1177                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1178                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1179                 if (IS_GEN9(dev_priv))
1180                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1181                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1182                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1183                 else
1184                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1185                 cagf = intel_gpu_freq(dev_priv, cagf);
1186
1187                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1188                 mutex_unlock(&dev->struct_mutex);
1189
1190                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1191                         pm_ier = I915_READ(GEN6_PMIER);
1192                         pm_imr = I915_READ(GEN6_PMIMR);
1193                         pm_isr = I915_READ(GEN6_PMISR);
1194                         pm_iir = I915_READ(GEN6_PMIIR);
1195                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1196                 } else {
1197                         pm_ier = I915_READ(GEN8_GT_IER(2));
1198                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1199                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1200                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1201                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1202                 }
1203                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1204                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1205                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1206                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1207                 seq_printf(m, "Render p-state ratio: %d\n",
1208                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1209                 seq_printf(m, "Render p-state VID: %d\n",
1210                            gt_perf_status & 0xff);
1211                 seq_printf(m, "Render p-state limit: %d\n",
1212                            rp_state_limits & 0xff);
1213                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1214                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1215                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1216                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1217                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1218                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1219                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1220                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1221                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1222                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1223                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1224                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1225                 seq_printf(m, "Up threshold: %d%%\n",
1226                            dev_priv->rps.up_threshold);
1227
1228                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1229                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1230                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1231                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1232                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1233                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1234                 seq_printf(m, "Down threshold: %d%%\n",
1235                            dev_priv->rps.down_threshold);
1236
1237                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1238                             rp_state_cap >> 16) & 0xff;
1239                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1240                              GEN9_FREQ_SCALER : 1);
1241                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1242                            intel_gpu_freq(dev_priv, max_freq));
1243
1244                 max_freq = (rp_state_cap & 0xff00) >> 8;
1245                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1246                              GEN9_FREQ_SCALER : 1);
1247                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1248                            intel_gpu_freq(dev_priv, max_freq));
1249
1250                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1251                             rp_state_cap >> 0) & 0xff;
1252                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1253                              GEN9_FREQ_SCALER : 1);
1254                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1255                            intel_gpu_freq(dev_priv, max_freq));
1256                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1257                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1258
1259                 seq_printf(m, "Current freq: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1261                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1262                 seq_printf(m, "Idle freq: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1264                 seq_printf(m, "Min freq: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1266                 seq_printf(m, "Boost freq: %d MHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1268                 seq_printf(m, "Max freq: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1270                 seq_printf(m,
1271                            "efficient (RPe) frequency: %d MHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1273         } else {
1274                 seq_puts(m, "no P-state info available\n");
1275         }
1276
1277         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1278         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1279         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1280
1281 out:
1282         intel_runtime_pm_put(dev_priv);
1283         return ret;
1284 }
1285
1286 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1287                                struct seq_file *m,
1288                                struct intel_instdone *instdone)
1289 {
1290         int slice;
1291         int subslice;
1292
1293         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1294                    instdone->instdone);
1295
1296         if (INTEL_GEN(dev_priv) <= 3)
1297                 return;
1298
1299         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1300                    instdone->slice_common);
1301
1302         if (INTEL_GEN(dev_priv) <= 6)
1303                 return;
1304
1305         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1306                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1307                            slice, subslice, instdone->sampler[slice][subslice]);
1308
1309         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1310                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1311                            slice, subslice, instdone->row[slice][subslice]);
1312 }
1313
1314 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1315 {
1316         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1317         struct intel_engine_cs *engine;
1318         u64 acthd[I915_NUM_ENGINES];
1319         u32 seqno[I915_NUM_ENGINES];
1320         struct intel_instdone instdone;
1321         enum intel_engine_id id;
1322
1323         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1324                 seq_printf(m, "Wedged\n");
1325         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1326                 seq_printf(m, "Reset in progress\n");
1327         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1328                 seq_printf(m, "Waiter holding struct mutex\n");
1329         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1330                 seq_printf(m, "struct_mutex blocked for reset\n");
1331
1332         if (!i915.enable_hangcheck) {
1333                 seq_printf(m, "Hangcheck disabled\n");
1334                 return 0;
1335         }
1336
1337         intel_runtime_pm_get(dev_priv);
1338
1339         for_each_engine_id(engine, dev_priv, id) {
1340                 acthd[id] = intel_engine_get_active_head(engine);
1341                 seqno[id] = intel_engine_get_seqno(engine);
1342         }
1343
1344         i915_get_engine_instdone(dev_priv, RCS, &instdone);
1345
1346         intel_runtime_pm_put(dev_priv);
1347
1348         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1349                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1350                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1351                                             jiffies));
1352         } else
1353                 seq_printf(m, "Hangcheck inactive\n");
1354
1355         for_each_engine_id(engine, dev_priv, id) {
1356                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1357                 struct rb_node *rb;
1358
1359                 seq_printf(m, "%s:\n", engine->name);
1360                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1361                            engine->hangcheck.seqno,
1362                            seqno[id],
1363                            engine->last_submitted_seqno);
1364                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1365                            yesno(intel_engine_has_waiter(engine)),
1366                            yesno(test_bit(engine->id,
1367                                           &dev_priv->gpu_error.missed_irq_rings)));
1368                 spin_lock(&b->lock);
1369                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1370                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1371
1372                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1373                                    w->tsk->comm, w->tsk->pid, w->seqno);
1374                 }
1375                 spin_unlock(&b->lock);
1376
1377                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1378                            (long long)engine->hangcheck.acthd,
1379                            (long long)acthd[id]);
1380                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1381                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1382
1383                 if (engine->id == RCS) {
1384                         seq_puts(m, "\tinstdone read =\n");
1385
1386                         i915_instdone_info(dev_priv, m, &instdone);
1387
1388                         seq_puts(m, "\tinstdone accu =\n");
1389
1390                         i915_instdone_info(dev_priv, m,
1391                                            &engine->hangcheck.instdone);
1392                 }
1393         }
1394
1395         return 0;
1396 }
1397
1398 static int ironlake_drpc_info(struct seq_file *m)
1399 {
1400         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1401         struct drm_device *dev = &dev_priv->drm;
1402         u32 rgvmodectl, rstdbyctl;
1403         u16 crstandvid;
1404         int ret;
1405
1406         ret = mutex_lock_interruptible(&dev->struct_mutex);
1407         if (ret)
1408                 return ret;
1409         intel_runtime_pm_get(dev_priv);
1410
1411         rgvmodectl = I915_READ(MEMMODECTL);
1412         rstdbyctl = I915_READ(RSTDBYCTL);
1413         crstandvid = I915_READ16(CRSTANDVID);
1414
1415         intel_runtime_pm_put(dev_priv);
1416         mutex_unlock(&dev->struct_mutex);
1417
1418         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1419         seq_printf(m, "Boost freq: %d\n",
1420                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1421                    MEMMODE_BOOST_FREQ_SHIFT);
1422         seq_printf(m, "HW control enabled: %s\n",
1423                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1424         seq_printf(m, "SW control enabled: %s\n",
1425                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1426         seq_printf(m, "Gated voltage change: %s\n",
1427                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1428         seq_printf(m, "Starting frequency: P%d\n",
1429                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1430         seq_printf(m, "Max P-state: P%d\n",
1431                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1432         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1433         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1434         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1435         seq_printf(m, "Render standby enabled: %s\n",
1436                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1437         seq_puts(m, "Current RS state: ");
1438         switch (rstdbyctl & RSX_STATUS_MASK) {
1439         case RSX_STATUS_ON:
1440                 seq_puts(m, "on\n");
1441                 break;
1442         case RSX_STATUS_RC1:
1443                 seq_puts(m, "RC1\n");
1444                 break;
1445         case RSX_STATUS_RC1E:
1446                 seq_puts(m, "RC1E\n");
1447                 break;
1448         case RSX_STATUS_RS1:
1449                 seq_puts(m, "RS1\n");
1450                 break;
1451         case RSX_STATUS_RS2:
1452                 seq_puts(m, "RS2 (RC6)\n");
1453                 break;
1454         case RSX_STATUS_RS3:
1455                 seq_puts(m, "RC3 (RC6+)\n");
1456                 break;
1457         default:
1458                 seq_puts(m, "unknown\n");
1459                 break;
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int i915_forcewake_domains(struct seq_file *m, void *data)
1466 {
1467         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1468         struct intel_uncore_forcewake_domain *fw_domain;
1469
1470         spin_lock_irq(&dev_priv->uncore.lock);
1471         for_each_fw_domain(fw_domain, dev_priv) {
1472                 seq_printf(m, "%s.wake_count = %u\n",
1473                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1474                            fw_domain->wake_count);
1475         }
1476         spin_unlock_irq(&dev_priv->uncore.lock);
1477
1478         return 0;
1479 }
1480
1481 static int vlv_drpc_info(struct seq_file *m)
1482 {
1483         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1484         u32 rpmodectl1, rcctl1, pw_status;
1485
1486         intel_runtime_pm_get(dev_priv);
1487
1488         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1489         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1490         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1491
1492         intel_runtime_pm_put(dev_priv);
1493
1494         seq_printf(m, "Video Turbo Mode: %s\n",
1495                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1496         seq_printf(m, "Turbo enabled: %s\n",
1497                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498         seq_printf(m, "HW control enabled: %s\n",
1499                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500         seq_printf(m, "SW control enabled: %s\n",
1501                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1502                           GEN6_RP_MEDIA_SW_MODE));
1503         seq_printf(m, "RC6 Enabled: %s\n",
1504                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1505                                         GEN6_RC_CTL_EI_MODE(1))));
1506         seq_printf(m, "Render Power Well: %s\n",
1507                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1508         seq_printf(m, "Media Power Well: %s\n",
1509                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1510
1511         seq_printf(m, "Render RC6 residency since boot: %u\n",
1512                    I915_READ(VLV_GT_RENDER_RC6));
1513         seq_printf(m, "Media RC6 residency since boot: %u\n",
1514                    I915_READ(VLV_GT_MEDIA_RC6));
1515
1516         return i915_forcewake_domains(m, NULL);
1517 }
1518
1519 static int gen6_drpc_info(struct seq_file *m)
1520 {
1521         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1522         struct drm_device *dev = &dev_priv->drm;
1523         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1524         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1525         unsigned forcewake_count;
1526         int count = 0, ret;
1527
1528         ret = mutex_lock_interruptible(&dev->struct_mutex);
1529         if (ret)
1530                 return ret;
1531         intel_runtime_pm_get(dev_priv);
1532
1533         spin_lock_irq(&dev_priv->uncore.lock);
1534         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1535         spin_unlock_irq(&dev_priv->uncore.lock);
1536
1537         if (forcewake_count) {
1538                 seq_puts(m, "RC information inaccurate because somebody "
1539                             "holds a forcewake reference \n");
1540         } else {
1541                 /* NB: we cannot use forcewake, else we read the wrong values */
1542                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1543                         udelay(10);
1544                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1545         }
1546
1547         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1548         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1549
1550         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1551         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1552         if (INTEL_GEN(dev_priv) >= 9) {
1553                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1554                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1555         }
1556         mutex_unlock(&dev->struct_mutex);
1557         mutex_lock(&dev_priv->rps.hw_lock);
1558         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1559         mutex_unlock(&dev_priv->rps.hw_lock);
1560
1561         intel_runtime_pm_put(dev_priv);
1562
1563         seq_printf(m, "Video Turbo Mode: %s\n",
1564                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1565         seq_printf(m, "HW control enabled: %s\n",
1566                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1567         seq_printf(m, "SW control enabled: %s\n",
1568                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1569                           GEN6_RP_MEDIA_SW_MODE));
1570         seq_printf(m, "RC1e Enabled: %s\n",
1571                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1572         seq_printf(m, "RC6 Enabled: %s\n",
1573                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1574         if (INTEL_GEN(dev_priv) >= 9) {
1575                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1576                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1577                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1578                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1579         }
1580         seq_printf(m, "Deep RC6 Enabled: %s\n",
1581                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1582         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1583                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1584         seq_puts(m, "Current RC state: ");
1585         switch (gt_core_status & GEN6_RCn_MASK) {
1586         case GEN6_RC0:
1587                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1588                         seq_puts(m, "Core Power Down\n");
1589                 else
1590                         seq_puts(m, "on\n");
1591                 break;
1592         case GEN6_RC3:
1593                 seq_puts(m, "RC3\n");
1594                 break;
1595         case GEN6_RC6:
1596                 seq_puts(m, "RC6\n");
1597                 break;
1598         case GEN6_RC7:
1599                 seq_puts(m, "RC7\n");
1600                 break;
1601         default:
1602                 seq_puts(m, "Unknown\n");
1603                 break;
1604         }
1605
1606         seq_printf(m, "Core Power Down: %s\n",
1607                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1608         if (INTEL_GEN(dev_priv) >= 9) {
1609                 seq_printf(m, "Render Power Well: %s\n",
1610                         (gen9_powergate_status &
1611                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1612                 seq_printf(m, "Media Power Well: %s\n",
1613                         (gen9_powergate_status &
1614                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1615         }
1616
1617         /* Not exactly sure what this is */
1618         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1619                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1620         seq_printf(m, "RC6 residency since boot: %u\n",
1621                    I915_READ(GEN6_GT_GFX_RC6));
1622         seq_printf(m, "RC6+ residency since boot: %u\n",
1623                    I915_READ(GEN6_GT_GFX_RC6p));
1624         seq_printf(m, "RC6++ residency since boot: %u\n",
1625                    I915_READ(GEN6_GT_GFX_RC6pp));
1626
1627         seq_printf(m, "RC6   voltage: %dmV\n",
1628                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1629         seq_printf(m, "RC6+  voltage: %dmV\n",
1630                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1631         seq_printf(m, "RC6++ voltage: %dmV\n",
1632                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1633         return i915_forcewake_domains(m, NULL);
1634 }
1635
1636 static int i915_drpc_info(struct seq_file *m, void *unused)
1637 {
1638         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1639
1640         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1641                 return vlv_drpc_info(m);
1642         else if (INTEL_GEN(dev_priv) >= 6)
1643                 return gen6_drpc_info(m);
1644         else
1645                 return ironlake_drpc_info(m);
1646 }
1647
1648 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1649 {
1650         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1651
1652         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1653                    dev_priv->fb_tracking.busy_bits);
1654
1655         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1656                    dev_priv->fb_tracking.flip_bits);
1657
1658         return 0;
1659 }
1660
1661 static int i915_fbc_status(struct seq_file *m, void *unused)
1662 {
1663         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1664
1665         if (!HAS_FBC(dev_priv)) {
1666                 seq_puts(m, "FBC unsupported on this chipset\n");
1667                 return 0;
1668         }
1669
1670         intel_runtime_pm_get(dev_priv);
1671         mutex_lock(&dev_priv->fbc.lock);
1672
1673         if (intel_fbc_is_active(dev_priv))
1674                 seq_puts(m, "FBC enabled\n");
1675         else
1676                 seq_printf(m, "FBC disabled: %s\n",
1677                            dev_priv->fbc.no_fbc_reason);
1678
1679         if (intel_fbc_is_active(dev_priv) &&
1680             INTEL_GEN(dev_priv) >= 7)
1681                 seq_printf(m, "Compressing: %s\n",
1682                            yesno(I915_READ(FBC_STATUS2) &
1683                                  FBC_COMPRESSION_MASK));
1684
1685         mutex_unlock(&dev_priv->fbc.lock);
1686         intel_runtime_pm_put(dev_priv);
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_get(void *data, u64 *val)
1692 {
1693         struct drm_i915_private *dev_priv = data;
1694
1695         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1696                 return -ENODEV;
1697
1698         *val = dev_priv->fbc.false_color;
1699
1700         return 0;
1701 }
1702
1703 static int i915_fbc_fc_set(void *data, u64 val)
1704 {
1705         struct drm_i915_private *dev_priv = data;
1706         u32 reg;
1707
1708         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1709                 return -ENODEV;
1710
1711         mutex_lock(&dev_priv->fbc.lock);
1712
1713         reg = I915_READ(ILK_DPFC_CONTROL);
1714         dev_priv->fbc.false_color = val;
1715
1716         I915_WRITE(ILK_DPFC_CONTROL, val ?
1717                    (reg | FBC_CTL_FALSE_COLOR) :
1718                    (reg & ~FBC_CTL_FALSE_COLOR));
1719
1720         mutex_unlock(&dev_priv->fbc.lock);
1721         return 0;
1722 }
1723
1724 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1725                         i915_fbc_fc_get, i915_fbc_fc_set,
1726                         "%llu\n");
1727
1728 static int i915_ips_status(struct seq_file *m, void *unused)
1729 {
1730         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1731
1732         if (!HAS_IPS(dev_priv)) {
1733                 seq_puts(m, "not supported\n");
1734                 return 0;
1735         }
1736
1737         intel_runtime_pm_get(dev_priv);
1738
1739         seq_printf(m, "Enabled by kernel parameter: %s\n",
1740                    yesno(i915.enable_ips));
1741
1742         if (INTEL_GEN(dev_priv) >= 8) {
1743                 seq_puts(m, "Currently: unknown\n");
1744         } else {
1745                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1746                         seq_puts(m, "Currently: enabled\n");
1747                 else
1748                         seq_puts(m, "Currently: disabled\n");
1749         }
1750
1751         intel_runtime_pm_put(dev_priv);
1752
1753         return 0;
1754 }
1755
1756 static int i915_sr_status(struct seq_file *m, void *unused)
1757 {
1758         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1759         bool sr_enabled = false;
1760
1761         intel_runtime_pm_get(dev_priv);
1762
1763         if (HAS_PCH_SPLIT(dev_priv))
1764                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1765         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1766                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1767                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1768         else if (IS_I915GM(dev_priv))
1769                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1770         else if (IS_PINEVIEW(dev_priv))
1771                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1772         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1773                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1774
1775         intel_runtime_pm_put(dev_priv);
1776
1777         seq_printf(m, "self-refresh: %s\n",
1778                    sr_enabled ? "enabled" : "disabled");
1779
1780         return 0;
1781 }
1782
1783 static int i915_emon_status(struct seq_file *m, void *unused)
1784 {
1785         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1786         struct drm_device *dev = &dev_priv->drm;
1787         unsigned long temp, chipset, gfx;
1788         int ret;
1789
1790         if (!IS_GEN5(dev_priv))
1791                 return -ENODEV;
1792
1793         ret = mutex_lock_interruptible(&dev->struct_mutex);
1794         if (ret)
1795                 return ret;
1796
1797         temp = i915_mch_val(dev_priv);
1798         chipset = i915_chipset_val(dev_priv);
1799         gfx = i915_gfx_val(dev_priv);
1800         mutex_unlock(&dev->struct_mutex);
1801
1802         seq_printf(m, "GMCH temp: %ld\n", temp);
1803         seq_printf(m, "Chipset power: %ld\n", chipset);
1804         seq_printf(m, "GFX power: %ld\n", gfx);
1805         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1806
1807         return 0;
1808 }
1809
1810 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1811 {
1812         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1813         int ret = 0;
1814         int gpu_freq, ia_freq;
1815         unsigned int max_gpu_freq, min_gpu_freq;
1816
1817         if (!HAS_LLC(dev_priv)) {
1818                 seq_puts(m, "unsupported on this chipset\n");
1819                 return 0;
1820         }
1821
1822         intel_runtime_pm_get(dev_priv);
1823
1824         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1825         if (ret)
1826                 goto out;
1827
1828         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1829                 /* Convert GT frequency to 50 HZ units */
1830                 min_gpu_freq =
1831                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1832                 max_gpu_freq =
1833                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1834         } else {
1835                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1836                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1837         }
1838
1839         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1840
1841         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1842                 ia_freq = gpu_freq;
1843                 sandybridge_pcode_read(dev_priv,
1844                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1845                                        &ia_freq);
1846                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1847                            intel_gpu_freq(dev_priv, (gpu_freq *
1848                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1849                                  GEN9_FREQ_SCALER : 1))),
1850                            ((ia_freq >> 0) & 0xff) * 100,
1851                            ((ia_freq >> 8) & 0xff) * 100);
1852         }
1853
1854         mutex_unlock(&dev_priv->rps.hw_lock);
1855
1856 out:
1857         intel_runtime_pm_put(dev_priv);
1858         return ret;
1859 }
1860
1861 static int i915_opregion(struct seq_file *m, void *unused)
1862 {
1863         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1864         struct drm_device *dev = &dev_priv->drm;
1865         struct intel_opregion *opregion = &dev_priv->opregion;
1866         int ret;
1867
1868         ret = mutex_lock_interruptible(&dev->struct_mutex);
1869         if (ret)
1870                 goto out;
1871
1872         if (opregion->header)
1873                 seq_write(m, opregion->header, OPREGION_SIZE);
1874
1875         mutex_unlock(&dev->struct_mutex);
1876
1877 out:
1878         return 0;
1879 }
1880
1881 static int i915_vbt(struct seq_file *m, void *unused)
1882 {
1883         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1884
1885         if (opregion->vbt)
1886                 seq_write(m, opregion->vbt, opregion->vbt_size);
1887
1888         return 0;
1889 }
1890
1891 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1892 {
1893         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1894         struct drm_device *dev = &dev_priv->drm;
1895         struct intel_framebuffer *fbdev_fb = NULL;
1896         struct drm_framebuffer *drm_fb;
1897         int ret;
1898
1899         ret = mutex_lock_interruptible(&dev->struct_mutex);
1900         if (ret)
1901                 return ret;
1902
1903 #ifdef CONFIG_DRM_FBDEV_EMULATION
1904         if (dev_priv->fbdev) {
1905                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1906
1907                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1908                            fbdev_fb->base.width,
1909                            fbdev_fb->base.height,
1910                            fbdev_fb->base.depth,
1911                            fbdev_fb->base.bits_per_pixel,
1912                            fbdev_fb->base.modifier[0],
1913                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1914                 describe_obj(m, fbdev_fb->obj);
1915                 seq_putc(m, '\n');
1916         }
1917 #endif
1918
1919         mutex_lock(&dev->mode_config.fb_lock);
1920         drm_for_each_fb(drm_fb, dev) {
1921                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1922                 if (fb == fbdev_fb)
1923                         continue;
1924
1925                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1926                            fb->base.width,
1927                            fb->base.height,
1928                            fb->base.depth,
1929                            fb->base.bits_per_pixel,
1930                            fb->base.modifier[0],
1931                            drm_framebuffer_read_refcount(&fb->base));
1932                 describe_obj(m, fb->obj);
1933                 seq_putc(m, '\n');
1934         }
1935         mutex_unlock(&dev->mode_config.fb_lock);
1936         mutex_unlock(&dev->struct_mutex);
1937
1938         return 0;
1939 }
1940
1941 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1942 {
1943         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1944                    ring->space, ring->head, ring->tail,
1945                    ring->last_retired_head);
1946 }
1947
1948 static int i915_context_status(struct seq_file *m, void *unused)
1949 {
1950         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1951         struct drm_device *dev = &dev_priv->drm;
1952         struct intel_engine_cs *engine;
1953         struct i915_gem_context *ctx;
1954         int ret;
1955
1956         ret = mutex_lock_interruptible(&dev->struct_mutex);
1957         if (ret)
1958                 return ret;
1959
1960         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1961                 seq_printf(m, "HW context %u ", ctx->hw_id);
1962                 if (ctx->pid) {
1963                         struct task_struct *task;
1964
1965                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1966                         if (task) {
1967                                 seq_printf(m, "(%s [%d]) ",
1968                                            task->comm, task->pid);
1969                                 put_task_struct(task);
1970                         }
1971                 } else if (IS_ERR(ctx->file_priv)) {
1972                         seq_puts(m, "(deleted) ");
1973                 } else {
1974                         seq_puts(m, "(kernel) ");
1975                 }
1976
1977                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1978                 seq_putc(m, '\n');
1979
1980                 for_each_engine(engine, dev_priv) {
1981                         struct intel_context *ce = &ctx->engine[engine->id];
1982
1983                         seq_printf(m, "%s: ", engine->name);
1984                         seq_putc(m, ce->initialised ? 'I' : 'i');
1985                         if (ce->state)
1986                                 describe_obj(m, ce->state->obj);
1987                         if (ce->ring)
1988                                 describe_ctx_ring(m, ce->ring);
1989                         seq_putc(m, '\n');
1990                 }
1991
1992                 seq_putc(m, '\n');
1993         }
1994
1995         mutex_unlock(&dev->struct_mutex);
1996
1997         return 0;
1998 }
1999
2000 static void i915_dump_lrc_obj(struct seq_file *m,
2001                               struct i915_gem_context *ctx,
2002                               struct intel_engine_cs *engine)
2003 {
2004         struct i915_vma *vma = ctx->engine[engine->id].state;
2005         struct page *page;
2006         int j;
2007
2008         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2009
2010         if (!vma) {
2011                 seq_puts(m, "\tFake context\n");
2012                 return;
2013         }
2014
2015         if (vma->flags & I915_VMA_GLOBAL_BIND)
2016                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2017                            i915_ggtt_offset(vma));
2018
2019         if (i915_gem_object_get_pages(vma->obj)) {
2020                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2021                 return;
2022         }
2023
2024         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2025         if (page) {
2026                 u32 *reg_state = kmap_atomic(page);
2027
2028                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2029                         seq_printf(m,
2030                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2031                                    j * 4,
2032                                    reg_state[j], reg_state[j + 1],
2033                                    reg_state[j + 2], reg_state[j + 3]);
2034                 }
2035                 kunmap_atomic(reg_state);
2036         }
2037
2038         seq_putc(m, '\n');
2039 }
2040
2041 static int i915_dump_lrc(struct seq_file *m, void *unused)
2042 {
2043         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2044         struct drm_device *dev = &dev_priv->drm;
2045         struct intel_engine_cs *engine;
2046         struct i915_gem_context *ctx;
2047         int ret;
2048
2049         if (!i915.enable_execlists) {
2050                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2051                 return 0;
2052         }
2053
2054         ret = mutex_lock_interruptible(&dev->struct_mutex);
2055         if (ret)
2056                 return ret;
2057
2058         list_for_each_entry(ctx, &dev_priv->context_list, link)
2059                 for_each_engine(engine, dev_priv)
2060                         i915_dump_lrc_obj(m, ctx, engine);
2061
2062         mutex_unlock(&dev->struct_mutex);
2063
2064         return 0;
2065 }
2066
2067 static const char *swizzle_string(unsigned swizzle)
2068 {
2069         switch (swizzle) {
2070         case I915_BIT_6_SWIZZLE_NONE:
2071                 return "none";
2072         case I915_BIT_6_SWIZZLE_9:
2073                 return "bit9";
2074         case I915_BIT_6_SWIZZLE_9_10:
2075                 return "bit9/bit10";
2076         case I915_BIT_6_SWIZZLE_9_11:
2077                 return "bit9/bit11";
2078         case I915_BIT_6_SWIZZLE_9_10_11:
2079                 return "bit9/bit10/bit11";
2080         case I915_BIT_6_SWIZZLE_9_17:
2081                 return "bit9/bit17";
2082         case I915_BIT_6_SWIZZLE_9_10_17:
2083                 return "bit9/bit10/bit17";
2084         case I915_BIT_6_SWIZZLE_UNKNOWN:
2085                 return "unknown";
2086         }
2087
2088         return "bug";
2089 }
2090
2091 static int i915_swizzle_info(struct seq_file *m, void *data)
2092 {
2093         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2094         struct drm_device *dev = &dev_priv->drm;
2095         int ret;
2096
2097         ret = mutex_lock_interruptible(&dev->struct_mutex);
2098         if (ret)
2099                 return ret;
2100         intel_runtime_pm_get(dev_priv);
2101
2102         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2103                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2104         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2105                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2106
2107         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2108                 seq_printf(m, "DDC = 0x%08x\n",
2109                            I915_READ(DCC));
2110                 seq_printf(m, "DDC2 = 0x%08x\n",
2111                            I915_READ(DCC2));
2112                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2113                            I915_READ16(C0DRB3));
2114                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2115                            I915_READ16(C1DRB3));
2116         } else if (INTEL_GEN(dev_priv) >= 6) {
2117                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2118                            I915_READ(MAD_DIMM_C0));
2119                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2120                            I915_READ(MAD_DIMM_C1));
2121                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2122                            I915_READ(MAD_DIMM_C2));
2123                 seq_printf(m, "TILECTL = 0x%08x\n",
2124                            I915_READ(TILECTL));
2125                 if (INTEL_GEN(dev_priv) >= 8)
2126                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2127                                    I915_READ(GAMTARBMODE));
2128                 else
2129                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2130                                    I915_READ(ARB_MODE));
2131                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2132                            I915_READ(DISP_ARB_CTL));
2133         }
2134
2135         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2136                 seq_puts(m, "L-shaped memory detected\n");
2137
2138         intel_runtime_pm_put(dev_priv);
2139         mutex_unlock(&dev->struct_mutex);
2140
2141         return 0;
2142 }
2143
2144 static int per_file_ctx(int id, void *ptr, void *data)
2145 {
2146         struct i915_gem_context *ctx = ptr;
2147         struct seq_file *m = data;
2148         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2149
2150         if (!ppgtt) {
2151                 seq_printf(m, "  no ppgtt for context %d\n",
2152                            ctx->user_handle);
2153                 return 0;
2154         }
2155
2156         if (i915_gem_context_is_default(ctx))
2157                 seq_puts(m, "  default context:\n");
2158         else
2159                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2160         ppgtt->debug_dump(ppgtt, m);
2161
2162         return 0;
2163 }
2164
2165 static void gen8_ppgtt_info(struct seq_file *m,
2166                             struct drm_i915_private *dev_priv)
2167 {
2168         struct intel_engine_cs *engine;
2169         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2170         int i;
2171
2172         if (!ppgtt)
2173                 return;
2174
2175         for_each_engine(engine, dev_priv) {
2176                 seq_printf(m, "%s\n", engine->name);
2177                 for (i = 0; i < 4; i++) {
2178                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2179                         pdp <<= 32;
2180                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2181                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2182                 }
2183         }
2184 }
2185
2186 static void gen6_ppgtt_info(struct seq_file *m,
2187                             struct drm_i915_private *dev_priv)
2188 {
2189         struct intel_engine_cs *engine;
2190
2191         if (IS_GEN6(dev_priv))
2192                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2193
2194         for_each_engine(engine, dev_priv) {
2195                 seq_printf(m, "%s\n", engine->name);
2196                 if (IS_GEN7(dev_priv))
2197                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2198                                    I915_READ(RING_MODE_GEN7(engine)));
2199                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2200                            I915_READ(RING_PP_DIR_BASE(engine)));
2201                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2202                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2203                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2204                            I915_READ(RING_PP_DIR_DCLV(engine)));
2205         }
2206         if (dev_priv->mm.aliasing_ppgtt) {
2207                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2208
2209                 seq_puts(m, "aliasing PPGTT:\n");
2210                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2211
2212                 ppgtt->debug_dump(ppgtt, m);
2213         }
2214
2215         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2216 }
2217
2218 static int i915_ppgtt_info(struct seq_file *m, void *data)
2219 {
2220         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2221         struct drm_device *dev = &dev_priv->drm;
2222         struct drm_file *file;
2223         int ret;
2224
2225         mutex_lock(&dev->filelist_mutex);
2226         ret = mutex_lock_interruptible(&dev->struct_mutex);
2227         if (ret)
2228                 goto out_unlock;
2229
2230         intel_runtime_pm_get(dev_priv);
2231
2232         if (INTEL_GEN(dev_priv) >= 8)
2233                 gen8_ppgtt_info(m, dev_priv);
2234         else if (INTEL_GEN(dev_priv) >= 6)
2235                 gen6_ppgtt_info(m, dev_priv);
2236
2237         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2238                 struct drm_i915_file_private *file_priv = file->driver_priv;
2239                 struct task_struct *task;
2240
2241                 task = get_pid_task(file->pid, PIDTYPE_PID);
2242                 if (!task) {
2243                         ret = -ESRCH;
2244                         goto out_rpm;
2245                 }
2246                 seq_printf(m, "\nproc: %s\n", task->comm);
2247                 put_task_struct(task);
2248                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2249                              (void *)(unsigned long)m);
2250         }
2251
2252 out_rpm:
2253         intel_runtime_pm_put(dev_priv);
2254         mutex_unlock(&dev->struct_mutex);
2255 out_unlock:
2256         mutex_unlock(&dev->filelist_mutex);
2257         return ret;
2258 }
2259
2260 static int count_irq_waiters(struct drm_i915_private *i915)
2261 {
2262         struct intel_engine_cs *engine;
2263         int count = 0;
2264
2265         for_each_engine(engine, i915)
2266                 count += intel_engine_has_waiter(engine);
2267
2268         return count;
2269 }
2270
2271 static const char *rps_power_to_str(unsigned int power)
2272 {
2273         static const char * const strings[] = {
2274                 [LOW_POWER] = "low power",
2275                 [BETWEEN] = "mixed",
2276                 [HIGH_POWER] = "high power",
2277         };
2278
2279         if (power >= ARRAY_SIZE(strings) || !strings[power])
2280                 return "unknown";
2281
2282         return strings[power];
2283 }
2284
2285 static int i915_rps_boost_info(struct seq_file *m, void *data)
2286 {
2287         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2288         struct drm_device *dev = &dev_priv->drm;
2289         struct drm_file *file;
2290
2291         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2292         seq_printf(m, "GPU busy? %s [%x]\n",
2293                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2294         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2295         seq_printf(m, "Frequency requested %d\n",
2296                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2297         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2299                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2300                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2301                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2302         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2303                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2304                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2305                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2306
2307         mutex_lock(&dev->filelist_mutex);
2308         spin_lock(&dev_priv->rps.client_lock);
2309         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2310                 struct drm_i915_file_private *file_priv = file->driver_priv;
2311                 struct task_struct *task;
2312
2313                 rcu_read_lock();
2314                 task = pid_task(file->pid, PIDTYPE_PID);
2315                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2316                            task ? task->comm : "<unknown>",
2317                            task ? task->pid : -1,
2318                            file_priv->rps.boosts,
2319                            list_empty(&file_priv->rps.link) ? "" : ", active");
2320                 rcu_read_unlock();
2321         }
2322         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2323         spin_unlock(&dev_priv->rps.client_lock);
2324         mutex_unlock(&dev->filelist_mutex);
2325
2326         if (INTEL_GEN(dev_priv) >= 6 &&
2327             dev_priv->rps.enabled &&
2328             dev_priv->gt.active_engines) {
2329                 u32 rpup, rpupei;
2330                 u32 rpdown, rpdownei;
2331
2332                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2333                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2334                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2335                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2336                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2337                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2338
2339                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2340                            rps_power_to_str(dev_priv->rps.power));
2341                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2342                            100 * rpup / rpupei,
2343                            dev_priv->rps.up_threshold);
2344                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2345                            100 * rpdown / rpdownei,
2346                            dev_priv->rps.down_threshold);
2347         } else {
2348                 seq_puts(m, "\nRPS Autotuning inactive\n");
2349         }
2350
2351         return 0;
2352 }
2353
2354 static int i915_llc(struct seq_file *m, void *data)
2355 {
2356         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2357         const bool edram = INTEL_GEN(dev_priv) > 8;
2358
2359         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2360         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2361                    intel_uncore_edram_size(dev_priv)/1024/1024);
2362
2363         return 0;
2364 }
2365
2366 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2367 {
2368         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2369         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2370         u32 tmp, i;
2371
2372         if (!HAS_GUC_UCODE(dev_priv))
2373                 return 0;
2374
2375         seq_printf(m, "GuC firmware status:\n");
2376         seq_printf(m, "\tpath: %s\n",
2377                 guc_fw->guc_fw_path);
2378         seq_printf(m, "\tfetch: %s\n",
2379                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2380         seq_printf(m, "\tload: %s\n",
2381                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2382         seq_printf(m, "\tversion wanted: %d.%d\n",
2383                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2384         seq_printf(m, "\tversion found: %d.%d\n",
2385                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2386         seq_printf(m, "\theader: offset is %d; size = %d\n",
2387                 guc_fw->header_offset, guc_fw->header_size);
2388         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2389                 guc_fw->ucode_offset, guc_fw->ucode_size);
2390         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2391                 guc_fw->rsa_offset, guc_fw->rsa_size);
2392
2393         tmp = I915_READ(GUC_STATUS);
2394
2395         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2396         seq_printf(m, "\tBootrom status = 0x%x\n",
2397                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2398         seq_printf(m, "\tuKernel status = 0x%x\n",
2399                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2400         seq_printf(m, "\tMIA Core status = 0x%x\n",
2401                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2402         seq_puts(m, "\nScratch registers:\n");
2403         for (i = 0; i < 16; i++)
2404                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2405
2406         return 0;
2407 }
2408
2409 static void i915_guc_client_info(struct seq_file *m,
2410                                  struct drm_i915_private *dev_priv,
2411                                  struct i915_guc_client *client)
2412 {
2413         struct intel_engine_cs *engine;
2414         enum intel_engine_id id;
2415         uint64_t tot = 0;
2416
2417         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2418                 client->priority, client->ctx_index, client->proc_desc_offset);
2419         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2420                 client->doorbell_id, client->doorbell_offset, client->cookie);
2421         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2422                 client->wq_size, client->wq_offset, client->wq_tail);
2423
2424         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2425         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2426         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2427
2428         for_each_engine_id(engine, dev_priv, id) {
2429                 u64 submissions = client->submissions[id];
2430                 tot += submissions;
2431                 seq_printf(m, "\tSubmissions: %llu %s\n",
2432                                 submissions, engine->name);
2433         }
2434         seq_printf(m, "\tTotal: %llu\n", tot);
2435 }
2436
2437 static int i915_guc_info(struct seq_file *m, void *data)
2438 {
2439         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2440         struct drm_device *dev = &dev_priv->drm;
2441         struct intel_guc guc;
2442         struct i915_guc_client client = {};
2443         struct intel_engine_cs *engine;
2444         enum intel_engine_id id;
2445         u64 total = 0;
2446
2447         if (!HAS_GUC_SCHED(dev_priv))
2448                 return 0;
2449
2450         if (mutex_lock_interruptible(&dev->struct_mutex))
2451                 return 0;
2452
2453         /* Take a local copy of the GuC data, so we can dump it at leisure */
2454         guc = dev_priv->guc;
2455         if (guc.execbuf_client)
2456                 client = *guc.execbuf_client;
2457
2458         mutex_unlock(&dev->struct_mutex);
2459
2460         seq_printf(m, "Doorbell map:\n");
2461         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2462         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2463
2464         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2465         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2466         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2467         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2468         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2469
2470         seq_printf(m, "\nGuC submissions:\n");
2471         for_each_engine_id(engine, dev_priv, id) {
2472                 u64 submissions = guc.submissions[id];
2473                 total += submissions;
2474                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2475                         engine->name, submissions, guc.last_seqno[id]);
2476         }
2477         seq_printf(m, "\t%s: %llu\n", "Total", total);
2478
2479         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2480         i915_guc_client_info(m, dev_priv, &client);
2481
2482         /* Add more as required ... */
2483
2484         return 0;
2485 }
2486
2487 static int i915_guc_log_dump(struct seq_file *m, void *data)
2488 {
2489         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2490         struct drm_i915_gem_object *obj;
2491         int i = 0, pg;
2492
2493         if (!dev_priv->guc.log_vma)
2494                 return 0;
2495
2496         obj = dev_priv->guc.log_vma->obj;
2497         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2498                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2499
2500                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2501                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2502                                    *(log + i), *(log + i + 1),
2503                                    *(log + i + 2), *(log + i + 3));
2504
2505                 kunmap_atomic(log);
2506         }
2507
2508         seq_putc(m, '\n');
2509
2510         return 0;
2511 }
2512
2513 static int i915_edp_psr_status(struct seq_file *m, void *data)
2514 {
2515         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2516         u32 psrperf = 0;
2517         u32 stat[3];
2518         enum pipe pipe;
2519         bool enabled = false;
2520
2521         if (!HAS_PSR(dev_priv)) {
2522                 seq_puts(m, "PSR not supported\n");
2523                 return 0;
2524         }
2525
2526         intel_runtime_pm_get(dev_priv);
2527
2528         mutex_lock(&dev_priv->psr.lock);
2529         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2530         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2531         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2532         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2533         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2534                    dev_priv->psr.busy_frontbuffer_bits);
2535         seq_printf(m, "Re-enable work scheduled: %s\n",
2536                    yesno(work_busy(&dev_priv->psr.work.work)));
2537
2538         if (HAS_DDI(dev_priv))
2539                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2540         else {
2541                 for_each_pipe(dev_priv, pipe) {
2542                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2543                                 VLV_EDP_PSR_CURR_STATE_MASK;
2544                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2545                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2546                                 enabled = true;
2547                 }
2548         }
2549
2550         seq_printf(m, "Main link in standby mode: %s\n",
2551                    yesno(dev_priv->psr.link_standby));
2552
2553         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2554
2555         if (!HAS_DDI(dev_priv))
2556                 for_each_pipe(dev_priv, pipe) {
2557                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2558                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2559                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2560                 }
2561         seq_puts(m, "\n");
2562
2563         /*
2564          * VLV/CHV PSR has no kind of performance counter
2565          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2566          */
2567         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2568                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2569                         EDP_PSR_PERF_CNT_MASK;
2570
2571                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2572         }
2573         mutex_unlock(&dev_priv->psr.lock);
2574
2575         intel_runtime_pm_put(dev_priv);
2576         return 0;
2577 }
2578
2579 static int i915_sink_crc(struct seq_file *m, void *data)
2580 {
2581         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2582         struct drm_device *dev = &dev_priv->drm;
2583         struct intel_connector *connector;
2584         struct intel_dp *intel_dp = NULL;
2585         int ret;
2586         u8 crc[6];
2587
2588         drm_modeset_lock_all(dev);
2589         for_each_intel_connector(dev, connector) {
2590                 struct drm_crtc *crtc;
2591
2592                 if (!connector->base.state->best_encoder)
2593                         continue;
2594
2595                 crtc = connector->base.state->crtc;
2596                 if (!crtc->state->active)
2597                         continue;
2598
2599                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2600                         continue;
2601
2602                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2603
2604                 ret = intel_dp_sink_crc(intel_dp, crc);
2605                 if (ret)
2606                         goto out;
2607
2608                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2609                            crc[0], crc[1], crc[2],
2610                            crc[3], crc[4], crc[5]);
2611                 goto out;
2612         }
2613         ret = -ENODEV;
2614 out:
2615         drm_modeset_unlock_all(dev);
2616         return ret;
2617 }
2618
2619 static int i915_energy_uJ(struct seq_file *m, void *data)
2620 {
2621         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2622         u64 power;
2623         u32 units;
2624
2625         if (INTEL_GEN(dev_priv) < 6)
2626                 return -ENODEV;
2627
2628         intel_runtime_pm_get(dev_priv);
2629
2630         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2631         power = (power & 0x1f00) >> 8;
2632         units = 1000000 / (1 << power); /* convert to uJ */
2633         power = I915_READ(MCH_SECP_NRG_STTS);
2634         power *= units;
2635
2636         intel_runtime_pm_put(dev_priv);
2637
2638         seq_printf(m, "%llu", (long long unsigned)power);
2639
2640         return 0;
2641 }
2642
2643 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2644 {
2645         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2646         struct pci_dev *pdev = dev_priv->drm.pdev;
2647
2648         if (!HAS_RUNTIME_PM(dev_priv))
2649                 seq_puts(m, "Runtime power management not supported\n");
2650
2651         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2652         seq_printf(m, "IRQs disabled: %s\n",
2653                    yesno(!intel_irqs_enabled(dev_priv)));
2654 #ifdef CONFIG_PM
2655         seq_printf(m, "Usage count: %d\n",
2656                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2657 #else
2658         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2659 #endif
2660         seq_printf(m, "PCI device power state: %s [%d]\n",
2661                    pci_power_name(pdev->current_state),
2662                    pdev->current_state);
2663
2664         return 0;
2665 }
2666
2667 static int i915_power_domain_info(struct seq_file *m, void *unused)
2668 {
2669         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2670         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2671         int i;
2672
2673         mutex_lock(&power_domains->lock);
2674
2675         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2676         for (i = 0; i < power_domains->power_well_count; i++) {
2677                 struct i915_power_well *power_well;
2678                 enum intel_display_power_domain power_domain;
2679
2680                 power_well = &power_domains->power_wells[i];
2681                 seq_printf(m, "%-25s %d\n", power_well->name,
2682                            power_well->count);
2683
2684                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2685                      power_domain++) {
2686                         if (!(BIT(power_domain) & power_well->domains))
2687                                 continue;
2688
2689                         seq_printf(m, "  %-23s %d\n",
2690                                  intel_display_power_domain_str(power_domain),
2691                                  power_domains->domain_use_count[power_domain]);
2692                 }
2693         }
2694
2695         mutex_unlock(&power_domains->lock);
2696
2697         return 0;
2698 }
2699
2700 static int i915_dmc_info(struct seq_file *m, void *unused)
2701 {
2702         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2703         struct intel_csr *csr;
2704
2705         if (!HAS_CSR(dev_priv)) {
2706                 seq_puts(m, "not supported\n");
2707                 return 0;
2708         }
2709
2710         csr = &dev_priv->csr;
2711
2712         intel_runtime_pm_get(dev_priv);
2713
2714         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2715         seq_printf(m, "path: %s\n", csr->fw_path);
2716
2717         if (!csr->dmc_payload)
2718                 goto out;
2719
2720         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2721                    CSR_VERSION_MINOR(csr->version));
2722
2723         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2724                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2725                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2726                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2727                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2728         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2729                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2730                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2731         }
2732
2733 out:
2734         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2735         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2736         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2737
2738         intel_runtime_pm_put(dev_priv);
2739
2740         return 0;
2741 }
2742
2743 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2744                                  struct drm_display_mode *mode)
2745 {
2746         int i;
2747
2748         for (i = 0; i < tabs; i++)
2749                 seq_putc(m, '\t');
2750
2751         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2752                    mode->base.id, mode->name,
2753                    mode->vrefresh, mode->clock,
2754                    mode->hdisplay, mode->hsync_start,
2755                    mode->hsync_end, mode->htotal,
2756                    mode->vdisplay, mode->vsync_start,
2757                    mode->vsync_end, mode->vtotal,
2758                    mode->type, mode->flags);
2759 }
2760
2761 static void intel_encoder_info(struct seq_file *m,
2762                                struct intel_crtc *intel_crtc,
2763                                struct intel_encoder *intel_encoder)
2764 {
2765         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2766         struct drm_device *dev = &dev_priv->drm;
2767         struct drm_crtc *crtc = &intel_crtc->base;
2768         struct intel_connector *intel_connector;
2769         struct drm_encoder *encoder;
2770
2771         encoder = &intel_encoder->base;
2772         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2773                    encoder->base.id, encoder->name);
2774         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2775                 struct drm_connector *connector = &intel_connector->base;
2776                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2777                            connector->base.id,
2778                            connector->name,
2779                            drm_get_connector_status_name(connector->status));
2780                 if (connector->status == connector_status_connected) {
2781                         struct drm_display_mode *mode = &crtc->mode;
2782                         seq_printf(m, ", mode:\n");
2783                         intel_seq_print_mode(m, 2, mode);
2784                 } else {
2785                         seq_putc(m, '\n');
2786                 }
2787         }
2788 }
2789
2790 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2791 {
2792         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2793         struct drm_device *dev = &dev_priv->drm;
2794         struct drm_crtc *crtc = &intel_crtc->base;
2795         struct intel_encoder *intel_encoder;
2796         struct drm_plane_state *plane_state = crtc->primary->state;
2797         struct drm_framebuffer *fb = plane_state->fb;
2798
2799         if (fb)
2800                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2801                            fb->base.id, plane_state->src_x >> 16,
2802                            plane_state->src_y >> 16, fb->width, fb->height);
2803         else
2804                 seq_puts(m, "\tprimary plane disabled\n");
2805         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2806                 intel_encoder_info(m, intel_crtc, intel_encoder);
2807 }
2808
2809 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2810 {
2811         struct drm_display_mode *mode = panel->fixed_mode;
2812
2813         seq_printf(m, "\tfixed mode:\n");
2814         intel_seq_print_mode(m, 2, mode);
2815 }
2816
2817 static void intel_dp_info(struct seq_file *m,
2818                           struct intel_connector *intel_connector)
2819 {
2820         struct intel_encoder *intel_encoder = intel_connector->encoder;
2821         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2822
2823         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2824         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2825         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2826                 intel_panel_info(m, &intel_connector->panel);
2827
2828         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2829                                 &intel_dp->aux);
2830 }
2831
2832 static void intel_hdmi_info(struct seq_file *m,
2833                             struct intel_connector *intel_connector)
2834 {
2835         struct intel_encoder *intel_encoder = intel_connector->encoder;
2836         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2837
2838         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2839 }
2840
2841 static void intel_lvds_info(struct seq_file *m,
2842                             struct intel_connector *intel_connector)
2843 {
2844         intel_panel_info(m, &intel_connector->panel);
2845 }
2846
2847 static void intel_connector_info(struct seq_file *m,
2848                                  struct drm_connector *connector)
2849 {
2850         struct intel_connector *intel_connector = to_intel_connector(connector);
2851         struct intel_encoder *intel_encoder = intel_connector->encoder;
2852         struct drm_display_mode *mode;
2853
2854         seq_printf(m, "connector %d: type %s, status: %s\n",
2855                    connector->base.id, connector->name,
2856                    drm_get_connector_status_name(connector->status));
2857         if (connector->status == connector_status_connected) {
2858                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2859                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2860                            connector->display_info.width_mm,
2861                            connector->display_info.height_mm);
2862                 seq_printf(m, "\tsubpixel order: %s\n",
2863                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2864                 seq_printf(m, "\tCEA rev: %d\n",
2865                            connector->display_info.cea_rev);
2866         }
2867
2868         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2869                 return;
2870
2871         switch (connector->connector_type) {
2872         case DRM_MODE_CONNECTOR_DisplayPort:
2873         case DRM_MODE_CONNECTOR_eDP:
2874                 intel_dp_info(m, intel_connector);
2875                 break;
2876         case DRM_MODE_CONNECTOR_LVDS:
2877                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2878                         intel_lvds_info(m, intel_connector);
2879                 break;
2880         case DRM_MODE_CONNECTOR_HDMIA:
2881                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2882                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2883                         intel_hdmi_info(m, intel_connector);
2884                 break;
2885         default:
2886                 break;
2887         }
2888
2889         seq_printf(m, "\tmodes:\n");
2890         list_for_each_entry(mode, &connector->modes, head)
2891                 intel_seq_print_mode(m, 2, mode);
2892 }
2893
2894 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2895 {
2896         u32 state;
2897
2898         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2899                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2900         else
2901                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2902
2903         return state;
2904 }
2905
2906 static bool cursor_position(struct drm_i915_private *dev_priv,
2907                             int pipe, int *x, int *y)
2908 {
2909         u32 pos;
2910
2911         pos = I915_READ(CURPOS(pipe));
2912
2913         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2914         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2915                 *x = -*x;
2916
2917         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2918         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2919                 *y = -*y;
2920
2921         return cursor_active(dev_priv, pipe);
2922 }
2923
2924 static const char *plane_type(enum drm_plane_type type)
2925 {
2926         switch (type) {
2927         case DRM_PLANE_TYPE_OVERLAY:
2928                 return "OVL";
2929         case DRM_PLANE_TYPE_PRIMARY:
2930                 return "PRI";
2931         case DRM_PLANE_TYPE_CURSOR:
2932                 return "CUR";
2933         /*
2934          * Deliberately omitting default: to generate compiler warnings
2935          * when a new drm_plane_type gets added.
2936          */
2937         }
2938
2939         return "unknown";
2940 }
2941
2942 static const char *plane_rotation(unsigned int rotation)
2943 {
2944         static char buf[48];
2945         /*
2946          * According to doc only one DRM_ROTATE_ is allowed but this
2947          * will print them all to visualize if the values are misused
2948          */
2949         snprintf(buf, sizeof(buf),
2950                  "%s%s%s%s%s%s(0x%08x)",
2951                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2952                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2953                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2954                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2955                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2956                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2957                  rotation);
2958
2959         return buf;
2960 }
2961
2962 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2963 {
2964         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2965         struct drm_device *dev = &dev_priv->drm;
2966         struct intel_plane *intel_plane;
2967
2968         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2969                 struct drm_plane_state *state;
2970                 struct drm_plane *plane = &intel_plane->base;
2971
2972                 if (!plane->state) {
2973                         seq_puts(m, "plane->state is NULL!\n");
2974                         continue;
2975                 }
2976
2977                 state = plane->state;
2978
2979                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2980                            plane->base.id,
2981                            plane_type(intel_plane->base.type),
2982                            state->crtc_x, state->crtc_y,
2983                            state->crtc_w, state->crtc_h,
2984                            (state->src_x >> 16),
2985                            ((state->src_x & 0xffff) * 15625) >> 10,
2986                            (state->src_y >> 16),
2987                            ((state->src_y & 0xffff) * 15625) >> 10,
2988                            (state->src_w >> 16),
2989                            ((state->src_w & 0xffff) * 15625) >> 10,
2990                            (state->src_h >> 16),
2991                            ((state->src_h & 0xffff) * 15625) >> 10,
2992                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
2993                            plane_rotation(state->rotation));
2994         }
2995 }
2996
2997 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2998 {
2999         struct intel_crtc_state *pipe_config;
3000         int num_scalers = intel_crtc->num_scalers;
3001         int i;
3002
3003         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3004
3005         /* Not all platformas have a scaler */
3006         if (num_scalers) {
3007                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3008                            num_scalers,
3009                            pipe_config->scaler_state.scaler_users,
3010                            pipe_config->scaler_state.scaler_id);
3011
3012                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3013                         struct intel_scaler *sc =
3014                                         &pipe_config->scaler_state.scalers[i];
3015
3016                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3017                                    i, yesno(sc->in_use), sc->mode);
3018                 }
3019                 seq_puts(m, "\n");
3020         } else {
3021                 seq_puts(m, "\tNo scalers available on this platform\n");
3022         }
3023 }
3024
3025 static int i915_display_info(struct seq_file *m, void *unused)
3026 {
3027         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3028         struct drm_device *dev = &dev_priv->drm;
3029         struct intel_crtc *crtc;
3030         struct drm_connector *connector;
3031
3032         intel_runtime_pm_get(dev_priv);
3033         drm_modeset_lock_all(dev);
3034         seq_printf(m, "CRTC info\n");
3035         seq_printf(m, "---------\n");
3036         for_each_intel_crtc(dev, crtc) {
3037                 bool active;
3038                 struct intel_crtc_state *pipe_config;
3039                 int x, y;
3040
3041                 pipe_config = to_intel_crtc_state(crtc->base.state);
3042
3043                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3044                            crtc->base.base.id, pipe_name(crtc->pipe),
3045                            yesno(pipe_config->base.active),
3046                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3047                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3048
3049                 if (pipe_config->base.active) {
3050                         intel_crtc_info(m, crtc);
3051
3052                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3053                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3054                                    yesno(crtc->cursor_base),
3055                                    x, y, crtc->base.cursor->state->crtc_w,
3056                                    crtc->base.cursor->state->crtc_h,
3057                                    crtc->cursor_addr, yesno(active));
3058                         intel_scaler_info(m, crtc);
3059                         intel_plane_info(m, crtc);
3060                 }
3061
3062                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3063                            yesno(!crtc->cpu_fifo_underrun_disabled),
3064                            yesno(!crtc->pch_fifo_underrun_disabled));
3065         }
3066
3067         seq_printf(m, "\n");
3068         seq_printf(m, "Connector info\n");
3069         seq_printf(m, "--------------\n");
3070         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3071                 intel_connector_info(m, connector);
3072         }
3073         drm_modeset_unlock_all(dev);
3074         intel_runtime_pm_put(dev_priv);
3075
3076         return 0;
3077 }
3078
3079 static int i915_engine_info(struct seq_file *m, void *unused)
3080 {
3081         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3082         struct intel_engine_cs *engine;
3083
3084         for_each_engine(engine, dev_priv) {
3085                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3086                 struct drm_i915_gem_request *rq;
3087                 struct rb_node *rb;
3088                 u64 addr;
3089
3090                 seq_printf(m, "%s\n", engine->name);
3091                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3092                            intel_engine_get_seqno(engine),
3093                            engine->last_submitted_seqno,
3094                            engine->hangcheck.seqno,
3095                            engine->hangcheck.score);
3096
3097                 rcu_read_lock();
3098
3099                 seq_printf(m, "\tRequests:\n");
3100
3101                 rq = list_first_entry(&engine->request_list,
3102                                 struct drm_i915_gem_request, link);
3103                 if (&rq->link != &engine->request_list)
3104                         print_request(m, rq, "\t\tfirst  ");
3105
3106                 rq = list_last_entry(&engine->request_list,
3107                                 struct drm_i915_gem_request, link);
3108                 if (&rq->link != &engine->request_list)
3109                         print_request(m, rq, "\t\tlast   ");
3110
3111                 rq = i915_gem_find_active_request(engine);
3112                 if (rq) {
3113                         print_request(m, rq, "\t\tactive ");
3114                         seq_printf(m,
3115                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3116                                    rq->head, rq->postfix, rq->tail,
3117                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3118                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3119                 }
3120
3121                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3122                            I915_READ(RING_START(engine->mmio_base)),
3123                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3124                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3125                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3126                            rq ? rq->ring->head : 0);
3127                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3128                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3129                            rq ? rq->ring->tail : 0);
3130                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3131                            I915_READ(RING_CTL(engine->mmio_base)),
3132                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3133
3134                 rcu_read_unlock();
3135
3136                 addr = intel_engine_get_active_head(engine);
3137                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3138                            upper_32_bits(addr), lower_32_bits(addr));
3139                 addr = intel_engine_get_last_batch_head(engine);
3140                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3141                            upper_32_bits(addr), lower_32_bits(addr));
3142
3143                 if (i915.enable_execlists) {
3144                         u32 ptr, read, write;
3145
3146                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3147                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3148                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3149
3150                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3151                         read = GEN8_CSB_READ_PTR(ptr);
3152                         write = GEN8_CSB_WRITE_PTR(ptr);
3153                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3154                                    read, write);
3155                         if (read >= GEN8_CSB_ENTRIES)
3156                                 read = 0;
3157                         if (write >= GEN8_CSB_ENTRIES)
3158                                 write = 0;
3159                         if (read > write)
3160                                 write += GEN8_CSB_ENTRIES;
3161                         while (read < write) {
3162                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3163
3164                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3165                                            idx,
3166                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3167                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3168                         }
3169
3170                         rcu_read_lock();
3171                         rq = READ_ONCE(engine->execlist_port[0].request);
3172                         if (rq)
3173                                 print_request(m, rq, "\t\tELSP[0] ");
3174                         else
3175                                 seq_printf(m, "\t\tELSP[0] idle\n");
3176                         rq = READ_ONCE(engine->execlist_port[1].request);
3177                         if (rq)
3178                                 print_request(m, rq, "\t\tELSP[1] ");
3179                         else
3180                                 seq_printf(m, "\t\tELSP[1] idle\n");
3181                         rcu_read_unlock();
3182                 } else if (INTEL_GEN(dev_priv) > 6) {
3183                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3184                                    I915_READ(RING_PP_DIR_BASE(engine)));
3185                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3186                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3187                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3188                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3189                 }
3190
3191                 spin_lock(&b->lock);
3192                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3193                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3194
3195                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3196                                    w->tsk->comm, w->tsk->pid, w->seqno);
3197                 }
3198                 spin_unlock(&b->lock);
3199
3200                 seq_puts(m, "\n");
3201         }
3202
3203         return 0;
3204 }
3205
3206 static int i915_semaphore_status(struct seq_file *m, void *unused)
3207 {
3208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3209         struct drm_device *dev = &dev_priv->drm;
3210         struct intel_engine_cs *engine;
3211         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3212         enum intel_engine_id id;
3213         int j, ret;
3214
3215         if (!i915.semaphores) {
3216                 seq_puts(m, "Semaphores are disabled\n");
3217                 return 0;
3218         }
3219
3220         ret = mutex_lock_interruptible(&dev->struct_mutex);
3221         if (ret)
3222                 return ret;
3223         intel_runtime_pm_get(dev_priv);
3224
3225         if (IS_BROADWELL(dev_priv)) {
3226                 struct page *page;
3227                 uint64_t *seqno;
3228
3229                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3230
3231                 seqno = (uint64_t *)kmap_atomic(page);
3232                 for_each_engine_id(engine, dev_priv, id) {
3233                         uint64_t offset;
3234
3235                         seq_printf(m, "%s\n", engine->name);
3236
3237                         seq_puts(m, "  Last signal:");
3238                         for (j = 0; j < num_rings; j++) {
3239                                 offset = id * I915_NUM_ENGINES + j;
3240                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3241                                            seqno[offset], offset * 8);
3242                         }
3243                         seq_putc(m, '\n');
3244
3245                         seq_puts(m, "  Last wait:  ");
3246                         for (j = 0; j < num_rings; j++) {
3247                                 offset = id + (j * I915_NUM_ENGINES);
3248                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3249                                            seqno[offset], offset * 8);
3250                         }
3251                         seq_putc(m, '\n');
3252
3253                 }
3254                 kunmap_atomic(seqno);
3255         } else {
3256                 seq_puts(m, "  Last signal:");
3257                 for_each_engine(engine, dev_priv)
3258                         for (j = 0; j < num_rings; j++)
3259                                 seq_printf(m, "0x%08x\n",
3260                                            I915_READ(engine->semaphore.mbox.signal[j]));
3261                 seq_putc(m, '\n');
3262         }
3263
3264         seq_puts(m, "\nSync seqno:\n");
3265         for_each_engine(engine, dev_priv) {
3266                 for (j = 0; j < num_rings; j++)
3267                         seq_printf(m, "  0x%08x ",
3268                                    engine->semaphore.sync_seqno[j]);
3269                 seq_putc(m, '\n');
3270         }
3271         seq_putc(m, '\n');
3272
3273         intel_runtime_pm_put(dev_priv);
3274         mutex_unlock(&dev->struct_mutex);
3275         return 0;
3276 }
3277
3278 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3279 {
3280         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3281         struct drm_device *dev = &dev_priv->drm;
3282         int i;
3283
3284         drm_modeset_lock_all(dev);
3285         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3286                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3287
3288                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3289                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3290                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3291                 seq_printf(m, " tracked hardware state:\n");
3292                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3293                 seq_printf(m, " dpll_md: 0x%08x\n",
3294                            pll->config.hw_state.dpll_md);
3295                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3296                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3297                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3298         }
3299         drm_modeset_unlock_all(dev);
3300
3301         return 0;
3302 }
3303
3304 static int i915_wa_registers(struct seq_file *m, void *unused)
3305 {
3306         int i;
3307         int ret;
3308         struct intel_engine_cs *engine;
3309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3310         struct drm_device *dev = &dev_priv->drm;
3311         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3312         enum intel_engine_id id;
3313
3314         ret = mutex_lock_interruptible(&dev->struct_mutex);
3315         if (ret)
3316                 return ret;
3317
3318         intel_runtime_pm_get(dev_priv);
3319
3320         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3321         for_each_engine_id(engine, dev_priv, id)
3322                 seq_printf(m, "HW whitelist count for %s: %d\n",
3323                            engine->name, workarounds->hw_whitelist_count[id]);
3324         for (i = 0; i < workarounds->count; ++i) {
3325                 i915_reg_t addr;
3326                 u32 mask, value, read;
3327                 bool ok;
3328
3329                 addr = workarounds->reg[i].addr;
3330                 mask = workarounds->reg[i].mask;
3331                 value = workarounds->reg[i].value;
3332                 read = I915_READ(addr);
3333                 ok = (value & mask) == (read & mask);
3334                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3335                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3336         }
3337
3338         intel_runtime_pm_put(dev_priv);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         return 0;
3342 }
3343
3344 static int i915_ddb_info(struct seq_file *m, void *unused)
3345 {
3346         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3347         struct drm_device *dev = &dev_priv->drm;
3348         struct skl_ddb_allocation *ddb;
3349         struct skl_ddb_entry *entry;
3350         enum pipe pipe;
3351         int plane;
3352
3353         if (INTEL_GEN(dev_priv) < 9)
3354                 return 0;
3355
3356         drm_modeset_lock_all(dev);
3357
3358         ddb = &dev_priv->wm.skl_hw.ddb;
3359
3360         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3361
3362         for_each_pipe(dev_priv, pipe) {
3363                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3364
3365                 for_each_plane(dev_priv, pipe, plane) {
3366                         entry = &ddb->plane[pipe][plane];
3367                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3368                                    entry->start, entry->end,
3369                                    skl_ddb_entry_size(entry));
3370                 }
3371
3372                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3373                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3374                            entry->end, skl_ddb_entry_size(entry));
3375         }
3376
3377         drm_modeset_unlock_all(dev);
3378
3379         return 0;
3380 }
3381
3382 static void drrs_status_per_crtc(struct seq_file *m,
3383                                  struct drm_device *dev,
3384                                  struct intel_crtc *intel_crtc)
3385 {
3386         struct drm_i915_private *dev_priv = to_i915(dev);
3387         struct i915_drrs *drrs = &dev_priv->drrs;
3388         int vrefresh = 0;
3389         struct drm_connector *connector;
3390
3391         drm_for_each_connector(connector, dev) {
3392                 if (connector->state->crtc != &intel_crtc->base)
3393                         continue;
3394
3395                 seq_printf(m, "%s:\n", connector->name);
3396         }
3397
3398         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3399                 seq_puts(m, "\tVBT: DRRS_type: Static");
3400         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3401                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3402         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3403                 seq_puts(m, "\tVBT: DRRS_type: None");
3404         else
3405                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3406
3407         seq_puts(m, "\n\n");
3408
3409         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3410                 struct intel_panel *panel;
3411
3412                 mutex_lock(&drrs->mutex);
3413                 /* DRRS Supported */
3414                 seq_puts(m, "\tDRRS Supported: Yes\n");
3415
3416                 /* disable_drrs() will make drrs->dp NULL */
3417                 if (!drrs->dp) {
3418                         seq_puts(m, "Idleness DRRS: Disabled");
3419                         mutex_unlock(&drrs->mutex);
3420                         return;
3421                 }
3422
3423                 panel = &drrs->dp->attached_connector->panel;
3424                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3425                                         drrs->busy_frontbuffer_bits);
3426
3427                 seq_puts(m, "\n\t\t");
3428                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3429                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3430                         vrefresh = panel->fixed_mode->vrefresh;
3431                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3432                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3433                         vrefresh = panel->downclock_mode->vrefresh;
3434                 } else {
3435                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3436                                                 drrs->refresh_rate_type);
3437                         mutex_unlock(&drrs->mutex);
3438                         return;
3439                 }
3440                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3441
3442                 seq_puts(m, "\n\t\t");
3443                 mutex_unlock(&drrs->mutex);
3444         } else {
3445                 /* DRRS not supported. Print the VBT parameter*/
3446                 seq_puts(m, "\tDRRS Supported : No");
3447         }
3448         seq_puts(m, "\n");
3449 }
3450
3451 static int i915_drrs_status(struct seq_file *m, void *unused)
3452 {
3453         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3454         struct drm_device *dev = &dev_priv->drm;
3455         struct intel_crtc *intel_crtc;
3456         int active_crtc_cnt = 0;
3457
3458         drm_modeset_lock_all(dev);
3459         for_each_intel_crtc(dev, intel_crtc) {
3460                 if (intel_crtc->base.state->active) {
3461                         active_crtc_cnt++;
3462                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3463
3464                         drrs_status_per_crtc(m, dev, intel_crtc);
3465                 }
3466         }
3467         drm_modeset_unlock_all(dev);
3468
3469         if (!active_crtc_cnt)
3470                 seq_puts(m, "No active crtc found\n");
3471
3472         return 0;
3473 }
3474
3475 struct pipe_crc_info {
3476         const char *name;
3477         struct drm_i915_private *dev_priv;
3478         enum pipe pipe;
3479 };
3480
3481 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3482 {
3483         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3484         struct drm_device *dev = &dev_priv->drm;
3485         struct intel_encoder *intel_encoder;
3486         struct intel_digital_port *intel_dig_port;
3487         struct drm_connector *connector;
3488
3489         drm_modeset_lock_all(dev);
3490         drm_for_each_connector(connector, dev) {
3491                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3492                         continue;
3493
3494                 intel_encoder = intel_attached_encoder(connector);
3495                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3496                         continue;
3497
3498                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3499                 if (!intel_dig_port->dp.can_mst)
3500                         continue;
3501
3502                 seq_printf(m, "MST Source Port %c\n",
3503                            port_name(intel_dig_port->port));
3504                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3505         }
3506         drm_modeset_unlock_all(dev);
3507         return 0;
3508 }
3509
3510 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3511 {
3512         struct pipe_crc_info *info = inode->i_private;
3513         struct drm_i915_private *dev_priv = info->dev_priv;
3514         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3515
3516         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3517                 return -ENODEV;
3518
3519         spin_lock_irq(&pipe_crc->lock);
3520
3521         if (pipe_crc->opened) {
3522                 spin_unlock_irq(&pipe_crc->lock);
3523                 return -EBUSY; /* already open */
3524         }
3525
3526         pipe_crc->opened = true;
3527         filep->private_data = inode->i_private;
3528
3529         spin_unlock_irq(&pipe_crc->lock);
3530
3531         return 0;
3532 }
3533
3534 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3535 {
3536         struct pipe_crc_info *info = inode->i_private;
3537         struct drm_i915_private *dev_priv = info->dev_priv;
3538         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3539
3540         spin_lock_irq(&pipe_crc->lock);
3541         pipe_crc->opened = false;
3542         spin_unlock_irq(&pipe_crc->lock);
3543
3544         return 0;
3545 }
3546
3547 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3548 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3549 /* account for \'0' */
3550 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3551
3552 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3553 {
3554         assert_spin_locked(&pipe_crc->lock);
3555         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3556                         INTEL_PIPE_CRC_ENTRIES_NR);
3557 }
3558
3559 static ssize_t
3560 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3561                    loff_t *pos)
3562 {
3563         struct pipe_crc_info *info = filep->private_data;
3564         struct drm_i915_private *dev_priv = info->dev_priv;
3565         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3566         char buf[PIPE_CRC_BUFFER_LEN];
3567         int n_entries;
3568         ssize_t bytes_read;
3569
3570         /*
3571          * Don't allow user space to provide buffers not big enough to hold
3572          * a line of data.
3573          */
3574         if (count < PIPE_CRC_LINE_LEN)
3575                 return -EINVAL;
3576
3577         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3578                 return 0;
3579
3580         /* nothing to read */
3581         spin_lock_irq(&pipe_crc->lock);
3582         while (pipe_crc_data_count(pipe_crc) == 0) {
3583                 int ret;
3584
3585                 if (filep->f_flags & O_NONBLOCK) {
3586                         spin_unlock_irq(&pipe_crc->lock);
3587                         return -EAGAIN;
3588                 }
3589
3590                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3591                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3592                 if (ret) {
3593                         spin_unlock_irq(&pipe_crc->lock);
3594                         return ret;
3595                 }
3596         }
3597
3598         /* We now have one or more entries to read */
3599         n_entries = count / PIPE_CRC_LINE_LEN;
3600
3601         bytes_read = 0;
3602         while (n_entries > 0) {
3603                 struct intel_pipe_crc_entry *entry =
3604                         &pipe_crc->entries[pipe_crc->tail];
3605
3606                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3607                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3608                         break;
3609
3610                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3611                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3612
3613                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3614                                        "%8u %8x %8x %8x %8x %8x\n",
3615                                        entry->frame, entry->crc[0],
3616                                        entry->crc[1], entry->crc[2],
3617                                        entry->crc[3], entry->crc[4]);
3618
3619                 spin_unlock_irq(&pipe_crc->lock);
3620
3621                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3622                         return -EFAULT;
3623
3624                 user_buf += PIPE_CRC_LINE_LEN;
3625                 n_entries--;
3626
3627                 spin_lock_irq(&pipe_crc->lock);
3628         }
3629
3630         spin_unlock_irq(&pipe_crc->lock);
3631
3632         return bytes_read;
3633 }
3634
3635 static const struct file_operations i915_pipe_crc_fops = {
3636         .owner = THIS_MODULE,
3637         .open = i915_pipe_crc_open,
3638         .read = i915_pipe_crc_read,
3639         .release = i915_pipe_crc_release,
3640 };
3641
3642 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3643         {
3644                 .name = "i915_pipe_A_crc",
3645                 .pipe = PIPE_A,
3646         },
3647         {
3648                 .name = "i915_pipe_B_crc",
3649                 .pipe = PIPE_B,
3650         },
3651         {
3652                 .name = "i915_pipe_C_crc",
3653                 .pipe = PIPE_C,
3654         },
3655 };
3656
3657 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3658                                 enum pipe pipe)
3659 {
3660         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3661         struct dentry *ent;
3662         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3663
3664         info->dev_priv = dev_priv;
3665         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3666                                   &i915_pipe_crc_fops);
3667         if (!ent)
3668                 return -ENOMEM;
3669
3670         return drm_add_fake_info_node(minor, ent, info);
3671 }
3672
3673 static const char * const pipe_crc_sources[] = {
3674         "none",
3675         "plane1",
3676         "plane2",
3677         "pf",
3678         "pipe",
3679         "TV",
3680         "DP-B",
3681         "DP-C",
3682         "DP-D",
3683         "auto",
3684 };
3685
3686 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3687 {
3688         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3689         return pipe_crc_sources[source];
3690 }
3691
3692 static int display_crc_ctl_show(struct seq_file *m, void *data)
3693 {
3694         struct drm_i915_private *dev_priv = m->private;
3695         int i;
3696
3697         for (i = 0; i < I915_MAX_PIPES; i++)
3698                 seq_printf(m, "%c %s\n", pipe_name(i),
3699                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3700
3701         return 0;
3702 }
3703
3704 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3705 {
3706         return single_open(file, display_crc_ctl_show, inode->i_private);
3707 }
3708
3709 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3710                                  uint32_t *val)
3711 {
3712         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3713                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3714
3715         switch (*source) {
3716         case INTEL_PIPE_CRC_SOURCE_PIPE:
3717                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3718                 break;
3719         case INTEL_PIPE_CRC_SOURCE_NONE:
3720                 *val = 0;
3721                 break;
3722         default:
3723                 return -EINVAL;
3724         }
3725
3726         return 0;
3727 }
3728
3729 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3730                                      enum pipe pipe,
3731                                      enum intel_pipe_crc_source *source)
3732 {
3733         struct drm_device *dev = &dev_priv->drm;
3734         struct intel_encoder *encoder;
3735         struct intel_crtc *crtc;
3736         struct intel_digital_port *dig_port;
3737         int ret = 0;
3738
3739         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3740
3741         drm_modeset_lock_all(dev);
3742         for_each_intel_encoder(dev, encoder) {
3743                 if (!encoder->base.crtc)
3744                         continue;
3745
3746                 crtc = to_intel_crtc(encoder->base.crtc);
3747
3748                 if (crtc->pipe != pipe)
3749                         continue;
3750
3751                 switch (encoder->type) {
3752                 case INTEL_OUTPUT_TVOUT:
3753                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3754                         break;
3755                 case INTEL_OUTPUT_DP:
3756                 case INTEL_OUTPUT_EDP:
3757                         dig_port = enc_to_dig_port(&encoder->base);
3758                         switch (dig_port->port) {
3759                         case PORT_B:
3760                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3761                                 break;
3762                         case PORT_C:
3763                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3764                                 break;
3765                         case PORT_D:
3766                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3767                                 break;
3768                         default:
3769                                 WARN(1, "nonexisting DP port %c\n",
3770                                      port_name(dig_port->port));
3771                                 break;
3772                         }
3773                         break;
3774                 default:
3775                         break;
3776                 }
3777         }
3778         drm_modeset_unlock_all(dev);
3779
3780         return ret;
3781 }
3782
3783 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3784                                 enum pipe pipe,
3785                                 enum intel_pipe_crc_source *source,
3786                                 uint32_t *val)
3787 {
3788         bool need_stable_symbols = false;
3789
3790         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3791                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3792                 if (ret)
3793                         return ret;
3794         }
3795
3796         switch (*source) {
3797         case INTEL_PIPE_CRC_SOURCE_PIPE:
3798                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3799                 break;
3800         case INTEL_PIPE_CRC_SOURCE_DP_B:
3801                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3802                 need_stable_symbols = true;
3803                 break;
3804         case INTEL_PIPE_CRC_SOURCE_DP_C:
3805                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3806                 need_stable_symbols = true;
3807                 break;
3808         case INTEL_PIPE_CRC_SOURCE_DP_D:
3809                 if (!IS_CHERRYVIEW(dev_priv))
3810                         return -EINVAL;
3811                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3812                 need_stable_symbols = true;
3813                 break;
3814         case INTEL_PIPE_CRC_SOURCE_NONE:
3815                 *val = 0;
3816                 break;
3817         default:
3818                 return -EINVAL;
3819         }
3820
3821         /*
3822          * When the pipe CRC tap point is after the transcoders we need
3823          * to tweak symbol-level features to produce a deterministic series of
3824          * symbols for a given frame. We need to reset those features only once
3825          * a frame (instead of every nth symbol):
3826          *   - DC-balance: used to ensure a better clock recovery from the data
3827          *     link (SDVO)
3828          *   - DisplayPort scrambling: used for EMI reduction
3829          */
3830         if (need_stable_symbols) {
3831                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3832
3833                 tmp |= DC_BALANCE_RESET_VLV;
3834                 switch (pipe) {
3835                 case PIPE_A:
3836                         tmp |= PIPE_A_SCRAMBLE_RESET;
3837                         break;
3838                 case PIPE_B:
3839                         tmp |= PIPE_B_SCRAMBLE_RESET;
3840                         break;
3841                 case PIPE_C:
3842                         tmp |= PIPE_C_SCRAMBLE_RESET;
3843                         break;
3844                 default:
3845                         return -EINVAL;
3846                 }
3847                 I915_WRITE(PORT_DFT2_G4X, tmp);
3848         }
3849
3850         return 0;
3851 }
3852
3853 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3854                                  enum pipe pipe,
3855                                  enum intel_pipe_crc_source *source,
3856                                  uint32_t *val)
3857 {
3858         bool need_stable_symbols = false;
3859
3860         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3861                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3862                 if (ret)
3863                         return ret;
3864         }
3865
3866         switch (*source) {
3867         case INTEL_PIPE_CRC_SOURCE_PIPE:
3868                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3869                 break;
3870         case INTEL_PIPE_CRC_SOURCE_TV:
3871                 if (!SUPPORTS_TV(dev_priv))
3872                         return -EINVAL;
3873                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3874                 break;
3875         case INTEL_PIPE_CRC_SOURCE_DP_B:
3876                 if (!IS_G4X(dev_priv))
3877                         return -EINVAL;
3878                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3879                 need_stable_symbols = true;
3880                 break;
3881         case INTEL_PIPE_CRC_SOURCE_DP_C:
3882                 if (!IS_G4X(dev_priv))
3883                         return -EINVAL;
3884                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3885                 need_stable_symbols = true;
3886                 break;
3887         case INTEL_PIPE_CRC_SOURCE_DP_D:
3888                 if (!IS_G4X(dev_priv))
3889                         return -EINVAL;
3890                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3891                 need_stable_symbols = true;
3892                 break;
3893         case INTEL_PIPE_CRC_SOURCE_NONE:
3894                 *val = 0;
3895                 break;
3896         default:
3897                 return -EINVAL;
3898         }
3899
3900         /*
3901          * When the pipe CRC tap point is after the transcoders we need
3902          * to tweak symbol-level features to produce a deterministic series of
3903          * symbols for a given frame. We need to reset those features only once
3904          * a frame (instead of every nth symbol):
3905          *   - DC-balance: used to ensure a better clock recovery from the data
3906          *     link (SDVO)
3907          *   - DisplayPort scrambling: used for EMI reduction
3908          */
3909         if (need_stable_symbols) {
3910                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3911
3912                 WARN_ON(!IS_G4X(dev_priv));
3913
3914                 I915_WRITE(PORT_DFT_I9XX,
3915                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3916
3917                 if (pipe == PIPE_A)
3918                         tmp |= PIPE_A_SCRAMBLE_RESET;
3919                 else
3920                         tmp |= PIPE_B_SCRAMBLE_RESET;
3921
3922                 I915_WRITE(PORT_DFT2_G4X, tmp);
3923         }
3924
3925         return 0;
3926 }
3927
3928 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3929                                          enum pipe pipe)
3930 {
3931         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3932
3933         switch (pipe) {
3934         case PIPE_A:
3935                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3936                 break;
3937         case PIPE_B:
3938                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3939                 break;
3940         case PIPE_C:
3941                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3942                 break;
3943         default:
3944                 return;
3945         }
3946         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3947                 tmp &= ~DC_BALANCE_RESET_VLV;
3948         I915_WRITE(PORT_DFT2_G4X, tmp);
3949
3950 }
3951
3952 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3953                                          enum pipe pipe)
3954 {
3955         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3956
3957         if (pipe == PIPE_A)
3958                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3959         else
3960                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3961         I915_WRITE(PORT_DFT2_G4X, tmp);
3962
3963         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3964                 I915_WRITE(PORT_DFT_I9XX,
3965                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3966         }
3967 }
3968
3969 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3970                                 uint32_t *val)
3971 {
3972         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3973                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3974
3975         switch (*source) {
3976         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3977                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3978                 break;
3979         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3980                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3981                 break;
3982         case INTEL_PIPE_CRC_SOURCE_PIPE:
3983                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3984                 break;
3985         case INTEL_PIPE_CRC_SOURCE_NONE:
3986                 *val = 0;
3987                 break;
3988         default:
3989                 return -EINVAL;
3990         }
3991
3992         return 0;
3993 }
3994
3995 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
3996                                         bool enable)
3997 {
3998         struct drm_device *dev = &dev_priv->drm;
3999         struct intel_crtc *crtc =
4000                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4001         struct intel_crtc_state *pipe_config;
4002         struct drm_atomic_state *state;
4003         int ret = 0;
4004
4005         drm_modeset_lock_all(dev);
4006         state = drm_atomic_state_alloc(dev);
4007         if (!state) {
4008                 ret = -ENOMEM;
4009                 goto out;
4010         }
4011
4012         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4013         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4014         if (IS_ERR(pipe_config)) {
4015                 ret = PTR_ERR(pipe_config);
4016                 goto out;
4017         }
4018
4019         pipe_config->pch_pfit.force_thru = enable;
4020         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4021             pipe_config->pch_pfit.enabled != enable)
4022                 pipe_config->base.connectors_changed = true;
4023
4024         ret = drm_atomic_commit(state);
4025 out:
4026         drm_modeset_unlock_all(dev);
4027         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4028         if (ret)
4029                 drm_atomic_state_free(state);
4030 }
4031
4032 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4033                                 enum pipe pipe,
4034                                 enum intel_pipe_crc_source *source,
4035                                 uint32_t *val)
4036 {
4037         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4038                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4039
4040         switch (*source) {
4041         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4042                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4043                 break;
4044         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4045                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4046                 break;
4047         case INTEL_PIPE_CRC_SOURCE_PF:
4048                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4049                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4050
4051                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4052                 break;
4053         case INTEL_PIPE_CRC_SOURCE_NONE:
4054                 *val = 0;
4055                 break;
4056         default:
4057                 return -EINVAL;
4058         }
4059
4060         return 0;
4061 }
4062
4063 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4064                                enum pipe pipe,
4065                                enum intel_pipe_crc_source source)
4066 {
4067         struct drm_device *dev = &dev_priv->drm;
4068         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4069         struct intel_crtc *crtc =
4070                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4071         enum intel_display_power_domain power_domain;
4072         u32 val = 0; /* shut up gcc */
4073         int ret;
4074
4075         if (pipe_crc->source == source)
4076                 return 0;
4077
4078         /* forbid changing the source without going back to 'none' */
4079         if (pipe_crc->source && source)
4080                 return -EINVAL;
4081
4082         power_domain = POWER_DOMAIN_PIPE(pipe);
4083         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4084                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4085                 return -EIO;
4086         }
4087
4088         if (IS_GEN2(dev_priv))
4089                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4090         else if (INTEL_GEN(dev_priv) < 5)
4091                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4092         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4093                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4094         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4095                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4096         else
4097                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4098
4099         if (ret != 0)
4100                 goto out;
4101
4102         /* none -> real source transition */
4103         if (source) {
4104                 struct intel_pipe_crc_entry *entries;
4105
4106                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4107                                  pipe_name(pipe), pipe_crc_source_name(source));
4108
4109                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4110                                   sizeof(pipe_crc->entries[0]),
4111                                   GFP_KERNEL);
4112                 if (!entries) {
4113                         ret = -ENOMEM;
4114                         goto out;
4115                 }
4116
4117                 /*
4118                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4119                  * enabled and disabled dynamically based on package C states,
4120                  * user space can't make reliable use of the CRCs, so let's just
4121                  * completely disable it.
4122                  */
4123                 hsw_disable_ips(crtc);
4124
4125                 spin_lock_irq(&pipe_crc->lock);
4126                 kfree(pipe_crc->entries);
4127                 pipe_crc->entries = entries;
4128                 pipe_crc->head = 0;
4129                 pipe_crc->tail = 0;
4130                 spin_unlock_irq(&pipe_crc->lock);
4131         }
4132
4133         pipe_crc->source = source;
4134
4135         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4136         POSTING_READ(PIPE_CRC_CTL(pipe));
4137
4138         /* real source -> none transition */
4139         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4140                 struct intel_pipe_crc_entry *entries;
4141                 struct intel_crtc *crtc =
4142                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4143
4144                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4145                                  pipe_name(pipe));
4146
4147                 drm_modeset_lock(&crtc->base.mutex, NULL);
4148                 if (crtc->base.state->active)
4149                         intel_wait_for_vblank(dev, pipe);
4150                 drm_modeset_unlock(&crtc->base.mutex);
4151
4152                 spin_lock_irq(&pipe_crc->lock);
4153                 entries = pipe_crc->entries;
4154                 pipe_crc->entries = NULL;
4155                 pipe_crc->head = 0;
4156                 pipe_crc->tail = 0;
4157                 spin_unlock_irq(&pipe_crc->lock);
4158
4159                 kfree(entries);
4160
4161                 if (IS_G4X(dev_priv))
4162                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4163                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4164                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4165                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4166                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4167
4168                 hsw_enable_ips(crtc);
4169         }
4170
4171         ret = 0;
4172
4173 out:
4174         intel_display_power_put(dev_priv, power_domain);
4175
4176         return ret;
4177 }
4178
4179 /*
4180  * Parse pipe CRC command strings:
4181  *   command: wsp* object wsp+ name wsp+ source wsp*
4182  *   object: 'pipe'
4183  *   name: (A | B | C)
4184  *   source: (none | plane1 | plane2 | pf)
4185  *   wsp: (#0x20 | #0x9 | #0xA)+
4186  *
4187  * eg.:
4188  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4189  *  "pipe A none"    ->  Stop CRC
4190  */
4191 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4192 {
4193         int n_words = 0;
4194
4195         while (*buf) {
4196                 char *end;
4197
4198                 /* skip leading white space */
4199                 buf = skip_spaces(buf);
4200                 if (!*buf)
4201                         break;  /* end of buffer */
4202
4203                 /* find end of word */
4204                 for (end = buf; *end && !isspace(*end); end++)
4205                         ;
4206
4207                 if (n_words == max_words) {
4208                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4209                                          max_words);
4210                         return -EINVAL; /* ran out of words[] before bytes */
4211                 }
4212
4213                 if (*end)
4214                         *end++ = '\0';
4215                 words[n_words++] = buf;
4216                 buf = end;
4217         }
4218
4219         return n_words;
4220 }
4221
4222 enum intel_pipe_crc_object {
4223         PIPE_CRC_OBJECT_PIPE,
4224 };
4225
4226 static const char * const pipe_crc_objects[] = {
4227         "pipe",
4228 };
4229
4230 static int
4231 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4232 {
4233         int i;
4234
4235         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4236                 if (!strcmp(buf, pipe_crc_objects[i])) {
4237                         *o = i;
4238                         return 0;
4239                     }
4240
4241         return -EINVAL;
4242 }
4243
4244 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4245 {
4246         const char name = buf[0];
4247
4248         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4249                 return -EINVAL;
4250
4251         *pipe = name - 'A';
4252
4253         return 0;
4254 }
4255
4256 static int
4257 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4258 {
4259         int i;
4260
4261         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4262                 if (!strcmp(buf, pipe_crc_sources[i])) {
4263                         *s = i;
4264                         return 0;
4265                     }
4266
4267         return -EINVAL;
4268 }
4269
4270 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4271                                  char *buf, size_t len)
4272 {
4273 #define N_WORDS 3
4274         int n_words;
4275         char *words[N_WORDS];
4276         enum pipe pipe;
4277         enum intel_pipe_crc_object object;
4278         enum intel_pipe_crc_source source;
4279
4280         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4281         if (n_words != N_WORDS) {
4282                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4283                                  N_WORDS);
4284                 return -EINVAL;
4285         }
4286
4287         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4288                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4289                 return -EINVAL;
4290         }
4291
4292         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4293                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4294                 return -EINVAL;
4295         }
4296
4297         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4298                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4299                 return -EINVAL;
4300         }
4301
4302         return pipe_crc_set_source(dev_priv, pipe, source);
4303 }
4304
4305 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4306                                      size_t len, loff_t *offp)
4307 {
4308         struct seq_file *m = file->private_data;
4309         struct drm_i915_private *dev_priv = m->private;
4310         char *tmpbuf;
4311         int ret;
4312
4313         if (len == 0)
4314                 return 0;
4315
4316         if (len > PAGE_SIZE - 1) {
4317                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4318                                  PAGE_SIZE);
4319                 return -E2BIG;
4320         }
4321
4322         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4323         if (!tmpbuf)
4324                 return -ENOMEM;
4325
4326         if (copy_from_user(tmpbuf, ubuf, len)) {
4327                 ret = -EFAULT;
4328                 goto out;
4329         }
4330         tmpbuf[len] = '\0';
4331
4332         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4333
4334 out:
4335         kfree(tmpbuf);
4336         if (ret < 0)
4337                 return ret;
4338
4339         *offp += len;
4340         return len;
4341 }
4342
4343 static const struct file_operations i915_display_crc_ctl_fops = {
4344         .owner = THIS_MODULE,
4345         .open = display_crc_ctl_open,
4346         .read = seq_read,
4347         .llseek = seq_lseek,
4348         .release = single_release,
4349         .write = display_crc_ctl_write
4350 };
4351
4352 static ssize_t i915_displayport_test_active_write(struct file *file,
4353                                                   const char __user *ubuf,
4354                                                   size_t len, loff_t *offp)
4355 {
4356         char *input_buffer;
4357         int status = 0;
4358         struct drm_device *dev;
4359         struct drm_connector *connector;
4360         struct list_head *connector_list;
4361         struct intel_dp *intel_dp;
4362         int val = 0;
4363
4364         dev = ((struct seq_file *)file->private_data)->private;
4365
4366         connector_list = &dev->mode_config.connector_list;
4367
4368         if (len == 0)
4369                 return 0;
4370
4371         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4372         if (!input_buffer)
4373                 return -ENOMEM;
4374
4375         if (copy_from_user(input_buffer, ubuf, len)) {
4376                 status = -EFAULT;
4377                 goto out;
4378         }
4379
4380         input_buffer[len] = '\0';
4381         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4382
4383         list_for_each_entry(connector, connector_list, head) {
4384                 if (connector->connector_type !=
4385                     DRM_MODE_CONNECTOR_DisplayPort)
4386                         continue;
4387
4388                 if (connector->status == connector_status_connected &&
4389                     connector->encoder != NULL) {
4390                         intel_dp = enc_to_intel_dp(connector->encoder);
4391                         status = kstrtoint(input_buffer, 10, &val);
4392                         if (status < 0)
4393                                 goto out;
4394                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4395                         /* To prevent erroneous activation of the compliance
4396                          * testing code, only accept an actual value of 1 here
4397                          */
4398                         if (val == 1)
4399                                 intel_dp->compliance_test_active = 1;
4400                         else
4401                                 intel_dp->compliance_test_active = 0;
4402                 }
4403         }
4404 out:
4405         kfree(input_buffer);
4406         if (status < 0)
4407                 return status;
4408
4409         *offp += len;
4410         return len;
4411 }
4412
4413 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4414 {
4415         struct drm_device *dev = m->private;
4416         struct drm_connector *connector;
4417         struct list_head *connector_list = &dev->mode_config.connector_list;
4418         struct intel_dp *intel_dp;
4419
4420         list_for_each_entry(connector, connector_list, head) {
4421                 if (connector->connector_type !=
4422                     DRM_MODE_CONNECTOR_DisplayPort)
4423                         continue;
4424
4425                 if (connector->status == connector_status_connected &&
4426                     connector->encoder != NULL) {
4427                         intel_dp = enc_to_intel_dp(connector->encoder);
4428                         if (intel_dp->compliance_test_active)
4429                                 seq_puts(m, "1");
4430                         else
4431                                 seq_puts(m, "0");
4432                 } else
4433                         seq_puts(m, "0");
4434         }
4435
4436         return 0;
4437 }
4438
4439 static int i915_displayport_test_active_open(struct inode *inode,
4440                                              struct file *file)
4441 {
4442         struct drm_i915_private *dev_priv = inode->i_private;
4443
4444         return single_open(file, i915_displayport_test_active_show,
4445                            &dev_priv->drm);
4446 }
4447
4448 static const struct file_operations i915_displayport_test_active_fops = {
4449         .owner = THIS_MODULE,
4450         .open = i915_displayport_test_active_open,
4451         .read = seq_read,
4452         .llseek = seq_lseek,
4453         .release = single_release,
4454         .write = i915_displayport_test_active_write
4455 };
4456
4457 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4458 {
4459         struct drm_device *dev = m->private;
4460         struct drm_connector *connector;
4461         struct list_head *connector_list = &dev->mode_config.connector_list;
4462         struct intel_dp *intel_dp;
4463
4464         list_for_each_entry(connector, connector_list, head) {
4465                 if (connector->connector_type !=
4466                     DRM_MODE_CONNECTOR_DisplayPort)
4467                         continue;
4468
4469                 if (connector->status == connector_status_connected &&
4470                     connector->encoder != NULL) {
4471                         intel_dp = enc_to_intel_dp(connector->encoder);
4472                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4473                 } else
4474                         seq_puts(m, "0");
4475         }
4476
4477         return 0;
4478 }
4479 static int i915_displayport_test_data_open(struct inode *inode,
4480                                            struct file *file)
4481 {
4482         struct drm_i915_private *dev_priv = inode->i_private;
4483
4484         return single_open(file, i915_displayport_test_data_show,
4485                            &dev_priv->drm);
4486 }
4487
4488 static const struct file_operations i915_displayport_test_data_fops = {
4489         .owner = THIS_MODULE,
4490         .open = i915_displayport_test_data_open,
4491         .read = seq_read,
4492         .llseek = seq_lseek,
4493         .release = single_release
4494 };
4495
4496 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4497 {
4498         struct drm_device *dev = m->private;
4499         struct drm_connector *connector;
4500         struct list_head *connector_list = &dev->mode_config.connector_list;
4501         struct intel_dp *intel_dp;
4502
4503         list_for_each_entry(connector, connector_list, head) {
4504                 if (connector->connector_type !=
4505                     DRM_MODE_CONNECTOR_DisplayPort)
4506                         continue;
4507
4508                 if (connector->status == connector_status_connected &&
4509                     connector->encoder != NULL) {
4510                         intel_dp = enc_to_intel_dp(connector->encoder);
4511                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4512                 } else
4513                         seq_puts(m, "0");
4514         }
4515
4516         return 0;
4517 }
4518
4519 static int i915_displayport_test_type_open(struct inode *inode,
4520                                        struct file *file)
4521 {
4522         struct drm_i915_private *dev_priv = inode->i_private;
4523
4524         return single_open(file, i915_displayport_test_type_show,
4525                            &dev_priv->drm);
4526 }
4527
4528 static const struct file_operations i915_displayport_test_type_fops = {
4529         .owner = THIS_MODULE,
4530         .open = i915_displayport_test_type_open,
4531         .read = seq_read,
4532         .llseek = seq_lseek,
4533         .release = single_release
4534 };
4535
4536 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4537 {
4538         struct drm_i915_private *dev_priv = m->private;
4539         struct drm_device *dev = &dev_priv->drm;
4540         int level;
4541         int num_levels;
4542
4543         if (IS_CHERRYVIEW(dev_priv))
4544                 num_levels = 3;
4545         else if (IS_VALLEYVIEW(dev_priv))
4546                 num_levels = 1;
4547         else
4548                 num_levels = ilk_wm_max_level(dev) + 1;
4549
4550         drm_modeset_lock_all(dev);
4551
4552         for (level = 0; level < num_levels; level++) {
4553                 unsigned int latency = wm[level];
4554
4555                 /*
4556                  * - WM1+ latency values in 0.5us units
4557                  * - latencies are in us on gen9/vlv/chv
4558                  */
4559                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4560                     IS_CHERRYVIEW(dev_priv))
4561                         latency *= 10;
4562                 else if (level > 0)
4563                         latency *= 5;
4564
4565                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4566                            level, wm[level], latency / 10, latency % 10);
4567         }
4568
4569         drm_modeset_unlock_all(dev);
4570 }
4571
4572 static int pri_wm_latency_show(struct seq_file *m, void *data)
4573 {
4574         struct drm_i915_private *dev_priv = m->private;
4575         const uint16_t *latencies;
4576
4577         if (INTEL_GEN(dev_priv) >= 9)
4578                 latencies = dev_priv->wm.skl_latency;
4579         else
4580                 latencies = dev_priv->wm.pri_latency;
4581
4582         wm_latency_show(m, latencies);
4583
4584         return 0;
4585 }
4586
4587 static int spr_wm_latency_show(struct seq_file *m, void *data)
4588 {
4589         struct drm_i915_private *dev_priv = m->private;
4590         const uint16_t *latencies;
4591
4592         if (INTEL_GEN(dev_priv) >= 9)
4593                 latencies = dev_priv->wm.skl_latency;
4594         else
4595                 latencies = dev_priv->wm.spr_latency;
4596
4597         wm_latency_show(m, latencies);
4598
4599         return 0;
4600 }
4601
4602 static int cur_wm_latency_show(struct seq_file *m, void *data)
4603 {
4604         struct drm_i915_private *dev_priv = m->private;
4605         const uint16_t *latencies;
4606
4607         if (INTEL_GEN(dev_priv) >= 9)
4608                 latencies = dev_priv->wm.skl_latency;
4609         else
4610                 latencies = dev_priv->wm.cur_latency;
4611
4612         wm_latency_show(m, latencies);
4613
4614         return 0;
4615 }
4616
4617 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4618 {
4619         struct drm_i915_private *dev_priv = inode->i_private;
4620
4621         if (INTEL_GEN(dev_priv) < 5)
4622                 return -ENODEV;
4623
4624         return single_open(file, pri_wm_latency_show, dev_priv);
4625 }
4626
4627 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4628 {
4629         struct drm_i915_private *dev_priv = inode->i_private;
4630
4631         if (HAS_GMCH_DISPLAY(dev_priv))
4632                 return -ENODEV;
4633
4634         return single_open(file, spr_wm_latency_show, dev_priv);
4635 }
4636
4637 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4638 {
4639         struct drm_i915_private *dev_priv = inode->i_private;
4640
4641         if (HAS_GMCH_DISPLAY(dev_priv))
4642                 return -ENODEV;
4643
4644         return single_open(file, cur_wm_latency_show, dev_priv);
4645 }
4646
4647 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4648                                 size_t len, loff_t *offp, uint16_t wm[8])
4649 {
4650         struct seq_file *m = file->private_data;
4651         struct drm_i915_private *dev_priv = m->private;
4652         struct drm_device *dev = &dev_priv->drm;
4653         uint16_t new[8] = { 0 };
4654         int num_levels;
4655         int level;
4656         int ret;
4657         char tmp[32];
4658
4659         if (IS_CHERRYVIEW(dev_priv))
4660                 num_levels = 3;
4661         else if (IS_VALLEYVIEW(dev_priv))
4662                 num_levels = 1;
4663         else
4664                 num_levels = ilk_wm_max_level(dev) + 1;
4665
4666         if (len >= sizeof(tmp))
4667                 return -EINVAL;
4668
4669         if (copy_from_user(tmp, ubuf, len))
4670                 return -EFAULT;
4671
4672         tmp[len] = '\0';
4673
4674         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4675                      &new[0], &new[1], &new[2], &new[3],
4676                      &new[4], &new[5], &new[6], &new[7]);
4677         if (ret != num_levels)
4678                 return -EINVAL;
4679
4680         drm_modeset_lock_all(dev);
4681
4682         for (level = 0; level < num_levels; level++)
4683                 wm[level] = new[level];
4684
4685         drm_modeset_unlock_all(dev);
4686
4687         return len;
4688 }
4689
4690
4691 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4692                                     size_t len, loff_t *offp)
4693 {
4694         struct seq_file *m = file->private_data;
4695         struct drm_i915_private *dev_priv = m->private;
4696         uint16_t *latencies;
4697
4698         if (INTEL_GEN(dev_priv) >= 9)
4699                 latencies = dev_priv->wm.skl_latency;
4700         else
4701                 latencies = dev_priv->wm.pri_latency;
4702
4703         return wm_latency_write(file, ubuf, len, offp, latencies);
4704 }
4705
4706 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4707                                     size_t len, loff_t *offp)
4708 {
4709         struct seq_file *m = file->private_data;
4710         struct drm_i915_private *dev_priv = m->private;
4711         uint16_t *latencies;
4712
4713         if (INTEL_GEN(dev_priv) >= 9)
4714                 latencies = dev_priv->wm.skl_latency;
4715         else
4716                 latencies = dev_priv->wm.spr_latency;
4717
4718         return wm_latency_write(file, ubuf, len, offp, latencies);
4719 }
4720
4721 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4722                                     size_t len, loff_t *offp)
4723 {
4724         struct seq_file *m = file->private_data;
4725         struct drm_i915_private *dev_priv = m->private;
4726         uint16_t *latencies;
4727
4728         if (INTEL_GEN(dev_priv) >= 9)
4729                 latencies = dev_priv->wm.skl_latency;
4730         else
4731                 latencies = dev_priv->wm.cur_latency;
4732
4733         return wm_latency_write(file, ubuf, len, offp, latencies);
4734 }
4735
4736 static const struct file_operations i915_pri_wm_latency_fops = {
4737         .owner = THIS_MODULE,
4738         .open = pri_wm_latency_open,
4739         .read = seq_read,
4740         .llseek = seq_lseek,
4741         .release = single_release,
4742         .write = pri_wm_latency_write
4743 };
4744
4745 static const struct file_operations i915_spr_wm_latency_fops = {
4746         .owner = THIS_MODULE,
4747         .open = spr_wm_latency_open,
4748         .read = seq_read,
4749         .llseek = seq_lseek,
4750         .release = single_release,
4751         .write = spr_wm_latency_write
4752 };
4753
4754 static const struct file_operations i915_cur_wm_latency_fops = {
4755         .owner = THIS_MODULE,
4756         .open = cur_wm_latency_open,
4757         .read = seq_read,
4758         .llseek = seq_lseek,
4759         .release = single_release,
4760         .write = cur_wm_latency_write
4761 };
4762
4763 static int
4764 i915_wedged_get(void *data, u64 *val)
4765 {
4766         struct drm_i915_private *dev_priv = data;
4767
4768         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4769
4770         return 0;
4771 }
4772
4773 static int
4774 i915_wedged_set(void *data, u64 val)
4775 {
4776         struct drm_i915_private *dev_priv = data;
4777
4778         /*
4779          * There is no safeguard against this debugfs entry colliding
4780          * with the hangcheck calling same i915_handle_error() in
4781          * parallel, causing an explosion. For now we assume that the
4782          * test harness is responsible enough not to inject gpu hangs
4783          * while it is writing to 'i915_wedged'
4784          */
4785
4786         if (i915_reset_in_progress(&dev_priv->gpu_error))
4787                 return -EAGAIN;
4788
4789         intel_runtime_pm_get(dev_priv);
4790
4791         i915_handle_error(dev_priv, val,
4792                           "Manually setting wedged to %llu", val);
4793
4794         intel_runtime_pm_put(dev_priv);
4795
4796         return 0;
4797 }
4798
4799 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4800                         i915_wedged_get, i915_wedged_set,
4801                         "%llu\n");
4802
4803 static int
4804 i915_ring_missed_irq_get(void *data, u64 *val)
4805 {
4806         struct drm_i915_private *dev_priv = data;
4807
4808         *val = dev_priv->gpu_error.missed_irq_rings;
4809         return 0;
4810 }
4811
4812 static int
4813 i915_ring_missed_irq_set(void *data, u64 val)
4814 {
4815         struct drm_i915_private *dev_priv = data;
4816         struct drm_device *dev = &dev_priv->drm;
4817         int ret;
4818
4819         /* Lock against concurrent debugfs callers */
4820         ret = mutex_lock_interruptible(&dev->struct_mutex);
4821         if (ret)
4822                 return ret;
4823         dev_priv->gpu_error.missed_irq_rings = val;
4824         mutex_unlock(&dev->struct_mutex);
4825
4826         return 0;
4827 }
4828
4829 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4830                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4831                         "0x%08llx\n");
4832
4833 static int
4834 i915_ring_test_irq_get(void *data, u64 *val)
4835 {
4836         struct drm_i915_private *dev_priv = data;
4837
4838         *val = dev_priv->gpu_error.test_irq_rings;
4839
4840         return 0;
4841 }
4842
4843 static int
4844 i915_ring_test_irq_set(void *data, u64 val)
4845 {
4846         struct drm_i915_private *dev_priv = data;
4847
4848         val &= INTEL_INFO(dev_priv)->ring_mask;
4849         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4850         dev_priv->gpu_error.test_irq_rings = val;
4851
4852         return 0;
4853 }
4854
4855 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4856                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4857                         "0x%08llx\n");
4858
4859 #define DROP_UNBOUND 0x1
4860 #define DROP_BOUND 0x2
4861 #define DROP_RETIRE 0x4
4862 #define DROP_ACTIVE 0x8
4863 #define DROP_ALL (DROP_UNBOUND | \
4864                   DROP_BOUND | \
4865                   DROP_RETIRE | \
4866                   DROP_ACTIVE)
4867 static int
4868 i915_drop_caches_get(void *data, u64 *val)
4869 {
4870         *val = DROP_ALL;
4871
4872         return 0;
4873 }
4874
4875 static int
4876 i915_drop_caches_set(void *data, u64 val)
4877 {
4878         struct drm_i915_private *dev_priv = data;
4879         struct drm_device *dev = &dev_priv->drm;
4880         int ret;
4881
4882         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4883
4884         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4885          * on ioctls on -EAGAIN. */
4886         ret = mutex_lock_interruptible(&dev->struct_mutex);
4887         if (ret)
4888                 return ret;
4889
4890         if (val & DROP_ACTIVE) {
4891                 ret = i915_gem_wait_for_idle(dev_priv,
4892                                              I915_WAIT_INTERRUPTIBLE |
4893                                              I915_WAIT_LOCKED);
4894                 if (ret)
4895                         goto unlock;
4896         }
4897
4898         if (val & (DROP_RETIRE | DROP_ACTIVE))
4899                 i915_gem_retire_requests(dev_priv);
4900
4901         if (val & DROP_BOUND)
4902                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4903
4904         if (val & DROP_UNBOUND)
4905                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4906
4907 unlock:
4908         mutex_unlock(&dev->struct_mutex);
4909
4910         return ret;
4911 }
4912
4913 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4914                         i915_drop_caches_get, i915_drop_caches_set,
4915                         "0x%08llx\n");
4916
4917 static int
4918 i915_max_freq_get(void *data, u64 *val)
4919 {
4920         struct drm_i915_private *dev_priv = data;
4921
4922         if (INTEL_GEN(dev_priv) < 6)
4923                 return -ENODEV;
4924
4925         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4926         return 0;
4927 }
4928
4929 static int
4930 i915_max_freq_set(void *data, u64 val)
4931 {
4932         struct drm_i915_private *dev_priv = data;
4933         u32 hw_max, hw_min;
4934         int ret;
4935
4936         if (INTEL_GEN(dev_priv) < 6)
4937                 return -ENODEV;
4938
4939         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4940
4941         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4942         if (ret)
4943                 return ret;
4944
4945         /*
4946          * Turbo will still be enabled, but won't go above the set value.
4947          */
4948         val = intel_freq_opcode(dev_priv, val);
4949
4950         hw_max = dev_priv->rps.max_freq;
4951         hw_min = dev_priv->rps.min_freq;
4952
4953         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4954                 mutex_unlock(&dev_priv->rps.hw_lock);
4955                 return -EINVAL;
4956         }
4957
4958         dev_priv->rps.max_freq_softlimit = val;
4959
4960         intel_set_rps(dev_priv, val);
4961
4962         mutex_unlock(&dev_priv->rps.hw_lock);
4963
4964         return 0;
4965 }
4966
4967 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4968                         i915_max_freq_get, i915_max_freq_set,
4969                         "%llu\n");
4970
4971 static int
4972 i915_min_freq_get(void *data, u64 *val)
4973 {
4974         struct drm_i915_private *dev_priv = data;
4975
4976         if (INTEL_GEN(dev_priv) < 6)
4977                 return -ENODEV;
4978
4979         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4980         return 0;
4981 }
4982
4983 static int
4984 i915_min_freq_set(void *data, u64 val)
4985 {
4986         struct drm_i915_private *dev_priv = data;
4987         u32 hw_max, hw_min;
4988         int ret;
4989
4990         if (INTEL_GEN(dev_priv) < 6)
4991                 return -ENODEV;
4992
4993         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4994
4995         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4996         if (ret)
4997                 return ret;
4998
4999         /*
5000          * Turbo will still be enabled, but won't go below the set value.
5001          */
5002         val = intel_freq_opcode(dev_priv, val);
5003
5004         hw_max = dev_priv->rps.max_freq;
5005         hw_min = dev_priv->rps.min_freq;
5006
5007         if (val < hw_min ||
5008             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5009                 mutex_unlock(&dev_priv->rps.hw_lock);
5010                 return -EINVAL;
5011         }
5012
5013         dev_priv->rps.min_freq_softlimit = val;
5014
5015         intel_set_rps(dev_priv, val);
5016
5017         mutex_unlock(&dev_priv->rps.hw_lock);
5018
5019         return 0;
5020 }
5021
5022 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5023                         i915_min_freq_get, i915_min_freq_set,
5024                         "%llu\n");
5025
5026 static int
5027 i915_cache_sharing_get(void *data, u64 *val)
5028 {
5029         struct drm_i915_private *dev_priv = data;
5030         struct drm_device *dev = &dev_priv->drm;
5031         u32 snpcr;
5032         int ret;
5033
5034         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5035                 return -ENODEV;
5036
5037         ret = mutex_lock_interruptible(&dev->struct_mutex);
5038         if (ret)
5039                 return ret;
5040         intel_runtime_pm_get(dev_priv);
5041
5042         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5043
5044         intel_runtime_pm_put(dev_priv);
5045         mutex_unlock(&dev->struct_mutex);
5046
5047         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5048
5049         return 0;
5050 }
5051
5052 static int
5053 i915_cache_sharing_set(void *data, u64 val)
5054 {
5055         struct drm_i915_private *dev_priv = data;
5056         u32 snpcr;
5057
5058         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5059                 return -ENODEV;
5060
5061         if (val > 3)
5062                 return -EINVAL;
5063
5064         intel_runtime_pm_get(dev_priv);
5065         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5066
5067         /* Update the cache sharing policy here as well */
5068         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5069         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5070         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5071         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5072
5073         intel_runtime_pm_put(dev_priv);
5074         return 0;
5075 }
5076
5077 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5078                         i915_cache_sharing_get, i915_cache_sharing_set,
5079                         "%llu\n");
5080
5081 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5082                                           struct sseu_dev_info *sseu)
5083 {
5084         int ss_max = 2;
5085         int ss;
5086         u32 sig1[ss_max], sig2[ss_max];
5087
5088         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5089         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5090         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5091         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5092
5093         for (ss = 0; ss < ss_max; ss++) {
5094                 unsigned int eu_cnt;
5095
5096                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5097                         /* skip disabled subslice */
5098                         continue;
5099
5100                 sseu->slice_mask = BIT(0);
5101                 sseu->subslice_mask |= BIT(ss);
5102                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5103                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5104                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5105                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5106                 sseu->eu_total += eu_cnt;
5107                 sseu->eu_per_subslice = max_t(unsigned int,
5108                                               sseu->eu_per_subslice, eu_cnt);
5109         }
5110 }
5111
5112 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5113                                     struct sseu_dev_info *sseu)
5114 {
5115         int s_max = 3, ss_max = 4;
5116         int s, ss;
5117         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5118
5119         /* BXT has a single slice and at most 3 subslices. */
5120         if (IS_BROXTON(dev_priv)) {
5121                 s_max = 1;
5122                 ss_max = 3;
5123         }
5124
5125         for (s = 0; s < s_max; s++) {
5126                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5127                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5128                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5129         }
5130
5131         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5132                      GEN9_PGCTL_SSA_EU19_ACK |
5133                      GEN9_PGCTL_SSA_EU210_ACK |
5134                      GEN9_PGCTL_SSA_EU311_ACK;
5135         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5136                      GEN9_PGCTL_SSB_EU19_ACK |
5137                      GEN9_PGCTL_SSB_EU210_ACK |
5138                      GEN9_PGCTL_SSB_EU311_ACK;
5139
5140         for (s = 0; s < s_max; s++) {
5141                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5142                         /* skip disabled slice */
5143                         continue;
5144
5145                 sseu->slice_mask |= BIT(s);
5146
5147                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5148                         sseu->subslice_mask =
5149                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5150
5151                 for (ss = 0; ss < ss_max; ss++) {
5152                         unsigned int eu_cnt;
5153
5154                         if (IS_BROXTON(dev_priv)) {
5155                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5156                                         /* skip disabled subslice */
5157                                         continue;
5158
5159                                 sseu->subslice_mask |= BIT(ss);
5160                         }
5161
5162                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5163                                                eu_mask[ss%2]);
5164                         sseu->eu_total += eu_cnt;
5165                         sseu->eu_per_subslice = max_t(unsigned int,
5166                                                       sseu->eu_per_subslice,
5167                                                       eu_cnt);
5168                 }
5169         }
5170 }
5171
5172 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5173                                          struct sseu_dev_info *sseu)
5174 {
5175         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5176         int s;
5177
5178         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5179
5180         if (sseu->slice_mask) {
5181                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5182                 sseu->eu_per_subslice =
5183                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5184                 sseu->eu_total = sseu->eu_per_subslice *
5185                                  sseu_subslice_total(sseu);
5186
5187                 /* subtract fused off EU(s) from enabled slice(s) */
5188                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5189                         u8 subslice_7eu =
5190                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5191
5192                         sseu->eu_total -= hweight8(subslice_7eu);
5193                 }
5194         }
5195 }
5196
5197 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5198                                  const struct sseu_dev_info *sseu)
5199 {
5200         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5201         const char *type = is_available_info ? "Available" : "Enabled";
5202
5203         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5204                    sseu->slice_mask);
5205         seq_printf(m, "  %s Slice Total: %u\n", type,
5206                    hweight8(sseu->slice_mask));
5207         seq_printf(m, "  %s Subslice Total: %u\n", type,
5208                    sseu_subslice_total(sseu));
5209         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5210                    sseu->subslice_mask);
5211         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5212                    hweight8(sseu->subslice_mask));
5213         seq_printf(m, "  %s EU Total: %u\n", type,
5214                    sseu->eu_total);
5215         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5216                    sseu->eu_per_subslice);
5217
5218         if (!is_available_info)
5219                 return;
5220
5221         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5222         if (HAS_POOLED_EU(dev_priv))
5223                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5224
5225         seq_printf(m, "  Has Slice Power Gating: %s\n",
5226                    yesno(sseu->has_slice_pg));
5227         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5228                    yesno(sseu->has_subslice_pg));
5229         seq_printf(m, "  Has EU Power Gating: %s\n",
5230                    yesno(sseu->has_eu_pg));
5231 }
5232
5233 static int i915_sseu_status(struct seq_file *m, void *unused)
5234 {
5235         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5236         struct sseu_dev_info sseu;
5237
5238         if (INTEL_GEN(dev_priv) < 8)
5239                 return -ENODEV;
5240
5241         seq_puts(m, "SSEU Device Info\n");
5242         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5243
5244         seq_puts(m, "SSEU Device Status\n");
5245         memset(&sseu, 0, sizeof(sseu));
5246
5247         intel_runtime_pm_get(dev_priv);
5248
5249         if (IS_CHERRYVIEW(dev_priv)) {
5250                 cherryview_sseu_device_status(dev_priv, &sseu);
5251         } else if (IS_BROADWELL(dev_priv)) {
5252                 broadwell_sseu_device_status(dev_priv, &sseu);
5253         } else if (INTEL_GEN(dev_priv) >= 9) {
5254                 gen9_sseu_device_status(dev_priv, &sseu);
5255         }
5256
5257         intel_runtime_pm_put(dev_priv);
5258
5259         i915_print_sseu_info(m, false, &sseu);
5260
5261         return 0;
5262 }
5263
5264 static int i915_forcewake_open(struct inode *inode, struct file *file)
5265 {
5266         struct drm_i915_private *dev_priv = inode->i_private;
5267
5268         if (INTEL_GEN(dev_priv) < 6)
5269                 return 0;
5270
5271         intel_runtime_pm_get(dev_priv);
5272         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5273
5274         return 0;
5275 }
5276
5277 static int i915_forcewake_release(struct inode *inode, struct file *file)
5278 {
5279         struct drm_i915_private *dev_priv = inode->i_private;
5280
5281         if (INTEL_GEN(dev_priv) < 6)
5282                 return 0;
5283
5284         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5285         intel_runtime_pm_put(dev_priv);
5286
5287         return 0;
5288 }
5289
5290 static const struct file_operations i915_forcewake_fops = {
5291         .owner = THIS_MODULE,
5292         .open = i915_forcewake_open,
5293         .release = i915_forcewake_release,
5294 };
5295
5296 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5297 {
5298         struct dentry *ent;
5299
5300         ent = debugfs_create_file("i915_forcewake_user",
5301                                   S_IRUSR,
5302                                   root, to_i915(minor->dev),
5303                                   &i915_forcewake_fops);
5304         if (!ent)
5305                 return -ENOMEM;
5306
5307         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5308 }
5309
5310 static int i915_debugfs_create(struct dentry *root,
5311                                struct drm_minor *minor,
5312                                const char *name,
5313                                const struct file_operations *fops)
5314 {
5315         struct dentry *ent;
5316
5317         ent = debugfs_create_file(name,
5318                                   S_IRUGO | S_IWUSR,
5319                                   root, to_i915(minor->dev),
5320                                   fops);
5321         if (!ent)
5322                 return -ENOMEM;
5323
5324         return drm_add_fake_info_node(minor, ent, fops);
5325 }
5326
5327 static const struct drm_info_list i915_debugfs_list[] = {
5328         {"i915_capabilities", i915_capabilities, 0},
5329         {"i915_gem_objects", i915_gem_object_info, 0},
5330         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5331         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5332         {"i915_gem_stolen", i915_gem_stolen_list_info },
5333         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5334         {"i915_gem_request", i915_gem_request_info, 0},
5335         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5336         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5337         {"i915_gem_interrupt", i915_interrupt_info, 0},
5338         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5339         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5340         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5341         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5342         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5343         {"i915_guc_info", i915_guc_info, 0},
5344         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5345         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5346         {"i915_frequency_info", i915_frequency_info, 0},
5347         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5348         {"i915_drpc_info", i915_drpc_info, 0},
5349         {"i915_emon_status", i915_emon_status, 0},
5350         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5351         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5352         {"i915_fbc_status", i915_fbc_status, 0},
5353         {"i915_ips_status", i915_ips_status, 0},
5354         {"i915_sr_status", i915_sr_status, 0},
5355         {"i915_opregion", i915_opregion, 0},
5356         {"i915_vbt", i915_vbt, 0},
5357         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5358         {"i915_context_status", i915_context_status, 0},
5359         {"i915_dump_lrc", i915_dump_lrc, 0},
5360         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5361         {"i915_swizzle_info", i915_swizzle_info, 0},
5362         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5363         {"i915_llc", i915_llc, 0},
5364         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5365         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5366         {"i915_energy_uJ", i915_energy_uJ, 0},
5367         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5368         {"i915_power_domain_info", i915_power_domain_info, 0},
5369         {"i915_dmc_info", i915_dmc_info, 0},
5370         {"i915_display_info", i915_display_info, 0},
5371         {"i915_engine_info", i915_engine_info, 0},
5372         {"i915_semaphore_status", i915_semaphore_status, 0},
5373         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5374         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5375         {"i915_wa_registers", i915_wa_registers, 0},
5376         {"i915_ddb_info", i915_ddb_info, 0},
5377         {"i915_sseu_status", i915_sseu_status, 0},
5378         {"i915_drrs_status", i915_drrs_status, 0},
5379         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5380 };
5381 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5382
5383 static const struct i915_debugfs_files {
5384         const char *name;
5385         const struct file_operations *fops;
5386 } i915_debugfs_files[] = {
5387         {"i915_wedged", &i915_wedged_fops},
5388         {"i915_max_freq", &i915_max_freq_fops},
5389         {"i915_min_freq", &i915_min_freq_fops},
5390         {"i915_cache_sharing", &i915_cache_sharing_fops},
5391         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5392         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5393         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5394         {"i915_error_state", &i915_error_state_fops},
5395         {"i915_next_seqno", &i915_next_seqno_fops},
5396         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5397         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5398         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5399         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5400         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5401         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5402         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5403         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5404 };
5405
5406 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5407 {
5408         enum pipe pipe;
5409
5410         for_each_pipe(dev_priv, pipe) {
5411                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5412
5413                 pipe_crc->opened = false;
5414                 spin_lock_init(&pipe_crc->lock);
5415                 init_waitqueue_head(&pipe_crc->wq);
5416         }
5417 }
5418
5419 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5420 {
5421         struct drm_minor *minor = dev_priv->drm.primary;
5422         int ret, i;
5423
5424         ret = i915_forcewake_create(minor->debugfs_root, minor);
5425         if (ret)
5426                 return ret;
5427
5428         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5429                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5430                 if (ret)
5431                         return ret;
5432         }
5433
5434         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5435                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5436                                           i915_debugfs_files[i].name,
5437                                           i915_debugfs_files[i].fops);
5438                 if (ret)
5439                         return ret;
5440         }
5441
5442         return drm_debugfs_create_files(i915_debugfs_list,
5443                                         I915_DEBUGFS_ENTRIES,
5444                                         minor->debugfs_root, minor);
5445 }
5446
5447 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5448 {
5449         struct drm_minor *minor = dev_priv->drm.primary;
5450         int i;
5451
5452         drm_debugfs_remove_files(i915_debugfs_list,
5453                                  I915_DEBUGFS_ENTRIES, minor);
5454
5455         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5456                                  1, minor);
5457
5458         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5459                 struct drm_info_list *info_list =
5460                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5461
5462                 drm_debugfs_remove_files(info_list, 1, minor);
5463         }
5464
5465         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5466                 struct drm_info_list *info_list =
5467                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5468
5469                 drm_debugfs_remove_files(info_list, 1, minor);
5470         }
5471 }
5472
5473 struct dpcd_block {
5474         /* DPCD dump start address. */
5475         unsigned int offset;
5476         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5477         unsigned int end;
5478         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5479         size_t size;
5480         /* Only valid for eDP. */
5481         bool edp;
5482 };
5483
5484 static const struct dpcd_block i915_dpcd_debug[] = {
5485         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5486         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5487         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5488         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5489         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5490         { .offset = DP_SET_POWER },
5491         { .offset = DP_EDP_DPCD_REV },
5492         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5493         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5494         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5495 };
5496
5497 static int i915_dpcd_show(struct seq_file *m, void *data)
5498 {
5499         struct drm_connector *connector = m->private;
5500         struct intel_dp *intel_dp =
5501                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5502         uint8_t buf[16];
5503         ssize_t err;
5504         int i;
5505
5506         if (connector->status != connector_status_connected)
5507                 return -ENODEV;
5508
5509         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5510                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5511                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5512
5513                 if (b->edp &&
5514                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5515                         continue;
5516
5517                 /* low tech for now */
5518                 if (WARN_ON(size > sizeof(buf)))
5519                         continue;
5520
5521                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5522                 if (err <= 0) {
5523                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5524                                   size, b->offset, err);
5525                         continue;
5526                 }
5527
5528                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5529         }
5530
5531         return 0;
5532 }
5533
5534 static int i915_dpcd_open(struct inode *inode, struct file *file)
5535 {
5536         return single_open(file, i915_dpcd_show, inode->i_private);
5537 }
5538
5539 static const struct file_operations i915_dpcd_fops = {
5540         .owner = THIS_MODULE,
5541         .open = i915_dpcd_open,
5542         .read = seq_read,
5543         .llseek = seq_lseek,
5544         .release = single_release,
5545 };
5546
5547 static int i915_panel_show(struct seq_file *m, void *data)
5548 {
5549         struct drm_connector *connector = m->private;
5550         struct intel_dp *intel_dp =
5551                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5552
5553         if (connector->status != connector_status_connected)
5554                 return -ENODEV;
5555
5556         seq_printf(m, "Panel power up delay: %d\n",
5557                    intel_dp->panel_power_up_delay);
5558         seq_printf(m, "Panel power down delay: %d\n",
5559                    intel_dp->panel_power_down_delay);
5560         seq_printf(m, "Backlight on delay: %d\n",
5561                    intel_dp->backlight_on_delay);
5562         seq_printf(m, "Backlight off delay: %d\n",
5563                    intel_dp->backlight_off_delay);
5564
5565         return 0;
5566 }
5567
5568 static int i915_panel_open(struct inode *inode, struct file *file)
5569 {
5570         return single_open(file, i915_panel_show, inode->i_private);
5571 }
5572
5573 static const struct file_operations i915_panel_fops = {
5574         .owner = THIS_MODULE,
5575         .open = i915_panel_open,
5576         .read = seq_read,
5577         .llseek = seq_lseek,
5578         .release = single_release,
5579 };
5580
5581 /**
5582  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5583  * @connector: pointer to a registered drm_connector
5584  *
5585  * Cleanup will be done by drm_connector_unregister() through a call to
5586  * drm_debugfs_connector_remove().
5587  *
5588  * Returns 0 on success, negative error codes on error.
5589  */
5590 int i915_debugfs_connector_add(struct drm_connector *connector)
5591 {
5592         struct dentry *root = connector->debugfs_entry;
5593
5594         /* The connector must have been registered beforehands. */
5595         if (!root)
5596                 return -ENODEV;
5597
5598         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5599             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5600                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5601                                     connector, &i915_dpcd_fops);
5602
5603         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5604                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5605                                     connector, &i915_panel_fops);
5606
5607         return 0;
5608 }