drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/list_sort.h>
  31 #include "intel_drv.h"
  32
  33 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  34 {
  35         return to_i915(node->minor->dev);
  36 }
  37
  38 static __always_inline void seq_print_param(struct seq_file *m,
  39                                             const char *name,
  40                                             const char *type,
  41                                             const void *x)
  42 {
  43         if (!__builtin_strcmp(type, "bool"))
  44                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  45         else if (!__builtin_strcmp(type, "int"))
  46                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  47         else if (!__builtin_strcmp(type, "unsigned int"))
  48                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  49         else if (!__builtin_strcmp(type, "char *"))
  50                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  51         else
  52                 BUILD_BUG();
  53 }
  54
  55 static int i915_capabilities(struct seq_file *m, void *data)
  56 {
  57         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  58         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  59
  60         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  61         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  63
  64 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  65         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  66 #undef PRINT_FLAG
  67
  68         kernel_param_lock(THIS_MODULE);
  69 #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x);
  70         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  71 #undef PRINT_PARAM
  72         kernel_param_unlock(THIS_MODULE);
  73
  74         return 0;
  75 }
  76
  77 static char get_active_flag(struct drm_i915_gem_object *obj)
  78 {
  79         return i915_gem_object_is_active(obj) ? '*' : ' ';
  80 }
  81
  82 static char get_pin_flag(struct drm_i915_gem_object *obj)
  83 {
  84         return obj->pin_display ? 'p' : ' ';
  85 }
  86
  87 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  88 {
  89         switch (i915_gem_object_get_tiling(obj)) {
  90         default:
  91         case I915_TILING_NONE: return ' ';
  92         case I915_TILING_X: return 'X';
  93         case I915_TILING_Y: return 'Y';
  94         }
  95 }
  96
  97 static char get_global_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 100 }
 101
 102 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 103 {
 104         return obj->mm.mapping ? 'M' : ' ';
 105 }
 106
 107 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 108 {
 109         u64 size = 0;
 110         struct i915_vma *vma;
 111
 112         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 113                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 114                         size += vma->node.size;
 115         }
 116
 117         return size;
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 124         struct intel_engine_cs *engine;
 125         struct i915_vma *vma;
 126         unsigned int frontbuffer_bits;
 127         int pin_count = 0;
 128
 129         lockdep_assert_held(&obj->base.dev->struct_mutex);
 130
 131         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 132                    &obj->base,
 133                    get_active_flag(obj),
 134                    get_pin_flag(obj),
 135                    get_tiling_flag(obj),
 136                    get_global_flag(obj),
 137                    get_pin_mapped_flag(obj),
 138                    obj->base.size / 1024,
 139                    obj->base.read_domains,
 140                    obj->base.write_domain,
 141                    i915_cache_level_str(dev_priv, obj->cache_level),
 142                    obj->mm.dirty ? " dirty" : "",
 143                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 144         if (obj->base.name)
 145                 seq_printf(m, " (name: %d)", obj->base.name);
 146         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 147                 if (i915_vma_is_pinned(vma))
 148                         pin_count++;
 149         }
 150         seq_printf(m, " (pinned x %d)", pin_count);
 151         if (obj->pin_display)
 152                 seq_printf(m, " (display)");
 153         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 154                 if (!drm_mm_node_allocated(&vma->node))
 155                         continue;
 156
 157                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 158                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 159                            vma->node.start, vma->node.size);
 160                 if (i915_vma_is_ggtt(vma)) {
 161                         switch (vma->ggtt_view.type) {
 162                         case I915_GGTT_VIEW_NORMAL:
 163                                 seq_puts(m, ", normal");
 164                                 break;
 165
 166                         case I915_GGTT_VIEW_PARTIAL:
 167                                 seq_printf(m, ", partial [%08llx+%x]",
 168                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 169                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 170                                 break;
 171
 172                         case I915_GGTT_VIEW_ROTATED:
 173                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 174                                            vma->ggtt_view.rotated.plane[0].width,
 175                                            vma->ggtt_view.rotated.plane[0].height,
 176                                            vma->ggtt_view.rotated.plane[0].stride,
 177                                            vma->ggtt_view.rotated.plane[0].offset,
 178                                            vma->ggtt_view.rotated.plane[1].width,
 179                                            vma->ggtt_view.rotated.plane[1].height,
 180                                            vma->ggtt_view.rotated.plane[1].stride,
 181                                            vma->ggtt_view.rotated.plane[1].offset);
 182                                 break;
 183
 184                         default:
 185                                 MISSING_CASE(vma->ggtt_view.type);
 186                                 break;
 187                         }
 188                 }
 189                 if (vma->fence)
 190                         seq_printf(m, " , fence: %d%s",
 191                                    vma->fence->id,
 192                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 193                 seq_puts(m, ")");
 194         }
 195         if (obj->stolen)
 196                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 197
 198         engine = i915_gem_object_last_write_engine(obj);
 199         if (engine)
 200                 seq_printf(m, " (%s)", engine->name);
 201
 202         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 203         if (frontbuffer_bits)
 204                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 205 }
 206
 207 static int obj_rank_by_stolen(void *priv,
 208                               struct list_head *A, struct list_head *B)
 209 {
 210         struct drm_i915_gem_object *a =
 211                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 212         struct drm_i915_gem_object *b =
 213                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 214
 215         if (a->stolen->start < b->stolen->start)
 216                 return -1;
 217         if (a->stolen->start > b->stolen->start)
 218                 return 1;
 219         return 0;
 220 }
 221
 222 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 223 {
 224         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 225         struct drm_device *dev = &dev_priv->drm;
 226         struct drm_i915_gem_object *obj;
 227         u64 total_obj_size, total_gtt_size;
 228         LIST_HEAD(stolen);
 229         int count, ret;
 230
 231         ret = mutex_lock_interruptible(&dev->struct_mutex);
 232         if (ret)
 233                 return ret;
 234
 235         total_obj_size = total_gtt_size = count = 0;
 236         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 237                 if (obj->stolen == NULL)
 238                         continue;
 239
 240                 list_add(&obj->obj_exec_link, &stolen);
 241
 242                 total_obj_size += obj->base.size;
 243                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 244                 count++;
 245         }
 246         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 247                 if (obj->stolen == NULL)
 248                         continue;
 249
 250                 list_add(&obj->obj_exec_link, &stolen);
 251
 252                 total_obj_size += obj->base.size;
 253                 count++;
 254         }
 255         list_sort(NULL, &stolen, obj_rank_by_stolen);
 256         seq_puts(m, "Stolen:\n");
 257         while (!list_empty(&stolen)) {
 258                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 259                 seq_puts(m, "   ");
 260                 describe_obj(m, obj);
 261                 seq_putc(m, '\n');
 262                 list_del_init(&obj->obj_exec_link);
 263         }
 264         mutex_unlock(&dev->struct_mutex);
 265
 266         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 267                    count, total_obj_size, total_gtt_size);
 268         return 0;
 269 }
 270
 271 struct file_stats {
 272         struct drm_i915_file_private *file_priv;
 273         unsigned long count;
 274         u64 total, unbound;
 275         u64 global, shared;
 276         u64 active, inactive;
 277 };
 278
 279 static int per_file_stats(int id, void *ptr, void *data)
 280 {
 281         struct drm_i915_gem_object *obj = ptr;
 282         struct file_stats *stats = data;
 283         struct i915_vma *vma;
 284
 285         stats->count++;
 286         stats->total += obj->base.size;
 287         if (!obj->bind_count)
 288                 stats->unbound += obj->base.size;
 289         if (obj->base.name || obj->base.dma_buf)
 290                 stats->shared += obj->base.size;
 291
 292         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 293                 if (!drm_mm_node_allocated(&vma->node))
 294                         continue;
 295
 296                 if (i915_vma_is_ggtt(vma)) {
 297                         stats->global += vma->node.size;
 298                 } else {
 299                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 300
 301                         if (ppgtt->base.file != stats->file_priv)
 302                                 continue;
 303                 }
 304
 305                 if (i915_vma_is_active(vma))
 306                         stats->active += vma->node.size;
 307                 else
 308                         stats->inactive += vma->node.size;
 309         }
 310
 311         return 0;
 312 }
 313
 314 #define print_file_stats(m, name, stats) do { \
 315         if (stats.count) \
 316                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 317                            name, \
 318                            stats.count, \
 319                            stats.total, \
 320                            stats.active, \
 321                            stats.inactive, \
 322                            stats.global, \
 323                            stats.shared, \
 324                            stats.unbound); \
 325 } while (0)
 326
 327 static void print_batch_pool_stats(struct seq_file *m,
 328                                    struct drm_i915_private *dev_priv)
 329 {
 330         struct drm_i915_gem_object *obj;
 331         struct file_stats stats;
 332         struct intel_engine_cs *engine;
 333         enum intel_engine_id id;
 334         int j;
 335
 336         memset(&stats, 0, sizeof(stats));
 337
 338         for_each_engine(engine, dev_priv, id) {
 339                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 340                         list_for_each_entry(obj,
 341                                             &engine->batch_pool.cache_list[j],
 342                                             batch_pool_link)
 343                                 per_file_stats(0, obj, &stats);
 344                 }
 345         }
 346
 347         print_file_stats(m, "[k]batch pool", stats);
 348 }
 349
 350 static int per_file_ctx_stats(int id, void *ptr, void *data)
 351 {
 352         struct i915_gem_context *ctx = ptr;
 353         int n;
 354
 355         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 356                 if (ctx->engine[n].state)
 357                         per_file_stats(0, ctx->engine[n].state->obj, data);
 358                 if (ctx->engine[n].ring)
 359                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 360         }
 361
 362         return 0;
 363 }
 364
 365 static void print_context_stats(struct seq_file *m,
 366                                 struct drm_i915_private *dev_priv)
 367 {
 368         struct drm_device *dev = &dev_priv->drm;
 369         struct file_stats stats;
 370         struct drm_file *file;
 371
 372         memset(&stats, 0, sizeof(stats));
 373
 374         mutex_lock(&dev->struct_mutex);
 375         if (dev_priv->kernel_context)
 376                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 377
 378         list_for_each_entry(file, &dev->filelist, lhead) {
 379                 struct drm_i915_file_private *fpriv = file->driver_priv;
 380                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 381         }
 382         mutex_unlock(&dev->struct_mutex);
 383
 384         print_file_stats(m, "[k]contexts", stats);
 385 }
 386
 387 static int i915_gem_object_info(struct seq_file *m, void *data)
 388 {
 389         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 390         struct drm_device *dev = &dev_priv->drm;
 391         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 392         u32 count, mapped_count, purgeable_count, dpy_count;
 393         u64 size, mapped_size, purgeable_size, dpy_size;
 394         struct drm_i915_gem_object *obj;
 395         struct drm_file *file;
 396         int ret;
 397
 398         ret = mutex_lock_interruptible(&dev->struct_mutex);
 399         if (ret)
 400                 return ret;
 401
 402         seq_printf(m, "%u objects, %llu bytes\n",
 403                    dev_priv->mm.object_count,
 404                    dev_priv->mm.object_memory);
 405
 406         size = count = 0;
 407         mapped_size = mapped_count = 0;
 408         purgeable_size = purgeable_count = 0;
 409         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 410                 size += obj->base.size;
 411                 ++count;
 412
 413                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 414                         purgeable_size += obj->base.size;
 415                         ++purgeable_count;
 416                 }
 417
 418                 if (obj->mm.mapping) {
 419                         mapped_count++;
 420                         mapped_size += obj->base.size;
 421                 }
 422         }
 423         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 424
 425         size = count = dpy_size = dpy_count = 0;
 426         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 427                 size += obj->base.size;
 428                 ++count;
 429
 430                 if (obj->pin_display) {
 431                         dpy_size += obj->base.size;
 432                         ++dpy_count;
 433                 }
 434
 435                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 436                         purgeable_size += obj->base.size;
 437                         ++purgeable_count;
 438                 }
 439
 440                 if (obj->mm.mapping) {
 441                         mapped_count++;
 442                         mapped_size += obj->base.size;
 443                 }
 444         }
 445         seq_printf(m, "%u bound objects, %llu bytes\n",
 446                    count, size);
 447         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 448                    purgeable_count, purgeable_size);
 449         seq_printf(m, "%u mapped objects, %llu bytes\n",
 450                    mapped_count, mapped_size);
 451         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 452                    dpy_count, dpy_size);
 453
 454         seq_printf(m, "%llu [%llu] gtt total\n",
 455                    ggtt->base.total, ggtt->mappable_end);
 456
 457         seq_putc(m, '\n');
 458         print_batch_pool_stats(m, dev_priv);
 459         mutex_unlock(&dev->struct_mutex);
 460
 461         mutex_lock(&dev->filelist_mutex);
 462         print_context_stats(m, dev_priv);
 463         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 464                 struct file_stats stats;
 465                 struct drm_i915_file_private *file_priv = file->driver_priv;
 466                 struct drm_i915_gem_request *request;
 467                 struct task_struct *task;
 468
 469                 memset(&stats, 0, sizeof(stats));
 470                 stats.file_priv = file->driver_priv;
 471                 spin_lock(&file->table_lock);
 472                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 473                 spin_unlock(&file->table_lock);
 474                 /*
 475                  * Although we have a valid reference on file->pid, that does
 476                  * not guarantee that the task_struct who called get_pid() is
 477                  * still alive (e.g. get_pid(current) => fork() => exit()).
 478                  * Therefore, we need to protect this ->comm access using RCU.
 479                  */
 480                 mutex_lock(&dev->struct_mutex);
 481                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 482                                                    struct drm_i915_gem_request,
 483                                                    client_link);
 484                 rcu_read_lock();
 485                 task = pid_task(request && request->ctx->pid ?
 486                                 request->ctx->pid : file->pid,
 487                                 PIDTYPE_PID);
 488                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 489                 rcu_read_unlock();
 490                 mutex_unlock(&dev->struct_mutex);
 491         }
 492         mutex_unlock(&dev->filelist_mutex);
 493
 494         return 0;
 495 }
 496
 497 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 498 {
 499         struct drm_info_node *node = m->private;
 500         struct drm_i915_private *dev_priv = node_to_i915(node);
 501         struct drm_device *dev = &dev_priv->drm;
 502         bool show_pin_display_only = !!node->info_ent->data;
 503         struct drm_i915_gem_object *obj;
 504         u64 total_obj_size, total_gtt_size;
 505         int count, ret;
 506
 507         ret = mutex_lock_interruptible(&dev->struct_mutex);
 508         if (ret)
 509                 return ret;
 510
 511         total_obj_size = total_gtt_size = count = 0;
 512         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 513                 if (show_pin_display_only && !obj->pin_display)
 514                         continue;
 515
 516                 seq_puts(m, "   ");
 517                 describe_obj(m, obj);
 518                 seq_putc(m, '\n');
 519                 total_obj_size += obj->base.size;
 520                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 521                 count++;
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 527                    count, total_obj_size, total_gtt_size);
 528
 529         return 0;
 530 }
 531
 532 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 533 {
 534         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 535         struct drm_device *dev = &dev_priv->drm;
 536         struct intel_crtc *crtc;
 537         int ret;
 538
 539         ret = mutex_lock_interruptible(&dev->struct_mutex);
 540         if (ret)
 541                 return ret;
 542
 543         for_each_intel_crtc(dev, crtc) {
 544                 const char pipe = pipe_name(crtc->pipe);
 545                 const char plane = plane_name(crtc->plane);
 546                 struct intel_flip_work *work;
 547
 548                 spin_lock_irq(&dev->event_lock);
 549                 work = crtc->flip_work;
 550                 if (work == NULL) {
 551                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 552                                    pipe, plane);
 553                 } else {
 554                         u32 pending;
 555                         u32 addr;
 556
 557                         pending = atomic_read(&work->pending);
 558                         if (pending) {
 559                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 560                                            pipe, plane);
 561                         } else {
 562                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         }
 565                         if (work->flip_queued_req) {
 566                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 567
 568                                 seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n",
 569                                            engine->name,
 570                                            work->flip_queued_req->global_seqno,
 571                                            intel_engine_last_submit(engine),
 572                                            intel_engine_get_seqno(engine),
 573                                            i915_gem_request_completed(work->flip_queued_req));
 574                         } else
 575                                 seq_printf(m, "Flip not associated with any ring\n");
 576                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 577                                    work->flip_queued_vblank,
 578                                    work->flip_ready_vblank,
 579                                    intel_crtc_get_vblank_counter(crtc));
 580                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 581
 582                         if (INTEL_GEN(dev_priv) >= 4)
 583                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 584                         else
 585                                 addr = I915_READ(DSPADDR(crtc->plane));
 586                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 587
 588                         if (work->pending_flip_obj) {
 589                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 590                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 591                         }
 592                 }
 593                 spin_unlock_irq(&dev->event_lock);
 594         }
 595
 596         mutex_unlock(&dev->struct_mutex);
 597
 598         return 0;
 599 }
 600
 601 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 602 {
 603         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 604         struct drm_device *dev = &dev_priv->drm;
 605         struct drm_i915_gem_object *obj;
 606         struct intel_engine_cs *engine;
 607         enum intel_engine_id id;
 608         int total = 0;
 609         int ret, j;
 610
 611         ret = mutex_lock_interruptible(&dev->struct_mutex);
 612         if (ret)
 613                 return ret;
 614
 615         for_each_engine(engine, dev_priv, id) {
 616                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 617                         int count;
 618
 619                         count = 0;
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link)
 623                                 count++;
 624                         seq_printf(m, "%s cache[%d]: %d objects\n",
 625                                    engine->name, j, count);
 626
 627                         list_for_each_entry(obj,
 628                                             &engine->batch_pool.cache_list[j],
 629                                             batch_pool_link) {
 630                                 seq_puts(m, "   ");
 631                                 describe_obj(m, obj);
 632                                 seq_putc(m, '\n');
 633                         }
 634
 635                         total += count;
 636                 }
 637         }
 638
 639         seq_printf(m, "total: %d\n", total);
 640
 641         mutex_unlock(&dev->struct_mutex);
 642
 643         return 0;
 644 }
 645
 646 static void print_request(struct seq_file *m,
 647                           struct drm_i915_gem_request *rq,
 648                           const char *prefix)
 649 {
 650         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 651                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 652                    rq->priotree.priority,
 653                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 654                    rq->timeline->common->name);
 655 }
 656
 657 static int i915_gem_request_info(struct seq_file *m, void *data)
 658 {
 659         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 660         struct drm_device *dev = &dev_priv->drm;
 661         struct drm_i915_gem_request *req;
 662         struct intel_engine_cs *engine;
 663         enum intel_engine_id id;
 664         int ret, any;
 665
 666         ret = mutex_lock_interruptible(&dev->struct_mutex);
 667         if (ret)
 668                 return ret;
 669
 670         any = 0;
 671         for_each_engine(engine, dev_priv, id) {
 672                 int count;
 673
 674                 count = 0;
 675                 list_for_each_entry(req, &engine->timeline->requests, link)
 676                         count++;
 677                 if (count == 0)
 678                         continue;
 679
 680                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 681                 list_for_each_entry(req, &engine->timeline->requests, link)
 682                         print_request(m, req, "    ");
 683
 684                 any++;
 685         }
 686         mutex_unlock(&dev->struct_mutex);
 687
 688         if (any == 0)
 689                 seq_puts(m, "No requests\n");
 690
 691         return 0;
 692 }
 693
 694 static void i915_ring_seqno_info(struct seq_file *m,
 695                                  struct intel_engine_cs *engine)
 696 {
 697         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 698         struct rb_node *rb;
 699
 700         seq_printf(m, "Current sequence (%s): %x\n",
 701                    engine->name, intel_engine_get_seqno(engine));
 702
 703         spin_lock_irq(&b->rb_lock);
 704         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 705                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 706
 707                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 708                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 709         }
 710         spin_unlock_irq(&b->rb_lock);
 711 }
 712
 713 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 714 {
 715         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 716         struct intel_engine_cs *engine;
 717         enum intel_engine_id id;
 718
 719         for_each_engine(engine, dev_priv, id)
 720                 i915_ring_seqno_info(m, engine);
 721
 722         return 0;
 723 }
 724
 725
 726 static int i915_interrupt_info(struct seq_file *m, void *data)
 727 {
 728         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 729         struct intel_engine_cs *engine;
 730         enum intel_engine_id id;
 731         int i, pipe;
 732
 733         intel_runtime_pm_get(dev_priv);
 734
 735         if (IS_CHERRYVIEW(dev_priv)) {
 736                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 737                            I915_READ(GEN8_MASTER_IRQ));
 738
 739                 seq_printf(m, "Display IER:\t%08x\n",
 740                            I915_READ(VLV_IER));
 741                 seq_printf(m, "Display IIR:\t%08x\n",
 742                            I915_READ(VLV_IIR));
 743                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 744                            I915_READ(VLV_IIR_RW));
 745                 seq_printf(m, "Display IMR:\t%08x\n",
 746                            I915_READ(VLV_IMR));
 747                 for_each_pipe(dev_priv, pipe) {
 748                         enum intel_display_power_domain power_domain;
 749
 750                         power_domain = POWER_DOMAIN_PIPE(pipe);
 751                         if (!intel_display_power_get_if_enabled(dev_priv,
 752                                                                 power_domain)) {
 753                                 seq_printf(m, "Pipe %c power disabled\n",
 754                                            pipe_name(pipe));
 755                                 continue;
 756                         }
 757
 758                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 759                                    pipe_name(pipe),
 760                                    I915_READ(PIPESTAT(pipe)));
 761
 762                         intel_display_power_put(dev_priv, power_domain);
 763                 }
 764
 765                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 766                 seq_printf(m, "Port hotplug:\t%08x\n",
 767                            I915_READ(PORT_HOTPLUG_EN));
 768                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 769                            I915_READ(VLV_DPFLIPSTAT));
 770                 seq_printf(m, "DPINVGTT:\t%08x\n",
 771                            I915_READ(DPINVGTT));
 772                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 773
 774                 for (i = 0; i < 4; i++) {
 775                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 776                                    i, I915_READ(GEN8_GT_IMR(i)));
 777                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 778                                    i, I915_READ(GEN8_GT_IIR(i)));
 779                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 780                                    i, I915_READ(GEN8_GT_IER(i)));
 781                 }
 782
 783                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 784                            I915_READ(GEN8_PCU_IMR));
 785                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 786                            I915_READ(GEN8_PCU_IIR));
 787                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 788                            I915_READ(GEN8_PCU_IER));
 789         } else if (INTEL_GEN(dev_priv) >= 8) {
 790                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 791                            I915_READ(GEN8_MASTER_IRQ));
 792
 793                 for (i = 0; i < 4; i++) {
 794                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 795                                    i, I915_READ(GEN8_GT_IMR(i)));
 796                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IIR(i)));
 798                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IER(i)));
 800                 }
 801
 802                 for_each_pipe(dev_priv, pipe) {
 803                         enum intel_display_power_domain power_domain;
 804
 805                         power_domain = POWER_DOMAIN_PIPE(pipe);
 806                         if (!intel_display_power_get_if_enabled(dev_priv,
 807                                                                 power_domain)) {
 808                                 seq_printf(m, "Pipe %c power disabled\n",
 809                                            pipe_name(pipe));
 810                                 continue;
 811                         }
 812                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 813                                    pipe_name(pipe),
 814                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 815                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 816                                    pipe_name(pipe),
 817                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 818                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 819                                    pipe_name(pipe),
 820                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 821
 822                         intel_display_power_put(dev_priv, power_domain);
 823                 }
 824
 825                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 826                            I915_READ(GEN8_DE_PORT_IMR));
 827                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 828                            I915_READ(GEN8_DE_PORT_IIR));
 829                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 830                            I915_READ(GEN8_DE_PORT_IER));
 831
 832                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 833                            I915_READ(GEN8_DE_MISC_IMR));
 834                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 835                            I915_READ(GEN8_DE_MISC_IIR));
 836                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 837                            I915_READ(GEN8_DE_MISC_IER));
 838
 839                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 840                            I915_READ(GEN8_PCU_IMR));
 841                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 842                            I915_READ(GEN8_PCU_IIR));
 843                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 844                            I915_READ(GEN8_PCU_IER));
 845         } else if (IS_VALLEYVIEW(dev_priv)) {
 846                 seq_printf(m, "Display IER:\t%08x\n",
 847                            I915_READ(VLV_IER));
 848                 seq_printf(m, "Display IIR:\t%08x\n",
 849                            I915_READ(VLV_IIR));
 850                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 851                            I915_READ(VLV_IIR_RW));
 852                 seq_printf(m, "Display IMR:\t%08x\n",
 853                            I915_READ(VLV_IMR));
 854                 for_each_pipe(dev_priv, pipe) {
 855                         enum intel_display_power_domain power_domain;
 856
 857                         power_domain = POWER_DOMAIN_PIPE(pipe);
 858                         if (!intel_display_power_get_if_enabled(dev_priv,
 859                                                                 power_domain)) {
 860                                 seq_printf(m, "Pipe %c power disabled\n",
 861                                            pipe_name(pipe));
 862                                 continue;
 863                         }
 864
 865                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 866                                    pipe_name(pipe),
 867                                    I915_READ(PIPESTAT(pipe)));
 868                         intel_display_power_put(dev_priv, power_domain);
 869                 }
 870
 871                 seq_printf(m, "Master IER:\t%08x\n",
 872                            I915_READ(VLV_MASTER_IER));
 873
 874                 seq_printf(m, "Render IER:\t%08x\n",
 875                            I915_READ(GTIER));
 876                 seq_printf(m, "Render IIR:\t%08x\n",
 877                            I915_READ(GTIIR));
 878                 seq_printf(m, "Render IMR:\t%08x\n",
 879                            I915_READ(GTIMR));
 880
 881                 seq_printf(m, "PM IER:\t\t%08x\n",
 882                            I915_READ(GEN6_PMIER));
 883                 seq_printf(m, "PM IIR:\t\t%08x\n",
 884                            I915_READ(GEN6_PMIIR));
 885                 seq_printf(m, "PM IMR:\t\t%08x\n",
 886                            I915_READ(GEN6_PMIMR));
 887
 888                 seq_printf(m, "Port hotplug:\t%08x\n",
 889                            I915_READ(PORT_HOTPLUG_EN));
 890                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 891                            I915_READ(VLV_DPFLIPSTAT));
 892                 seq_printf(m, "DPINVGTT:\t%08x\n",
 893                            I915_READ(DPINVGTT));
 894
 895         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 896                 seq_printf(m, "Interrupt enable:    %08x\n",
 897                            I915_READ(IER));
 898                 seq_printf(m, "Interrupt identity:  %08x\n",
 899                            I915_READ(IIR));
 900                 seq_printf(m, "Interrupt mask:      %08x\n",
 901                            I915_READ(IMR));
 902                 for_each_pipe(dev_priv, pipe)
 903                         seq_printf(m, "Pipe %c stat:         %08x\n",
 904                                    pipe_name(pipe),
 905                                    I915_READ(PIPESTAT(pipe)));
 906         } else {
 907                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 908                            I915_READ(DEIER));
 909                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 910                            I915_READ(DEIIR));
 911                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 912                            I915_READ(DEIMR));
 913                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 914                            I915_READ(SDEIER));
 915                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 916                            I915_READ(SDEIIR));
 917                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 918                            I915_READ(SDEIMR));
 919                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 920                            I915_READ(GTIER));
 921                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 922                            I915_READ(GTIIR));
 923                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 924                            I915_READ(GTIMR));
 925         }
 926         for_each_engine(engine, dev_priv, id) {
 927                 if (INTEL_GEN(dev_priv) >= 6) {
 928                         seq_printf(m,
 929                                    "Graphics Interrupt mask (%s):       %08x\n",
 930                                    engine->name, I915_READ_IMR(engine));
 931                 }
 932                 i915_ring_seqno_info(m, engine);
 933         }
 934         intel_runtime_pm_put(dev_priv);
 935
 936         return 0;
 937 }
 938
 939 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 940 {
 941         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 942         struct drm_device *dev = &dev_priv->drm;
 943         int i, ret;
 944
 945         ret = mutex_lock_interruptible(&dev->struct_mutex);
 946         if (ret)
 947                 return ret;
 948
 949         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 950         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 951                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 952
 953                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 954                            i, dev_priv->fence_regs[i].pin_count);
 955                 if (!vma)
 956                         seq_puts(m, "unused");
 957                 else
 958                         describe_obj(m, vma->obj);
 959                 seq_putc(m, '\n');
 960         }
 961
 962         mutex_unlock(&dev->struct_mutex);
 963         return 0;
 964 }
 965
 966 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 967 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 968                               size_t count, loff_t *pos)
 969 {
 970         struct i915_gpu_state *error = file->private_data;
 971         struct drm_i915_error_state_buf str;
 972         ssize_t ret;
 973         loff_t tmp;
 974
 975         if (!error)
 976                 return 0;
 977
 978         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 979         if (ret)
 980                 return ret;
 981
 982         ret = i915_error_state_to_str(&str, error);
 983         if (ret)
 984                 goto out;
 985
 986         tmp = 0;
 987         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 988         if (ret < 0)
 989                 goto out;
 990
 991         *pos = str.start + ret;
 992 out:
 993         i915_error_state_buf_release(&str);
 994         return ret;
 995 }
 996
 997 static int gpu_state_release(struct inode *inode, struct file *file)
 998 {
 999         i915_gpu_state_put(file->private_data);
1000         return 0;
1001 }
1002
1003 static int i915_gpu_info_open(struct inode *inode, struct file *file)
1004 {
1005         struct i915_gpu_state *gpu;
1006
1007         gpu = i915_capture_gpu_state(inode->i_private);
1008         if (!gpu)
1009                 return -ENOMEM;
1010
1011         file->private_data = gpu;
1012         return 0;
1013 }
1014
1015 static const struct file_operations i915_gpu_info_fops = {
1016         .owner = THIS_MODULE,
1017         .open = i915_gpu_info_open,
1018         .read = gpu_state_read,
1019         .llseek = default_llseek,
1020         .release = gpu_state_release,
1021 };
1022
1023 static ssize_t
1024 i915_error_state_write(struct file *filp,
1025                        const char __user *ubuf,
1026                        size_t cnt,
1027                        loff_t *ppos)
1028 {
1029         struct i915_gpu_state *error = filp->private_data;
1030
1031         if (!error)
1032                 return 0;
1033
1034         DRM_DEBUG_DRIVER("Resetting error state\n");
1035         i915_reset_error_state(error->i915);
1036
1037         return cnt;
1038 }
1039
1040 static int i915_error_state_open(struct inode *inode, struct file *file)
1041 {
1042         file->private_data = i915_first_error_state(inode->i_private);
1043         return 0;
1044 }
1045
1046 static const struct file_operations i915_error_state_fops = {
1047         .owner = THIS_MODULE,
1048         .open = i915_error_state_open,
1049         .read = gpu_state_read,
1050         .write = i915_error_state_write,
1051         .llseek = default_llseek,
1052         .release = gpu_state_release,
1053 };
1054 #endif
1055
1056 static int
1057 i915_next_seqno_set(void *data, u64 val)
1058 {
1059         struct drm_i915_private *dev_priv = data;
1060         struct drm_device *dev = &dev_priv->drm;
1061         int ret;
1062
1063         ret = mutex_lock_interruptible(&dev->struct_mutex);
1064         if (ret)
1065                 return ret;
1066
1067         ret = i915_gem_set_global_seqno(dev, val);
1068         mutex_unlock(&dev->struct_mutex);
1069
1070         return ret;
1071 }
1072
1073 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1074                         NULL, i915_next_seqno_set,
1075                         "0x%llx\n");
1076
1077 static int i915_frequency_info(struct seq_file *m, void *unused)
1078 {
1079         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1080         int ret = 0;
1081
1082         intel_runtime_pm_get(dev_priv);
1083
1084         if (IS_GEN5(dev_priv)) {
1085                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1086                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1087
1088                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1089                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1090                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1091                            MEMSTAT_VID_SHIFT);
1092                 seq_printf(m, "Current P-state: %d\n",
1093                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1094         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1095                 u32 freq_sts;
1096
1097                 mutex_lock(&dev_priv->rps.hw_lock);
1098                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1099                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1100                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1101
1102                 seq_printf(m, "actual GPU freq: %d MHz\n",
1103                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1104
1105                 seq_printf(m, "current GPU freq: %d MHz\n",
1106                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1107
1108                 seq_printf(m, "max GPU freq: %d MHz\n",
1109                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1110
1111                 seq_printf(m, "min GPU freq: %d MHz\n",
1112                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1113
1114                 seq_printf(m, "idle GPU freq: %d MHz\n",
1115                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1116
1117                 seq_printf(m,
1118                            "efficient (RPe) frequency: %d MHz\n",
1119                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1120                 mutex_unlock(&dev_priv->rps.hw_lock);
1121         } else if (INTEL_GEN(dev_priv) >= 6) {
1122                 u32 rp_state_limits;
1123                 u32 gt_perf_status;
1124                 u32 rp_state_cap;
1125                 u32 rpmodectl, rpinclimit, rpdeclimit;
1126                 u32 rpstat, cagf, reqf;
1127                 u32 rpupei, rpcurup, rpprevup;
1128                 u32 rpdownei, rpcurdown, rpprevdown;
1129                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1130                 int max_freq;
1131
1132                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1133                 if (IS_GEN9_LP(dev_priv)) {
1134                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1135                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1136                 } else {
1137                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1138                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1139                 }
1140
1141                 /* RPSTAT1 is in the GT power well */
1142                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1143
1144                 reqf = I915_READ(GEN6_RPNSWREQ);
1145                 if (IS_GEN9(dev_priv))
1146                         reqf >>= 23;
1147                 else {
1148                         reqf &= ~GEN6_TURBO_DISABLE;
1149                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1150                                 reqf >>= 24;
1151                         else
1152                                 reqf >>= 25;
1153                 }
1154                 reqf = intel_gpu_freq(dev_priv, reqf);
1155
1156                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1157                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1158                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1159
1160                 rpstat = I915_READ(GEN6_RPSTAT1);
1161                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1162                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1163                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1164                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1165                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1166                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1167                 if (IS_GEN9(dev_priv))
1168                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1169                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1170                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1171                 else
1172                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1173                 cagf = intel_gpu_freq(dev_priv, cagf);
1174
1175                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1176
1177                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1178                         pm_ier = I915_READ(GEN6_PMIER);
1179                         pm_imr = I915_READ(GEN6_PMIMR);
1180                         pm_isr = I915_READ(GEN6_PMISR);
1181                         pm_iir = I915_READ(GEN6_PMIIR);
1182                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1183                 } else {
1184                         pm_ier = I915_READ(GEN8_GT_IER(2));
1185                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1186                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1187                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1188                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1189                 }
1190                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1191                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1192                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1193                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1194                 seq_printf(m, "Render p-state ratio: %d\n",
1195                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1196                 seq_printf(m, "Render p-state VID: %d\n",
1197                            gt_perf_status & 0xff);
1198                 seq_printf(m, "Render p-state limit: %d\n",
1199                            rp_state_limits & 0xff);
1200                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1201                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1202                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1203                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1204                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1205                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1206                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1207                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1208                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1209                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1210                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1211                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1212                 seq_printf(m, "Up threshold: %d%%\n",
1213                            dev_priv->rps.up_threshold);
1214
1215                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1216                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1217                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1218                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1219                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1220                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1221                 seq_printf(m, "Down threshold: %d%%\n",
1222                            dev_priv->rps.down_threshold);
1223
1224                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1225                             rp_state_cap >> 16) & 0xff;
1226                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1227                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1228                            intel_gpu_freq(dev_priv, max_freq));
1229
1230                 max_freq = (rp_state_cap & 0xff00) >> 8;
1231                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1232                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1233                            intel_gpu_freq(dev_priv, max_freq));
1234
1235                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1236                             rp_state_cap >> 0) & 0xff;
1237                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1238                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1239                            intel_gpu_freq(dev_priv, max_freq));
1240                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1241                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1242
1243                 seq_printf(m, "Current freq: %d MHz\n",
1244                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1245                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1246                 seq_printf(m, "Idle freq: %d MHz\n",
1247                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1248                 seq_printf(m, "Min freq: %d MHz\n",
1249                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1250                 seq_printf(m, "Boost freq: %d MHz\n",
1251                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1252                 seq_printf(m, "Max freq: %d MHz\n",
1253                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1254                 seq_printf(m,
1255                            "efficient (RPe) frequency: %d MHz\n",
1256                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1257         } else {
1258                 seq_puts(m, "no P-state info available\n");
1259         }
1260
1261         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1262         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1263         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1264
1265         intel_runtime_pm_put(dev_priv);
1266         return ret;
1267 }
1268
1269 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1270                                struct seq_file *m,
1271                                struct intel_instdone *instdone)
1272 {
1273         int slice;
1274         int subslice;
1275
1276         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1277                    instdone->instdone);
1278
1279         if (INTEL_GEN(dev_priv) <= 3)
1280                 return;
1281
1282         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1283                    instdone->slice_common);
1284
1285         if (INTEL_GEN(dev_priv) <= 6)
1286                 return;
1287
1288         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1289                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1290                            slice, subslice, instdone->sampler[slice][subslice]);
1291
1292         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1293                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1294                            slice, subslice, instdone->row[slice][subslice]);
1295 }
1296
1297 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298 {
1299         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1300         struct intel_engine_cs *engine;
1301         u64 acthd[I915_NUM_ENGINES];
1302         u32 seqno[I915_NUM_ENGINES];
1303         struct intel_instdone instdone;
1304         enum intel_engine_id id;
1305
1306         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1307                 seq_printf(m, "Wedged\n");
1308         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1309                 seq_printf(m, "Reset in progress\n");
1310         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1311                 seq_printf(m, "Waiter holding struct mutex\n");
1312         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1313                 seq_printf(m, "struct_mutex blocked for reset\n");
1314
1315         if (!i915.enable_hangcheck) {
1316                 seq_printf(m, "Hangcheck disabled\n");
1317                 return 0;
1318         }
1319
1320         intel_runtime_pm_get(dev_priv);
1321
1322         for_each_engine(engine, dev_priv, id) {
1323                 acthd[id] = intel_engine_get_active_head(engine);
1324                 seqno[id] = intel_engine_get_seqno(engine);
1325         }
1326
1327         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1328
1329         intel_runtime_pm_put(dev_priv);
1330
1331         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1332                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1333                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1334                                             jiffies));
1335         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1336                 seq_puts(m, "Hangcheck active, work pending\n");
1337         else
1338                 seq_puts(m, "Hangcheck inactive\n");
1339
1340         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1341
1342         for_each_engine(engine, dev_priv, id) {
1343                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1344                 struct rb_node *rb;
1345
1346                 seq_printf(m, "%s:\n", engine->name);
1347                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1348                            engine->hangcheck.seqno, seqno[id],
1349                            intel_engine_last_submit(engine),
1350                            engine->timeline->inflight_seqnos);
1351                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1352                            yesno(intel_engine_has_waiter(engine)),
1353                            yesno(test_bit(engine->id,
1354                                           &dev_priv->gpu_error.missed_irq_rings)),
1355                            yesno(engine->hangcheck.stalled));
1356
1357                 spin_lock_irq(&b->rb_lock);
1358                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1359                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1360
1361                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1362                                    w->tsk->comm, w->tsk->pid, w->seqno);
1363                 }
1364                 spin_unlock_irq(&b->rb_lock);
1365
1366                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1367                            (long long)engine->hangcheck.acthd,
1368                            (long long)acthd[id]);
1369                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1370                            hangcheck_action_to_str(engine->hangcheck.action),
1371                            engine->hangcheck.action,
1372                            jiffies_to_msecs(jiffies -
1373                                             engine->hangcheck.action_timestamp));
1374
1375                 if (engine->id == RCS) {
1376                         seq_puts(m, "\tinstdone read =\n");
1377
1378                         i915_instdone_info(dev_priv, m, &instdone);
1379
1380                         seq_puts(m, "\tinstdone accu =\n");
1381
1382                         i915_instdone_info(dev_priv, m,
1383                                            &engine->hangcheck.instdone);
1384                 }
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int ironlake_drpc_info(struct seq_file *m)
1391 {
1392         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1393         u32 rgvmodectl, rstdbyctl;
1394         u16 crstandvid;
1395
1396         intel_runtime_pm_get(dev_priv);
1397
1398         rgvmodectl = I915_READ(MEMMODECTL);
1399         rstdbyctl = I915_READ(RSTDBYCTL);
1400         crstandvid = I915_READ16(CRSTANDVID);
1401
1402         intel_runtime_pm_put(dev_priv);
1403
1404         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1405         seq_printf(m, "Boost freq: %d\n",
1406                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1407                    MEMMODE_BOOST_FREQ_SHIFT);
1408         seq_printf(m, "HW control enabled: %s\n",
1409                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1410         seq_printf(m, "SW control enabled: %s\n",
1411                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1412         seq_printf(m, "Gated voltage change: %s\n",
1413                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1414         seq_printf(m, "Starting frequency: P%d\n",
1415                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1416         seq_printf(m, "Max P-state: P%d\n",
1417                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1418         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1419         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1420         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1421         seq_printf(m, "Render standby enabled: %s\n",
1422                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1423         seq_puts(m, "Current RS state: ");
1424         switch (rstdbyctl & RSX_STATUS_MASK) {
1425         case RSX_STATUS_ON:
1426                 seq_puts(m, "on\n");
1427                 break;
1428         case RSX_STATUS_RC1:
1429                 seq_puts(m, "RC1\n");
1430                 break;
1431         case RSX_STATUS_RC1E:
1432                 seq_puts(m, "RC1E\n");
1433                 break;
1434         case RSX_STATUS_RS1:
1435                 seq_puts(m, "RS1\n");
1436                 break;
1437         case RSX_STATUS_RS2:
1438                 seq_puts(m, "RS2 (RC6)\n");
1439                 break;
1440         case RSX_STATUS_RS3:
1441                 seq_puts(m, "RC3 (RC6+)\n");
1442                 break;
1443         default:
1444                 seq_puts(m, "unknown\n");
1445                 break;
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int i915_forcewake_domains(struct seq_file *m, void *data)
1452 {
1453         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1454         struct intel_uncore_forcewake_domain *fw_domain;
1455
1456         spin_lock_irq(&dev_priv->uncore.lock);
1457         for_each_fw_domain(fw_domain, dev_priv) {
1458                 seq_printf(m, "%s.wake_count = %u\n",
1459                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1460                            fw_domain->wake_count);
1461         }
1462         spin_unlock_irq(&dev_priv->uncore.lock);
1463
1464         return 0;
1465 }
1466
1467 static int vlv_drpc_info(struct seq_file *m)
1468 {
1469         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1470         u32 rpmodectl1, rcctl1, pw_status;
1471
1472         intel_runtime_pm_get(dev_priv);
1473
1474         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1475         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1476         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1477
1478         intel_runtime_pm_put(dev_priv);
1479
1480         seq_printf(m, "Video Turbo Mode: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1482         seq_printf(m, "Turbo enabled: %s\n",
1483                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1484         seq_printf(m, "HW control enabled: %s\n",
1485                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1486         seq_printf(m, "SW control enabled: %s\n",
1487                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1488                           GEN6_RP_MEDIA_SW_MODE));
1489         seq_printf(m, "RC6 Enabled: %s\n",
1490                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1491                                         GEN6_RC_CTL_EI_MODE(1))));
1492         seq_printf(m, "Render Power Well: %s\n",
1493                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1494         seq_printf(m, "Media Power Well: %s\n",
1495                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1496
1497         seq_printf(m, "Render RC6 residency since boot: %u\n",
1498                    I915_READ(VLV_GT_RENDER_RC6));
1499         seq_printf(m, "Media RC6 residency since boot: %u\n",
1500                    I915_READ(VLV_GT_MEDIA_RC6));
1501
1502         return i915_forcewake_domains(m, NULL);
1503 }
1504
1505 static int gen6_drpc_info(struct seq_file *m)
1506 {
1507         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1508         struct drm_device *dev = &dev_priv->drm;
1509         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1510         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1511         unsigned forcewake_count;
1512         int count = 0, ret;
1513
1514         ret = mutex_lock_interruptible(&dev->struct_mutex);
1515         if (ret)
1516                 return ret;
1517         intel_runtime_pm_get(dev_priv);
1518
1519         spin_lock_irq(&dev_priv->uncore.lock);
1520         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1521         spin_unlock_irq(&dev_priv->uncore.lock);
1522
1523         if (forcewake_count) {
1524                 seq_puts(m, "RC information inaccurate because somebody "
1525                             "holds a forcewake reference \n");
1526         } else {
1527                 /* NB: we cannot use forcewake, else we read the wrong values */
1528                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1529                         udelay(10);
1530                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1531         }
1532
1533         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1534         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1535
1536         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1537         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1538         if (INTEL_GEN(dev_priv) >= 9) {
1539                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1540                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1541         }
1542         mutex_unlock(&dev->struct_mutex);
1543         mutex_lock(&dev_priv->rps.hw_lock);
1544         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1545         mutex_unlock(&dev_priv->rps.hw_lock);
1546
1547         intel_runtime_pm_put(dev_priv);
1548
1549         seq_printf(m, "Video Turbo Mode: %s\n",
1550                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1551         seq_printf(m, "HW control enabled: %s\n",
1552                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1553         seq_printf(m, "SW control enabled: %s\n",
1554                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1555                           GEN6_RP_MEDIA_SW_MODE));
1556         seq_printf(m, "RC1e Enabled: %s\n",
1557                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1558         seq_printf(m, "RC6 Enabled: %s\n",
1559                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1560         if (INTEL_GEN(dev_priv) >= 9) {
1561                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1562                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1563                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1564                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1565         }
1566         seq_printf(m, "Deep RC6 Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1568         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1570         seq_puts(m, "Current RC state: ");
1571         switch (gt_core_status & GEN6_RCn_MASK) {
1572         case GEN6_RC0:
1573                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1574                         seq_puts(m, "Core Power Down\n");
1575                 else
1576                         seq_puts(m, "on\n");
1577                 break;
1578         case GEN6_RC3:
1579                 seq_puts(m, "RC3\n");
1580                 break;
1581         case GEN6_RC6:
1582                 seq_puts(m, "RC6\n");
1583                 break;
1584         case GEN6_RC7:
1585                 seq_puts(m, "RC7\n");
1586                 break;
1587         default:
1588                 seq_puts(m, "Unknown\n");
1589                 break;
1590         }
1591
1592         seq_printf(m, "Core Power Down: %s\n",
1593                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1594         if (INTEL_GEN(dev_priv) >= 9) {
1595                 seq_printf(m, "Render Power Well: %s\n",
1596                         (gen9_powergate_status &
1597                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1598                 seq_printf(m, "Media Power Well: %s\n",
1599                         (gen9_powergate_status &
1600                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1601         }
1602
1603         /* Not exactly sure what this is */
1604         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1605                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1606         seq_printf(m, "RC6 residency since boot: %u\n",
1607                    I915_READ(GEN6_GT_GFX_RC6));
1608         seq_printf(m, "RC6+ residency since boot: %u\n",
1609                    I915_READ(GEN6_GT_GFX_RC6p));
1610         seq_printf(m, "RC6++ residency since boot: %u\n",
1611                    I915_READ(GEN6_GT_GFX_RC6pp));
1612
1613         seq_printf(m, "RC6   voltage: %dmV\n",
1614                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1615         seq_printf(m, "RC6+  voltage: %dmV\n",
1616                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1617         seq_printf(m, "RC6++ voltage: %dmV\n",
1618                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1619         return i915_forcewake_domains(m, NULL);
1620 }
1621
1622 static int i915_drpc_info(struct seq_file *m, void *unused)
1623 {
1624         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1625
1626         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1627                 return vlv_drpc_info(m);
1628         else if (INTEL_GEN(dev_priv) >= 6)
1629                 return gen6_drpc_info(m);
1630         else
1631                 return ironlake_drpc_info(m);
1632 }
1633
1634 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1635 {
1636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639                    dev_priv->fb_tracking.busy_bits);
1640
1641         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642                    dev_priv->fb_tracking.flip_bits);
1643
1644         return 0;
1645 }
1646
1647 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 {
1649         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1650
1651         if (!HAS_FBC(dev_priv)) {
1652                 seq_puts(m, "FBC unsupported on this chipset\n");
1653                 return 0;
1654         }
1655
1656         intel_runtime_pm_get(dev_priv);
1657         mutex_lock(&dev_priv->fbc.lock);
1658
1659         if (intel_fbc_is_active(dev_priv))
1660                 seq_puts(m, "FBC enabled\n");
1661         else
1662                 seq_printf(m, "FBC disabled: %s\n",
1663                            dev_priv->fbc.no_fbc_reason);
1664
1665         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1666                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1667                                 BDW_FBC_COMPRESSION_MASK :
1668                                 IVB_FBC_COMPRESSION_MASK;
1669                 seq_printf(m, "Compressing: %s\n",
1670                            yesno(I915_READ(FBC_STATUS2) & mask));
1671         }
1672
1673         mutex_unlock(&dev_priv->fbc.lock);
1674         intel_runtime_pm_put(dev_priv);
1675
1676         return 0;
1677 }
1678
1679 static int i915_fbc_fc_get(void *data, u64 *val)
1680 {
1681         struct drm_i915_private *dev_priv = data;
1682
1683         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1684                 return -ENODEV;
1685
1686         *val = dev_priv->fbc.false_color;
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_set(void *data, u64 val)
1692 {
1693         struct drm_i915_private *dev_priv = data;
1694         u32 reg;
1695
1696         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1697                 return -ENODEV;
1698
1699         mutex_lock(&dev_priv->fbc.lock);
1700
1701         reg = I915_READ(ILK_DPFC_CONTROL);
1702         dev_priv->fbc.false_color = val;
1703
1704         I915_WRITE(ILK_DPFC_CONTROL, val ?
1705                    (reg | FBC_CTL_FALSE_COLOR) :
1706                    (reg & ~FBC_CTL_FALSE_COLOR));
1707
1708         mutex_unlock(&dev_priv->fbc.lock);
1709         return 0;
1710 }
1711
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713                         i915_fbc_fc_get, i915_fbc_fc_set,
1714                         "%llu\n");
1715
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1717 {
1718         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1719
1720         if (!HAS_IPS(dev_priv)) {
1721                 seq_puts(m, "not supported\n");
1722                 return 0;
1723         }
1724
1725         intel_runtime_pm_get(dev_priv);
1726
1727         seq_printf(m, "Enabled by kernel parameter: %s\n",
1728                    yesno(i915.enable_ips));
1729
1730         if (INTEL_GEN(dev_priv) >= 8) {
1731                 seq_puts(m, "Currently: unknown\n");
1732         } else {
1733                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1734                         seq_puts(m, "Currently: enabled\n");
1735                 else
1736                         seq_puts(m, "Currently: disabled\n");
1737         }
1738
1739         intel_runtime_pm_put(dev_priv);
1740
1741         return 0;
1742 }
1743
1744 static int i915_sr_status(struct seq_file *m, void *unused)
1745 {
1746         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1747         bool sr_enabled = false;
1748
1749         intel_runtime_pm_get(dev_priv);
1750         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1751
1752         if (INTEL_GEN(dev_priv) >= 9)
1753                 /* no global SR status; inspect per-plane WM */;
1754         else if (HAS_PCH_SPLIT(dev_priv))
1755                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1756         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1757                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1758                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1759         else if (IS_I915GM(dev_priv))
1760                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1761         else if (IS_PINEVIEW(dev_priv))
1762                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1763         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1764                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1765
1766         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1767         intel_runtime_pm_put(dev_priv);
1768
1769         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1770
1771         return 0;
1772 }
1773
1774 static int i915_emon_status(struct seq_file *m, void *unused)
1775 {
1776         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1777         struct drm_device *dev = &dev_priv->drm;
1778         unsigned long temp, chipset, gfx;
1779         int ret;
1780
1781         if (!IS_GEN5(dev_priv))
1782                 return -ENODEV;
1783
1784         ret = mutex_lock_interruptible(&dev->struct_mutex);
1785         if (ret)
1786                 return ret;
1787
1788         temp = i915_mch_val(dev_priv);
1789         chipset = i915_chipset_val(dev_priv);
1790         gfx = i915_gfx_val(dev_priv);
1791         mutex_unlock(&dev->struct_mutex);
1792
1793         seq_printf(m, "GMCH temp: %ld\n", temp);
1794         seq_printf(m, "Chipset power: %ld\n", chipset);
1795         seq_printf(m, "GFX power: %ld\n", gfx);
1796         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1797
1798         return 0;
1799 }
1800
1801 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1802 {
1803         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1804         int ret = 0;
1805         int gpu_freq, ia_freq;
1806         unsigned int max_gpu_freq, min_gpu_freq;
1807
1808         if (!HAS_LLC(dev_priv)) {
1809                 seq_puts(m, "unsupported on this chipset\n");
1810                 return 0;
1811         }
1812
1813         intel_runtime_pm_get(dev_priv);
1814
1815         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1816         if (ret)
1817                 goto out;
1818
1819         if (IS_GEN9_BC(dev_priv)) {
1820                 /* Convert GT frequency to 50 HZ units */
1821                 min_gpu_freq =
1822                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1823                 max_gpu_freq =
1824                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1825         } else {
1826                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1827                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1828         }
1829
1830         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1831
1832         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1833                 ia_freq = gpu_freq;
1834                 sandybridge_pcode_read(dev_priv,
1835                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1836                                        &ia_freq);
1837                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1838                            intel_gpu_freq(dev_priv, (gpu_freq *
1839                                                      (IS_GEN9_BC(dev_priv) ?
1840                                                       GEN9_FREQ_SCALER : 1))),
1841                            ((ia_freq >> 0) & 0xff) * 100,
1842                            ((ia_freq >> 8) & 0xff) * 100);
1843         }
1844
1845         mutex_unlock(&dev_priv->rps.hw_lock);
1846
1847 out:
1848         intel_runtime_pm_put(dev_priv);
1849         return ret;
1850 }
1851
1852 static int i915_opregion(struct seq_file *m, void *unused)
1853 {
1854         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1855         struct drm_device *dev = &dev_priv->drm;
1856         struct intel_opregion *opregion = &dev_priv->opregion;
1857         int ret;
1858
1859         ret = mutex_lock_interruptible(&dev->struct_mutex);
1860         if (ret)
1861                 goto out;
1862
1863         if (opregion->header)
1864                 seq_write(m, opregion->header, OPREGION_SIZE);
1865
1866         mutex_unlock(&dev->struct_mutex);
1867
1868 out:
1869         return 0;
1870 }
1871
1872 static int i915_vbt(struct seq_file *m, void *unused)
1873 {
1874         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1875
1876         if (opregion->vbt)
1877                 seq_write(m, opregion->vbt, opregion->vbt_size);
1878
1879         return 0;
1880 }
1881
1882 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1883 {
1884         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1885         struct drm_device *dev = &dev_priv->drm;
1886         struct intel_framebuffer *fbdev_fb = NULL;
1887         struct drm_framebuffer *drm_fb;
1888         int ret;
1889
1890         ret = mutex_lock_interruptible(&dev->struct_mutex);
1891         if (ret)
1892                 return ret;
1893
1894 #ifdef CONFIG_DRM_FBDEV_EMULATION
1895         if (dev_priv->fbdev) {
1896                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1897
1898                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1899                            fbdev_fb->base.width,
1900                            fbdev_fb->base.height,
1901                            fbdev_fb->base.format->depth,
1902                            fbdev_fb->base.format->cpp[0] * 8,
1903                            fbdev_fb->base.modifier,
1904                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1905                 describe_obj(m, fbdev_fb->obj);
1906                 seq_putc(m, '\n');
1907         }
1908 #endif
1909
1910         mutex_lock(&dev->mode_config.fb_lock);
1911         drm_for_each_fb(drm_fb, dev) {
1912                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1913                 if (fb == fbdev_fb)
1914                         continue;
1915
1916                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1917                            fb->base.width,
1918                            fb->base.height,
1919                            fb->base.format->depth,
1920                            fb->base.format->cpp[0] * 8,
1921                            fb->base.modifier,
1922                            drm_framebuffer_read_refcount(&fb->base));
1923                 describe_obj(m, fb->obj);
1924                 seq_putc(m, '\n');
1925         }
1926         mutex_unlock(&dev->mode_config.fb_lock);
1927         mutex_unlock(&dev->struct_mutex);
1928
1929         return 0;
1930 }
1931
1932 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1933 {
1934         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1935                    ring->space, ring->head, ring->tail,
1936                    ring->last_retired_head);
1937 }
1938
1939 static int i915_context_status(struct seq_file *m, void *unused)
1940 {
1941         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1942         struct drm_device *dev = &dev_priv->drm;
1943         struct intel_engine_cs *engine;
1944         struct i915_gem_context *ctx;
1945         enum intel_engine_id id;
1946         int ret;
1947
1948         ret = mutex_lock_interruptible(&dev->struct_mutex);
1949         if (ret)
1950                 return ret;
1951
1952         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1953                 seq_printf(m, "HW context %u ", ctx->hw_id);
1954                 if (ctx->pid) {
1955                         struct task_struct *task;
1956
1957                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1958                         if (task) {
1959                                 seq_printf(m, "(%s [%d]) ",
1960                                            task->comm, task->pid);
1961                                 put_task_struct(task);
1962                         }
1963                 } else if (IS_ERR(ctx->file_priv)) {
1964                         seq_puts(m, "(deleted) ");
1965                 } else {
1966                         seq_puts(m, "(kernel) ");
1967                 }
1968
1969                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1970                 seq_putc(m, '\n');
1971
1972                 for_each_engine(engine, dev_priv, id) {
1973                         struct intel_context *ce = &ctx->engine[engine->id];
1974
1975                         seq_printf(m, "%s: ", engine->name);
1976                         seq_putc(m, ce->initialised ? 'I' : 'i');
1977                         if (ce->state)
1978                                 describe_obj(m, ce->state->obj);
1979                         if (ce->ring)
1980                                 describe_ctx_ring(m, ce->ring);
1981                         seq_putc(m, '\n');
1982                 }
1983
1984                 seq_putc(m, '\n');
1985         }
1986
1987         mutex_unlock(&dev->struct_mutex);
1988
1989         return 0;
1990 }
1991
1992 static void i915_dump_lrc_obj(struct seq_file *m,
1993                               struct i915_gem_context *ctx,
1994                               struct intel_engine_cs *engine)
1995 {
1996         struct i915_vma *vma = ctx->engine[engine->id].state;
1997         struct page *page;
1998         int j;
1999
2000         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2001
2002         if (!vma) {
2003                 seq_puts(m, "\tFake context\n");
2004                 return;
2005         }
2006
2007         if (vma->flags & I915_VMA_GLOBAL_BIND)
2008                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2009                            i915_ggtt_offset(vma));
2010
2011         if (i915_gem_object_pin_pages(vma->obj)) {
2012                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2013                 return;
2014         }
2015
2016         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2017         if (page) {
2018                 u32 *reg_state = kmap_atomic(page);
2019
2020                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2021                         seq_printf(m,
2022                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2023                                    j * 4,
2024                                    reg_state[j], reg_state[j + 1],
2025                                    reg_state[j + 2], reg_state[j + 3]);
2026                 }
2027                 kunmap_atomic(reg_state);
2028         }
2029
2030         i915_gem_object_unpin_pages(vma->obj);
2031         seq_putc(m, '\n');
2032 }
2033
2034 static int i915_dump_lrc(struct seq_file *m, void *unused)
2035 {
2036         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2037         struct drm_device *dev = &dev_priv->drm;
2038         struct intel_engine_cs *engine;
2039         struct i915_gem_context *ctx;
2040         enum intel_engine_id id;
2041         int ret;
2042
2043         if (!i915.enable_execlists) {
2044                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2045                 return 0;
2046         }
2047
2048         ret = mutex_lock_interruptible(&dev->struct_mutex);
2049         if (ret)
2050                 return ret;
2051
2052         list_for_each_entry(ctx, &dev_priv->context_list, link)
2053                 for_each_engine(engine, dev_priv, id)
2054                         i915_dump_lrc_obj(m, ctx, engine);
2055
2056         mutex_unlock(&dev->struct_mutex);
2057
2058         return 0;
2059 }
2060
2061 static const char *swizzle_string(unsigned swizzle)
2062 {
2063         switch (swizzle) {
2064         case I915_BIT_6_SWIZZLE_NONE:
2065                 return "none";
2066         case I915_BIT_6_SWIZZLE_9:
2067                 return "bit9";
2068         case I915_BIT_6_SWIZZLE_9_10:
2069                 return "bit9/bit10";
2070         case I915_BIT_6_SWIZZLE_9_11:
2071                 return "bit9/bit11";
2072         case I915_BIT_6_SWIZZLE_9_10_11:
2073                 return "bit9/bit10/bit11";
2074         case I915_BIT_6_SWIZZLE_9_17:
2075                 return "bit9/bit17";
2076         case I915_BIT_6_SWIZZLE_9_10_17:
2077                 return "bit9/bit10/bit17";
2078         case I915_BIT_6_SWIZZLE_UNKNOWN:
2079                 return "unknown";
2080         }
2081
2082         return "bug";
2083 }
2084
2085 static int i915_swizzle_info(struct seq_file *m, void *data)
2086 {
2087         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2088
2089         intel_runtime_pm_get(dev_priv);
2090
2091         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2092                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2093         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2094                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2095
2096         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2097                 seq_printf(m, "DDC = 0x%08x\n",
2098                            I915_READ(DCC));
2099                 seq_printf(m, "DDC2 = 0x%08x\n",
2100                            I915_READ(DCC2));
2101                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2102                            I915_READ16(C0DRB3));
2103                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2104                            I915_READ16(C1DRB3));
2105         } else if (INTEL_GEN(dev_priv) >= 6) {
2106                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2107                            I915_READ(MAD_DIMM_C0));
2108                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2109                            I915_READ(MAD_DIMM_C1));
2110                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2111                            I915_READ(MAD_DIMM_C2));
2112                 seq_printf(m, "TILECTL = 0x%08x\n",
2113                            I915_READ(TILECTL));
2114                 if (INTEL_GEN(dev_priv) >= 8)
2115                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2116                                    I915_READ(GAMTARBMODE));
2117                 else
2118                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2119                                    I915_READ(ARB_MODE));
2120                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2121                            I915_READ(DISP_ARB_CTL));
2122         }
2123
2124         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2125                 seq_puts(m, "L-shaped memory detected\n");
2126
2127         intel_runtime_pm_put(dev_priv);
2128
2129         return 0;
2130 }
2131
2132 static int per_file_ctx(int id, void *ptr, void *data)
2133 {
2134         struct i915_gem_context *ctx = ptr;
2135         struct seq_file *m = data;
2136         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2137
2138         if (!ppgtt) {
2139                 seq_printf(m, "  no ppgtt for context %d\n",
2140                            ctx->user_handle);
2141                 return 0;
2142         }
2143
2144         if (i915_gem_context_is_default(ctx))
2145                 seq_puts(m, "  default context:\n");
2146         else
2147                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2148         ppgtt->debug_dump(ppgtt, m);
2149
2150         return 0;
2151 }
2152
2153 static void gen8_ppgtt_info(struct seq_file *m,
2154                             struct drm_i915_private *dev_priv)
2155 {
2156         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2157         struct intel_engine_cs *engine;
2158         enum intel_engine_id id;
2159         int i;
2160
2161         if (!ppgtt)
2162                 return;
2163
2164         for_each_engine(engine, dev_priv, id) {
2165                 seq_printf(m, "%s\n", engine->name);
2166                 for (i = 0; i < 4; i++) {
2167                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2168                         pdp <<= 32;
2169                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2170                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2171                 }
2172         }
2173 }
2174
2175 static void gen6_ppgtt_info(struct seq_file *m,
2176                             struct drm_i915_private *dev_priv)
2177 {
2178         struct intel_engine_cs *engine;
2179         enum intel_engine_id id;
2180
2181         if (IS_GEN6(dev_priv))
2182                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2183
2184         for_each_engine(engine, dev_priv, id) {
2185                 seq_printf(m, "%s\n", engine->name);
2186                 if (IS_GEN7(dev_priv))
2187                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2188                                    I915_READ(RING_MODE_GEN7(engine)));
2189                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2190                            I915_READ(RING_PP_DIR_BASE(engine)));
2191                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2192                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2193                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2194                            I915_READ(RING_PP_DIR_DCLV(engine)));
2195         }
2196         if (dev_priv->mm.aliasing_ppgtt) {
2197                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2198
2199                 seq_puts(m, "aliasing PPGTT:\n");
2200                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2201
2202                 ppgtt->debug_dump(ppgtt, m);
2203         }
2204
2205         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2206 }
2207
2208 static int i915_ppgtt_info(struct seq_file *m, void *data)
2209 {
2210         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2211         struct drm_device *dev = &dev_priv->drm;
2212         struct drm_file *file;
2213         int ret;
2214
2215         mutex_lock(&dev->filelist_mutex);
2216         ret = mutex_lock_interruptible(&dev->struct_mutex);
2217         if (ret)
2218                 goto out_unlock;
2219
2220         intel_runtime_pm_get(dev_priv);
2221
2222         if (INTEL_GEN(dev_priv) >= 8)
2223                 gen8_ppgtt_info(m, dev_priv);
2224         else if (INTEL_GEN(dev_priv) >= 6)
2225                 gen6_ppgtt_info(m, dev_priv);
2226
2227         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2228                 struct drm_i915_file_private *file_priv = file->driver_priv;
2229                 struct task_struct *task;
2230
2231                 task = get_pid_task(file->pid, PIDTYPE_PID);
2232                 if (!task) {
2233                         ret = -ESRCH;
2234                         goto out_rpm;
2235                 }
2236                 seq_printf(m, "\nproc: %s\n", task->comm);
2237                 put_task_struct(task);
2238                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2239                              (void *)(unsigned long)m);
2240         }
2241
2242 out_rpm:
2243         intel_runtime_pm_put(dev_priv);
2244         mutex_unlock(&dev->struct_mutex);
2245 out_unlock:
2246         mutex_unlock(&dev->filelist_mutex);
2247         return ret;
2248 }
2249
2250 static int count_irq_waiters(struct drm_i915_private *i915)
2251 {
2252         struct intel_engine_cs *engine;
2253         enum intel_engine_id id;
2254         int count = 0;
2255
2256         for_each_engine(engine, i915, id)
2257                 count += intel_engine_has_waiter(engine);
2258
2259         return count;
2260 }
2261
2262 static const char *rps_power_to_str(unsigned int power)
2263 {
2264         static const char * const strings[] = {
2265                 [LOW_POWER] = "low power",
2266                 [BETWEEN] = "mixed",
2267                 [HIGH_POWER] = "high power",
2268         };
2269
2270         if (power >= ARRAY_SIZE(strings) || !strings[power])
2271                 return "unknown";
2272
2273         return strings[power];
2274 }
2275
2276 static int i915_rps_boost_info(struct seq_file *m, void *data)
2277 {
2278         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2279         struct drm_device *dev = &dev_priv->drm;
2280         struct drm_file *file;
2281
2282         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2283         seq_printf(m, "GPU busy? %s [%d requests]\n",
2284                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2285         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2286         seq_printf(m, "Frequency requested %d\n",
2287                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2288         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2289                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2290                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2291                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2292                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2293         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2295                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2296                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2297
2298         mutex_lock(&dev->filelist_mutex);
2299         spin_lock(&dev_priv->rps.client_lock);
2300         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2301                 struct drm_i915_file_private *file_priv = file->driver_priv;
2302                 struct task_struct *task;
2303
2304                 rcu_read_lock();
2305                 task = pid_task(file->pid, PIDTYPE_PID);
2306                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2307                            task ? task->comm : "<unknown>",
2308                            task ? task->pid : -1,
2309                            file_priv->rps.boosts,
2310                            list_empty(&file_priv->rps.link) ? "" : ", active");
2311                 rcu_read_unlock();
2312         }
2313         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2314         spin_unlock(&dev_priv->rps.client_lock);
2315         mutex_unlock(&dev->filelist_mutex);
2316
2317         if (INTEL_GEN(dev_priv) >= 6 &&
2318             dev_priv->rps.enabled &&
2319             dev_priv->gt.active_requests) {
2320                 u32 rpup, rpupei;
2321                 u32 rpdown, rpdownei;
2322
2323                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2324                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2325                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2326                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2327                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2328                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2329
2330                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2331                            rps_power_to_str(dev_priv->rps.power));
2332                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2333                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2334                            dev_priv->rps.up_threshold);
2335                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2336                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2337                            dev_priv->rps.down_threshold);
2338         } else {
2339                 seq_puts(m, "\nRPS Autotuning inactive\n");
2340         }
2341
2342         return 0;
2343 }
2344
2345 static int i915_llc(struct seq_file *m, void *data)
2346 {
2347         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2348         const bool edram = INTEL_GEN(dev_priv) > 8;
2349
2350         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2351         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2352                    intel_uncore_edram_size(dev_priv)/1024/1024);
2353
2354         return 0;
2355 }
2356
2357 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2358 {
2359         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2360         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2361
2362         if (!HAS_HUC_UCODE(dev_priv))
2363                 return 0;
2364
2365         seq_puts(m, "HuC firmware status:\n");
2366         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2367         seq_printf(m, "\tfetch: %s\n",
2368                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2369         seq_printf(m, "\tload: %s\n",
2370                 intel_uc_fw_status_repr(huc_fw->load_status));
2371         seq_printf(m, "\tversion wanted: %d.%d\n",
2372                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2373         seq_printf(m, "\tversion found: %d.%d\n",
2374                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2375         seq_printf(m, "\theader: offset is %d; size = %d\n",
2376                 huc_fw->header_offset, huc_fw->header_size);
2377         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2378                 huc_fw->ucode_offset, huc_fw->ucode_size);
2379         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2380                 huc_fw->rsa_offset, huc_fw->rsa_size);
2381
2382         intel_runtime_pm_get(dev_priv);
2383         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2384         intel_runtime_pm_put(dev_priv);
2385
2386         return 0;
2387 }
2388
2389 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2390 {
2391         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2392         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2393         u32 tmp, i;
2394
2395         if (!HAS_GUC_UCODE(dev_priv))
2396                 return 0;
2397
2398         seq_printf(m, "GuC firmware status:\n");
2399         seq_printf(m, "\tpath: %s\n",
2400                 guc_fw->path);
2401         seq_printf(m, "\tfetch: %s\n",
2402                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2403         seq_printf(m, "\tload: %s\n",
2404                 intel_uc_fw_status_repr(guc_fw->load_status));
2405         seq_printf(m, "\tversion wanted: %d.%d\n",
2406                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2407         seq_printf(m, "\tversion found: %d.%d\n",
2408                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2409         seq_printf(m, "\theader: offset is %d; size = %d\n",
2410                 guc_fw->header_offset, guc_fw->header_size);
2411         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2412                 guc_fw->ucode_offset, guc_fw->ucode_size);
2413         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2414                 guc_fw->rsa_offset, guc_fw->rsa_size);
2415
2416         intel_runtime_pm_get(dev_priv);
2417
2418         tmp = I915_READ(GUC_STATUS);
2419
2420         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2421         seq_printf(m, "\tBootrom status = 0x%x\n",
2422                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2423         seq_printf(m, "\tuKernel status = 0x%x\n",
2424                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2425         seq_printf(m, "\tMIA Core status = 0x%x\n",
2426                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2427         seq_puts(m, "\nScratch registers:\n");
2428         for (i = 0; i < 16; i++)
2429                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2430
2431         intel_runtime_pm_put(dev_priv);
2432
2433         return 0;
2434 }
2435
2436 static void i915_guc_log_info(struct seq_file *m,
2437                               struct drm_i915_private *dev_priv)
2438 {
2439         struct intel_guc *guc = &dev_priv->guc;
2440
2441         seq_puts(m, "\nGuC logging stats:\n");
2442
2443         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2444                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2445                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2446
2447         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2448                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2449                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2450
2451         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2452                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2453                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2454
2455         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2456                    guc->log.flush_interrupt_count);
2457
2458         seq_printf(m, "\tCapture miss count: %u\n",
2459                    guc->log.capture_miss_count);
2460 }
2461
2462 static void i915_guc_client_info(struct seq_file *m,
2463                                  struct drm_i915_private *dev_priv,
2464                                  struct i915_guc_client *client)
2465 {
2466         struct intel_engine_cs *engine;
2467         enum intel_engine_id id;
2468         uint64_t tot = 0;
2469
2470         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2471                 client->priority, client->ctx_index, client->proc_desc_offset);
2472         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2473                 client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
2474         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2475                 client->wq_size, client->wq_offset, client->wq_tail);
2476
2477         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2478         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2479         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2480
2481         for_each_engine(engine, dev_priv, id) {
2482                 u64 submissions = client->submissions[id];
2483                 tot += submissions;
2484                 seq_printf(m, "\tSubmissions: %llu %s\n",
2485                                 submissions, engine->name);
2486         }
2487         seq_printf(m, "\tTotal: %llu\n", tot);
2488 }
2489
2490 static int i915_guc_info(struct seq_file *m, void *data)
2491 {
2492         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2493         const struct intel_guc *guc = &dev_priv->guc;
2494         struct intel_engine_cs *engine;
2495         enum intel_engine_id id;
2496         u64 total;
2497
2498         if (!guc->execbuf_client) {
2499                 seq_printf(m, "GuC submission %s\n",
2500                            HAS_GUC_SCHED(dev_priv) ?
2501                            "disabled" :
2502                            "not supported");
2503                 return 0;
2504         }
2505
2506         seq_printf(m, "Doorbell map:\n");
2507         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap);
2508         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2509
2510         seq_printf(m, "GuC total action count: %llu\n", guc->action_count);
2511         seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);
2512         seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);
2513         seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);
2514         seq_printf(m, "GuC last action error code: %d\n", guc->action_err);
2515
2516         total = 0;
2517         seq_printf(m, "\nGuC submissions:\n");
2518         for_each_engine(engine, dev_priv, id) {
2519                 u64 submissions = guc->submissions[id];
2520                 total += submissions;
2521                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2522                         engine->name, submissions, guc->last_seqno[id]);
2523         }
2524         seq_printf(m, "\t%s: %llu\n", "Total", total);
2525
2526         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2527         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2528
2529         i915_guc_log_info(m, dev_priv);
2530
2531         /* Add more as required ... */
2532
2533         return 0;
2534 }
2535
2536 static int i915_guc_log_dump(struct seq_file *m, void *data)
2537 {
2538         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2539         struct drm_i915_gem_object *obj;
2540         int i = 0, pg;
2541
2542         if (!dev_priv->guc.log.vma)
2543                 return 0;
2544
2545         obj = dev_priv->guc.log.vma->obj;
2546         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2547                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2548
2549                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2550                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2551                                    *(log + i), *(log + i + 1),
2552                                    *(log + i + 2), *(log + i + 3));
2553
2554                 kunmap_atomic(log);
2555         }
2556
2557         seq_putc(m, '\n');
2558
2559         return 0;
2560 }
2561
2562 static int i915_guc_log_control_get(void *data, u64 *val)
2563 {
2564         struct drm_device *dev = data;
2565         struct drm_i915_private *dev_priv = to_i915(dev);
2566
2567         if (!dev_priv->guc.log.vma)
2568                 return -EINVAL;
2569
2570         *val = i915.guc_log_level;
2571
2572         return 0;
2573 }
2574
2575 static int i915_guc_log_control_set(void *data, u64 val)
2576 {
2577         struct drm_device *dev = data;
2578         struct drm_i915_private *dev_priv = to_i915(dev);
2579         int ret;
2580
2581         if (!dev_priv->guc.log.vma)
2582                 return -EINVAL;
2583
2584         ret = mutex_lock_interruptible(&dev->struct_mutex);
2585         if (ret)
2586                 return ret;
2587
2588         intel_runtime_pm_get(dev_priv);
2589         ret = i915_guc_log_control(dev_priv, val);
2590         intel_runtime_pm_put(dev_priv);
2591
2592         mutex_unlock(&dev->struct_mutex);
2593         return ret;
2594 }
2595
2596 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2597                         i915_guc_log_control_get, i915_guc_log_control_set,
2598                         "%lld\n");
2599
2600 static const char *psr2_live_status(u32 val)
2601 {
2602         static const char * const live_status[] = {
2603                 "IDLE",
2604                 "CAPTURE",
2605                 "CAPTURE_FS",
2606                 "SLEEP",
2607                 "BUFON_FW",
2608                 "ML_UP",
2609                 "SU_STANDBY",
2610                 "FAST_SLEEP",
2611                 "DEEP_SLEEP",
2612                 "BUF_ON",
2613                 "TG_ON"
2614         };
2615
2616         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2617         if (val < ARRAY_SIZE(live_status))
2618                 return live_status[val];
2619
2620         return "unknown";
2621 }
2622
2623 static int i915_edp_psr_status(struct seq_file *m, void *data)
2624 {
2625         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2626         u32 psrperf = 0;
2627         u32 stat[3];
2628         enum pipe pipe;
2629         bool enabled = false;
2630
2631         if (!HAS_PSR(dev_priv)) {
2632                 seq_puts(m, "PSR not supported\n");
2633                 return 0;
2634         }
2635
2636         intel_runtime_pm_get(dev_priv);
2637
2638         mutex_lock(&dev_priv->psr.lock);
2639         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2640         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2641         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2642         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2643         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2644                    dev_priv->psr.busy_frontbuffer_bits);
2645         seq_printf(m, "Re-enable work scheduled: %s\n",
2646                    yesno(work_busy(&dev_priv->psr.work.work)));
2647
2648         if (HAS_DDI(dev_priv)) {
2649                 if (dev_priv->psr.psr2_support)
2650                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2651                 else
2652                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2653         } else {
2654                 for_each_pipe(dev_priv, pipe) {
2655                         enum transcoder cpu_transcoder =
2656                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2657                         enum intel_display_power_domain power_domain;
2658
2659                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2660                         if (!intel_display_power_get_if_enabled(dev_priv,
2661                                                                 power_domain))
2662                                 continue;
2663
2664                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2665                                 VLV_EDP_PSR_CURR_STATE_MASK;
2666                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2667                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2668                                 enabled = true;
2669
2670                         intel_display_power_put(dev_priv, power_domain);
2671                 }
2672         }
2673
2674         seq_printf(m, "Main link in standby mode: %s\n",
2675                    yesno(dev_priv->psr.link_standby));
2676
2677         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2678
2679         if (!HAS_DDI(dev_priv))
2680                 for_each_pipe(dev_priv, pipe) {
2681                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2682                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2683                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2684                 }
2685         seq_puts(m, "\n");
2686
2687         /*
2688          * VLV/CHV PSR has no kind of performance counter
2689          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2690          */
2691         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2692                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2693                         EDP_PSR_PERF_CNT_MASK;
2694
2695                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2696         }
2697         if (dev_priv->psr.psr2_support) {
2698                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2699
2700                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2701                            psr2, psr2_live_status(psr2));
2702         }
2703         mutex_unlock(&dev_priv->psr.lock);
2704
2705         intel_runtime_pm_put(dev_priv);
2706         return 0;
2707 }
2708
2709 static int i915_sink_crc(struct seq_file *m, void *data)
2710 {
2711         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2712         struct drm_device *dev = &dev_priv->drm;
2713         struct intel_connector *connector;
2714         struct drm_connector_list_iter conn_iter;
2715         struct intel_dp *intel_dp = NULL;
2716         int ret;
2717         u8 crc[6];
2718
2719         drm_modeset_lock_all(dev);
2720         drm_connector_list_iter_begin(dev, &conn_iter);
2721         for_each_intel_connector_iter(connector, &conn_iter) {
2722                 struct drm_crtc *crtc;
2723
2724                 if (!connector->base.state->best_encoder)
2725                         continue;
2726
2727                 crtc = connector->base.state->crtc;
2728                 if (!crtc->state->active)
2729                         continue;
2730
2731                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2732                         continue;
2733
2734                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2735
2736                 ret = intel_dp_sink_crc(intel_dp, crc);
2737                 if (ret)
2738                         goto out;
2739
2740                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2741                            crc[0], crc[1], crc[2],
2742                            crc[3], crc[4], crc[5]);
2743                 goto out;
2744         }
2745         ret = -ENODEV;
2746 out:
2747         drm_connector_list_iter_end(&conn_iter);
2748         drm_modeset_unlock_all(dev);
2749         return ret;
2750 }
2751
2752 static int i915_energy_uJ(struct seq_file *m, void *data)
2753 {
2754         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2755         u64 power;
2756         u32 units;
2757
2758         if (INTEL_GEN(dev_priv) < 6)
2759                 return -ENODEV;
2760
2761         intel_runtime_pm_get(dev_priv);
2762
2763         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2764         power = (power & 0x1f00) >> 8;
2765         units = 1000000 / (1 << power); /* convert to uJ */
2766         power = I915_READ(MCH_SECP_NRG_STTS);
2767         power *= units;
2768
2769         intel_runtime_pm_put(dev_priv);
2770
2771         seq_printf(m, "%llu", (long long unsigned)power);
2772
2773         return 0;
2774 }
2775
2776 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2777 {
2778         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2779         struct pci_dev *pdev = dev_priv->drm.pdev;
2780
2781         if (!HAS_RUNTIME_PM(dev_priv))
2782                 seq_puts(m, "Runtime power management not supported\n");
2783
2784         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2785         seq_printf(m, "IRQs disabled: %s\n",
2786                    yesno(!intel_irqs_enabled(dev_priv)));
2787 #ifdef CONFIG_PM
2788         seq_printf(m, "Usage count: %d\n",
2789                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2790 #else
2791         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2792 #endif
2793         seq_printf(m, "PCI device power state: %s [%d]\n",
2794                    pci_power_name(pdev->current_state),
2795                    pdev->current_state);
2796
2797         return 0;
2798 }
2799
2800 static int i915_power_domain_info(struct seq_file *m, void *unused)
2801 {
2802         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2803         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2804         int i;
2805
2806         mutex_lock(&power_domains->lock);
2807
2808         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2809         for (i = 0; i < power_domains->power_well_count; i++) {
2810                 struct i915_power_well *power_well;
2811                 enum intel_display_power_domain power_domain;
2812
2813                 power_well = &power_domains->power_wells[i];
2814                 seq_printf(m, "%-25s %d\n", power_well->name,
2815                            power_well->count);
2816
2817                 for_each_power_domain(power_domain, power_well->domains)
2818                         seq_printf(m, "  %-23s %d\n",
2819                                  intel_display_power_domain_str(power_domain),
2820                                  power_domains->domain_use_count[power_domain]);
2821         }
2822
2823         mutex_unlock(&power_domains->lock);
2824
2825         return 0;
2826 }
2827
2828 static int i915_dmc_info(struct seq_file *m, void *unused)
2829 {
2830         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2831         struct intel_csr *csr;
2832
2833         if (!HAS_CSR(dev_priv)) {
2834                 seq_puts(m, "not supported\n");
2835                 return 0;
2836         }
2837
2838         csr = &dev_priv->csr;
2839
2840         intel_runtime_pm_get(dev_priv);
2841
2842         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2843         seq_printf(m, "path: %s\n", csr->fw_path);
2844
2845         if (!csr->dmc_payload)
2846                 goto out;
2847
2848         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2849                    CSR_VERSION_MINOR(csr->version));
2850
2851         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2852                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2853                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2854                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2855                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2856         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2857                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2858                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2859         }
2860
2861 out:
2862         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2863         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2864         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2865
2866         intel_runtime_pm_put(dev_priv);
2867
2868         return 0;
2869 }
2870
2871 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2872                                  struct drm_display_mode *mode)
2873 {
2874         int i;
2875
2876         for (i = 0; i < tabs; i++)
2877                 seq_putc(m, '\t');
2878
2879         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2880                    mode->base.id, mode->name,
2881                    mode->vrefresh, mode->clock,
2882                    mode->hdisplay, mode->hsync_start,
2883                    mode->hsync_end, mode->htotal,
2884                    mode->vdisplay, mode->vsync_start,
2885                    mode->vsync_end, mode->vtotal,
2886                    mode->type, mode->flags);
2887 }
2888
2889 static void intel_encoder_info(struct seq_file *m,
2890                                struct intel_crtc *intel_crtc,
2891                                struct intel_encoder *intel_encoder)
2892 {
2893         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2894         struct drm_device *dev = &dev_priv->drm;
2895         struct drm_crtc *crtc = &intel_crtc->base;
2896         struct intel_connector *intel_connector;
2897         struct drm_encoder *encoder;
2898
2899         encoder = &intel_encoder->base;
2900         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2901                    encoder->base.id, encoder->name);
2902         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2903                 struct drm_connector *connector = &intel_connector->base;
2904                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2905                            connector->base.id,
2906                            connector->name,
2907                            drm_get_connector_status_name(connector->status));
2908                 if (connector->status == connector_status_connected) {
2909                         struct drm_display_mode *mode = &crtc->mode;
2910                         seq_printf(m, ", mode:\n");
2911                         intel_seq_print_mode(m, 2, mode);
2912                 } else {
2913                         seq_putc(m, '\n');
2914                 }
2915         }
2916 }
2917
2918 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2919 {
2920         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2921         struct drm_device *dev = &dev_priv->drm;
2922         struct drm_crtc *crtc = &intel_crtc->base;
2923         struct intel_encoder *intel_encoder;
2924         struct drm_plane_state *plane_state = crtc->primary->state;
2925         struct drm_framebuffer *fb = plane_state->fb;
2926
2927         if (fb)
2928                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2929                            fb->base.id, plane_state->src_x >> 16,
2930                            plane_state->src_y >> 16, fb->width, fb->height);
2931         else
2932                 seq_puts(m, "\tprimary plane disabled\n");
2933         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2934                 intel_encoder_info(m, intel_crtc, intel_encoder);
2935 }
2936
2937 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2938 {
2939         struct drm_display_mode *mode = panel->fixed_mode;
2940
2941         seq_printf(m, "\tfixed mode:\n");
2942         intel_seq_print_mode(m, 2, mode);
2943 }
2944
2945 static void intel_dp_info(struct seq_file *m,
2946                           struct intel_connector *intel_connector)
2947 {
2948         struct intel_encoder *intel_encoder = intel_connector->encoder;
2949         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2950
2951         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2952         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2953         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2954                 intel_panel_info(m, &intel_connector->panel);
2955
2956         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2957                                 &intel_dp->aux);
2958 }
2959
2960 static void intel_dp_mst_info(struct seq_file *m,
2961                           struct intel_connector *intel_connector)
2962 {
2963         struct intel_encoder *intel_encoder = intel_connector->encoder;
2964         struct intel_dp_mst_encoder *intel_mst =
2965                 enc_to_mst(&intel_encoder->base);
2966         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2967         struct intel_dp *intel_dp = &intel_dig_port->dp;
2968         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2969                                         intel_connector->port);
2970
2971         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2972 }
2973
2974 static void intel_hdmi_info(struct seq_file *m,
2975                             struct intel_connector *intel_connector)
2976 {
2977         struct intel_encoder *intel_encoder = intel_connector->encoder;
2978         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2979
2980         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2981 }
2982
2983 static void intel_lvds_info(struct seq_file *m,
2984                             struct intel_connector *intel_connector)
2985 {
2986         intel_panel_info(m, &intel_connector->panel);
2987 }
2988
2989 static void intel_connector_info(struct seq_file *m,
2990                                  struct drm_connector *connector)
2991 {
2992         struct intel_connector *intel_connector = to_intel_connector(connector);
2993         struct intel_encoder *intel_encoder = intel_connector->encoder;
2994         struct drm_display_mode *mode;
2995
2996         seq_printf(m, "connector %d: type %s, status: %s\n",
2997                    connector->base.id, connector->name,
2998                    drm_get_connector_status_name(connector->status));
2999         if (connector->status == connector_status_connected) {
3000                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3001                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3002                            connector->display_info.width_mm,
3003                            connector->display_info.height_mm);
3004                 seq_printf(m, "\tsubpixel order: %s\n",
3005                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3006                 seq_printf(m, "\tCEA rev: %d\n",
3007                            connector->display_info.cea_rev);
3008         }
3009
3010         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3011                 return;
3012
3013         switch (connector->connector_type) {
3014         case DRM_MODE_CONNECTOR_DisplayPort:
3015         case DRM_MODE_CONNECTOR_eDP:
3016                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3017                         intel_dp_mst_info(m, intel_connector);
3018                 else
3019                         intel_dp_info(m, intel_connector);
3020                 break;
3021         case DRM_MODE_CONNECTOR_LVDS:
3022                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3023                         intel_lvds_info(m, intel_connector);
3024                 break;
3025         case DRM_MODE_CONNECTOR_HDMIA:
3026                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3027                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3028                         intel_hdmi_info(m, intel_connector);
3029                 break;
3030         default:
3031                 break;
3032         }
3033
3034         seq_printf(m, "\tmodes:\n");
3035         list_for_each_entry(mode, &connector->modes, head)
3036                 intel_seq_print_mode(m, 2, mode);
3037 }
3038
3039 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
3040 {
3041         u32 state;
3042
3043         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
3044                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3045         else
3046                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3047
3048         return state;
3049 }
3050
3051 static bool cursor_position(struct drm_i915_private *dev_priv,
3052                             int pipe, int *x, int *y)
3053 {
3054         u32 pos;
3055
3056         pos = I915_READ(CURPOS(pipe));
3057
3058         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3059         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3060                 *x = -*x;
3061
3062         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3063         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3064                 *y = -*y;
3065
3066         return cursor_active(dev_priv, pipe);
3067 }
3068
3069 static const char *plane_type(enum drm_plane_type type)
3070 {
3071         switch (type) {
3072         case DRM_PLANE_TYPE_OVERLAY:
3073                 return "OVL";
3074         case DRM_PLANE_TYPE_PRIMARY:
3075                 return "PRI";
3076         case DRM_PLANE_TYPE_CURSOR:
3077                 return "CUR";
3078         /*
3079          * Deliberately omitting default: to generate compiler warnings
3080          * when a new drm_plane_type gets added.
3081          */
3082         }
3083
3084         return "unknown";
3085 }
3086
3087 static const char *plane_rotation(unsigned int rotation)
3088 {
3089         static char buf[48];
3090         /*
3091          * According to doc only one DRM_ROTATE_ is allowed but this
3092          * will print them all to visualize if the values are misused
3093          */
3094         snprintf(buf, sizeof(buf),
3095                  "%s%s%s%s%s%s(0x%08x)",
3096                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3097                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3098                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3099                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3100                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3101                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3102                  rotation);
3103
3104         return buf;
3105 }
3106
3107 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3108 {
3109         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3110         struct drm_device *dev = &dev_priv->drm;
3111         struct intel_plane *intel_plane;
3112
3113         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3114                 struct drm_plane_state *state;
3115                 struct drm_plane *plane = &intel_plane->base;
3116                 struct drm_format_name_buf format_name;
3117
3118                 if (!plane->state) {
3119                         seq_puts(m, "plane->state is NULL!\n");
3120                         continue;
3121                 }
3122
3123                 state = plane->state;
3124
3125                 if (state->fb) {
3126                         drm_get_format_name(state->fb->format->format,
3127                                             &format_name);
3128                 } else {
3129                         sprintf(format_name.str, "N/A");
3130                 }
3131
3132                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3133                            plane->base.id,
3134                            plane_type(intel_plane->base.type),
3135                            state->crtc_x, state->crtc_y,
3136                            state->crtc_w, state->crtc_h,
3137                            (state->src_x >> 16),
3138                            ((state->src_x & 0xffff) * 15625) >> 10,
3139                            (state->src_y >> 16),
3140                            ((state->src_y & 0xffff) * 15625) >> 10,
3141                            (state->src_w >> 16),
3142                            ((state->src_w & 0xffff) * 15625) >> 10,
3143                            (state->src_h >> 16),
3144                            ((state->src_h & 0xffff) * 15625) >> 10,
3145                            format_name.str,
3146                            plane_rotation(state->rotation));
3147         }
3148 }
3149
3150 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3151 {
3152         struct intel_crtc_state *pipe_config;
3153         int num_scalers = intel_crtc->num_scalers;
3154         int i;
3155
3156         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3157
3158         /* Not all platformas have a scaler */
3159         if (num_scalers) {
3160                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3161                            num_scalers,
3162                            pipe_config->scaler_state.scaler_users,
3163                            pipe_config->scaler_state.scaler_id);
3164
3165                 for (i = 0; i < num_scalers; i++) {
3166                         struct intel_scaler *sc =
3167                                         &pipe_config->scaler_state.scalers[i];
3168
3169                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3170                                    i, yesno(sc->in_use), sc->mode);
3171                 }
3172                 seq_puts(m, "\n");
3173         } else {
3174                 seq_puts(m, "\tNo scalers available on this platform\n");
3175         }
3176 }
3177
3178 static int i915_display_info(struct seq_file *m, void *unused)
3179 {
3180         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3181         struct drm_device *dev = &dev_priv->drm;
3182         struct intel_crtc *crtc;
3183         struct drm_connector *connector;
3184         struct drm_connector_list_iter conn_iter;
3185
3186         intel_runtime_pm_get(dev_priv);
3187         seq_printf(m, "CRTC info\n");
3188         seq_printf(m, "---------\n");
3189         for_each_intel_crtc(dev, crtc) {
3190                 bool active;
3191                 struct intel_crtc_state *pipe_config;
3192                 int x, y;
3193
3194                 drm_modeset_lock(&crtc->base.mutex, NULL);
3195                 pipe_config = to_intel_crtc_state(crtc->base.state);
3196
3197                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3198                            crtc->base.base.id, pipe_name(crtc->pipe),
3199                            yesno(pipe_config->base.active),
3200                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3201                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3202
3203                 if (pipe_config->base.active) {
3204                         intel_crtc_info(m, crtc);
3205
3206                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3207                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3208                                    yesno(crtc->cursor_base),
3209                                    x, y, crtc->base.cursor->state->crtc_w,
3210                                    crtc->base.cursor->state->crtc_h,
3211                                    crtc->cursor_addr, yesno(active));
3212                         intel_scaler_info(m, crtc);
3213                         intel_plane_info(m, crtc);
3214                 }
3215
3216                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3217                            yesno(!crtc->cpu_fifo_underrun_disabled),
3218                            yesno(!crtc->pch_fifo_underrun_disabled));
3219                 drm_modeset_unlock(&crtc->base.mutex);
3220         }
3221
3222         seq_printf(m, "\n");
3223         seq_printf(m, "Connector info\n");
3224         seq_printf(m, "--------------\n");
3225         mutex_lock(&dev->mode_config.mutex);
3226         drm_connector_list_iter_begin(dev, &conn_iter);
3227         drm_for_each_connector_iter(connector, &conn_iter)
3228                 intel_connector_info(m, connector);
3229         drm_connector_list_iter_end(&conn_iter);
3230         mutex_unlock(&dev->mode_config.mutex);
3231
3232         intel_runtime_pm_put(dev_priv);
3233
3234         return 0;
3235 }
3236
3237 static int i915_engine_info(struct seq_file *m, void *unused)
3238 {
3239         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3240         struct intel_engine_cs *engine;
3241         enum intel_engine_id id;
3242
3243         intel_runtime_pm_get(dev_priv);
3244
3245         seq_printf(m, "GT awake? %s\n",
3246                    yesno(dev_priv->gt.awake));
3247         seq_printf(m, "Global active requests: %d\n",
3248                    dev_priv->gt.active_requests);
3249
3250         for_each_engine(engine, dev_priv, id) {
3251                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3252                 struct drm_i915_gem_request *rq;
3253                 struct rb_node *rb;
3254                 u64 addr;
3255
3256                 seq_printf(m, "%s\n", engine->name);
3257                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
3258                            intel_engine_get_seqno(engine),
3259                            intel_engine_last_submit(engine),
3260                            engine->hangcheck.seqno,
3261                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
3262                            engine->timeline->inflight_seqnos);
3263
3264                 rcu_read_lock();
3265
3266                 seq_printf(m, "\tRequests:\n");
3267
3268                 rq = list_first_entry(&engine->timeline->requests,
3269                                       struct drm_i915_gem_request, link);
3270                 if (&rq->link != &engine->timeline->requests)
3271                         print_request(m, rq, "\t\tfirst  ");
3272
3273                 rq = list_last_entry(&engine->timeline->requests,
3274                                      struct drm_i915_gem_request, link);
3275                 if (&rq->link != &engine->timeline->requests)
3276                         print_request(m, rq, "\t\tlast   ");
3277
3278                 rq = i915_gem_find_active_request(engine);
3279                 if (rq) {
3280                         print_request(m, rq, "\t\tactive ");
3281                         seq_printf(m,
3282                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3283                                    rq->head, rq->postfix, rq->tail,
3284                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3285                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3286                 }
3287
3288                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3289                            I915_READ(RING_START(engine->mmio_base)),
3290                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3291                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3292                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3293                            rq ? rq->ring->head : 0);
3294                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3295                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3296                            rq ? rq->ring->tail : 0);
3297                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3298                            I915_READ(RING_CTL(engine->mmio_base)),
3299                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3300
3301                 rcu_read_unlock();
3302
3303                 addr = intel_engine_get_active_head(engine);
3304                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3305                            upper_32_bits(addr), lower_32_bits(addr));
3306                 addr = intel_engine_get_last_batch_head(engine);
3307                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3308                            upper_32_bits(addr), lower_32_bits(addr));
3309
3310                 if (i915.enable_execlists) {
3311                         u32 ptr, read, write;
3312                         struct rb_node *rb;
3313
3314                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3315                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3316                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3317
3318                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3319                         read = GEN8_CSB_READ_PTR(ptr);
3320                         write = GEN8_CSB_WRITE_PTR(ptr);
3321                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3322                                    read, write);
3323                         if (read >= GEN8_CSB_ENTRIES)
3324                                 read = 0;
3325                         if (write >= GEN8_CSB_ENTRIES)
3326                                 write = 0;
3327                         if (read > write)
3328                                 write += GEN8_CSB_ENTRIES;
3329                         while (read < write) {
3330                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3331
3332                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3333                                            idx,
3334                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3335                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3336                         }
3337
3338                         rcu_read_lock();
3339                         rq = READ_ONCE(engine->execlist_port[0].request);
3340                         if (rq) {
3341                                 seq_printf(m, "\t\tELSP[0] count=%d, ",
3342                                            engine->execlist_port[0].count);
3343                                 print_request(m, rq, "rq: ");
3344                         } else {
3345                                 seq_printf(m, "\t\tELSP[0] idle\n");
3346                         }
3347                         rq = READ_ONCE(engine->execlist_port[1].request);
3348                         if (rq) {
3349                                 seq_printf(m, "\t\tELSP[1] count=%d, ",
3350                                            engine->execlist_port[1].count);
3351                                 print_request(m, rq, "rq: ");
3352                         } else {
3353                                 seq_printf(m, "\t\tELSP[1] idle\n");
3354                         }
3355                         rcu_read_unlock();
3356
3357                         spin_lock_irq(&engine->timeline->lock);
3358                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3359                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3360                                 print_request(m, rq, "\t\tQ ");
3361                         }
3362                         spin_unlock_irq(&engine->timeline->lock);
3363                 } else if (INTEL_GEN(dev_priv) > 6) {
3364                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3365                                    I915_READ(RING_PP_DIR_BASE(engine)));
3366                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3367                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3368                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3369                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3370                 }
3371
3372                 spin_lock_irq(&b->rb_lock);
3373                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3374                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
3375
3376                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3377                                    w->tsk->comm, w->tsk->pid, w->seqno);
3378                 }
3379                 spin_unlock_irq(&b->rb_lock);
3380
3381                 seq_puts(m, "\n");
3382         }
3383
3384         intel_runtime_pm_put(dev_priv);
3385
3386         return 0;
3387 }
3388
3389 static int i915_semaphore_status(struct seq_file *m, void *unused)
3390 {
3391         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3392         struct drm_device *dev = &dev_priv->drm;
3393         struct intel_engine_cs *engine;
3394         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3395         enum intel_engine_id id;
3396         int j, ret;
3397
3398         if (!i915.semaphores) {
3399                 seq_puts(m, "Semaphores are disabled\n");
3400                 return 0;
3401         }
3402
3403         ret = mutex_lock_interruptible(&dev->struct_mutex);
3404         if (ret)
3405                 return ret;
3406         intel_runtime_pm_get(dev_priv);
3407
3408         if (IS_BROADWELL(dev_priv)) {
3409                 struct page *page;
3410                 uint64_t *seqno;
3411
3412                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3413
3414                 seqno = (uint64_t *)kmap_atomic(page);
3415                 for_each_engine(engine, dev_priv, id) {
3416                         uint64_t offset;
3417
3418                         seq_printf(m, "%s\n", engine->name);
3419
3420                         seq_puts(m, "  Last signal:");
3421                         for (j = 0; j < num_rings; j++) {
3422                                 offset = id * I915_NUM_ENGINES + j;
3423                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3424                                            seqno[offset], offset * 8);
3425                         }
3426                         seq_putc(m, '\n');
3427
3428                         seq_puts(m, "  Last wait:  ");
3429                         for (j = 0; j < num_rings; j++) {
3430                                 offset = id + (j * I915_NUM_ENGINES);
3431                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3432                                            seqno[offset], offset * 8);
3433                         }
3434                         seq_putc(m, '\n');
3435
3436                 }
3437                 kunmap_atomic(seqno);
3438         } else {
3439                 seq_puts(m, "  Last signal:");
3440                 for_each_engine(engine, dev_priv, id)
3441                         for (j = 0; j < num_rings; j++)
3442                                 seq_printf(m, "0x%08x\n",
3443                                            I915_READ(engine->semaphore.mbox.signal[j]));
3444                 seq_putc(m, '\n');
3445         }
3446
3447         intel_runtime_pm_put(dev_priv);
3448         mutex_unlock(&dev->struct_mutex);
3449         return 0;
3450 }
3451
3452 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3453 {
3454         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3455         struct drm_device *dev = &dev_priv->drm;
3456         int i;
3457
3458         drm_modeset_lock_all(dev);
3459         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3460                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3461
3462                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3463                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3464                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3465                 seq_printf(m, " tracked hardware state:\n");
3466                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3467                 seq_printf(m, " dpll_md: 0x%08x\n",
3468                            pll->state.hw_state.dpll_md);
3469                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3470                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3471                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3472         }
3473         drm_modeset_unlock_all(dev);
3474
3475         return 0;
3476 }
3477
3478 static int i915_wa_registers(struct seq_file *m, void *unused)
3479 {
3480         int i;
3481         int ret;
3482         struct intel_engine_cs *engine;
3483         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3484         struct drm_device *dev = &dev_priv->drm;
3485         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3486         enum intel_engine_id id;
3487
3488         ret = mutex_lock_interruptible(&dev->struct_mutex);
3489         if (ret)
3490                 return ret;
3491
3492         intel_runtime_pm_get(dev_priv);
3493
3494         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3495         for_each_engine(engine, dev_priv, id)
3496                 seq_printf(m, "HW whitelist count for %s: %d\n",
3497                            engine->name, workarounds->hw_whitelist_count[id]);
3498         for (i = 0; i < workarounds->count; ++i) {
3499                 i915_reg_t addr;
3500                 u32 mask, value, read;
3501                 bool ok;
3502
3503                 addr = workarounds->reg[i].addr;
3504                 mask = workarounds->reg[i].mask;
3505                 value = workarounds->reg[i].value;
3506                 read = I915_READ(addr);
3507                 ok = (value & mask) == (read & mask);
3508                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3509                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3510         }
3511
3512         intel_runtime_pm_put(dev_priv);
3513         mutex_unlock(&dev->struct_mutex);
3514
3515         return 0;
3516 }
3517
3518 static int i915_ddb_info(struct seq_file *m, void *unused)
3519 {
3520         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3521         struct drm_device *dev = &dev_priv->drm;
3522         struct skl_ddb_allocation *ddb;
3523         struct skl_ddb_entry *entry;
3524         enum pipe pipe;
3525         int plane;
3526
3527         if (INTEL_GEN(dev_priv) < 9)
3528                 return 0;
3529
3530         drm_modeset_lock_all(dev);
3531
3532         ddb = &dev_priv->wm.skl_hw.ddb;
3533
3534         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3535
3536         for_each_pipe(dev_priv, pipe) {
3537                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3538
3539                 for_each_universal_plane(dev_priv, pipe, plane) {
3540                         entry = &ddb->plane[pipe][plane];
3541                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3542                                    entry->start, entry->end,
3543                                    skl_ddb_entry_size(entry));
3544                 }
3545
3546                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3547                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3548                            entry->end, skl_ddb_entry_size(entry));
3549         }
3550
3551         drm_modeset_unlock_all(dev);
3552
3553         return 0;
3554 }
3555
3556 static void drrs_status_per_crtc(struct seq_file *m,
3557                                  struct drm_device *dev,
3558                                  struct intel_crtc *intel_crtc)
3559 {
3560         struct drm_i915_private *dev_priv = to_i915(dev);
3561         struct i915_drrs *drrs = &dev_priv->drrs;
3562         int vrefresh = 0;
3563         struct drm_connector *connector;
3564         struct drm_connector_list_iter conn_iter;
3565
3566         drm_connector_list_iter_begin(dev, &conn_iter);
3567         drm_for_each_connector_iter(connector, &conn_iter) {
3568                 if (connector->state->crtc != &intel_crtc->base)
3569                         continue;
3570
3571                 seq_printf(m, "%s:\n", connector->name);
3572         }
3573         drm_connector_list_iter_end(&conn_iter);
3574
3575         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3576                 seq_puts(m, "\tVBT: DRRS_type: Static");
3577         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3578                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3579         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3580                 seq_puts(m, "\tVBT: DRRS_type: None");
3581         else
3582                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3583
3584         seq_puts(m, "\n\n");
3585
3586         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3587                 struct intel_panel *panel;
3588
3589                 mutex_lock(&drrs->mutex);
3590                 /* DRRS Supported */
3591                 seq_puts(m, "\tDRRS Supported: Yes\n");
3592
3593                 /* disable_drrs() will make drrs->dp NULL */
3594                 if (!drrs->dp) {
3595                         seq_puts(m, "Idleness DRRS: Disabled");
3596                         mutex_unlock(&drrs->mutex);
3597                         return;
3598                 }
3599
3600                 panel = &drrs->dp->attached_connector->panel;
3601                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3602                                         drrs->busy_frontbuffer_bits);
3603
3604                 seq_puts(m, "\n\t\t");
3605                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3606                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3607                         vrefresh = panel->fixed_mode->vrefresh;
3608                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3609                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3610                         vrefresh = panel->downclock_mode->vrefresh;
3611                 } else {
3612                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3613                                                 drrs->refresh_rate_type);
3614                         mutex_unlock(&drrs->mutex);
3615                         return;
3616                 }
3617                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3618
3619                 seq_puts(m, "\n\t\t");
3620                 mutex_unlock(&drrs->mutex);
3621         } else {
3622                 /* DRRS not supported. Print the VBT parameter*/
3623                 seq_puts(m, "\tDRRS Supported : No");
3624         }
3625         seq_puts(m, "\n");
3626 }
3627
3628 static int i915_drrs_status(struct seq_file *m, void *unused)
3629 {
3630         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3631         struct drm_device *dev = &dev_priv->drm;
3632         struct intel_crtc *intel_crtc;
3633         int active_crtc_cnt = 0;
3634
3635         drm_modeset_lock_all(dev);
3636         for_each_intel_crtc(dev, intel_crtc) {
3637                 if (intel_crtc->base.state->active) {
3638                         active_crtc_cnt++;
3639                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3640
3641                         drrs_status_per_crtc(m, dev, intel_crtc);
3642                 }
3643         }
3644         drm_modeset_unlock_all(dev);
3645
3646         if (!active_crtc_cnt)
3647                 seq_puts(m, "No active crtc found\n");
3648
3649         return 0;
3650 }
3651
3652 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3653 {
3654         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3655         struct drm_device *dev = &dev_priv->drm;
3656         struct intel_encoder *intel_encoder;
3657         struct intel_digital_port *intel_dig_port;
3658         struct drm_connector *connector;
3659         struct drm_connector_list_iter conn_iter;
3660
3661         drm_connector_list_iter_begin(dev, &conn_iter);
3662         drm_for_each_connector_iter(connector, &conn_iter) {
3663                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3664                         continue;
3665
3666                 intel_encoder = intel_attached_encoder(connector);
3667                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3668                         continue;
3669
3670                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3671                 if (!intel_dig_port->dp.can_mst)
3672                         continue;
3673
3674                 seq_printf(m, "MST Source Port %c\n",
3675                            port_name(intel_dig_port->port));
3676                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3677         }
3678         drm_connector_list_iter_end(&conn_iter);
3679
3680         return 0;
3681 }
3682
3683 static ssize_t i915_displayport_test_active_write(struct file *file,
3684                                                   const char __user *ubuf,
3685                                                   size_t len, loff_t *offp)
3686 {
3687         char *input_buffer;
3688         int status = 0;
3689         struct drm_device *dev;
3690         struct drm_connector *connector;
3691         struct drm_connector_list_iter conn_iter;
3692         struct intel_dp *intel_dp;
3693         int val = 0;
3694
3695         dev = ((struct seq_file *)file->private_data)->private;
3696
3697         if (len == 0)
3698                 return 0;
3699
3700         input_buffer = kmalloc(len + 1, GFP_KERNEL);
3701         if (!input_buffer)
3702                 return -ENOMEM;
3703
3704         if (copy_from_user(input_buffer, ubuf, len)) {
3705                 status = -EFAULT;
3706                 goto out;
3707         }
3708
3709         input_buffer[len] = '\0';
3710         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3711
3712         drm_connector_list_iter_begin(dev, &conn_iter);
3713         drm_for_each_connector_iter(connector, &conn_iter) {
3714                 if (connector->connector_type !=
3715                     DRM_MODE_CONNECTOR_DisplayPort)
3716                         continue;
3717
3718                 if (connector->status == connector_status_connected &&
3719                     connector->encoder != NULL) {
3720                         intel_dp = enc_to_intel_dp(connector->encoder);
3721                         status = kstrtoint(input_buffer, 10, &val);
3722                         if (status < 0)
3723                                 break;
3724                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3725                         /* To prevent erroneous activation of the compliance
3726                          * testing code, only accept an actual value of 1 here
3727                          */
3728                         if (val == 1)
3729                                 intel_dp->compliance.test_active = 1;
3730                         else
3731                                 intel_dp->compliance.test_active = 0;
3732                 }
3733         }
3734         drm_connector_list_iter_end(&conn_iter);
3735 out:
3736         kfree(input_buffer);
3737         if (status < 0)
3738                 return status;
3739
3740         *offp += len;
3741         return len;
3742 }
3743
3744 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3745 {
3746         struct drm_device *dev = m->private;
3747         struct drm_connector *connector;
3748         struct drm_connector_list_iter conn_iter;
3749         struct intel_dp *intel_dp;
3750
3751         drm_connector_list_iter_begin(dev, &conn_iter);
3752         drm_for_each_connector_iter(connector, &conn_iter) {
3753                 if (connector->connector_type !=
3754                     DRM_MODE_CONNECTOR_DisplayPort)
3755                         continue;
3756
3757                 if (connector->status == connector_status_connected &&
3758                     connector->encoder != NULL) {
3759                         intel_dp = enc_to_intel_dp(connector->encoder);
3760                         if (intel_dp->compliance.test_active)
3761                                 seq_puts(m, "1");
3762                         else
3763                                 seq_puts(m, "0");
3764                 } else
3765                         seq_puts(m, "0");
3766         }
3767         drm_connector_list_iter_end(&conn_iter);
3768
3769         return 0;
3770 }
3771
3772 static int i915_displayport_test_active_open(struct inode *inode,
3773                                              struct file *file)
3774 {
3775         struct drm_i915_private *dev_priv = inode->i_private;
3776
3777         return single_open(file, i915_displayport_test_active_show,
3778                            &dev_priv->drm);
3779 }
3780
3781 static const struct file_operations i915_displayport_test_active_fops = {
3782         .owner = THIS_MODULE,
3783         .open = i915_displayport_test_active_open,
3784         .read = seq_read,
3785         .llseek = seq_lseek,
3786         .release = single_release,
3787         .write = i915_displayport_test_active_write
3788 };
3789
3790 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3791 {
3792         struct drm_device *dev = m->private;
3793         struct drm_connector *connector;
3794         struct drm_connector_list_iter conn_iter;
3795         struct intel_dp *intel_dp;
3796
3797         drm_connector_list_iter_begin(dev, &conn_iter);
3798         drm_for_each_connector_iter(connector, &conn_iter) {
3799                 if (connector->connector_type !=
3800                     DRM_MODE_CONNECTOR_DisplayPort)
3801                         continue;
3802
3803                 if (connector->status == connector_status_connected &&
3804                     connector->encoder != NULL) {
3805                         intel_dp = enc_to_intel_dp(connector->encoder);
3806                         if (intel_dp->compliance.test_type ==
3807                             DP_TEST_LINK_EDID_READ)
3808                                 seq_printf(m, "%lx",
3809                                            intel_dp->compliance.test_data.edid);
3810                         else if (intel_dp->compliance.test_type ==
3811                                  DP_TEST_LINK_VIDEO_PATTERN) {
3812                                 seq_printf(m, "hdisplay: %d\n",
3813                                            intel_dp->compliance.test_data.hdisplay);
3814                                 seq_printf(m, "vdisplay: %d\n",
3815                                            intel_dp->compliance.test_data.vdisplay);
3816                                 seq_printf(m, "bpc: %u\n",
3817                                            intel_dp->compliance.test_data.bpc);
3818                         }
3819                 } else
3820                         seq_puts(m, "0");
3821         }
3822         drm_connector_list_iter_end(&conn_iter);
3823
3824         return 0;
3825 }
3826 static int i915_displayport_test_data_open(struct inode *inode,
3827                                            struct file *file)
3828 {
3829         struct drm_i915_private *dev_priv = inode->i_private;
3830
3831         return single_open(file, i915_displayport_test_data_show,
3832                            &dev_priv->drm);
3833 }
3834
3835 static const struct file_operations i915_displayport_test_data_fops = {
3836         .owner = THIS_MODULE,
3837         .open = i915_displayport_test_data_open,
3838         .read = seq_read,
3839         .llseek = seq_lseek,
3840         .release = single_release
3841 };
3842
3843 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3844 {
3845         struct drm_device *dev = m->private;
3846         struct drm_connector *connector;
3847         struct drm_connector_list_iter conn_iter;
3848         struct intel_dp *intel_dp;
3849
3850         drm_connector_list_iter_begin(dev, &conn_iter);
3851         drm_for_each_connector_iter(connector, &conn_iter) {
3852                 if (connector->connector_type !=
3853                     DRM_MODE_CONNECTOR_DisplayPort)
3854                         continue;
3855
3856                 if (connector->status == connector_status_connected &&
3857                     connector->encoder != NULL) {
3858                         intel_dp = enc_to_intel_dp(connector->encoder);
3859                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3860                 } else
3861                         seq_puts(m, "0");
3862         }
3863         drm_connector_list_iter_end(&conn_iter);
3864
3865         return 0;
3866 }
3867
3868 static int i915_displayport_test_type_open(struct inode *inode,
3869                                        struct file *file)
3870 {
3871         struct drm_i915_private *dev_priv = inode->i_private;
3872
3873         return single_open(file, i915_displayport_test_type_show,
3874                            &dev_priv->drm);
3875 }
3876
3877 static const struct file_operations i915_displayport_test_type_fops = {
3878         .owner = THIS_MODULE,
3879         .open = i915_displayport_test_type_open,
3880         .read = seq_read,
3881         .llseek = seq_lseek,
3882         .release = single_release
3883 };
3884
3885 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3886 {
3887         struct drm_i915_private *dev_priv = m->private;
3888         struct drm_device *dev = &dev_priv->drm;
3889         int level;
3890         int num_levels;
3891
3892         if (IS_CHERRYVIEW(dev_priv))
3893                 num_levels = 3;
3894         else if (IS_VALLEYVIEW(dev_priv))
3895                 num_levels = 1;
3896         else
3897                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3898
3899         drm_modeset_lock_all(dev);
3900
3901         for (level = 0; level < num_levels; level++) {
3902                 unsigned int latency = wm[level];
3903
3904                 /*
3905                  * - WM1+ latency values in 0.5us units
3906                  * - latencies are in us on gen9/vlv/chv
3907                  */
3908                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
3909                     IS_CHERRYVIEW(dev_priv))
3910                         latency *= 10;
3911                 else if (level > 0)
3912                         latency *= 5;
3913
3914                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3915                            level, wm[level], latency / 10, latency % 10);
3916         }
3917
3918         drm_modeset_unlock_all(dev);
3919 }
3920
3921 static int pri_wm_latency_show(struct seq_file *m, void *data)
3922 {
3923         struct drm_i915_private *dev_priv = m->private;
3924         const uint16_t *latencies;
3925
3926         if (INTEL_GEN(dev_priv) >= 9)
3927                 latencies = dev_priv->wm.skl_latency;
3928         else
3929                 latencies = dev_priv->wm.pri_latency;
3930
3931         wm_latency_show(m, latencies);
3932
3933         return 0;
3934 }
3935
3936 static int spr_wm_latency_show(struct seq_file *m, void *data)
3937 {
3938         struct drm_i915_private *dev_priv = m->private;
3939         const uint16_t *latencies;
3940
3941         if (INTEL_GEN(dev_priv) >= 9)
3942                 latencies = dev_priv->wm.skl_latency;
3943         else
3944                 latencies = dev_priv->wm.spr_latency;
3945
3946         wm_latency_show(m, latencies);
3947
3948         return 0;
3949 }
3950
3951 static int cur_wm_latency_show(struct seq_file *m, void *data)
3952 {
3953         struct drm_i915_private *dev_priv = m->private;
3954         const uint16_t *latencies;
3955
3956         if (INTEL_GEN(dev_priv) >= 9)
3957                 latencies = dev_priv->wm.skl_latency;
3958         else
3959                 latencies = dev_priv->wm.cur_latency;
3960
3961         wm_latency_show(m, latencies);
3962
3963         return 0;
3964 }
3965
3966 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3967 {
3968         struct drm_i915_private *dev_priv = inode->i_private;
3969
3970         if (INTEL_GEN(dev_priv) < 5)
3971                 return -ENODEV;
3972
3973         return single_open(file, pri_wm_latency_show, dev_priv);
3974 }
3975
3976 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3977 {
3978         struct drm_i915_private *dev_priv = inode->i_private;
3979
3980         if (HAS_GMCH_DISPLAY(dev_priv))
3981                 return -ENODEV;
3982
3983         return single_open(file, spr_wm_latency_show, dev_priv);
3984 }
3985
3986 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3987 {
3988         struct drm_i915_private *dev_priv = inode->i_private;
3989
3990         if (HAS_GMCH_DISPLAY(dev_priv))
3991                 return -ENODEV;
3992
3993         return single_open(file, cur_wm_latency_show, dev_priv);
3994 }
3995
3996 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3997                                 size_t len, loff_t *offp, uint16_t wm[8])
3998 {
3999         struct seq_file *m = file->private_data;
4000         struct drm_i915_private *dev_priv = m->private;
4001         struct drm_device *dev = &dev_priv->drm;
4002         uint16_t new[8] = { 0 };
4003         int num_levels;
4004         int level;
4005         int ret;
4006         char tmp[32];
4007
4008         if (IS_CHERRYVIEW(dev_priv))
4009                 num_levels = 3;
4010         else if (IS_VALLEYVIEW(dev_priv))
4011                 num_levels = 1;
4012         else
4013                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4014
4015         if (len >= sizeof(tmp))
4016                 return -EINVAL;
4017
4018         if (copy_from_user(tmp, ubuf, len))
4019                 return -EFAULT;
4020
4021         tmp[len] = '\0';
4022
4023         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4024                      &new[0], &new[1], &new[2], &new[3],
4025                      &new[4], &new[5], &new[6], &new[7]);
4026         if (ret != num_levels)
4027                 return -EINVAL;
4028
4029         drm_modeset_lock_all(dev);
4030
4031         for (level = 0; level < num_levels; level++)
4032                 wm[level] = new[level];
4033
4034         drm_modeset_unlock_all(dev);
4035
4036         return len;
4037 }
4038
4039
4040 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4041                                     size_t len, loff_t *offp)
4042 {
4043         struct seq_file *m = file->private_data;
4044         struct drm_i915_private *dev_priv = m->private;
4045         uint16_t *latencies;
4046
4047         if (INTEL_GEN(dev_priv) >= 9)
4048                 latencies = dev_priv->wm.skl_latency;
4049         else
4050                 latencies = dev_priv->wm.pri_latency;
4051
4052         return wm_latency_write(file, ubuf, len, offp, latencies);
4053 }
4054
4055 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4056                                     size_t len, loff_t *offp)
4057 {
4058         struct seq_file *m = file->private_data;
4059         struct drm_i915_private *dev_priv = m->private;
4060         uint16_t *latencies;
4061
4062         if (INTEL_GEN(dev_priv) >= 9)
4063                 latencies = dev_priv->wm.skl_latency;
4064         else
4065                 latencies = dev_priv->wm.spr_latency;
4066
4067         return wm_latency_write(file, ubuf, len, offp, latencies);
4068 }
4069
4070 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4071                                     size_t len, loff_t *offp)
4072 {
4073         struct seq_file *m = file->private_data;
4074         struct drm_i915_private *dev_priv = m->private;
4075         uint16_t *latencies;
4076
4077         if (INTEL_GEN(dev_priv) >= 9)
4078                 latencies = dev_priv->wm.skl_latency;
4079         else
4080                 latencies = dev_priv->wm.cur_latency;
4081
4082         return wm_latency_write(file, ubuf, len, offp, latencies);
4083 }
4084
4085 static const struct file_operations i915_pri_wm_latency_fops = {
4086         .owner = THIS_MODULE,
4087         .open = pri_wm_latency_open,
4088         .read = seq_read,
4089         .llseek = seq_lseek,
4090         .release = single_release,
4091         .write = pri_wm_latency_write
4092 };
4093
4094 static const struct file_operations i915_spr_wm_latency_fops = {
4095         .owner = THIS_MODULE,
4096         .open = spr_wm_latency_open,
4097         .read = seq_read,
4098         .llseek = seq_lseek,
4099         .release = single_release,
4100         .write = spr_wm_latency_write
4101 };
4102
4103 static const struct file_operations i915_cur_wm_latency_fops = {
4104         .owner = THIS_MODULE,
4105         .open = cur_wm_latency_open,
4106         .read = seq_read,
4107         .llseek = seq_lseek,
4108         .release = single_release,
4109         .write = cur_wm_latency_write
4110 };
4111
4112 static int
4113 i915_wedged_get(void *data, u64 *val)
4114 {
4115         struct drm_i915_private *dev_priv = data;
4116
4117         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4118
4119         return 0;
4120 }
4121
4122 static int
4123 i915_wedged_set(void *data, u64 val)
4124 {
4125         struct drm_i915_private *dev_priv = data;
4126
4127         /*
4128          * There is no safeguard against this debugfs entry colliding
4129          * with the hangcheck calling same i915_handle_error() in
4130          * parallel, causing an explosion. For now we assume that the
4131          * test harness is responsible enough not to inject gpu hangs
4132          * while it is writing to 'i915_wedged'
4133          */
4134
4135         if (i915_reset_in_progress(&dev_priv->gpu_error))
4136                 return -EAGAIN;
4137
4138         i915_handle_error(dev_priv, val,
4139                           "Manually setting wedged to %llu", val);
4140
4141         return 0;
4142 }
4143
4144 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4145                         i915_wedged_get, i915_wedged_set,
4146                         "%llu\n");
4147
4148 static int
4149 fault_irq_set(struct drm_i915_private *i915,
4150               unsigned long *irq,
4151               unsigned long val)
4152 {
4153         int err;
4154
4155         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4156         if (err)
4157                 return err;
4158
4159         err = i915_gem_wait_for_idle(i915,
4160                                      I915_WAIT_LOCKED |
4161                                      I915_WAIT_INTERRUPTIBLE);
4162         if (err)
4163                 goto err_unlock;
4164
4165         /* Retire to kick idle work */
4166         i915_gem_retire_requests(i915);
4167         GEM_BUG_ON(i915->gt.active_requests);
4168
4169         *irq = val;
4170         mutex_unlock(&i915->drm.struct_mutex);
4171
4172         /* Flush idle worker to disarm irq */
4173         while (flush_delayed_work(&i915->gt.idle_work))
4174                 ;
4175
4176         return 0;
4177
4178 err_unlock:
4179         mutex_unlock(&i915->drm.struct_mutex);
4180         return err;
4181 }
4182
4183 static int
4184 i915_ring_missed_irq_get(void *data, u64 *val)
4185 {
4186         struct drm_i915_private *dev_priv = data;
4187
4188         *val = dev_priv->gpu_error.missed_irq_rings;
4189         return 0;
4190 }
4191
4192 static int
4193 i915_ring_missed_irq_set(void *data, u64 val)
4194 {
4195         struct drm_i915_private *i915 = data;
4196
4197         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4198 }
4199
4200 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4201                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4202                         "0x%08llx\n");
4203
4204 static int
4205 i915_ring_test_irq_get(void *data, u64 *val)
4206 {
4207         struct drm_i915_private *dev_priv = data;
4208
4209         *val = dev_priv->gpu_error.test_irq_rings;
4210
4211         return 0;
4212 }
4213
4214 static int
4215 i915_ring_test_irq_set(void *data, u64 val)
4216 {
4217         struct drm_i915_private *i915 = data;
4218
4219         val &= INTEL_INFO(i915)->ring_mask;
4220         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4221
4222         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4223 }
4224
4225 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4226                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4227                         "0x%08llx\n");
4228
4229 #define DROP_UNBOUND 0x1
4230 #define DROP_BOUND 0x2
4231 #define DROP_RETIRE 0x4
4232 #define DROP_ACTIVE 0x8
4233 #define DROP_FREED 0x10
4234 #define DROP_SHRINK_ALL 0x20
4235 #define DROP_ALL (DROP_UNBOUND  | \
4236                   DROP_BOUND    | \
4237                   DROP_RETIRE   | \
4238                   DROP_ACTIVE   | \
4239                   DROP_FREED    | \
4240                   DROP_SHRINK_ALL)
4241 static int
4242 i915_drop_caches_get(void *data, u64 *val)
4243 {
4244         *val = DROP_ALL;
4245
4246         return 0;
4247 }
4248
4249 static int
4250 i915_drop_caches_set(void *data, u64 val)
4251 {
4252         struct drm_i915_private *dev_priv = data;
4253         struct drm_device *dev = &dev_priv->drm;
4254         int ret;
4255
4256         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4257
4258         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4259          * on ioctls on -EAGAIN. */
4260         ret = mutex_lock_interruptible(&dev->struct_mutex);
4261         if (ret)
4262                 return ret;
4263
4264         if (val & DROP_ACTIVE) {
4265                 ret = i915_gem_wait_for_idle(dev_priv,
4266                                              I915_WAIT_INTERRUPTIBLE |
4267                                              I915_WAIT_LOCKED);
4268                 if (ret)
4269                         goto unlock;
4270         }
4271
4272         if (val & (DROP_RETIRE | DROP_ACTIVE))
4273                 i915_gem_retire_requests(dev_priv);
4274
4275         if (val & DROP_BOUND)
4276                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4277
4278         if (val & DROP_UNBOUND)
4279                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4280
4281         if (val & DROP_SHRINK_ALL)
4282                 i915_gem_shrink_all(dev_priv);
4283
4284 unlock:
4285         mutex_unlock(&dev->struct_mutex);
4286
4287         if (val & DROP_FREED) {
4288                 synchronize_rcu();
4289                 i915_gem_drain_freed_objects(dev_priv);
4290         }
4291
4292         return ret;
4293 }
4294
4295 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4296                         i915_drop_caches_get, i915_drop_caches_set,
4297                         "0x%08llx\n");
4298
4299 static int
4300 i915_max_freq_get(void *data, u64 *val)
4301 {
4302         struct drm_i915_private *dev_priv = data;
4303
4304         if (INTEL_GEN(dev_priv) < 6)
4305                 return -ENODEV;
4306
4307         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4308         return 0;
4309 }
4310
4311 static int
4312 i915_max_freq_set(void *data, u64 val)
4313 {
4314         struct drm_i915_private *dev_priv = data;
4315         u32 hw_max, hw_min;
4316         int ret;
4317
4318         if (INTEL_GEN(dev_priv) < 6)
4319                 return -ENODEV;
4320
4321         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4322
4323         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4324         if (ret)
4325                 return ret;
4326
4327         /*
4328          * Turbo will still be enabled, but won't go above the set value.
4329          */
4330         val = intel_freq_opcode(dev_priv, val);
4331
4332         hw_max = dev_priv->rps.max_freq;
4333         hw_min = dev_priv->rps.min_freq;
4334
4335         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4336                 mutex_unlock(&dev_priv->rps.hw_lock);
4337                 return -EINVAL;
4338         }
4339
4340         dev_priv->rps.max_freq_softlimit = val;
4341
4342         if (intel_set_rps(dev_priv, val))
4343                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4344
4345         mutex_unlock(&dev_priv->rps.hw_lock);
4346
4347         return 0;
4348 }
4349
4350 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4351                         i915_max_freq_get, i915_max_freq_set,
4352                         "%llu\n");
4353
4354 static int
4355 i915_min_freq_get(void *data, u64 *val)
4356 {
4357         struct drm_i915_private *dev_priv = data;
4358
4359         if (INTEL_GEN(dev_priv) < 6)
4360                 return -ENODEV;
4361
4362         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4363         return 0;
4364 }
4365
4366 static int
4367 i915_min_freq_set(void *data, u64 val)
4368 {
4369         struct drm_i915_private *dev_priv = data;
4370         u32 hw_max, hw_min;
4371         int ret;
4372
4373         if (INTEL_GEN(dev_priv) < 6)
4374                 return -ENODEV;
4375
4376         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4377
4378         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4379         if (ret)
4380                 return ret;
4381
4382         /*
4383          * Turbo will still be enabled, but won't go below the set value.
4384          */
4385         val = intel_freq_opcode(dev_priv, val);
4386
4387         hw_max = dev_priv->rps.max_freq;
4388         hw_min = dev_priv->rps.min_freq;
4389
4390         if (val < hw_min ||
4391             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4392                 mutex_unlock(&dev_priv->rps.hw_lock);
4393                 return -EINVAL;
4394         }
4395
4396         dev_priv->rps.min_freq_softlimit = val;
4397
4398         if (intel_set_rps(dev_priv, val))
4399                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4400
4401         mutex_unlock(&dev_priv->rps.hw_lock);
4402
4403         return 0;
4404 }
4405
4406 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4407                         i915_min_freq_get, i915_min_freq_set,
4408                         "%llu\n");
4409
4410 static int
4411 i915_cache_sharing_get(void *data, u64 *val)
4412 {
4413         struct drm_i915_private *dev_priv = data;
4414         u32 snpcr;
4415
4416         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4417                 return -ENODEV;
4418
4419         intel_runtime_pm_get(dev_priv);
4420
4421         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4422
4423         intel_runtime_pm_put(dev_priv);
4424
4425         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4426
4427         return 0;
4428 }
4429
4430 static int
4431 i915_cache_sharing_set(void *data, u64 val)
4432 {
4433         struct drm_i915_private *dev_priv = data;
4434         u32 snpcr;
4435
4436         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4437                 return -ENODEV;
4438
4439         if (val > 3)
4440                 return -EINVAL;
4441
4442         intel_runtime_pm_get(dev_priv);
4443         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4444
4445         /* Update the cache sharing policy here as well */
4446         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4447         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4448         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4449         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4450
4451         intel_runtime_pm_put(dev_priv);
4452         return 0;
4453 }
4454
4455 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4456                         i915_cache_sharing_get, i915_cache_sharing_set,
4457                         "%llu\n");
4458
4459 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4460                                           struct sseu_dev_info *sseu)
4461 {
4462         int ss_max = 2;
4463         int ss;
4464         u32 sig1[ss_max], sig2[ss_max];
4465
4466         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4467         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4468         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4469         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4470
4471         for (ss = 0; ss < ss_max; ss++) {
4472                 unsigned int eu_cnt;
4473
4474                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4475                         /* skip disabled subslice */
4476                         continue;
4477
4478                 sseu->slice_mask = BIT(0);
4479                 sseu->subslice_mask |= BIT(ss);
4480                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4481                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4482                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4483                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4484                 sseu->eu_total += eu_cnt;
4485                 sseu->eu_per_subslice = max_t(unsigned int,
4486                                               sseu->eu_per_subslice, eu_cnt);
4487         }
4488 }
4489
4490 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4491                                     struct sseu_dev_info *sseu)
4492 {
4493         int s_max = 3, ss_max = 4;
4494         int s, ss;
4495         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4496
4497         /* BXT has a single slice and at most 3 subslices. */
4498         if (IS_GEN9_LP(dev_priv)) {
4499                 s_max = 1;
4500                 ss_max = 3;
4501         }
4502
4503         for (s = 0; s < s_max; s++) {
4504                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4505                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4506                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4507         }
4508
4509         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4510                      GEN9_PGCTL_SSA_EU19_ACK |
4511                      GEN9_PGCTL_SSA_EU210_ACK |
4512                      GEN9_PGCTL_SSA_EU311_ACK;
4513         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4514                      GEN9_PGCTL_SSB_EU19_ACK |
4515                      GEN9_PGCTL_SSB_EU210_ACK |
4516                      GEN9_PGCTL_SSB_EU311_ACK;
4517
4518         for (s = 0; s < s_max; s++) {
4519                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4520                         /* skip disabled slice */
4521                         continue;
4522
4523                 sseu->slice_mask |= BIT(s);
4524
4525                 if (IS_GEN9_BC(dev_priv))
4526                         sseu->subslice_mask =
4527                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4528
4529                 for (ss = 0; ss < ss_max; ss++) {
4530                         unsigned int eu_cnt;
4531
4532                         if (IS_GEN9_LP(dev_priv)) {
4533                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4534                                         /* skip disabled subslice */
4535                                         continue;
4536
4537                                 sseu->subslice_mask |= BIT(ss);
4538                         }
4539
4540                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4541                                                eu_mask[ss%2]);
4542                         sseu->eu_total += eu_cnt;
4543                         sseu->eu_per_subslice = max_t(unsigned int,
4544                                                       sseu->eu_per_subslice,
4545                                                       eu_cnt);
4546                 }
4547         }
4548 }
4549
4550 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4551                                          struct sseu_dev_info *sseu)
4552 {
4553         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4554         int s;
4555
4556         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4557
4558         if (sseu->slice_mask) {
4559                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4560                 sseu->eu_per_subslice =
4561                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4562                 sseu->eu_total = sseu->eu_per_subslice *
4563                                  sseu_subslice_total(sseu);
4564
4565                 /* subtract fused off EU(s) from enabled slice(s) */
4566                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4567                         u8 subslice_7eu =
4568                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4569
4570                         sseu->eu_total -= hweight8(subslice_7eu);
4571                 }
4572         }
4573 }
4574
4575 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4576                                  const struct sseu_dev_info *sseu)
4577 {
4578         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4579         const char *type = is_available_info ? "Available" : "Enabled";
4580
4581         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4582                    sseu->slice_mask);
4583         seq_printf(m, "  %s Slice Total: %u\n", type,
4584                    hweight8(sseu->slice_mask));
4585         seq_printf(m, "  %s Subslice Total: %u\n", type,
4586                    sseu_subslice_total(sseu));
4587         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4588                    sseu->subslice_mask);
4589         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4590                    hweight8(sseu->subslice_mask));
4591         seq_printf(m, "  %s EU Total: %u\n", type,
4592                    sseu->eu_total);
4593         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4594                    sseu->eu_per_subslice);
4595
4596         if (!is_available_info)
4597                 return;
4598
4599         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4600         if (HAS_POOLED_EU(dev_priv))
4601                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4602
4603         seq_printf(m, "  Has Slice Power Gating: %s\n",
4604                    yesno(sseu->has_slice_pg));
4605         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4606                    yesno(sseu->has_subslice_pg));
4607         seq_printf(m, "  Has EU Power Gating: %s\n",
4608                    yesno(sseu->has_eu_pg));
4609 }
4610
4611 static int i915_sseu_status(struct seq_file *m, void *unused)
4612 {
4613         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4614         struct sseu_dev_info sseu;
4615
4616         if (INTEL_GEN(dev_priv) < 8)
4617                 return -ENODEV;
4618
4619         seq_puts(m, "SSEU Device Info\n");
4620         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4621
4622         seq_puts(m, "SSEU Device Status\n");
4623         memset(&sseu, 0, sizeof(sseu));
4624
4625         intel_runtime_pm_get(dev_priv);
4626
4627         if (IS_CHERRYVIEW(dev_priv)) {
4628                 cherryview_sseu_device_status(dev_priv, &sseu);
4629         } else if (IS_BROADWELL(dev_priv)) {
4630                 broadwell_sseu_device_status(dev_priv, &sseu);
4631         } else if (INTEL_GEN(dev_priv) >= 9) {
4632                 gen9_sseu_device_status(dev_priv, &sseu);
4633         }
4634
4635         intel_runtime_pm_put(dev_priv);
4636
4637         i915_print_sseu_info(m, false, &sseu);
4638
4639         return 0;
4640 }
4641
4642 static int i915_forcewake_open(struct inode *inode, struct file *file)
4643 {
4644         struct drm_i915_private *dev_priv = inode->i_private;
4645
4646         if (INTEL_GEN(dev_priv) < 6)
4647                 return 0;
4648
4649         intel_runtime_pm_get(dev_priv);
4650         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4651
4652         return 0;
4653 }
4654
4655 static int i915_forcewake_release(struct inode *inode, struct file *file)
4656 {
4657         struct drm_i915_private *dev_priv = inode->i_private;
4658
4659         if (INTEL_GEN(dev_priv) < 6)
4660                 return 0;
4661
4662         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4663         intel_runtime_pm_put(dev_priv);
4664
4665         return 0;
4666 }
4667
4668 static const struct file_operations i915_forcewake_fops = {
4669         .owner = THIS_MODULE,
4670         .open = i915_forcewake_open,
4671         .release = i915_forcewake_release,
4672 };
4673
4674 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4675 {
4676         struct drm_i915_private *dev_priv = m->private;
4677         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4678
4679         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4680         seq_printf(m, "Detected: %s\n",
4681                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4682
4683         return 0;
4684 }
4685
4686 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4687                                         const char __user *ubuf, size_t len,
4688                                         loff_t *offp)
4689 {
4690         struct seq_file *m = file->private_data;
4691         struct drm_i915_private *dev_priv = m->private;
4692         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4693         unsigned int new_threshold;
4694         int i;
4695         char *newline;
4696         char tmp[16];
4697
4698         if (len >= sizeof(tmp))
4699                 return -EINVAL;
4700
4701         if (copy_from_user(tmp, ubuf, len))
4702                 return -EFAULT;
4703
4704         tmp[len] = '\0';
4705
4706         /* Strip newline, if any */
4707         newline = strchr(tmp, '\n');
4708         if (newline)
4709                 *newline = '\0';
4710
4711         if (strcmp(tmp, "reset") == 0)
4712                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4713         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4714                 return -EINVAL;
4715
4716         if (new_threshold > 0)
4717                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4718                               new_threshold);
4719         else
4720                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4721
4722         spin_lock_irq(&dev_priv->irq_lock);
4723         hotplug->hpd_storm_threshold = new_threshold;
4724         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4725         for_each_hpd_pin(i)
4726                 hotplug->stats[i].count = 0;
4727         spin_unlock_irq(&dev_priv->irq_lock);
4728
4729         /* Re-enable hpd immediately if we were in an irq storm */
4730         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4731
4732         return len;
4733 }
4734
4735 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4736 {
4737         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4738 }
4739
4740 static const struct file_operations i915_hpd_storm_ctl_fops = {
4741         .owner = THIS_MODULE,
4742         .open = i915_hpd_storm_ctl_open,
4743         .read = seq_read,
4744         .llseek = seq_lseek,
4745         .release = single_release,
4746         .write = i915_hpd_storm_ctl_write
4747 };
4748
4749 static const struct drm_info_list i915_debugfs_list[] = {
4750         {"i915_capabilities", i915_capabilities, 0},
4751         {"i915_gem_objects", i915_gem_object_info, 0},
4752         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4753         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4754         {"i915_gem_stolen", i915_gem_stolen_list_info },
4755         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4756         {"i915_gem_request", i915_gem_request_info, 0},
4757         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4758         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4759         {"i915_gem_interrupt", i915_interrupt_info, 0},
4760         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4761         {"i915_guc_info", i915_guc_info, 0},
4762         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4763         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4764         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4765         {"i915_frequency_info", i915_frequency_info, 0},
4766         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4767         {"i915_drpc_info", i915_drpc_info, 0},
4768         {"i915_emon_status", i915_emon_status, 0},
4769         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4770         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4771         {"i915_fbc_status", i915_fbc_status, 0},
4772         {"i915_ips_status", i915_ips_status, 0},
4773         {"i915_sr_status", i915_sr_status, 0},
4774         {"i915_opregion", i915_opregion, 0},
4775         {"i915_vbt", i915_vbt, 0},
4776         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4777         {"i915_context_status", i915_context_status, 0},
4778         {"i915_dump_lrc", i915_dump_lrc, 0},
4779         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4780         {"i915_swizzle_info", i915_swizzle_info, 0},
4781         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4782         {"i915_llc", i915_llc, 0},
4783         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4784         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4785         {"i915_energy_uJ", i915_energy_uJ, 0},
4786         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4787         {"i915_power_domain_info", i915_power_domain_info, 0},
4788         {"i915_dmc_info", i915_dmc_info, 0},
4789         {"i915_display_info", i915_display_info, 0},
4790         {"i915_engine_info", i915_engine_info, 0},
4791         {"i915_semaphore_status", i915_semaphore_status, 0},
4792         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4793         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4794         {"i915_wa_registers", i915_wa_registers, 0},
4795         {"i915_ddb_info", i915_ddb_info, 0},
4796         {"i915_sseu_status", i915_sseu_status, 0},
4797         {"i915_drrs_status", i915_drrs_status, 0},
4798         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4799 };
4800 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4801
4802 static const struct i915_debugfs_files {
4803         const char *name;
4804         const struct file_operations *fops;
4805 } i915_debugfs_files[] = {
4806         {"i915_wedged", &i915_wedged_fops},
4807         {"i915_max_freq", &i915_max_freq_fops},
4808         {"i915_min_freq", &i915_min_freq_fops},
4809         {"i915_cache_sharing", &i915_cache_sharing_fops},
4810         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4811         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4812         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4813 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4814         {"i915_error_state", &i915_error_state_fops},
4815         {"i915_gpu_info", &i915_gpu_info_fops},
4816 #endif
4817         {"i915_next_seqno", &i915_next_seqno_fops},
4818         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4819         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4820         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4821         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4822         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4823         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4824         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4825         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4826         {"i915_guc_log_control", &i915_guc_log_control_fops},
4827         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
4828 };
4829
4830 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4831 {
4832         struct drm_minor *minor = dev_priv->drm.primary;
4833         struct dentry *ent;
4834         int ret, i;
4835
4836         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4837                                   minor->debugfs_root, to_i915(minor->dev),
4838                                   &i915_forcewake_fops);
4839         if (!ent)
4840                 return -ENOMEM;
4841
4842         ret = intel_pipe_crc_create(minor);
4843         if (ret)
4844                 return ret;
4845
4846         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4847                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4848                                           S_IRUGO | S_IWUSR,
4849                                           minor->debugfs_root,
4850                                           to_i915(minor->dev),
4851                                           i915_debugfs_files[i].fops);
4852                 if (!ent)
4853                         return -ENOMEM;
4854         }
4855
4856         return drm_debugfs_create_files(i915_debugfs_list,
4857                                         I915_DEBUGFS_ENTRIES,
4858                                         minor->debugfs_root, minor);
4859 }
4860
4861 struct dpcd_block {
4862         /* DPCD dump start address. */
4863         unsigned int offset;
4864         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4865         unsigned int end;
4866         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4867         size_t size;
4868         /* Only valid for eDP. */
4869         bool edp;
4870 };
4871
4872 static const struct dpcd_block i915_dpcd_debug[] = {
4873         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4874         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4875         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4876         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4877         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4878         { .offset = DP_SET_POWER },
4879         { .offset = DP_EDP_DPCD_REV },
4880         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4881         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4882         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4883 };
4884
4885 static int i915_dpcd_show(struct seq_file *m, void *data)
4886 {
4887         struct drm_connector *connector = m->private;
4888         struct intel_dp *intel_dp =
4889                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4890         uint8_t buf[16];
4891         ssize_t err;
4892         int i;
4893
4894         if (connector->status != connector_status_connected)
4895                 return -ENODEV;
4896
4897         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4898                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4899                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4900
4901                 if (b->edp &&
4902                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4903                         continue;
4904
4905                 /* low tech for now */
4906                 if (WARN_ON(size > sizeof(buf)))
4907                         continue;
4908
4909                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4910                 if (err <= 0) {
4911                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4912                                   size, b->offset, err);
4913                         continue;
4914                 }
4915
4916                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4917         }
4918
4919         return 0;
4920 }
4921
4922 static int i915_dpcd_open(struct inode *inode, struct file *file)
4923 {
4924         return single_open(file, i915_dpcd_show, inode->i_private);
4925 }
4926
4927 static const struct file_operations i915_dpcd_fops = {
4928         .owner = THIS_MODULE,
4929         .open = i915_dpcd_open,
4930         .read = seq_read,
4931         .llseek = seq_lseek,
4932         .release = single_release,
4933 };
4934
4935 static int i915_panel_show(struct seq_file *m, void *data)
4936 {
4937         struct drm_connector *connector = m->private;
4938         struct intel_dp *intel_dp =
4939                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4940
4941         if (connector->status != connector_status_connected)
4942                 return -ENODEV;
4943
4944         seq_printf(m, "Panel power up delay: %d\n",
4945                    intel_dp->panel_power_up_delay);
4946         seq_printf(m, "Panel power down delay: %d\n",
4947                    intel_dp->panel_power_down_delay);
4948         seq_printf(m, "Backlight on delay: %d\n",
4949                    intel_dp->backlight_on_delay);
4950         seq_printf(m, "Backlight off delay: %d\n",
4951                    intel_dp->backlight_off_delay);
4952
4953         return 0;
4954 }
4955
4956 static int i915_panel_open(struct inode *inode, struct file *file)
4957 {
4958         return single_open(file, i915_panel_show, inode->i_private);
4959 }
4960
4961 static const struct file_operations i915_panel_fops = {
4962         .owner = THIS_MODULE,
4963         .open = i915_panel_open,
4964         .read = seq_read,
4965         .llseek = seq_lseek,
4966         .release = single_release,
4967 };
4968
4969 /**
4970  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4971  * @connector: pointer to a registered drm_connector
4972  *
4973  * Cleanup will be done by drm_connector_unregister() through a call to
4974  * drm_debugfs_connector_remove().
4975  *
4976  * Returns 0 on success, negative error codes on error.
4977  */
4978 int i915_debugfs_connector_add(struct drm_connector *connector)
4979 {
4980         struct dentry *root = connector->debugfs_entry;
4981
4982         /* The connector must have been registered beforehands. */
4983         if (!root)
4984                 return -ENODEV;
4985
4986         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4987             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4988                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4989                                     connector, &i915_dpcd_fops);
4990
4991         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4992                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4993                                     connector, &i915_panel_fops);
4994
4995         return 0;
4996 }