drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 121                 if (i915_is_ggtt(vma->vm) &&
 122                     drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *ring;
 134         struct i915_vma *vma;
 135         int pin_count = 0;
 136         int i;
 137
 138         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 139                    &obj->base,
 140                    obj->active ? "*" : " ",
 141                    get_pin_flag(obj),
 142                    get_tiling_flag(obj),
 143                    get_global_flag(obj),
 144                    obj->base.size / 1024,
 145                    obj->base.read_domains,
 146                    obj->base.write_domain);
 147         for_each_ring(ring, dev_priv, i)
 148                 seq_printf(m, "%x ",
 149                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 150         seq_printf(m, "] %x %x%s%s%s",
 151                    i915_gem_request_get_seqno(obj->last_write_req),
 152                    i915_gem_request_get_seqno(obj->last_fenced_req),
 153                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 154                    obj->dirty ? " dirty" : "",
 155                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 156         if (obj->base.name)
 157                 seq_printf(m, " (name: %d)", obj->base.name);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (vma->pin_count > 0)
 160                         pin_count++;
 161         }
 162         seq_printf(m, " (pinned x %d)", pin_count);
 163         if (obj->pin_display)
 164                 seq_printf(m, " (display)");
 165         if (obj->fence_reg != I915_FENCE_REG_NONE)
 166                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 167         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_is_ggtt(vma->vm))
 172                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 173                 else
 174                         seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_ring(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         struct i915_address_space *vm = &dev_priv->gtt.base;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &vm->active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &vm->inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, mm_list) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         if (a->stolen->start < b->stolen->start)
 257                 return -1;
 258         if (a->stolen->start > b->stolen->start)
 259                 return 1;
 260         return 0;
 261 }
 262
 263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 264 {
 265         struct drm_info_node *node = m->private;
 266         struct drm_device *dev = node->minor->dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct drm_i915_gem_object *obj;
 269         u64 total_obj_size, total_gtt_size;
 270         LIST_HEAD(stolen);
 271         int count, ret;
 272
 273         ret = mutex_lock_interruptible(&dev->struct_mutex);
 274         if (ret)
 275                 return ret;
 276
 277         total_obj_size = total_gtt_size = count = 0;
 278         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 279                 if (obj->stolen == NULL)
 280                         continue;
 281
 282                 list_add(&obj->obj_exec_link, &stolen);
 283
 284                 total_obj_size += obj->base.size;
 285                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 286                 count++;
 287         }
 288         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 289                 if (obj->stolen == NULL)
 290                         continue;
 291
 292                 list_add(&obj->obj_exec_link, &stolen);
 293
 294                 total_obj_size += obj->base.size;
 295                 count++;
 296         }
 297         list_sort(NULL, &stolen, obj_rank_by_stolen);
 298         seq_puts(m, "Stolen:\n");
 299         while (!list_empty(&stolen)) {
 300                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 301                 seq_puts(m, "   ");
 302                 describe_obj(m, obj);
 303                 seq_putc(m, '\n');
 304                 list_del_init(&obj->obj_exec_link);
 305         }
 306         mutex_unlock(&dev->struct_mutex);
 307
 308         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 309                    count, total_obj_size, total_gtt_size);
 310         return 0;
 311 }
 312
 313 #define count_objects(list, member) do { \
 314         list_for_each_entry(obj, list, member) { \
 315                 size += i915_gem_obj_total_ggtt_size(obj); \
 316                 ++count; \
 317                 if (obj->map_and_fenceable) { \
 318                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 319                         ++mappable_count; \
 320                 } \
 321         } \
 322 } while (0)
 323
 324 struct file_stats {
 325         struct drm_i915_file_private *file_priv;
 326         unsigned long count;
 327         u64 total, unbound;
 328         u64 global, shared;
 329         u64 active, inactive;
 330 };
 331
 332 static int per_file_stats(int id, void *ptr, void *data)
 333 {
 334         struct drm_i915_gem_object *obj = ptr;
 335         struct file_stats *stats = data;
 336         struct i915_vma *vma;
 337
 338         stats->count++;
 339         stats->total += obj->base.size;
 340
 341         if (obj->base.name || obj->base.dma_buf)
 342                 stats->shared += obj->base.size;
 343
 344         if (USES_FULL_PPGTT(obj->base.dev)) {
 345                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 346                         struct i915_hw_ppgtt *ppgtt;
 347
 348                         if (!drm_mm_node_allocated(&vma->node))
 349                                 continue;
 350
 351                         if (i915_is_ggtt(vma->vm)) {
 352                                 stats->global += obj->base.size;
 353                                 continue;
 354                         }
 355
 356                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 357                         if (ppgtt->file_priv != stats->file_priv)
 358                                 continue;
 359
 360                         if (obj->active) /* XXX per-vma statistic */
 361                                 stats->active += obj->base.size;
 362                         else
 363                                 stats->inactive += obj->base.size;
 364
 365                         return 0;
 366                 }
 367         } else {
 368                 if (i915_gem_obj_ggtt_bound(obj)) {
 369                         stats->global += obj->base.size;
 370                         if (obj->active)
 371                                 stats->active += obj->base.size;
 372                         else
 373                                 stats->inactive += obj->base.size;
 374                         return 0;
 375                 }
 376         }
 377
 378         if (!list_empty(&obj->global_list))
 379                 stats->unbound += obj->base.size;
 380
 381         return 0;
 382 }
 383
 384 #define print_file_stats(m, name, stats) do { \
 385         if (stats.count) \
 386                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 387                            name, \
 388                            stats.count, \
 389                            stats.total, \
 390                            stats.active, \
 391                            stats.inactive, \
 392                            stats.global, \
 393                            stats.shared, \
 394                            stats.unbound); \
 395 } while (0)
 396
 397 static void print_batch_pool_stats(struct seq_file *m,
 398                                    struct drm_i915_private *dev_priv)
 399 {
 400         struct drm_i915_gem_object *obj;
 401         struct file_stats stats;
 402         struct intel_engine_cs *ring;
 403         int i, j;
 404
 405         memset(&stats, 0, sizeof(stats));
 406
 407         for_each_ring(ring, dev_priv, i) {
 408                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 409                         list_for_each_entry(obj,
 410                                             &ring->batch_pool.cache_list[j],
 411                                             batch_pool_link)
 412                                 per_file_stats(0, obj, &stats);
 413                 }
 414         }
 415
 416         print_file_stats(m, "[k]batch pool", stats);
 417 }
 418
 419 #define count_vmas(list, member) do { \
 420         list_for_each_entry(vma, list, member) { \
 421                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 422                 ++count; \
 423                 if (vma->obj->map_and_fenceable) { \
 424                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 425                         ++mappable_count; \
 426                 } \
 427         } \
 428 } while (0)
 429
 430 static int i915_gem_object_info(struct seq_file *m, void* data)
 431 {
 432         struct drm_info_node *node = m->private;
 433         struct drm_device *dev = node->minor->dev;
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         u32 count, mappable_count, purgeable_count;
 436         u64 size, mappable_size, purgeable_size;
 437         struct drm_i915_gem_object *obj;
 438         struct i915_address_space *vm = &dev_priv->gtt.base;
 439         struct drm_file *file;
 440         struct i915_vma *vma;
 441         int ret;
 442
 443         ret = mutex_lock_interruptible(&dev->struct_mutex);
 444         if (ret)
 445                 return ret;
 446
 447         seq_printf(m, "%u objects, %zu bytes\n",
 448                    dev_priv->mm.object_count,
 449                    dev_priv->mm.object_memory);
 450
 451         size = count = mappable_size = mappable_count = 0;
 452         count_objects(&dev_priv->mm.bound_list, global_list);
 453         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 454                    count, mappable_count, size, mappable_size);
 455
 456         size = count = mappable_size = mappable_count = 0;
 457         count_vmas(&vm->active_list, mm_list);
 458         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 459                    count, mappable_count, size, mappable_size);
 460
 461         size = count = mappable_size = mappable_count = 0;
 462         count_vmas(&vm->inactive_list, mm_list);
 463         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 464                    count, mappable_count, size, mappable_size);
 465
 466         size = count = purgeable_size = purgeable_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 468                 size += obj->base.size, ++count;
 469                 if (obj->madv == I915_MADV_DONTNEED)
 470                         purgeable_size += obj->base.size, ++purgeable_count;
 471         }
 472         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 473
 474         size = count = mappable_size = mappable_count = 0;
 475         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 476                 if (obj->fault_mappable) {
 477                         size += i915_gem_obj_ggtt_size(obj);
 478                         ++count;
 479                 }
 480                 if (obj->pin_display) {
 481                         mappable_size += i915_gem_obj_ggtt_size(obj);
 482                         ++mappable_count;
 483                 }
 484                 if (obj->madv == I915_MADV_DONTNEED) {
 485                         purgeable_size += obj->base.size;
 486                         ++purgeable_count;
 487                 }
 488         }
 489         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 490                    purgeable_count, purgeable_size);
 491         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 492                    mappable_count, mappable_size);
 493         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 494                    count, size);
 495
 496         seq_printf(m, "%llu [%llu] gtt total\n",
 497                    dev_priv->gtt.base.total,
 498                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 499
 500         seq_putc(m, '\n');
 501         print_batch_pool_stats(m, dev_priv);
 502         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 503                 struct file_stats stats;
 504                 struct task_struct *task;
 505
 506                 memset(&stats, 0, sizeof(stats));
 507                 stats.file_priv = file->driver_priv;
 508                 spin_lock(&file->table_lock);
 509                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 510                 spin_unlock(&file->table_lock);
 511                 /*
 512                  * Although we have a valid reference on file->pid, that does
 513                  * not guarantee that the task_struct who called get_pid() is
 514                  * still alive (e.g. get_pid(current) => fork() => exit()).
 515                  * Therefore, we need to protect this ->comm access using RCU.
 516                  */
 517                 rcu_read_lock();
 518                 task = pid_task(file->pid, PIDTYPE_PID);
 519                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 520                 rcu_read_unlock();
 521         }
 522
 523         mutex_unlock(&dev->struct_mutex);
 524
 525         return 0;
 526 }
 527
 528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 529 {
 530         struct drm_info_node *node = m->private;
 531         struct drm_device *dev = node->minor->dev;
 532         uintptr_t list = (uintptr_t) node->info_ent->data;
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534         struct drm_i915_gem_object *obj;
 535         u64 total_obj_size, total_gtt_size;
 536         int count, ret;
 537
 538         ret = mutex_lock_interruptible(&dev->struct_mutex);
 539         if (ret)
 540                 return ret;
 541
 542         total_obj_size = total_gtt_size = count = 0;
 543         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 544                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 545                         continue;
 546
 547                 seq_puts(m, "   ");
 548                 describe_obj(m, obj);
 549                 seq_putc(m, '\n');
 550                 total_obj_size += obj->base.size;
 551                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 552                 count++;
 553         }
 554
 555         mutex_unlock(&dev->struct_mutex);
 556
 557         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 558                    count, total_obj_size, total_gtt_size);
 559
 560         return 0;
 561 }
 562
 563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 564 {
 565         struct drm_info_node *node = m->private;
 566         struct drm_device *dev = node->minor->dev;
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct intel_crtc *crtc;
 569         int ret;
 570
 571         ret = mutex_lock_interruptible(&dev->struct_mutex);
 572         if (ret)
 573                 return ret;
 574
 575         for_each_intel_crtc(dev, crtc) {
 576                 const char pipe = pipe_name(crtc->pipe);
 577                 const char plane = plane_name(crtc->plane);
 578                 struct intel_unpin_work *work;
 579
 580                 spin_lock_irq(&dev->event_lock);
 581                 work = crtc->unpin_work;
 582                 if (work == NULL) {
 583                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 584                                    pipe, plane);
 585                 } else {
 586                         u32 addr;
 587
 588                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 589                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 590                                            pipe, plane);
 591                         } else {
 592                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 593                                            pipe, plane);
 594                         }
 595                         if (work->flip_queued_req) {
 596                                 struct intel_engine_cs *ring =
 597                                         i915_gem_request_get_ring(work->flip_queued_req);
 598
 599                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 600                                            ring->name,
 601                                            i915_gem_request_get_seqno(work->flip_queued_req),
 602                                            dev_priv->next_seqno,
 603                                            ring->get_seqno(ring, true),
 604                                            i915_gem_request_completed(work->flip_queued_req, true));
 605                         } else
 606                                 seq_printf(m, "Flip not associated with any ring\n");
 607                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 608                                    work->flip_queued_vblank,
 609                                    work->flip_ready_vblank,
 610                                    drm_crtc_vblank_count(&crtc->base));
 611                         if (work->enable_stall_check)
 612                                 seq_puts(m, "Stall check enabled, ");
 613                         else
 614                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 615                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 616
 617                         if (INTEL_INFO(dev)->gen >= 4)
 618                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 619                         else
 620                                 addr = I915_READ(DSPADDR(crtc->plane));
 621                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 622
 623                         if (work->pending_flip_obj) {
 624                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 625                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 626                         }
 627                 }
 628                 spin_unlock_irq(&dev->event_lock);
 629         }
 630
 631         mutex_unlock(&dev->struct_mutex);
 632
 633         return 0;
 634 }
 635
 636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 637 {
 638         struct drm_info_node *node = m->private;
 639         struct drm_device *dev = node->minor->dev;
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641         struct drm_i915_gem_object *obj;
 642         struct intel_engine_cs *ring;
 643         int total = 0;
 644         int ret, i, j;
 645
 646         ret = mutex_lock_interruptible(&dev->struct_mutex);
 647         if (ret)
 648                 return ret;
 649
 650         for_each_ring(ring, dev_priv, i) {
 651                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 652                         int count;
 653
 654                         count = 0;
 655                         list_for_each_entry(obj,
 656                                             &ring->batch_pool.cache_list[j],
 657                                             batch_pool_link)
 658                                 count++;
 659                         seq_printf(m, "%s cache[%d]: %d objects\n",
 660                                    ring->name, j, count);
 661
 662                         list_for_each_entry(obj,
 663                                             &ring->batch_pool.cache_list[j],
 664                                             batch_pool_link) {
 665                                 seq_puts(m, "   ");
 666                                 describe_obj(m, obj);
 667                                 seq_putc(m, '\n');
 668                         }
 669
 670                         total += count;
 671                 }
 672         }
 673
 674         seq_printf(m, "total: %d\n", total);
 675
 676         mutex_unlock(&dev->struct_mutex);
 677
 678         return 0;
 679 }
 680
 681 static int i915_gem_request_info(struct seq_file *m, void *data)
 682 {
 683         struct drm_info_node *node = m->private;
 684         struct drm_device *dev = node->minor->dev;
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct intel_engine_cs *ring;
 687         struct drm_i915_gem_request *req;
 688         int ret, any, i;
 689
 690         ret = mutex_lock_interruptible(&dev->struct_mutex);
 691         if (ret)
 692                 return ret;
 693
 694         any = 0;
 695         for_each_ring(ring, dev_priv, i) {
 696                 int count;
 697
 698                 count = 0;
 699                 list_for_each_entry(req, &ring->request_list, list)
 700                         count++;
 701                 if (count == 0)
 702                         continue;
 703
 704                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 705                 list_for_each_entry(req, &ring->request_list, list) {
 706                         struct task_struct *task;
 707
 708                         rcu_read_lock();
 709                         task = NULL;
 710                         if (req->pid)
 711                                 task = pid_task(req->pid, PIDTYPE_PID);
 712                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 713                                    req->seqno,
 714                                    (int) (jiffies - req->emitted_jiffies),
 715                                    task ? task->comm : "<unknown>",
 716                                    task ? task->pid : -1);
 717                         rcu_read_unlock();
 718                 }
 719
 720                 any++;
 721         }
 722         mutex_unlock(&dev->struct_mutex);
 723
 724         if (any == 0)
 725                 seq_puts(m, "No requests\n");
 726
 727         return 0;
 728 }
 729
 730 static void i915_ring_seqno_info(struct seq_file *m,
 731                                  struct intel_engine_cs *ring)
 732 {
 733         if (ring->get_seqno) {
 734                 seq_printf(m, "Current sequence (%s): %x\n",
 735                            ring->name, ring->get_seqno(ring, false));
 736         }
 737 }
 738
 739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 740 {
 741         struct drm_info_node *node = m->private;
 742         struct drm_device *dev = node->minor->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct intel_engine_cs *ring;
 745         int ret, i;
 746
 747         ret = mutex_lock_interruptible(&dev->struct_mutex);
 748         if (ret)
 749                 return ret;
 750         intel_runtime_pm_get(dev_priv);
 751
 752         for_each_ring(ring, dev_priv, i)
 753                 i915_ring_seqno_info(m, ring);
 754
 755         intel_runtime_pm_put(dev_priv);
 756         mutex_unlock(&dev->struct_mutex);
 757
 758         return 0;
 759 }
 760
 761
 762 static int i915_interrupt_info(struct seq_file *m, void *data)
 763 {
 764         struct drm_info_node *node = m->private;
 765         struct drm_device *dev = node->minor->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         struct intel_engine_cs *ring;
 768         int ret, i, pipe;
 769
 770         ret = mutex_lock_interruptible(&dev->struct_mutex);
 771         if (ret)
 772                 return ret;
 773         intel_runtime_pm_get(dev_priv);
 774
 775         if (IS_CHERRYVIEW(dev)) {
 776                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 777                            I915_READ(GEN8_MASTER_IRQ));
 778
 779                 seq_printf(m, "Display IER:\t%08x\n",
 780                            I915_READ(VLV_IER));
 781                 seq_printf(m, "Display IIR:\t%08x\n",
 782                            I915_READ(VLV_IIR));
 783                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 784                            I915_READ(VLV_IIR_RW));
 785                 seq_printf(m, "Display IMR:\t%08x\n",
 786                            I915_READ(VLV_IMR));
 787                 for_each_pipe(dev_priv, pipe)
 788                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 789                                    pipe_name(pipe),
 790                                    I915_READ(PIPESTAT(pipe)));
 791
 792                 seq_printf(m, "Port hotplug:\t%08x\n",
 793                            I915_READ(PORT_HOTPLUG_EN));
 794                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 795                            I915_READ(VLV_DPFLIPSTAT));
 796                 seq_printf(m, "DPINVGTT:\t%08x\n",
 797                            I915_READ(DPINVGTT));
 798
 799                 for (i = 0; i < 4; i++) {
 800                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IMR(i)));
 802                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 803                                    i, I915_READ(GEN8_GT_IIR(i)));
 804                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 805                                    i, I915_READ(GEN8_GT_IER(i)));
 806                 }
 807
 808                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IMR));
 810                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 811                            I915_READ(GEN8_PCU_IIR));
 812                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 813                            I915_READ(GEN8_PCU_IER));
 814         } else if (INTEL_INFO(dev)->gen >= 8) {
 815                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 816                            I915_READ(GEN8_MASTER_IRQ));
 817
 818                 for (i = 0; i < 4; i++) {
 819                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IMR(i)));
 821                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 822                                    i, I915_READ(GEN8_GT_IIR(i)));
 823                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 824                                    i, I915_READ(GEN8_GT_IER(i)));
 825                 }
 826
 827                 for_each_pipe(dev_priv, pipe) {
 828                         if (!intel_display_power_is_enabled(dev_priv,
 829                                                 POWER_DOMAIN_PIPE(pipe))) {
 830                                 seq_printf(m, "Pipe %c power disabled\n",
 831                                            pipe_name(pipe));
 832                                 continue;
 833                         }
 834                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 835                                    pipe_name(pipe),
 836                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 837                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 838                                    pipe_name(pipe),
 839                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 840                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 841                                    pipe_name(pipe),
 842                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 843                 }
 844
 845                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 846                            I915_READ(GEN8_DE_PORT_IMR));
 847                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 848                            I915_READ(GEN8_DE_PORT_IIR));
 849                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 850                            I915_READ(GEN8_DE_PORT_IER));
 851
 852                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 853                            I915_READ(GEN8_DE_MISC_IMR));
 854                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 855                            I915_READ(GEN8_DE_MISC_IIR));
 856                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 857                            I915_READ(GEN8_DE_MISC_IER));
 858
 859                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 860                            I915_READ(GEN8_PCU_IMR));
 861                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 862                            I915_READ(GEN8_PCU_IIR));
 863                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 864                            I915_READ(GEN8_PCU_IER));
 865         } else if (IS_VALLEYVIEW(dev)) {
 866                 seq_printf(m, "Display IER:\t%08x\n",
 867                            I915_READ(VLV_IER));
 868                 seq_printf(m, "Display IIR:\t%08x\n",
 869                            I915_READ(VLV_IIR));
 870                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 871                            I915_READ(VLV_IIR_RW));
 872                 seq_printf(m, "Display IMR:\t%08x\n",
 873                            I915_READ(VLV_IMR));
 874                 for_each_pipe(dev_priv, pipe)
 875                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 876                                    pipe_name(pipe),
 877                                    I915_READ(PIPESTAT(pipe)));
 878
 879                 seq_printf(m, "Master IER:\t%08x\n",
 880                            I915_READ(VLV_MASTER_IER));
 881
 882                 seq_printf(m, "Render IER:\t%08x\n",
 883                            I915_READ(GTIER));
 884                 seq_printf(m, "Render IIR:\t%08x\n",
 885                            I915_READ(GTIIR));
 886                 seq_printf(m, "Render IMR:\t%08x\n",
 887                            I915_READ(GTIMR));
 888
 889                 seq_printf(m, "PM IER:\t\t%08x\n",
 890                            I915_READ(GEN6_PMIER));
 891                 seq_printf(m, "PM IIR:\t\t%08x\n",
 892                            I915_READ(GEN6_PMIIR));
 893                 seq_printf(m, "PM IMR:\t\t%08x\n",
 894                            I915_READ(GEN6_PMIMR));
 895
 896                 seq_printf(m, "Port hotplug:\t%08x\n",
 897                            I915_READ(PORT_HOTPLUG_EN));
 898                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 899                            I915_READ(VLV_DPFLIPSTAT));
 900                 seq_printf(m, "DPINVGTT:\t%08x\n",
 901                            I915_READ(DPINVGTT));
 902
 903         } else if (!HAS_PCH_SPLIT(dev)) {
 904                 seq_printf(m, "Interrupt enable:    %08x\n",
 905                            I915_READ(IER));
 906                 seq_printf(m, "Interrupt identity:  %08x\n",
 907                            I915_READ(IIR));
 908                 seq_printf(m, "Interrupt mask:      %08x\n",
 909                            I915_READ(IMR));
 910                 for_each_pipe(dev_priv, pipe)
 911                         seq_printf(m, "Pipe %c stat:         %08x\n",
 912                                    pipe_name(pipe),
 913                                    I915_READ(PIPESTAT(pipe)));
 914         } else {
 915                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 916                            I915_READ(DEIER));
 917                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 918                            I915_READ(DEIIR));
 919                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 920                            I915_READ(DEIMR));
 921                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 922                            I915_READ(SDEIER));
 923                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 924                            I915_READ(SDEIIR));
 925                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 926                            I915_READ(SDEIMR));
 927                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 928                            I915_READ(GTIER));
 929                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 930                            I915_READ(GTIIR));
 931                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 932                            I915_READ(GTIMR));
 933         }
 934         for_each_ring(ring, dev_priv, i) {
 935                 if (INTEL_INFO(dev)->gen >= 6) {
 936                         seq_printf(m,
 937                                    "Graphics Interrupt mask (%s):       %08x\n",
 938                                    ring->name, I915_READ_IMR(ring));
 939                 }
 940                 i915_ring_seqno_info(m, ring);
 941         }
 942         intel_runtime_pm_put(dev_priv);
 943         mutex_unlock(&dev->struct_mutex);
 944
 945         return 0;
 946 }
 947
 948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 949 {
 950         struct drm_info_node *node = m->private;
 951         struct drm_device *dev = node->minor->dev;
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         int i, ret;
 954
 955         ret = mutex_lock_interruptible(&dev->struct_mutex);
 956         if (ret)
 957                 return ret;
 958
 959         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 960         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 961                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 962
 963                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 964                            i, dev_priv->fence_regs[i].pin_count);
 965                 if (obj == NULL)
 966                         seq_puts(m, "unused");
 967                 else
 968                         describe_obj(m, obj);
 969                 seq_putc(m, '\n');
 970         }
 971
 972         mutex_unlock(&dev->struct_mutex);
 973         return 0;
 974 }
 975
 976 static int i915_hws_info(struct seq_file *m, void *data)
 977 {
 978         struct drm_info_node *node = m->private;
 979         struct drm_device *dev = node->minor->dev;
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981         struct intel_engine_cs *ring;
 982         const u32 *hws;
 983         int i;
 984
 985         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 986         hws = ring->status_page.page_addr;
 987         if (hws == NULL)
 988                 return 0;
 989
 990         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 991                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 992                            i * 4,
 993                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 994         }
 995         return 0;
 996 }
 997
 998 static ssize_t
 999 i915_error_state_write(struct file *filp,
1000                        const char __user *ubuf,
1001                        size_t cnt,
1002                        loff_t *ppos)
1003 {
1004         struct i915_error_state_file_priv *error_priv = filp->private_data;
1005         struct drm_device *dev = error_priv->dev;
1006         int ret;
1007
1008         DRM_DEBUG_DRIVER("Resetting error state\n");
1009
1010         ret = mutex_lock_interruptible(&dev->struct_mutex);
1011         if (ret)
1012                 return ret;
1013
1014         i915_destroy_error_state(dev);
1015         mutex_unlock(&dev->struct_mutex);
1016
1017         return cnt;
1018 }
1019
1020 static int i915_error_state_open(struct inode *inode, struct file *file)
1021 {
1022         struct drm_device *dev = inode->i_private;
1023         struct i915_error_state_file_priv *error_priv;
1024
1025         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1026         if (!error_priv)
1027                 return -ENOMEM;
1028
1029         error_priv->dev = dev;
1030
1031         i915_error_state_get(dev, error_priv);
1032
1033         file->private_data = error_priv;
1034
1035         return 0;
1036 }
1037
1038 static int i915_error_state_release(struct inode *inode, struct file *file)
1039 {
1040         struct i915_error_state_file_priv *error_priv = file->private_data;
1041
1042         i915_error_state_put(error_priv);
1043         kfree(error_priv);
1044
1045         return 0;
1046 }
1047
1048 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049                                      size_t count, loff_t *pos)
1050 {
1051         struct i915_error_state_file_priv *error_priv = file->private_data;
1052         struct drm_i915_error_state_buf error_str;
1053         loff_t tmp_pos = 0;
1054         ssize_t ret_count = 0;
1055         int ret;
1056
1057         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1058         if (ret)
1059                 return ret;
1060
1061         ret = i915_error_state_to_str(&error_str, error_priv);
1062         if (ret)
1063                 goto out;
1064
1065         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1066                                             error_str.buf,
1067                                             error_str.bytes);
1068
1069         if (ret_count < 0)
1070                 ret = ret_count;
1071         else
1072                 *pos = error_str.start + ret_count;
1073 out:
1074         i915_error_state_buf_release(&error_str);
1075         return ret ?: ret_count;
1076 }
1077
1078 static const struct file_operations i915_error_state_fops = {
1079         .owner = THIS_MODULE,
1080         .open = i915_error_state_open,
1081         .read = i915_error_state_read,
1082         .write = i915_error_state_write,
1083         .llseek = default_llseek,
1084         .release = i915_error_state_release,
1085 };
1086
1087 static int
1088 i915_next_seqno_get(void *data, u64 *val)
1089 {
1090         struct drm_device *dev = data;
1091         struct drm_i915_private *dev_priv = dev->dev_private;
1092         int ret;
1093
1094         ret = mutex_lock_interruptible(&dev->struct_mutex);
1095         if (ret)
1096                 return ret;
1097
1098         *val = dev_priv->next_seqno;
1099         mutex_unlock(&dev->struct_mutex);
1100
1101         return 0;
1102 }
1103
1104 static int
1105 i915_next_seqno_set(void *data, u64 val)
1106 {
1107         struct drm_device *dev = data;
1108         int ret;
1109
1110         ret = mutex_lock_interruptible(&dev->struct_mutex);
1111         if (ret)
1112                 return ret;
1113
1114         ret = i915_gem_set_seqno(dev, val);
1115         mutex_unlock(&dev->struct_mutex);
1116
1117         return ret;
1118 }
1119
1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121                         i915_next_seqno_get, i915_next_seqno_set,
1122                         "0x%llx\n");
1123
1124 static int i915_frequency_info(struct seq_file *m, void *unused)
1125 {
1126         struct drm_info_node *node = m->private;
1127         struct drm_device *dev = node->minor->dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129         int ret = 0;
1130
1131         intel_runtime_pm_get(dev_priv);
1132
1133         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1134
1135         if (IS_GEN5(dev)) {
1136                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1138
1139                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1142                            MEMSTAT_VID_SHIFT);
1143                 seq_printf(m, "Current P-state: %d\n",
1144                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1145         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1146                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1147                 u32 rp_state_limits;
1148                 u32 gt_perf_status;
1149                 u32 rp_state_cap;
1150                 u32 rpmodectl, rpinclimit, rpdeclimit;
1151                 u32 rpstat, cagf, reqf;
1152                 u32 rpupei, rpcurup, rpprevup;
1153                 u32 rpdownei, rpcurdown, rpprevdown;
1154                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1155                 int max_freq;
1156
1157                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1158                 if (IS_BROXTON(dev)) {
1159                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1160                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1161                 } else {
1162                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1163                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1164                 }
1165
1166                 /* RPSTAT1 is in the GT power well */
1167                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1168                 if (ret)
1169                         goto out;
1170
1171                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1172
1173                 reqf = I915_READ(GEN6_RPNSWREQ);
1174                 if (IS_GEN9(dev))
1175                         reqf >>= 23;
1176                 else {
1177                         reqf &= ~GEN6_TURBO_DISABLE;
1178                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1179                                 reqf >>= 24;
1180                         else
1181                                 reqf >>= 25;
1182                 }
1183                 reqf = intel_gpu_freq(dev_priv, reqf);
1184
1185                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1186                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1187                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1188
1189                 rpstat = I915_READ(GEN6_RPSTAT1);
1190                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1191                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1192                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1193                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1194                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1195                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1196                 if (IS_GEN9(dev))
1197                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1198                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1199                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1200                 else
1201                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1202                 cagf = intel_gpu_freq(dev_priv, cagf);
1203
1204                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1205                 mutex_unlock(&dev->struct_mutex);
1206
1207                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1208                         pm_ier = I915_READ(GEN6_PMIER);
1209                         pm_imr = I915_READ(GEN6_PMIMR);
1210                         pm_isr = I915_READ(GEN6_PMISR);
1211                         pm_iir = I915_READ(GEN6_PMIIR);
1212                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1213                 } else {
1214                         pm_ier = I915_READ(GEN8_GT_IER(2));
1215                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1216                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1217                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1218                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1219                 }
1220                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1222                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1223                 seq_printf(m, "Render p-state ratio: %d\n",
1224                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1225                 seq_printf(m, "Render p-state VID: %d\n",
1226                            gt_perf_status & 0xff);
1227                 seq_printf(m, "Render p-state limit: %d\n",
1228                            rp_state_limits & 0xff);
1229                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1230                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1231                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1232                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1233                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1234                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1235                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1236                            GEN6_CURICONT_MASK);
1237                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1238                            GEN6_CURBSYTAVG_MASK);
1239                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1240                            GEN6_CURBSYTAVG_MASK);
1241                 seq_printf(m, "Up threshold: %d%%\n",
1242                            dev_priv->rps.up_threshold);
1243
1244                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1245                            GEN6_CURIAVG_MASK);
1246                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1247                            GEN6_CURBSYTAVG_MASK);
1248                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1249                            GEN6_CURBSYTAVG_MASK);
1250                 seq_printf(m, "Down threshold: %d%%\n",
1251                            dev_priv->rps.down_threshold);
1252
1253                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1254                             rp_state_cap >> 16) & 0xff;
1255                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1256                              GEN9_FREQ_SCALER : 1);
1257                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1258                            intel_gpu_freq(dev_priv, max_freq));
1259
1260                 max_freq = (rp_state_cap & 0xff00) >> 8;
1261                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1262                              GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265
1266                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267                             rp_state_cap >> 0) & 0xff;
1268                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1269                              GEN9_FREQ_SCALER : 1);
1270                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1271                            intel_gpu_freq(dev_priv, max_freq));
1272                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1274
1275                 seq_printf(m, "Current freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1277                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1278                 seq_printf(m, "Idle freq: %d MHz\n",
1279                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1280                 seq_printf(m, "Min freq: %d MHz\n",
1281                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1282                 seq_printf(m, "Max freq: %d MHz\n",
1283                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1284                 seq_printf(m,
1285                            "efficient (RPe) frequency: %d MHz\n",
1286                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1287         } else if (IS_VALLEYVIEW(dev)) {
1288                 u32 freq_sts;
1289
1290                 mutex_lock(&dev_priv->rps.hw_lock);
1291                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1292                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1293                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1294
1295                 seq_printf(m, "actual GPU freq: %d MHz\n",
1296                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1297
1298                 seq_printf(m, "current GPU freq: %d MHz\n",
1299                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1300
1301                 seq_printf(m, "max GPU freq: %d MHz\n",
1302                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304                 seq_printf(m, "min GPU freq: %d MHz\n",
1305                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1306
1307                 seq_printf(m, "idle GPU freq: %d MHz\n",
1308                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309
1310                 seq_printf(m,
1311                            "efficient (RPe) frequency: %d MHz\n",
1312                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1313                 mutex_unlock(&dev_priv->rps.hw_lock);
1314         } else {
1315                 seq_puts(m, "no P-state info available\n");
1316         }
1317
1318         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1319         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1320         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1321
1322 out:
1323         intel_runtime_pm_put(dev_priv);
1324         return ret;
1325 }
1326
1327 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1328 {
1329         struct drm_info_node *node = m->private;
1330         struct drm_device *dev = node->minor->dev;
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         struct intel_engine_cs *ring;
1333         u64 acthd[I915_NUM_RINGS];
1334         u32 seqno[I915_NUM_RINGS];
1335         int i;
1336
1337         if (!i915.enable_hangcheck) {
1338                 seq_printf(m, "Hangcheck disabled\n");
1339                 return 0;
1340         }
1341
1342         intel_runtime_pm_get(dev_priv);
1343
1344         for_each_ring(ring, dev_priv, i) {
1345                 seqno[i] = ring->get_seqno(ring, false);
1346                 acthd[i] = intel_ring_get_active_head(ring);
1347         }
1348
1349         intel_runtime_pm_put(dev_priv);
1350
1351         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1352                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1353                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1354                                             jiffies));
1355         } else
1356                 seq_printf(m, "Hangcheck inactive\n");
1357
1358         for_each_ring(ring, dev_priv, i) {
1359                 seq_printf(m, "%s:\n", ring->name);
1360                 seq_printf(m, "\tseqno = %x [current %x]\n",
1361                            ring->hangcheck.seqno, seqno[i]);
1362                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1363                            (long long)ring->hangcheck.acthd,
1364                            (long long)acthd[i]);
1365                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1366                            (long long)ring->hangcheck.max_acthd);
1367                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1368                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ironlake_drpc_info(struct seq_file *m)
1375 {
1376         struct drm_info_node *node = m->private;
1377         struct drm_device *dev = node->minor->dev;
1378         struct drm_i915_private *dev_priv = dev->dev_private;
1379         u32 rgvmodectl, rstdbyctl;
1380         u16 crstandvid;
1381         int ret;
1382
1383         ret = mutex_lock_interruptible(&dev->struct_mutex);
1384         if (ret)
1385                 return ret;
1386         intel_runtime_pm_get(dev_priv);
1387
1388         rgvmodectl = I915_READ(MEMMODECTL);
1389         rstdbyctl = I915_READ(RSTDBYCTL);
1390         crstandvid = I915_READ16(CRSTANDVID);
1391
1392         intel_runtime_pm_put(dev_priv);
1393         mutex_unlock(&dev->struct_mutex);
1394
1395         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1396         seq_printf(m, "Boost freq: %d\n",
1397                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1398                    MEMMODE_BOOST_FREQ_SHIFT);
1399         seq_printf(m, "HW control enabled: %s\n",
1400                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1401         seq_printf(m, "SW control enabled: %s\n",
1402                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1403         seq_printf(m, "Gated voltage change: %s\n",
1404                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1405         seq_printf(m, "Starting frequency: P%d\n",
1406                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1407         seq_printf(m, "Max P-state: P%d\n",
1408                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1409         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1410         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1411         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1412         seq_printf(m, "Render standby enabled: %s\n",
1413                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1414         seq_puts(m, "Current RS state: ");
1415         switch (rstdbyctl & RSX_STATUS_MASK) {
1416         case RSX_STATUS_ON:
1417                 seq_puts(m, "on\n");
1418                 break;
1419         case RSX_STATUS_RC1:
1420                 seq_puts(m, "RC1\n");
1421                 break;
1422         case RSX_STATUS_RC1E:
1423                 seq_puts(m, "RC1E\n");
1424                 break;
1425         case RSX_STATUS_RS1:
1426                 seq_puts(m, "RS1\n");
1427                 break;
1428         case RSX_STATUS_RS2:
1429                 seq_puts(m, "RS2 (RC6)\n");
1430                 break;
1431         case RSX_STATUS_RS3:
1432                 seq_puts(m, "RC3 (RC6+)\n");
1433                 break;
1434         default:
1435                 seq_puts(m, "unknown\n");
1436                 break;
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int i915_forcewake_domains(struct seq_file *m, void *data)
1443 {
1444         struct drm_info_node *node = m->private;
1445         struct drm_device *dev = node->minor->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         struct intel_uncore_forcewake_domain *fw_domain;
1448         int i;
1449
1450         spin_lock_irq(&dev_priv->uncore.lock);
1451         for_each_fw_domain(fw_domain, dev_priv, i) {
1452                 seq_printf(m, "%s.wake_count = %u\n",
1453                            intel_uncore_forcewake_domain_to_str(i),
1454                            fw_domain->wake_count);
1455         }
1456         spin_unlock_irq(&dev_priv->uncore.lock);
1457
1458         return 0;
1459 }
1460
1461 static int vlv_drpc_info(struct seq_file *m)
1462 {
1463         struct drm_info_node *node = m->private;
1464         struct drm_device *dev = node->minor->dev;
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         u32 rpmodectl1, rcctl1, pw_status;
1467
1468         intel_runtime_pm_get(dev_priv);
1469
1470         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1471         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1472         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1473
1474         intel_runtime_pm_put(dev_priv);
1475
1476         seq_printf(m, "Video Turbo Mode: %s\n",
1477                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1478         seq_printf(m, "Turbo enabled: %s\n",
1479                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1480         seq_printf(m, "HW control enabled: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1482         seq_printf(m, "SW control enabled: %s\n",
1483                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1484                           GEN6_RP_MEDIA_SW_MODE));
1485         seq_printf(m, "RC6 Enabled: %s\n",
1486                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1487                                         GEN6_RC_CTL_EI_MODE(1))));
1488         seq_printf(m, "Render Power Well: %s\n",
1489                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1490         seq_printf(m, "Media Power Well: %s\n",
1491                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1492
1493         seq_printf(m, "Render RC6 residency since boot: %u\n",
1494                    I915_READ(VLV_GT_RENDER_RC6));
1495         seq_printf(m, "Media RC6 residency since boot: %u\n",
1496                    I915_READ(VLV_GT_MEDIA_RC6));
1497
1498         return i915_forcewake_domains(m, NULL);
1499 }
1500
1501 static int gen6_drpc_info(struct seq_file *m)
1502 {
1503         struct drm_info_node *node = m->private;
1504         struct drm_device *dev = node->minor->dev;
1505         struct drm_i915_private *dev_priv = dev->dev_private;
1506         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1507         unsigned forcewake_count;
1508         int count = 0, ret;
1509
1510         ret = mutex_lock_interruptible(&dev->struct_mutex);
1511         if (ret)
1512                 return ret;
1513         intel_runtime_pm_get(dev_priv);
1514
1515         spin_lock_irq(&dev_priv->uncore.lock);
1516         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1517         spin_unlock_irq(&dev_priv->uncore.lock);
1518
1519         if (forcewake_count) {
1520                 seq_puts(m, "RC information inaccurate because somebody "
1521                             "holds a forcewake reference \n");
1522         } else {
1523                 /* NB: we cannot use forcewake, else we read the wrong values */
1524                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1525                         udelay(10);
1526                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1527         }
1528
1529         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1530         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1531
1532         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1533         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1534         mutex_unlock(&dev->struct_mutex);
1535         mutex_lock(&dev_priv->rps.hw_lock);
1536         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1537         mutex_unlock(&dev_priv->rps.hw_lock);
1538
1539         intel_runtime_pm_put(dev_priv);
1540
1541         seq_printf(m, "Video Turbo Mode: %s\n",
1542                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1543         seq_printf(m, "HW control enabled: %s\n",
1544                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1545         seq_printf(m, "SW control enabled: %s\n",
1546                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1547                           GEN6_RP_MEDIA_SW_MODE));
1548         seq_printf(m, "RC1e Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1550         seq_printf(m, "RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1552         seq_printf(m, "Deep RC6 Enabled: %s\n",
1553                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1554         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1555                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1556         seq_puts(m, "Current RC state: ");
1557         switch (gt_core_status & GEN6_RCn_MASK) {
1558         case GEN6_RC0:
1559                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1560                         seq_puts(m, "Core Power Down\n");
1561                 else
1562                         seq_puts(m, "on\n");
1563                 break;
1564         case GEN6_RC3:
1565                 seq_puts(m, "RC3\n");
1566                 break;
1567         case GEN6_RC6:
1568                 seq_puts(m, "RC6\n");
1569                 break;
1570         case GEN6_RC7:
1571                 seq_puts(m, "RC7\n");
1572                 break;
1573         default:
1574                 seq_puts(m, "Unknown\n");
1575                 break;
1576         }
1577
1578         seq_printf(m, "Core Power Down: %s\n",
1579                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1580
1581         /* Not exactly sure what this is */
1582         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1583                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1584         seq_printf(m, "RC6 residency since boot: %u\n",
1585                    I915_READ(GEN6_GT_GFX_RC6));
1586         seq_printf(m, "RC6+ residency since boot: %u\n",
1587                    I915_READ(GEN6_GT_GFX_RC6p));
1588         seq_printf(m, "RC6++ residency since boot: %u\n",
1589                    I915_READ(GEN6_GT_GFX_RC6pp));
1590
1591         seq_printf(m, "RC6   voltage: %dmV\n",
1592                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1593         seq_printf(m, "RC6+  voltage: %dmV\n",
1594                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1595         seq_printf(m, "RC6++ voltage: %dmV\n",
1596                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1597         return 0;
1598 }
1599
1600 static int i915_drpc_info(struct seq_file *m, void *unused)
1601 {
1602         struct drm_info_node *node = m->private;
1603         struct drm_device *dev = node->minor->dev;
1604
1605         if (IS_VALLEYVIEW(dev))
1606                 return vlv_drpc_info(m);
1607         else if (INTEL_INFO(dev)->gen >= 6)
1608                 return gen6_drpc_info(m);
1609         else
1610                 return ironlake_drpc_info(m);
1611 }
1612
1613 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1614 {
1615         struct drm_info_node *node = m->private;
1616         struct drm_device *dev = node->minor->dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1620                    dev_priv->fb_tracking.busy_bits);
1621
1622         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1623                    dev_priv->fb_tracking.flip_bits);
1624
1625         return 0;
1626 }
1627
1628 static int i915_fbc_status(struct seq_file *m, void *unused)
1629 {
1630         struct drm_info_node *node = m->private;
1631         struct drm_device *dev = node->minor->dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634         if (!HAS_FBC(dev)) {
1635                 seq_puts(m, "FBC unsupported on this chipset\n");
1636                 return 0;
1637         }
1638
1639         intel_runtime_pm_get(dev_priv);
1640         mutex_lock(&dev_priv->fbc.lock);
1641
1642         if (intel_fbc_enabled(dev_priv))
1643                 seq_puts(m, "FBC enabled\n");
1644         else
1645                 seq_printf(m, "FBC disabled: %s\n",
1646                            dev_priv->fbc.no_fbc_reason);
1647
1648         if (INTEL_INFO(dev_priv)->gen >= 7)
1649                 seq_printf(m, "Compressing: %s\n",
1650                            yesno(I915_READ(FBC_STATUS2) &
1651                                  FBC_COMPRESSION_MASK));
1652
1653         mutex_unlock(&dev_priv->fbc.lock);
1654         intel_runtime_pm_put(dev_priv);
1655
1656         return 0;
1657 }
1658
1659 static int i915_fbc_fc_get(void *data, u64 *val)
1660 {
1661         struct drm_device *dev = data;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1665                 return -ENODEV;
1666
1667         *val = dev_priv->fbc.false_color;
1668
1669         return 0;
1670 }
1671
1672 static int i915_fbc_fc_set(void *data, u64 val)
1673 {
1674         struct drm_device *dev = data;
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676         u32 reg;
1677
1678         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1679                 return -ENODEV;
1680
1681         mutex_lock(&dev_priv->fbc.lock);
1682
1683         reg = I915_READ(ILK_DPFC_CONTROL);
1684         dev_priv->fbc.false_color = val;
1685
1686         I915_WRITE(ILK_DPFC_CONTROL, val ?
1687                    (reg | FBC_CTL_FALSE_COLOR) :
1688                    (reg & ~FBC_CTL_FALSE_COLOR));
1689
1690         mutex_unlock(&dev_priv->fbc.lock);
1691         return 0;
1692 }
1693
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695                         i915_fbc_fc_get, i915_fbc_fc_set,
1696                         "%llu\n");
1697
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1699 {
1700         struct drm_info_node *node = m->private;
1701         struct drm_device *dev = node->minor->dev;
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703
1704         if (!HAS_IPS(dev)) {
1705                 seq_puts(m, "not supported\n");
1706                 return 0;
1707         }
1708
1709         intel_runtime_pm_get(dev_priv);
1710
1711         seq_printf(m, "Enabled by kernel parameter: %s\n",
1712                    yesno(i915.enable_ips));
1713
1714         if (INTEL_INFO(dev)->gen >= 8) {
1715                 seq_puts(m, "Currently: unknown\n");
1716         } else {
1717                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1718                         seq_puts(m, "Currently: enabled\n");
1719                 else
1720                         seq_puts(m, "Currently: disabled\n");
1721         }
1722
1723         intel_runtime_pm_put(dev_priv);
1724
1725         return 0;
1726 }
1727
1728 static int i915_sr_status(struct seq_file *m, void *unused)
1729 {
1730         struct drm_info_node *node = m->private;
1731         struct drm_device *dev = node->minor->dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         bool sr_enabled = false;
1734
1735         intel_runtime_pm_get(dev_priv);
1736
1737         if (HAS_PCH_SPLIT(dev))
1738                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1739         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1740                  IS_I945G(dev) || IS_I945GM(dev))
1741                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1742         else if (IS_I915GM(dev))
1743                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1744         else if (IS_PINEVIEW(dev))
1745                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1746         else if (IS_VALLEYVIEW(dev))
1747                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1748
1749         intel_runtime_pm_put(dev_priv);
1750
1751         seq_printf(m, "self-refresh: %s\n",
1752                    sr_enabled ? "enabled" : "disabled");
1753
1754         return 0;
1755 }
1756
1757 static int i915_emon_status(struct seq_file *m, void *unused)
1758 {
1759         struct drm_info_node *node = m->private;
1760         struct drm_device *dev = node->minor->dev;
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762         unsigned long temp, chipset, gfx;
1763         int ret;
1764
1765         if (!IS_GEN5(dev))
1766                 return -ENODEV;
1767
1768         ret = mutex_lock_interruptible(&dev->struct_mutex);
1769         if (ret)
1770                 return ret;
1771
1772         temp = i915_mch_val(dev_priv);
1773         chipset = i915_chipset_val(dev_priv);
1774         gfx = i915_gfx_val(dev_priv);
1775         mutex_unlock(&dev->struct_mutex);
1776
1777         seq_printf(m, "GMCH temp: %ld\n", temp);
1778         seq_printf(m, "Chipset power: %ld\n", chipset);
1779         seq_printf(m, "GFX power: %ld\n", gfx);
1780         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1781
1782         return 0;
1783 }
1784
1785 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1786 {
1787         struct drm_info_node *node = m->private;
1788         struct drm_device *dev = node->minor->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         int ret = 0;
1791         int gpu_freq, ia_freq;
1792         unsigned int max_gpu_freq, min_gpu_freq;
1793
1794         if (!HAS_CORE_RING_FREQ(dev)) {
1795                 seq_puts(m, "unsupported on this chipset\n");
1796                 return 0;
1797         }
1798
1799         intel_runtime_pm_get(dev_priv);
1800
1801         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1802
1803         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1804         if (ret)
1805                 goto out;
1806
1807         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1808                 /* Convert GT frequency to 50 HZ units */
1809                 min_gpu_freq =
1810                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1811                 max_gpu_freq =
1812                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1813         } else {
1814                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1815                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1816         }
1817
1818         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1819
1820         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1821                 ia_freq = gpu_freq;
1822                 sandybridge_pcode_read(dev_priv,
1823                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1824                                        &ia_freq);
1825                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1826                            intel_gpu_freq(dev_priv, (gpu_freq *
1827                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1828                                  GEN9_FREQ_SCALER : 1))),
1829                            ((ia_freq >> 0) & 0xff) * 100,
1830                            ((ia_freq >> 8) & 0xff) * 100);
1831         }
1832
1833         mutex_unlock(&dev_priv->rps.hw_lock);
1834
1835 out:
1836         intel_runtime_pm_put(dev_priv);
1837         return ret;
1838 }
1839
1840 static int i915_opregion(struct seq_file *m, void *unused)
1841 {
1842         struct drm_info_node *node = m->private;
1843         struct drm_device *dev = node->minor->dev;
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         struct intel_opregion *opregion = &dev_priv->opregion;
1846         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1847         int ret;
1848
1849         if (data == NULL)
1850                 return -ENOMEM;
1851
1852         ret = mutex_lock_interruptible(&dev->struct_mutex);
1853         if (ret)
1854                 goto out;
1855
1856         if (opregion->header) {
1857                 memcpy(data, opregion->header, OPREGION_SIZE);
1858                 seq_write(m, data, OPREGION_SIZE);
1859         }
1860
1861         mutex_unlock(&dev->struct_mutex);
1862
1863 out:
1864         kfree(data);
1865         return 0;
1866 }
1867
1868 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1869 {
1870         struct drm_info_node *node = m->private;
1871         struct drm_device *dev = node->minor->dev;
1872         struct intel_fbdev *ifbdev = NULL;
1873         struct intel_framebuffer *fb;
1874         struct drm_framebuffer *drm_fb;
1875
1876 #ifdef CONFIG_DRM_FBDEV_EMULATION
1877         struct drm_i915_private *dev_priv = dev->dev_private;
1878
1879         ifbdev = dev_priv->fbdev;
1880         if (ifbdev) {
1881                 fb = to_intel_framebuffer(ifbdev->helper.fb);
1882
1883                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1884                            fb->base.width,
1885                            fb->base.height,
1886                            fb->base.depth,
1887                            fb->base.bits_per_pixel,
1888                            fb->base.modifier[0],
1889                            atomic_read(&fb->base.refcount.refcount));
1890                 describe_obj(m, fb->obj);
1891                 seq_putc(m, '\n');
1892         }
1893 #endif
1894
1895         mutex_lock(&dev->mode_config.fb_lock);
1896         drm_for_each_fb(drm_fb, dev) {
1897                 fb = to_intel_framebuffer(drm_fb);
1898                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1899                         continue;
1900
1901                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1902                            fb->base.width,
1903                            fb->base.height,
1904                            fb->base.depth,
1905                            fb->base.bits_per_pixel,
1906                            fb->base.modifier[0],
1907                            atomic_read(&fb->base.refcount.refcount));
1908                 describe_obj(m, fb->obj);
1909                 seq_putc(m, '\n');
1910         }
1911         mutex_unlock(&dev->mode_config.fb_lock);
1912
1913         return 0;
1914 }
1915
1916 static void describe_ctx_ringbuf(struct seq_file *m,
1917                                  struct intel_ringbuffer *ringbuf)
1918 {
1919         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1920                    ringbuf->space, ringbuf->head, ringbuf->tail,
1921                    ringbuf->last_retired_head);
1922 }
1923
1924 static int i915_context_status(struct seq_file *m, void *unused)
1925 {
1926         struct drm_info_node *node = m->private;
1927         struct drm_device *dev = node->minor->dev;
1928         struct drm_i915_private *dev_priv = dev->dev_private;
1929         struct intel_engine_cs *ring;
1930         struct intel_context *ctx;
1931         int ret, i;
1932
1933         ret = mutex_lock_interruptible(&dev->struct_mutex);
1934         if (ret)
1935                 return ret;
1936
1937         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1938                 if (!i915.enable_execlists &&
1939                     ctx->legacy_hw_ctx.rcs_state == NULL)
1940                         continue;
1941
1942                 seq_puts(m, "HW context ");
1943                 describe_ctx(m, ctx);
1944                 for_each_ring(ring, dev_priv, i) {
1945                         if (ring->default_context == ctx)
1946                                 seq_printf(m, "(default context %s) ",
1947                                            ring->name);
1948                 }
1949
1950                 if (i915.enable_execlists) {
1951                         seq_putc(m, '\n');
1952                         for_each_ring(ring, dev_priv, i) {
1953                                 struct drm_i915_gem_object *ctx_obj =
1954                                         ctx->engine[i].state;
1955                                 struct intel_ringbuffer *ringbuf =
1956                                         ctx->engine[i].ringbuf;
1957
1958                                 seq_printf(m, "%s: ", ring->name);
1959                                 if (ctx_obj)
1960                                         describe_obj(m, ctx_obj);
1961                                 if (ringbuf)
1962                                         describe_ctx_ringbuf(m, ringbuf);
1963                                 seq_putc(m, '\n');
1964                         }
1965                 } else {
1966                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1967                 }
1968
1969                 seq_putc(m, '\n');
1970         }
1971
1972         mutex_unlock(&dev->struct_mutex);
1973
1974         return 0;
1975 }
1976
1977 static void i915_dump_lrc_obj(struct seq_file *m,
1978                               struct intel_engine_cs *ring,
1979                               struct drm_i915_gem_object *ctx_obj)
1980 {
1981         struct page *page;
1982         uint32_t *reg_state;
1983         int j;
1984         unsigned long ggtt_offset = 0;
1985
1986         if (ctx_obj == NULL) {
1987                 seq_printf(m, "Context on %s with no gem object\n",
1988                            ring->name);
1989                 return;
1990         }
1991
1992         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1993                    intel_execlists_ctx_id(ctx_obj));
1994
1995         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1996                 seq_puts(m, "\tNot bound in GGTT\n");
1997         else
1998                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1999
2000         if (i915_gem_object_get_pages(ctx_obj)) {
2001                 seq_puts(m, "\tFailed to get pages for context object\n");
2002                 return;
2003         }
2004
2005         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2006         if (!WARN_ON(page == NULL)) {
2007                 reg_state = kmap_atomic(page);
2008
2009                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2010                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2011                                    ggtt_offset + 4096 + (j * 4),
2012                                    reg_state[j], reg_state[j + 1],
2013                                    reg_state[j + 2], reg_state[j + 3]);
2014                 }
2015                 kunmap_atomic(reg_state);
2016         }
2017
2018         seq_putc(m, '\n');
2019 }
2020
2021 static int i915_dump_lrc(struct seq_file *m, void *unused)
2022 {
2023         struct drm_info_node *node = (struct drm_info_node *) m->private;
2024         struct drm_device *dev = node->minor->dev;
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         struct intel_engine_cs *ring;
2027         struct intel_context *ctx;
2028         int ret, i;
2029
2030         if (!i915.enable_execlists) {
2031                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2032                 return 0;
2033         }
2034
2035         ret = mutex_lock_interruptible(&dev->struct_mutex);
2036         if (ret)
2037                 return ret;
2038
2039         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2040                 for_each_ring(ring, dev_priv, i) {
2041                         if (ring->default_context != ctx)
2042                                 i915_dump_lrc_obj(m, ring,
2043                                                   ctx->engine[i].state);
2044                 }
2045         }
2046
2047         mutex_unlock(&dev->struct_mutex);
2048
2049         return 0;
2050 }
2051
2052 static int i915_execlists(struct seq_file *m, void *data)
2053 {
2054         struct drm_info_node *node = (struct drm_info_node *)m->private;
2055         struct drm_device *dev = node->minor->dev;
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057         struct intel_engine_cs *ring;
2058         u32 status_pointer;
2059         u8 read_pointer;
2060         u8 write_pointer;
2061         u32 status;
2062         u32 ctx_id;
2063         struct list_head *cursor;
2064         int ring_id, i;
2065         int ret;
2066
2067         if (!i915.enable_execlists) {
2068                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2069                 return 0;
2070         }
2071
2072         ret = mutex_lock_interruptible(&dev->struct_mutex);
2073         if (ret)
2074                 return ret;
2075
2076         intel_runtime_pm_get(dev_priv);
2077
2078         for_each_ring(ring, dev_priv, ring_id) {
2079                 struct drm_i915_gem_request *head_req = NULL;
2080                 int count = 0;
2081                 unsigned long flags;
2082
2083                 seq_printf(m, "%s\n", ring->name);
2084
2085                 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2086                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2087                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2088                            status, ctx_id);
2089
2090                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2091                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2092
2093                 read_pointer = ring->next_context_status_buffer;
2094                 write_pointer = status_pointer & 0x07;
2095                 if (read_pointer > write_pointer)
2096                         write_pointer += 6;
2097                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2098                            read_pointer, write_pointer);
2099
2100                 for (i = 0; i < 6; i++) {
2101                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2102                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2103
2104                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2105                                    i, status, ctx_id);
2106                 }
2107
2108                 spin_lock_irqsave(&ring->execlist_lock, flags);
2109                 list_for_each(cursor, &ring->execlist_queue)
2110                         count++;
2111                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2112                                 struct drm_i915_gem_request, execlist_link);
2113                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2114
2115                 seq_printf(m, "\t%d requests in queue\n", count);
2116                 if (head_req) {
2117                         struct drm_i915_gem_object *ctx_obj;
2118
2119                         ctx_obj = head_req->ctx->engine[ring_id].state;
2120                         seq_printf(m, "\tHead request id: %u\n",
2121                                    intel_execlists_ctx_id(ctx_obj));
2122                         seq_printf(m, "\tHead request tail: %u\n",
2123                                    head_req->tail);
2124                 }
2125
2126                 seq_putc(m, '\n');
2127         }
2128
2129         intel_runtime_pm_put(dev_priv);
2130         mutex_unlock(&dev->struct_mutex);
2131
2132         return 0;
2133 }
2134
2135 static const char *swizzle_string(unsigned swizzle)
2136 {
2137         switch (swizzle) {
2138         case I915_BIT_6_SWIZZLE_NONE:
2139                 return "none";
2140         case I915_BIT_6_SWIZZLE_9:
2141                 return "bit9";
2142         case I915_BIT_6_SWIZZLE_9_10:
2143                 return "bit9/bit10";
2144         case I915_BIT_6_SWIZZLE_9_11:
2145                 return "bit9/bit11";
2146         case I915_BIT_6_SWIZZLE_9_10_11:
2147                 return "bit9/bit10/bit11";
2148         case I915_BIT_6_SWIZZLE_9_17:
2149                 return "bit9/bit17";
2150         case I915_BIT_6_SWIZZLE_9_10_17:
2151                 return "bit9/bit10/bit17";
2152         case I915_BIT_6_SWIZZLE_UNKNOWN:
2153                 return "unknown";
2154         }
2155
2156         return "bug";
2157 }
2158
2159 static int i915_swizzle_info(struct seq_file *m, void *data)
2160 {
2161         struct drm_info_node *node = m->private;
2162         struct drm_device *dev = node->minor->dev;
2163         struct drm_i915_private *dev_priv = dev->dev_private;
2164         int ret;
2165
2166         ret = mutex_lock_interruptible(&dev->struct_mutex);
2167         if (ret)
2168                 return ret;
2169         intel_runtime_pm_get(dev_priv);
2170
2171         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2172                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2173         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2174                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2175
2176         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2177                 seq_printf(m, "DDC = 0x%08x\n",
2178                            I915_READ(DCC));
2179                 seq_printf(m, "DDC2 = 0x%08x\n",
2180                            I915_READ(DCC2));
2181                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2182                            I915_READ16(C0DRB3));
2183                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2184                            I915_READ16(C1DRB3));
2185         } else if (INTEL_INFO(dev)->gen >= 6) {
2186                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2187                            I915_READ(MAD_DIMM_C0));
2188                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2189                            I915_READ(MAD_DIMM_C1));
2190                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2191                            I915_READ(MAD_DIMM_C2));
2192                 seq_printf(m, "TILECTL = 0x%08x\n",
2193                            I915_READ(TILECTL));
2194                 if (INTEL_INFO(dev)->gen >= 8)
2195                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2196                                    I915_READ(GAMTARBMODE));
2197                 else
2198                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2199                                    I915_READ(ARB_MODE));
2200                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2201                            I915_READ(DISP_ARB_CTL));
2202         }
2203
2204         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2205                 seq_puts(m, "L-shaped memory detected\n");
2206
2207         intel_runtime_pm_put(dev_priv);
2208         mutex_unlock(&dev->struct_mutex);
2209
2210         return 0;
2211 }
2212
2213 static int per_file_ctx(int id, void *ptr, void *data)
2214 {
2215         struct intel_context *ctx = ptr;
2216         struct seq_file *m = data;
2217         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2218
2219         if (!ppgtt) {
2220                 seq_printf(m, "  no ppgtt for context %d\n",
2221                            ctx->user_handle);
2222                 return 0;
2223         }
2224
2225         if (i915_gem_context_is_default(ctx))
2226                 seq_puts(m, "  default context:\n");
2227         else
2228                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2229         ppgtt->debug_dump(ppgtt, m);
2230
2231         return 0;
2232 }
2233
2234 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2235 {
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         struct intel_engine_cs *ring;
2238         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2239         int unused, i;
2240
2241         if (!ppgtt)
2242                 return;
2243
2244         for_each_ring(ring, dev_priv, unused) {
2245                 seq_printf(m, "%s\n", ring->name);
2246                 for (i = 0; i < 4; i++) {
2247                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2248                         pdp <<= 32;
2249                         pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2250                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2251                 }
2252         }
2253 }
2254
2255 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2256 {
2257         struct drm_i915_private *dev_priv = dev->dev_private;
2258         struct intel_engine_cs *ring;
2259         int i;
2260
2261         if (INTEL_INFO(dev)->gen == 6)
2262                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2263
2264         for_each_ring(ring, dev_priv, i) {
2265                 seq_printf(m, "%s\n", ring->name);
2266                 if (INTEL_INFO(dev)->gen == 7)
2267                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2268                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2269                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2270                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2271         }
2272         if (dev_priv->mm.aliasing_ppgtt) {
2273                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2274
2275                 seq_puts(m, "aliasing PPGTT:\n");
2276                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2277
2278                 ppgtt->debug_dump(ppgtt, m);
2279         }
2280
2281         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2282 }
2283
2284 static int i915_ppgtt_info(struct seq_file *m, void *data)
2285 {
2286         struct drm_info_node *node = m->private;
2287         struct drm_device *dev = node->minor->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct drm_file *file;
2290
2291         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2292         if (ret)
2293                 return ret;
2294         intel_runtime_pm_get(dev_priv);
2295
2296         if (INTEL_INFO(dev)->gen >= 8)
2297                 gen8_ppgtt_info(m, dev);
2298         else if (INTEL_INFO(dev)->gen >= 6)
2299                 gen6_ppgtt_info(m, dev);
2300
2301         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2302                 struct drm_i915_file_private *file_priv = file->driver_priv;
2303                 struct task_struct *task;
2304
2305                 task = get_pid_task(file->pid, PIDTYPE_PID);
2306                 if (!task) {
2307                         ret = -ESRCH;
2308                         goto out_put;
2309                 }
2310                 seq_printf(m, "\nproc: %s\n", task->comm);
2311                 put_task_struct(task);
2312                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2313                              (void *)(unsigned long)m);
2314         }
2315
2316 out_put:
2317         intel_runtime_pm_put(dev_priv);
2318         mutex_unlock(&dev->struct_mutex);
2319
2320         return ret;
2321 }
2322
2323 static int count_irq_waiters(struct drm_i915_private *i915)
2324 {
2325         struct intel_engine_cs *ring;
2326         int count = 0;
2327         int i;
2328
2329         for_each_ring(ring, i915, i)
2330                 count += ring->irq_refcount;
2331
2332         return count;
2333 }
2334
2335 static int i915_rps_boost_info(struct seq_file *m, void *data)
2336 {
2337         struct drm_info_node *node = m->private;
2338         struct drm_device *dev = node->minor->dev;
2339         struct drm_i915_private *dev_priv = dev->dev_private;
2340         struct drm_file *file;
2341
2342         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2343         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2344         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2345         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2346                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2347                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2348                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2349                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2350                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2351         spin_lock(&dev_priv->rps.client_lock);
2352         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2353                 struct drm_i915_file_private *file_priv = file->driver_priv;
2354                 struct task_struct *task;
2355
2356                 rcu_read_lock();
2357                 task = pid_task(file->pid, PIDTYPE_PID);
2358                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2359                            task ? task->comm : "<unknown>",
2360                            task ? task->pid : -1,
2361                            file_priv->rps.boosts,
2362                            list_empty(&file_priv->rps.link) ? "" : ", active");
2363                 rcu_read_unlock();
2364         }
2365         seq_printf(m, "Semaphore boosts: %d%s\n",
2366                    dev_priv->rps.semaphores.boosts,
2367                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2368         seq_printf(m, "MMIO flip boosts: %d%s\n",
2369                    dev_priv->rps.mmioflips.boosts,
2370                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2371         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2372         spin_unlock(&dev_priv->rps.client_lock);
2373
2374         return 0;
2375 }
2376
2377 static int i915_llc(struct seq_file *m, void *data)
2378 {
2379         struct drm_info_node *node = m->private;
2380         struct drm_device *dev = node->minor->dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382
2383         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2384         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2385         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2386
2387         return 0;
2388 }
2389
2390 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2391 {
2392         struct drm_info_node *node = m->private;
2393         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2394         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2395         u32 tmp, i;
2396
2397         if (!HAS_GUC_UCODE(dev_priv->dev))
2398                 return 0;
2399
2400         seq_printf(m, "GuC firmware status:\n");
2401         seq_printf(m, "\tpath: %s\n",
2402                 guc_fw->guc_fw_path);
2403         seq_printf(m, "\tfetch: %s\n",
2404                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2405         seq_printf(m, "\tload: %s\n",
2406                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2407         seq_printf(m, "\tversion wanted: %d.%d\n",
2408                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2409         seq_printf(m, "\tversion found: %d.%d\n",
2410                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2411         seq_printf(m, "\theader: offset is %d; size = %d\n",
2412                 guc_fw->header_offset, guc_fw->header_size);
2413         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2414                 guc_fw->ucode_offset, guc_fw->ucode_size);
2415         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2416                 guc_fw->rsa_offset, guc_fw->rsa_size);
2417
2418         tmp = I915_READ(GUC_STATUS);
2419
2420         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2421         seq_printf(m, "\tBootrom status = 0x%x\n",
2422                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2423         seq_printf(m, "\tuKernel status = 0x%x\n",
2424                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2425         seq_printf(m, "\tMIA Core status = 0x%x\n",
2426                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2427         seq_puts(m, "\nScratch registers:\n");
2428         for (i = 0; i < 16; i++)
2429                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2430
2431         return 0;
2432 }
2433
2434 static void i915_guc_client_info(struct seq_file *m,
2435                                  struct drm_i915_private *dev_priv,
2436                                  struct i915_guc_client *client)
2437 {
2438         struct intel_engine_cs *ring;
2439         uint64_t tot = 0;
2440         uint32_t i;
2441
2442         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2443                 client->priority, client->ctx_index, client->proc_desc_offset);
2444         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2445                 client->doorbell_id, client->doorbell_offset, client->cookie);
2446         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2447                 client->wq_size, client->wq_offset, client->wq_tail);
2448
2449         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2450         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2451         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2452
2453         for_each_ring(ring, dev_priv, i) {
2454                 seq_printf(m, "\tSubmissions: %llu %s\n",
2455                                 client->submissions[i],
2456                                 ring->name);
2457                 tot += client->submissions[i];
2458         }
2459         seq_printf(m, "\tTotal: %llu\n", tot);
2460 }
2461
2462 static int i915_guc_info(struct seq_file *m, void *data)
2463 {
2464         struct drm_info_node *node = m->private;
2465         struct drm_device *dev = node->minor->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_guc guc;
2468         struct i915_guc_client client = {};
2469         struct intel_engine_cs *ring;
2470         enum intel_ring_id i;
2471         u64 total = 0;
2472
2473         if (!HAS_GUC_SCHED(dev_priv->dev))
2474                 return 0;
2475
2476         /* Take a local copy of the GuC data, so we can dump it at leisure */
2477         spin_lock(&dev_priv->guc.host2guc_lock);
2478         guc = dev_priv->guc;
2479         if (guc.execbuf_client) {
2480                 spin_lock(&guc.execbuf_client->wq_lock);
2481                 client = *guc.execbuf_client;
2482                 spin_unlock(&guc.execbuf_client->wq_lock);
2483         }
2484         spin_unlock(&dev_priv->guc.host2guc_lock);
2485
2486         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2487         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2488         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2489         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2490         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2491
2492         seq_printf(m, "\nGuC submissions:\n");
2493         for_each_ring(ring, dev_priv, i) {
2494                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2495                         ring->name, guc.submissions[i],
2496                         guc.last_seqno[i], guc.last_seqno[i]);
2497                 total += guc.submissions[i];
2498         }
2499         seq_printf(m, "\t%s: %llu\n", "Total", total);
2500
2501         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2502         i915_guc_client_info(m, dev_priv, &client);
2503
2504         /* Add more as required ... */
2505
2506         return 0;
2507 }
2508
2509 static int i915_guc_log_dump(struct seq_file *m, void *data)
2510 {
2511         struct drm_info_node *node = m->private;
2512         struct drm_device *dev = node->minor->dev;
2513         struct drm_i915_private *dev_priv = dev->dev_private;
2514         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2515         u32 *log;
2516         int i = 0, pg;
2517
2518         if (!log_obj)
2519                 return 0;
2520
2521         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2522                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2523
2524                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2525                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2526                                    *(log + i), *(log + i + 1),
2527                                    *(log + i + 2), *(log + i + 3));
2528
2529                 kunmap_atomic(log);
2530         }
2531
2532         seq_putc(m, '\n');
2533
2534         return 0;
2535 }
2536
2537 static int i915_edp_psr_status(struct seq_file *m, void *data)
2538 {
2539         struct drm_info_node *node = m->private;
2540         struct drm_device *dev = node->minor->dev;
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         u32 psrperf = 0;
2543         u32 stat[3];
2544         enum pipe pipe;
2545         bool enabled = false;
2546
2547         if (!HAS_PSR(dev)) {
2548                 seq_puts(m, "PSR not supported\n");
2549                 return 0;
2550         }
2551
2552         intel_runtime_pm_get(dev_priv);
2553
2554         mutex_lock(&dev_priv->psr.lock);
2555         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2556         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2557         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2558         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2559         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2560                    dev_priv->psr.busy_frontbuffer_bits);
2561         seq_printf(m, "Re-enable work scheduled: %s\n",
2562                    yesno(work_busy(&dev_priv->psr.work.work)));
2563
2564         if (HAS_DDI(dev))
2565                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2566         else {
2567                 for_each_pipe(dev_priv, pipe) {
2568                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2569                                 VLV_EDP_PSR_CURR_STATE_MASK;
2570                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2571                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2572                                 enabled = true;
2573                 }
2574         }
2575         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2576
2577         if (!HAS_DDI(dev))
2578                 for_each_pipe(dev_priv, pipe) {
2579                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2580                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2581                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2582                 }
2583         seq_puts(m, "\n");
2584
2585         /* CHV PSR has no kind of performance counter */
2586         if (HAS_DDI(dev)) {
2587                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2588                         EDP_PSR_PERF_CNT_MASK;
2589
2590                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2591         }
2592         mutex_unlock(&dev_priv->psr.lock);
2593
2594         intel_runtime_pm_put(dev_priv);
2595         return 0;
2596 }
2597
2598 static int i915_sink_crc(struct seq_file *m, void *data)
2599 {
2600         struct drm_info_node *node = m->private;
2601         struct drm_device *dev = node->minor->dev;
2602         struct intel_encoder *encoder;
2603         struct intel_connector *connector;
2604         struct intel_dp *intel_dp = NULL;
2605         int ret;
2606         u8 crc[6];
2607
2608         drm_modeset_lock_all(dev);
2609         for_each_intel_connector(dev, connector) {
2610
2611                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2612                         continue;
2613
2614                 if (!connector->base.encoder)
2615                         continue;
2616
2617                 encoder = to_intel_encoder(connector->base.encoder);
2618                 if (encoder->type != INTEL_OUTPUT_EDP)
2619                         continue;
2620
2621                 intel_dp = enc_to_intel_dp(&encoder->base);
2622
2623                 ret = intel_dp_sink_crc(intel_dp, crc);
2624                 if (ret)
2625                         goto out;
2626
2627                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2628                            crc[0], crc[1], crc[2],
2629                            crc[3], crc[4], crc[5]);
2630                 goto out;
2631         }
2632         ret = -ENODEV;
2633 out:
2634         drm_modeset_unlock_all(dev);
2635         return ret;
2636 }
2637
2638 static int i915_energy_uJ(struct seq_file *m, void *data)
2639 {
2640         struct drm_info_node *node = m->private;
2641         struct drm_device *dev = node->minor->dev;
2642         struct drm_i915_private *dev_priv = dev->dev_private;
2643         u64 power;
2644         u32 units;
2645
2646         if (INTEL_INFO(dev)->gen < 6)
2647                 return -ENODEV;
2648
2649         intel_runtime_pm_get(dev_priv);
2650
2651         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2652         power = (power & 0x1f00) >> 8;
2653         units = 1000000 / (1 << power); /* convert to uJ */
2654         power = I915_READ(MCH_SECP_NRG_STTS);
2655         power *= units;
2656
2657         intel_runtime_pm_put(dev_priv);
2658
2659         seq_printf(m, "%llu", (long long unsigned)power);
2660
2661         return 0;
2662 }
2663
2664 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2665 {
2666         struct drm_info_node *node = m->private;
2667         struct drm_device *dev = node->minor->dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669
2670         if (!HAS_RUNTIME_PM(dev)) {
2671                 seq_puts(m, "not supported\n");
2672                 return 0;
2673         }
2674
2675         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2676         seq_printf(m, "IRQs disabled: %s\n",
2677                    yesno(!intel_irqs_enabled(dev_priv)));
2678 #ifdef CONFIG_PM
2679         seq_printf(m, "Usage count: %d\n",
2680                    atomic_read(&dev->dev->power.usage_count));
2681 #else
2682         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2683 #endif
2684
2685         return 0;
2686 }
2687
2688 static const char *power_domain_str(enum intel_display_power_domain domain)
2689 {
2690         switch (domain) {
2691         case POWER_DOMAIN_PIPE_A:
2692                 return "PIPE_A";
2693         case POWER_DOMAIN_PIPE_B:
2694                 return "PIPE_B";
2695         case POWER_DOMAIN_PIPE_C:
2696                 return "PIPE_C";
2697         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2698                 return "PIPE_A_PANEL_FITTER";
2699         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2700                 return "PIPE_B_PANEL_FITTER";
2701         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2702                 return "PIPE_C_PANEL_FITTER";
2703         case POWER_DOMAIN_TRANSCODER_A:
2704                 return "TRANSCODER_A";
2705         case POWER_DOMAIN_TRANSCODER_B:
2706                 return "TRANSCODER_B";
2707         case POWER_DOMAIN_TRANSCODER_C:
2708                 return "TRANSCODER_C";
2709         case POWER_DOMAIN_TRANSCODER_EDP:
2710                 return "TRANSCODER_EDP";
2711         case POWER_DOMAIN_PORT_DDI_A_LANES:
2712                 return "PORT_DDI_A_LANES";
2713         case POWER_DOMAIN_PORT_DDI_B_LANES:
2714                 return "PORT_DDI_B_LANES";
2715         case POWER_DOMAIN_PORT_DDI_C_LANES:
2716                 return "PORT_DDI_C_LANES";
2717         case POWER_DOMAIN_PORT_DDI_D_LANES:
2718                 return "PORT_DDI_D_LANES";
2719         case POWER_DOMAIN_PORT_DDI_E_LANES:
2720                 return "PORT_DDI_E_LANES";
2721         case POWER_DOMAIN_PORT_DSI:
2722                 return "PORT_DSI";
2723         case POWER_DOMAIN_PORT_CRT:
2724                 return "PORT_CRT";
2725         case POWER_DOMAIN_PORT_OTHER:
2726                 return "PORT_OTHER";
2727         case POWER_DOMAIN_VGA:
2728                 return "VGA";
2729         case POWER_DOMAIN_AUDIO:
2730                 return "AUDIO";
2731         case POWER_DOMAIN_PLLS:
2732                 return "PLLS";
2733         case POWER_DOMAIN_AUX_A:
2734                 return "AUX_A";
2735         case POWER_DOMAIN_AUX_B:
2736                 return "AUX_B";
2737         case POWER_DOMAIN_AUX_C:
2738                 return "AUX_C";
2739         case POWER_DOMAIN_AUX_D:
2740                 return "AUX_D";
2741         case POWER_DOMAIN_GMBUS:
2742                 return "GMBUS";
2743         case POWER_DOMAIN_MODESET:
2744                 return "MODESET";
2745         case POWER_DOMAIN_INIT:
2746                 return "INIT";
2747         default:
2748                 MISSING_CASE(domain);
2749                 return "?";
2750         }
2751 }
2752
2753 static int i915_power_domain_info(struct seq_file *m, void *unused)
2754 {
2755         struct drm_info_node *node = m->private;
2756         struct drm_device *dev = node->minor->dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2759         int i;
2760
2761         mutex_lock(&power_domains->lock);
2762
2763         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2764         for (i = 0; i < power_domains->power_well_count; i++) {
2765                 struct i915_power_well *power_well;
2766                 enum intel_display_power_domain power_domain;
2767
2768                 power_well = &power_domains->power_wells[i];
2769                 seq_printf(m, "%-25s %d\n", power_well->name,
2770                            power_well->count);
2771
2772                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2773                      power_domain++) {
2774                         if (!(BIT(power_domain) & power_well->domains))
2775                                 continue;
2776
2777                         seq_printf(m, "  %-23s %d\n",
2778                                  power_domain_str(power_domain),
2779                                  power_domains->domain_use_count[power_domain]);
2780                 }
2781         }
2782
2783         mutex_unlock(&power_domains->lock);
2784
2785         return 0;
2786 }
2787
2788 static int i915_dmc_info(struct seq_file *m, void *unused)
2789 {
2790         struct drm_info_node *node = m->private;
2791         struct drm_device *dev = node->minor->dev;
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         struct intel_csr *csr;
2794
2795         if (!HAS_CSR(dev)) {
2796                 seq_puts(m, "not supported\n");
2797                 return 0;
2798         }
2799
2800         csr = &dev_priv->csr;
2801
2802         intel_runtime_pm_get(dev_priv);
2803
2804         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2805         seq_printf(m, "path: %s\n", csr->fw_path);
2806
2807         if (!csr->dmc_payload)
2808                 goto out;
2809
2810         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2811                    CSR_VERSION_MINOR(csr->version));
2812
2813         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2814                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2815                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2816                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2817                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2818         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2819                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2820                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2821         }
2822
2823 out:
2824         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2825         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2826         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2827
2828         intel_runtime_pm_put(dev_priv);
2829
2830         return 0;
2831 }
2832
2833 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2834                                  struct drm_display_mode *mode)
2835 {
2836         int i;
2837
2838         for (i = 0; i < tabs; i++)
2839                 seq_putc(m, '\t');
2840
2841         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2842                    mode->base.id, mode->name,
2843                    mode->vrefresh, mode->clock,
2844                    mode->hdisplay, mode->hsync_start,
2845                    mode->hsync_end, mode->htotal,
2846                    mode->vdisplay, mode->vsync_start,
2847                    mode->vsync_end, mode->vtotal,
2848                    mode->type, mode->flags);
2849 }
2850
2851 static void intel_encoder_info(struct seq_file *m,
2852                                struct intel_crtc *intel_crtc,
2853                                struct intel_encoder *intel_encoder)
2854 {
2855         struct drm_info_node *node = m->private;
2856         struct drm_device *dev = node->minor->dev;
2857         struct drm_crtc *crtc = &intel_crtc->base;
2858         struct intel_connector *intel_connector;
2859         struct drm_encoder *encoder;
2860
2861         encoder = &intel_encoder->base;
2862         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2863                    encoder->base.id, encoder->name);
2864         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2865                 struct drm_connector *connector = &intel_connector->base;
2866                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2867                            connector->base.id,
2868                            connector->name,
2869                            drm_get_connector_status_name(connector->status));
2870                 if (connector->status == connector_status_connected) {
2871                         struct drm_display_mode *mode = &crtc->mode;
2872                         seq_printf(m, ", mode:\n");
2873                         intel_seq_print_mode(m, 2, mode);
2874                 } else {
2875                         seq_putc(m, '\n');
2876                 }
2877         }
2878 }
2879
2880 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2881 {
2882         struct drm_info_node *node = m->private;
2883         struct drm_device *dev = node->minor->dev;
2884         struct drm_crtc *crtc = &intel_crtc->base;
2885         struct intel_encoder *intel_encoder;
2886         struct drm_plane_state *plane_state = crtc->primary->state;
2887         struct drm_framebuffer *fb = plane_state->fb;
2888
2889         if (fb)
2890                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2891                            fb->base.id, plane_state->src_x >> 16,
2892                            plane_state->src_y >> 16, fb->width, fb->height);
2893         else
2894                 seq_puts(m, "\tprimary plane disabled\n");
2895         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2896                 intel_encoder_info(m, intel_crtc, intel_encoder);
2897 }
2898
2899 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2900 {
2901         struct drm_display_mode *mode = panel->fixed_mode;
2902
2903         seq_printf(m, "\tfixed mode:\n");
2904         intel_seq_print_mode(m, 2, mode);
2905 }
2906
2907 static void intel_dp_info(struct seq_file *m,
2908                           struct intel_connector *intel_connector)
2909 {
2910         struct intel_encoder *intel_encoder = intel_connector->encoder;
2911         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2912
2913         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2914         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2915         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2916                 intel_panel_info(m, &intel_connector->panel);
2917 }
2918
2919 static void intel_hdmi_info(struct seq_file *m,
2920                             struct intel_connector *intel_connector)
2921 {
2922         struct intel_encoder *intel_encoder = intel_connector->encoder;
2923         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2924
2925         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2926 }
2927
2928 static void intel_lvds_info(struct seq_file *m,
2929                             struct intel_connector *intel_connector)
2930 {
2931         intel_panel_info(m, &intel_connector->panel);
2932 }
2933
2934 static void intel_connector_info(struct seq_file *m,
2935                                  struct drm_connector *connector)
2936 {
2937         struct intel_connector *intel_connector = to_intel_connector(connector);
2938         struct intel_encoder *intel_encoder = intel_connector->encoder;
2939         struct drm_display_mode *mode;
2940
2941         seq_printf(m, "connector %d: type %s, status: %s\n",
2942                    connector->base.id, connector->name,
2943                    drm_get_connector_status_name(connector->status));
2944         if (connector->status == connector_status_connected) {
2945                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2946                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2947                            connector->display_info.width_mm,
2948                            connector->display_info.height_mm);
2949                 seq_printf(m, "\tsubpixel order: %s\n",
2950                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2951                 seq_printf(m, "\tCEA rev: %d\n",
2952                            connector->display_info.cea_rev);
2953         }
2954         if (intel_encoder) {
2955                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2956                     intel_encoder->type == INTEL_OUTPUT_EDP)
2957                         intel_dp_info(m, intel_connector);
2958                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2959                         intel_hdmi_info(m, intel_connector);
2960                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2961                         intel_lvds_info(m, intel_connector);
2962         }
2963
2964         seq_printf(m, "\tmodes:\n");
2965         list_for_each_entry(mode, &connector->modes, head)
2966                 intel_seq_print_mode(m, 2, mode);
2967 }
2968
2969 static bool cursor_active(struct drm_device *dev, int pipe)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         u32 state;
2973
2974         if (IS_845G(dev) || IS_I865G(dev))
2975                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2976         else
2977                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2978
2979         return state;
2980 }
2981
2982 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2983 {
2984         struct drm_i915_private *dev_priv = dev->dev_private;
2985         u32 pos;
2986
2987         pos = I915_READ(CURPOS(pipe));
2988
2989         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2990         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2991                 *x = -*x;
2992
2993         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2994         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2995                 *y = -*y;
2996
2997         return cursor_active(dev, pipe);
2998 }
2999
3000 static const char *plane_type(enum drm_plane_type type)
3001 {
3002         switch (type) {
3003         case DRM_PLANE_TYPE_OVERLAY:
3004                 return "OVL";
3005         case DRM_PLANE_TYPE_PRIMARY:
3006                 return "PRI";
3007         case DRM_PLANE_TYPE_CURSOR:
3008                 return "CUR";
3009         /*
3010          * Deliberately omitting default: to generate compiler warnings
3011          * when a new drm_plane_type gets added.
3012          */
3013         }
3014
3015         return "unknown";
3016 }
3017
3018 static const char *plane_rotation(unsigned int rotation)
3019 {
3020         static char buf[48];
3021         /*
3022          * According to doc only one DRM_ROTATE_ is allowed but this
3023          * will print them all to visualize if the values are misused
3024          */
3025         snprintf(buf, sizeof(buf),
3026                  "%s%s%s%s%s%s(0x%08x)",
3027                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3028                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3029                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3030                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3031                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3032                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3033                  rotation);
3034
3035         return buf;
3036 }
3037
3038 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3039 {
3040         struct drm_info_node *node = m->private;
3041         struct drm_device *dev = node->minor->dev;
3042         struct intel_plane *intel_plane;
3043
3044         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3045                 struct drm_plane_state *state;
3046                 struct drm_plane *plane = &intel_plane->base;
3047
3048                 if (!plane->state) {
3049                         seq_puts(m, "plane->state is NULL!\n");
3050                         continue;
3051                 }
3052
3053                 state = plane->state;
3054
3055                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3056                            plane->base.id,
3057                            plane_type(intel_plane->base.type),
3058                            state->crtc_x, state->crtc_y,
3059                            state->crtc_w, state->crtc_h,
3060                            (state->src_x >> 16),
3061                            ((state->src_x & 0xffff) * 15625) >> 10,
3062                            (state->src_y >> 16),
3063                            ((state->src_y & 0xffff) * 15625) >> 10,
3064                            (state->src_w >> 16),
3065                            ((state->src_w & 0xffff) * 15625) >> 10,
3066                            (state->src_h >> 16),
3067                            ((state->src_h & 0xffff) * 15625) >> 10,
3068                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3069                            plane_rotation(state->rotation));
3070         }
3071 }
3072
3073 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3074 {
3075         struct intel_crtc_state *pipe_config;
3076         int num_scalers = intel_crtc->num_scalers;
3077         int i;
3078
3079         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3080
3081         /* Not all platformas have a scaler */
3082         if (num_scalers) {
3083                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3084                            num_scalers,
3085                            pipe_config->scaler_state.scaler_users,
3086                            pipe_config->scaler_state.scaler_id);
3087
3088                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3089                         struct intel_scaler *sc =
3090                                         &pipe_config->scaler_state.scalers[i];
3091
3092                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3093                                    i, yesno(sc->in_use), sc->mode);
3094                 }
3095                 seq_puts(m, "\n");
3096         } else {
3097                 seq_puts(m, "\tNo scalers available on this platform\n");
3098         }
3099 }
3100
3101 static int i915_display_info(struct seq_file *m, void *unused)
3102 {
3103         struct drm_info_node *node = m->private;
3104         struct drm_device *dev = node->minor->dev;
3105         struct drm_i915_private *dev_priv = dev->dev_private;
3106         struct intel_crtc *crtc;
3107         struct drm_connector *connector;
3108
3109         intel_runtime_pm_get(dev_priv);
3110         drm_modeset_lock_all(dev);
3111         seq_printf(m, "CRTC info\n");
3112         seq_printf(m, "---------\n");
3113         for_each_intel_crtc(dev, crtc) {
3114                 bool active;
3115                 struct intel_crtc_state *pipe_config;
3116                 int x, y;
3117
3118                 pipe_config = to_intel_crtc_state(crtc->base.state);
3119
3120                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3121                            crtc->base.base.id, pipe_name(crtc->pipe),
3122                            yesno(pipe_config->base.active),
3123                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3124                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3125
3126                 if (pipe_config->base.active) {
3127                         intel_crtc_info(m, crtc);
3128
3129                         active = cursor_position(dev, crtc->pipe, &x, &y);
3130                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3131                                    yesno(crtc->cursor_base),
3132                                    x, y, crtc->base.cursor->state->crtc_w,
3133                                    crtc->base.cursor->state->crtc_h,
3134                                    crtc->cursor_addr, yesno(active));
3135                         intel_scaler_info(m, crtc);
3136                         intel_plane_info(m, crtc);
3137                 }
3138
3139                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3140                            yesno(!crtc->cpu_fifo_underrun_disabled),
3141                            yesno(!crtc->pch_fifo_underrun_disabled));
3142         }
3143
3144         seq_printf(m, "\n");
3145         seq_printf(m, "Connector info\n");
3146         seq_printf(m, "--------------\n");
3147         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3148                 intel_connector_info(m, connector);
3149         }
3150         drm_modeset_unlock_all(dev);
3151         intel_runtime_pm_put(dev_priv);
3152
3153         return 0;
3154 }
3155
3156 static int i915_semaphore_status(struct seq_file *m, void *unused)
3157 {
3158         struct drm_info_node *node = (struct drm_info_node *) m->private;
3159         struct drm_device *dev = node->minor->dev;
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161         struct intel_engine_cs *ring;
3162         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3163         int i, j, ret;
3164
3165         if (!i915_semaphore_is_enabled(dev)) {
3166                 seq_puts(m, "Semaphores are disabled\n");
3167                 return 0;
3168         }
3169
3170         ret = mutex_lock_interruptible(&dev->struct_mutex);
3171         if (ret)
3172                 return ret;
3173         intel_runtime_pm_get(dev_priv);
3174
3175         if (IS_BROADWELL(dev)) {
3176                 struct page *page;
3177                 uint64_t *seqno;
3178
3179                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3180
3181                 seqno = (uint64_t *)kmap_atomic(page);
3182                 for_each_ring(ring, dev_priv, i) {
3183                         uint64_t offset;
3184
3185                         seq_printf(m, "%s\n", ring->name);
3186
3187                         seq_puts(m, "  Last signal:");
3188                         for (j = 0; j < num_rings; j++) {
3189                                 offset = i * I915_NUM_RINGS + j;
3190                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3191                                            seqno[offset], offset * 8);
3192                         }
3193                         seq_putc(m, '\n');
3194
3195                         seq_puts(m, "  Last wait:  ");
3196                         for (j = 0; j < num_rings; j++) {
3197                                 offset = i + (j * I915_NUM_RINGS);
3198                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3199                                            seqno[offset], offset * 8);
3200                         }
3201                         seq_putc(m, '\n');
3202
3203                 }
3204                 kunmap_atomic(seqno);
3205         } else {
3206                 seq_puts(m, "  Last signal:");
3207                 for_each_ring(ring, dev_priv, i)
3208                         for (j = 0; j < num_rings; j++)
3209                                 seq_printf(m, "0x%08x\n",
3210                                            I915_READ(ring->semaphore.mbox.signal[j]));
3211                 seq_putc(m, '\n');
3212         }
3213
3214         seq_puts(m, "\nSync seqno:\n");
3215         for_each_ring(ring, dev_priv, i) {
3216                 for (j = 0; j < num_rings; j++) {
3217                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3218                 }
3219                 seq_putc(m, '\n');
3220         }
3221         seq_putc(m, '\n');
3222
3223         intel_runtime_pm_put(dev_priv);
3224         mutex_unlock(&dev->struct_mutex);
3225         return 0;
3226 }
3227
3228 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3229 {
3230         struct drm_info_node *node = (struct drm_info_node *) m->private;
3231         struct drm_device *dev = node->minor->dev;
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         int i;
3234
3235         drm_modeset_lock_all(dev);
3236         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3237                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3238
3239                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3240                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3241                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3242                 seq_printf(m, " tracked hardware state:\n");
3243                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3244                 seq_printf(m, " dpll_md: 0x%08x\n",
3245                            pll->config.hw_state.dpll_md);
3246                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3247                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3248                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3249         }
3250         drm_modeset_unlock_all(dev);
3251
3252         return 0;
3253 }
3254
3255 static int i915_wa_registers(struct seq_file *m, void *unused)
3256 {
3257         int i;
3258         int ret;
3259         struct drm_info_node *node = (struct drm_info_node *) m->private;
3260         struct drm_device *dev = node->minor->dev;
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262
3263         ret = mutex_lock_interruptible(&dev->struct_mutex);
3264         if (ret)
3265                 return ret;
3266
3267         intel_runtime_pm_get(dev_priv);
3268
3269         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3270         for (i = 0; i < dev_priv->workarounds.count; ++i) {
3271                 i915_reg_t addr;
3272                 u32 mask, value, read;
3273                 bool ok;
3274
3275                 addr = dev_priv->workarounds.reg[i].addr;
3276                 mask = dev_priv->workarounds.reg[i].mask;
3277                 value = dev_priv->workarounds.reg[i].value;
3278                 read = I915_READ(addr);
3279                 ok = (value & mask) == (read & mask);
3280                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3281                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3282         }
3283
3284         intel_runtime_pm_put(dev_priv);
3285         mutex_unlock(&dev->struct_mutex);
3286
3287         return 0;
3288 }
3289
3290 static int i915_ddb_info(struct seq_file *m, void *unused)
3291 {
3292         struct drm_info_node *node = m->private;
3293         struct drm_device *dev = node->minor->dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         struct skl_ddb_allocation *ddb;
3296         struct skl_ddb_entry *entry;
3297         enum pipe pipe;
3298         int plane;
3299
3300         if (INTEL_INFO(dev)->gen < 9)
3301                 return 0;
3302
3303         drm_modeset_lock_all(dev);
3304
3305         ddb = &dev_priv->wm.skl_hw.ddb;
3306
3307         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3308
3309         for_each_pipe(dev_priv, pipe) {
3310                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3311
3312                 for_each_plane(dev_priv, pipe, plane) {
3313                         entry = &ddb->plane[pipe][plane];
3314                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3315                                    entry->start, entry->end,
3316                                    skl_ddb_entry_size(entry));
3317                 }
3318
3319                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3320                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3321                            entry->end, skl_ddb_entry_size(entry));
3322         }
3323
3324         drm_modeset_unlock_all(dev);
3325
3326         return 0;
3327 }
3328
3329 static void drrs_status_per_crtc(struct seq_file *m,
3330                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3331 {
3332         struct intel_encoder *intel_encoder;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         struct i915_drrs *drrs = &dev_priv->drrs;
3335         int vrefresh = 0;
3336
3337         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3338                 /* Encoder connected on this CRTC */
3339                 switch (intel_encoder->type) {
3340                 case INTEL_OUTPUT_EDP:
3341                         seq_puts(m, "eDP:\n");
3342                         break;
3343                 case INTEL_OUTPUT_DSI:
3344                         seq_puts(m, "DSI:\n");
3345                         break;
3346                 case INTEL_OUTPUT_HDMI:
3347                         seq_puts(m, "HDMI:\n");
3348                         break;
3349                 case INTEL_OUTPUT_DISPLAYPORT:
3350                         seq_puts(m, "DP:\n");
3351                         break;
3352                 default:
3353                         seq_printf(m, "Other encoder (id=%d).\n",
3354                                                 intel_encoder->type);
3355                         return;
3356                 }
3357         }
3358
3359         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3360                 seq_puts(m, "\tVBT: DRRS_type: Static");
3361         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3362                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3363         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3364                 seq_puts(m, "\tVBT: DRRS_type: None");
3365         else
3366                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3367
3368         seq_puts(m, "\n\n");
3369
3370         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3371                 struct intel_panel *panel;
3372
3373                 mutex_lock(&drrs->mutex);
3374                 /* DRRS Supported */
3375                 seq_puts(m, "\tDRRS Supported: Yes\n");
3376
3377                 /* disable_drrs() will make drrs->dp NULL */
3378                 if (!drrs->dp) {
3379                         seq_puts(m, "Idleness DRRS: Disabled");
3380                         mutex_unlock(&drrs->mutex);
3381                         return;
3382                 }
3383
3384                 panel = &drrs->dp->attached_connector->panel;
3385                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3386                                         drrs->busy_frontbuffer_bits);
3387
3388                 seq_puts(m, "\n\t\t");
3389                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3390                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3391                         vrefresh = panel->fixed_mode->vrefresh;
3392                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3393                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3394                         vrefresh = panel->downclock_mode->vrefresh;
3395                 } else {
3396                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3397                                                 drrs->refresh_rate_type);
3398                         mutex_unlock(&drrs->mutex);
3399                         return;
3400                 }
3401                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3402
3403                 seq_puts(m, "\n\t\t");
3404                 mutex_unlock(&drrs->mutex);
3405         } else {
3406                 /* DRRS not supported. Print the VBT parameter*/
3407                 seq_puts(m, "\tDRRS Supported : No");
3408         }
3409         seq_puts(m, "\n");
3410 }
3411
3412 static int i915_drrs_status(struct seq_file *m, void *unused)
3413 {
3414         struct drm_info_node *node = m->private;
3415         struct drm_device *dev = node->minor->dev;
3416         struct intel_crtc *intel_crtc;
3417         int active_crtc_cnt = 0;
3418
3419         for_each_intel_crtc(dev, intel_crtc) {
3420                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3421
3422                 if (intel_crtc->base.state->active) {
3423                         active_crtc_cnt++;
3424                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3425
3426                         drrs_status_per_crtc(m, dev, intel_crtc);
3427                 }
3428
3429                 drm_modeset_unlock(&intel_crtc->base.mutex);
3430         }
3431
3432         if (!active_crtc_cnt)
3433                 seq_puts(m, "No active crtc found\n");
3434
3435         return 0;
3436 }
3437
3438 struct pipe_crc_info {
3439         const char *name;
3440         struct drm_device *dev;
3441         enum pipe pipe;
3442 };
3443
3444 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3445 {
3446         struct drm_info_node *node = (struct drm_info_node *) m->private;
3447         struct drm_device *dev = node->minor->dev;
3448         struct drm_encoder *encoder;
3449         struct intel_encoder *intel_encoder;
3450         struct intel_digital_port *intel_dig_port;
3451         drm_modeset_lock_all(dev);
3452         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3453                 intel_encoder = to_intel_encoder(encoder);
3454                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3455                         continue;
3456                 intel_dig_port = enc_to_dig_port(encoder);
3457                 if (!intel_dig_port->dp.can_mst)
3458                         continue;
3459
3460                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3461         }
3462         drm_modeset_unlock_all(dev);
3463         return 0;
3464 }
3465
3466 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3467 {
3468         struct pipe_crc_info *info = inode->i_private;
3469         struct drm_i915_private *dev_priv = info->dev->dev_private;
3470         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3471
3472         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3473                 return -ENODEV;
3474
3475         spin_lock_irq(&pipe_crc->lock);
3476
3477         if (pipe_crc->opened) {
3478                 spin_unlock_irq(&pipe_crc->lock);
3479                 return -EBUSY; /* already open */
3480         }
3481
3482         pipe_crc->opened = true;
3483         filep->private_data = inode->i_private;
3484
3485         spin_unlock_irq(&pipe_crc->lock);
3486
3487         return 0;
3488 }
3489
3490 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3491 {
3492         struct pipe_crc_info *info = inode->i_private;
3493         struct drm_i915_private *dev_priv = info->dev->dev_private;
3494         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3495
3496         spin_lock_irq(&pipe_crc->lock);
3497         pipe_crc->opened = false;
3498         spin_unlock_irq(&pipe_crc->lock);
3499
3500         return 0;
3501 }
3502
3503 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3504 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3505 /* account for \'0' */
3506 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3507
3508 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3509 {
3510         assert_spin_locked(&pipe_crc->lock);
3511         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3512                         INTEL_PIPE_CRC_ENTRIES_NR);
3513 }
3514
3515 static ssize_t
3516 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3517                    loff_t *pos)
3518 {
3519         struct pipe_crc_info *info = filep->private_data;
3520         struct drm_device *dev = info->dev;
3521         struct drm_i915_private *dev_priv = dev->dev_private;
3522         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3523         char buf[PIPE_CRC_BUFFER_LEN];
3524         int n_entries;
3525         ssize_t bytes_read;
3526
3527         /*
3528          * Don't allow user space to provide buffers not big enough to hold
3529          * a line of data.
3530          */
3531         if (count < PIPE_CRC_LINE_LEN)
3532                 return -EINVAL;
3533
3534         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3535                 return 0;
3536
3537         /* nothing to read */
3538         spin_lock_irq(&pipe_crc->lock);
3539         while (pipe_crc_data_count(pipe_crc) == 0) {
3540                 int ret;
3541
3542                 if (filep->f_flags & O_NONBLOCK) {
3543                         spin_unlock_irq(&pipe_crc->lock);
3544                         return -EAGAIN;
3545                 }
3546
3547                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3548                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3549                 if (ret) {
3550                         spin_unlock_irq(&pipe_crc->lock);
3551                         return ret;
3552                 }
3553         }
3554
3555         /* We now have one or more entries to read */
3556         n_entries = count / PIPE_CRC_LINE_LEN;
3557
3558         bytes_read = 0;
3559         while (n_entries > 0) {
3560                 struct intel_pipe_crc_entry *entry =
3561                         &pipe_crc->entries[pipe_crc->tail];
3562                 int ret;
3563
3564                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3565                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3566                         break;
3567
3568                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3569                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3570
3571                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3572                                        "%8u %8x %8x %8x %8x %8x\n",
3573                                        entry->frame, entry->crc[0],
3574                                        entry->crc[1], entry->crc[2],
3575                                        entry->crc[3], entry->crc[4]);
3576
3577                 spin_unlock_irq(&pipe_crc->lock);
3578
3579                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3580                 if (ret == PIPE_CRC_LINE_LEN)
3581                         return -EFAULT;
3582
3583                 user_buf += PIPE_CRC_LINE_LEN;
3584                 n_entries--;
3585
3586                 spin_lock_irq(&pipe_crc->lock);
3587         }
3588
3589         spin_unlock_irq(&pipe_crc->lock);
3590
3591         return bytes_read;
3592 }
3593
3594 static const struct file_operations i915_pipe_crc_fops = {
3595         .owner = THIS_MODULE,
3596         .open = i915_pipe_crc_open,
3597         .read = i915_pipe_crc_read,
3598         .release = i915_pipe_crc_release,
3599 };
3600
3601 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3602         {
3603                 .name = "i915_pipe_A_crc",
3604                 .pipe = PIPE_A,
3605         },
3606         {
3607                 .name = "i915_pipe_B_crc",
3608                 .pipe = PIPE_B,
3609         },
3610         {
3611                 .name = "i915_pipe_C_crc",
3612                 .pipe = PIPE_C,
3613         },
3614 };
3615
3616 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3617                                 enum pipe pipe)
3618 {
3619         struct drm_device *dev = minor->dev;
3620         struct dentry *ent;
3621         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3622
3623         info->dev = dev;
3624         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3625                                   &i915_pipe_crc_fops);
3626         if (!ent)
3627                 return -ENOMEM;
3628
3629         return drm_add_fake_info_node(minor, ent, info);
3630 }
3631
3632 static const char * const pipe_crc_sources[] = {
3633         "none",
3634         "plane1",
3635         "plane2",
3636         "pf",
3637         "pipe",
3638         "TV",
3639         "DP-B",
3640         "DP-C",
3641         "DP-D",
3642         "auto",
3643 };
3644
3645 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3646 {
3647         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3648         return pipe_crc_sources[source];
3649 }
3650
3651 static int display_crc_ctl_show(struct seq_file *m, void *data)
3652 {
3653         struct drm_device *dev = m->private;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         int i;
3656
3657         for (i = 0; i < I915_MAX_PIPES; i++)
3658                 seq_printf(m, "%c %s\n", pipe_name(i),
3659                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3660
3661         return 0;
3662 }
3663
3664 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3665 {
3666         struct drm_device *dev = inode->i_private;
3667
3668         return single_open(file, display_crc_ctl_show, dev);
3669 }
3670
3671 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3672                                  uint32_t *val)
3673 {
3674         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3675                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3676
3677         switch (*source) {
3678         case INTEL_PIPE_CRC_SOURCE_PIPE:
3679                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3680                 break;
3681         case INTEL_PIPE_CRC_SOURCE_NONE:
3682                 *val = 0;
3683                 break;
3684         default:
3685                 return -EINVAL;
3686         }
3687
3688         return 0;
3689 }
3690
3691 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3692                                      enum intel_pipe_crc_source *source)
3693 {
3694         struct intel_encoder *encoder;
3695         struct intel_crtc *crtc;
3696         struct intel_digital_port *dig_port;
3697         int ret = 0;
3698
3699         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3700
3701         drm_modeset_lock_all(dev);
3702         for_each_intel_encoder(dev, encoder) {
3703                 if (!encoder->base.crtc)
3704                         continue;
3705
3706                 crtc = to_intel_crtc(encoder->base.crtc);
3707
3708                 if (crtc->pipe != pipe)
3709                         continue;
3710
3711                 switch (encoder->type) {
3712                 case INTEL_OUTPUT_TVOUT:
3713                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3714                         break;
3715                 case INTEL_OUTPUT_DISPLAYPORT:
3716                 case INTEL_OUTPUT_EDP:
3717                         dig_port = enc_to_dig_port(&encoder->base);
3718                         switch (dig_port->port) {
3719                         case PORT_B:
3720                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3721                                 break;
3722                         case PORT_C:
3723                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3724                                 break;
3725                         case PORT_D:
3726                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3727                                 break;
3728                         default:
3729                                 WARN(1, "nonexisting DP port %c\n",
3730                                      port_name(dig_port->port));
3731                                 break;
3732                         }
3733                         break;
3734                 default:
3735                         break;
3736                 }
3737         }
3738         drm_modeset_unlock_all(dev);
3739
3740         return ret;
3741 }
3742
3743 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3744                                 enum pipe pipe,
3745                                 enum intel_pipe_crc_source *source,
3746                                 uint32_t *val)
3747 {
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         bool need_stable_symbols = false;
3750
3751         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3752                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3753                 if (ret)
3754                         return ret;
3755         }
3756
3757         switch (*source) {
3758         case INTEL_PIPE_CRC_SOURCE_PIPE:
3759                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3760                 break;
3761         case INTEL_PIPE_CRC_SOURCE_DP_B:
3762                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3763                 need_stable_symbols = true;
3764                 break;
3765         case INTEL_PIPE_CRC_SOURCE_DP_C:
3766                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3767                 need_stable_symbols = true;
3768                 break;
3769         case INTEL_PIPE_CRC_SOURCE_DP_D:
3770                 if (!IS_CHERRYVIEW(dev))
3771                         return -EINVAL;
3772                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3773                 need_stable_symbols = true;
3774                 break;
3775         case INTEL_PIPE_CRC_SOURCE_NONE:
3776                 *val = 0;
3777                 break;
3778         default:
3779                 return -EINVAL;
3780         }
3781
3782         /*
3783          * When the pipe CRC tap point is after the transcoders we need
3784          * to tweak symbol-level features to produce a deterministic series of
3785          * symbols for a given frame. We need to reset those features only once
3786          * a frame (instead of every nth symbol):
3787          *   - DC-balance: used to ensure a better clock recovery from the data
3788          *     link (SDVO)
3789          *   - DisplayPort scrambling: used for EMI reduction
3790          */
3791         if (need_stable_symbols) {
3792                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3793
3794                 tmp |= DC_BALANCE_RESET_VLV;
3795                 switch (pipe) {
3796                 case PIPE_A:
3797                         tmp |= PIPE_A_SCRAMBLE_RESET;
3798                         break;
3799                 case PIPE_B:
3800                         tmp |= PIPE_B_SCRAMBLE_RESET;
3801                         break;
3802                 case PIPE_C:
3803                         tmp |= PIPE_C_SCRAMBLE_RESET;
3804                         break;
3805                 default:
3806                         return -EINVAL;
3807                 }
3808                 I915_WRITE(PORT_DFT2_G4X, tmp);
3809         }
3810
3811         return 0;
3812 }
3813
3814 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3815                                  enum pipe pipe,
3816                                  enum intel_pipe_crc_source *source,
3817                                  uint32_t *val)
3818 {
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         bool need_stable_symbols = false;
3821
3822         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3823                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3824                 if (ret)
3825                         return ret;
3826         }
3827
3828         switch (*source) {
3829         case INTEL_PIPE_CRC_SOURCE_PIPE:
3830                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3831                 break;
3832         case INTEL_PIPE_CRC_SOURCE_TV:
3833                 if (!SUPPORTS_TV(dev))
3834                         return -EINVAL;
3835                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3836                 break;
3837         case INTEL_PIPE_CRC_SOURCE_DP_B:
3838                 if (!IS_G4X(dev))
3839                         return -EINVAL;
3840                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3841                 need_stable_symbols = true;
3842                 break;
3843         case INTEL_PIPE_CRC_SOURCE_DP_C:
3844                 if (!IS_G4X(dev))
3845                         return -EINVAL;
3846                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3847                 need_stable_symbols = true;
3848                 break;
3849         case INTEL_PIPE_CRC_SOURCE_DP_D:
3850                 if (!IS_G4X(dev))
3851                         return -EINVAL;
3852                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3853                 need_stable_symbols = true;
3854                 break;
3855         case INTEL_PIPE_CRC_SOURCE_NONE:
3856                 *val = 0;
3857                 break;
3858         default:
3859                 return -EINVAL;
3860         }
3861
3862         /*
3863          * When the pipe CRC tap point is after the transcoders we need
3864          * to tweak symbol-level features to produce a deterministic series of
3865          * symbols for a given frame. We need to reset those features only once
3866          * a frame (instead of every nth symbol):
3867          *   - DC-balance: used to ensure a better clock recovery from the data
3868          *     link (SDVO)
3869          *   - DisplayPort scrambling: used for EMI reduction
3870          */
3871         if (need_stable_symbols) {
3872                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3873
3874                 WARN_ON(!IS_G4X(dev));
3875
3876                 I915_WRITE(PORT_DFT_I9XX,
3877                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3878
3879                 if (pipe == PIPE_A)
3880                         tmp |= PIPE_A_SCRAMBLE_RESET;
3881                 else
3882                         tmp |= PIPE_B_SCRAMBLE_RESET;
3883
3884                 I915_WRITE(PORT_DFT2_G4X, tmp);
3885         }
3886
3887         return 0;
3888 }
3889
3890 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3891                                          enum pipe pipe)
3892 {
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3895
3896         switch (pipe) {
3897         case PIPE_A:
3898                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3899                 break;
3900         case PIPE_B:
3901                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3902                 break;
3903         case PIPE_C:
3904                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3905                 break;
3906         default:
3907                 return;
3908         }
3909         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3910                 tmp &= ~DC_BALANCE_RESET_VLV;
3911         I915_WRITE(PORT_DFT2_G4X, tmp);
3912
3913 }
3914
3915 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3916                                          enum pipe pipe)
3917 {
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3920
3921         if (pipe == PIPE_A)
3922                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3923         else
3924                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3925         I915_WRITE(PORT_DFT2_G4X, tmp);
3926
3927         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3928                 I915_WRITE(PORT_DFT_I9XX,
3929                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3930         }
3931 }
3932
3933 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3934                                 uint32_t *val)
3935 {
3936         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3937                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3938
3939         switch (*source) {
3940         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3941                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3942                 break;
3943         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3944                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3945                 break;
3946         case INTEL_PIPE_CRC_SOURCE_PIPE:
3947                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3948                 break;
3949         case INTEL_PIPE_CRC_SOURCE_NONE:
3950                 *val = 0;
3951                 break;
3952         default:
3953                 return -EINVAL;
3954         }
3955
3956         return 0;
3957 }
3958
3959 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3960 {
3961         struct drm_i915_private *dev_priv = dev->dev_private;
3962         struct intel_crtc *crtc =
3963                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3964         struct intel_crtc_state *pipe_config;
3965         struct drm_atomic_state *state;
3966         int ret = 0;
3967
3968         drm_modeset_lock_all(dev);
3969         state = drm_atomic_state_alloc(dev);
3970         if (!state) {
3971                 ret = -ENOMEM;
3972                 goto out;
3973         }
3974
3975         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3976         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3977         if (IS_ERR(pipe_config)) {
3978                 ret = PTR_ERR(pipe_config);
3979                 goto out;
3980         }
3981
3982         pipe_config->pch_pfit.force_thru = enable;
3983         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3984             pipe_config->pch_pfit.enabled != enable)
3985                 pipe_config->base.connectors_changed = true;
3986
3987         ret = drm_atomic_commit(state);
3988 out:
3989         drm_modeset_unlock_all(dev);
3990         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3991         if (ret)
3992                 drm_atomic_state_free(state);
3993 }
3994
3995 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3996                                 enum pipe pipe,
3997                                 enum intel_pipe_crc_source *source,
3998                                 uint32_t *val)
3999 {
4000         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4001                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4002
4003         switch (*source) {
4004         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4005                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4006                 break;
4007         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4008                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4009                 break;
4010         case INTEL_PIPE_CRC_SOURCE_PF:
4011                 if (IS_HASWELL(dev) && pipe == PIPE_A)
4012                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
4013
4014                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4015                 break;
4016         case INTEL_PIPE_CRC_SOURCE_NONE:
4017                 *val = 0;
4018                 break;
4019         default:
4020                 return -EINVAL;
4021         }
4022
4023         return 0;
4024 }
4025
4026 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4027                                enum intel_pipe_crc_source source)
4028 {
4029         struct drm_i915_private *dev_priv = dev->dev_private;
4030         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4031         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4032                                                                         pipe));
4033         u32 val = 0; /* shut up gcc */
4034         int ret;
4035
4036         if (pipe_crc->source == source)
4037                 return 0;
4038
4039         /* forbid changing the source without going back to 'none' */
4040         if (pipe_crc->source && source)
4041                 return -EINVAL;
4042
4043         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
4044                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4045                 return -EIO;
4046         }
4047
4048         if (IS_GEN2(dev))
4049                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4050         else if (INTEL_INFO(dev)->gen < 5)
4051                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4052         else if (IS_VALLEYVIEW(dev))
4053                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4054         else if (IS_GEN5(dev) || IS_GEN6(dev))
4055                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4056         else
4057                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4058
4059         if (ret != 0)
4060                 return ret;
4061
4062         /* none -> real source transition */
4063         if (source) {
4064                 struct intel_pipe_crc_entry *entries;
4065
4066                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4067                                  pipe_name(pipe), pipe_crc_source_name(source));
4068
4069                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4070                                   sizeof(pipe_crc->entries[0]),
4071                                   GFP_KERNEL);
4072                 if (!entries)
4073                         return -ENOMEM;
4074
4075                 /*
4076                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4077                  * enabled and disabled dynamically based on package C states,
4078                  * user space can't make reliable use of the CRCs, so let's just
4079                  * completely disable it.
4080                  */
4081                 hsw_disable_ips(crtc);
4082
4083                 spin_lock_irq(&pipe_crc->lock);
4084                 kfree(pipe_crc->entries);
4085                 pipe_crc->entries = entries;
4086                 pipe_crc->head = 0;
4087                 pipe_crc->tail = 0;
4088                 spin_unlock_irq(&pipe_crc->lock);
4089         }
4090
4091         pipe_crc->source = source;
4092
4093         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4094         POSTING_READ(PIPE_CRC_CTL(pipe));
4095
4096         /* real source -> none transition */
4097         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4098                 struct intel_pipe_crc_entry *entries;
4099                 struct intel_crtc *crtc =
4100                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4101
4102                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4103                                  pipe_name(pipe));
4104
4105                 drm_modeset_lock(&crtc->base.mutex, NULL);
4106                 if (crtc->base.state->active)
4107                         intel_wait_for_vblank(dev, pipe);
4108                 drm_modeset_unlock(&crtc->base.mutex);
4109
4110                 spin_lock_irq(&pipe_crc->lock);
4111                 entries = pipe_crc->entries;
4112                 pipe_crc->entries = NULL;
4113                 pipe_crc->head = 0;
4114                 pipe_crc->tail = 0;
4115                 spin_unlock_irq(&pipe_crc->lock);
4116
4117                 kfree(entries);
4118
4119                 if (IS_G4X(dev))
4120                         g4x_undo_pipe_scramble_reset(dev, pipe);
4121                 else if (IS_VALLEYVIEW(dev))
4122                         vlv_undo_pipe_scramble_reset(dev, pipe);
4123                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4124                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4125
4126                 hsw_enable_ips(crtc);
4127         }
4128
4129         return 0;
4130 }
4131
4132 /*
4133  * Parse pipe CRC command strings:
4134  *   command: wsp* object wsp+ name wsp+ source wsp*
4135  *   object: 'pipe'
4136  *   name: (A | B | C)
4137  *   source: (none | plane1 | plane2 | pf)
4138  *   wsp: (#0x20 | #0x9 | #0xA)+
4139  *
4140  * eg.:
4141  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4142  *  "pipe A none"    ->  Stop CRC
4143  */
4144 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4145 {
4146         int n_words = 0;
4147
4148         while (*buf) {
4149                 char *end;
4150
4151                 /* skip leading white space */
4152                 buf = skip_spaces(buf);
4153                 if (!*buf)
4154                         break;  /* end of buffer */
4155
4156                 /* find end of word */
4157                 for (end = buf; *end && !isspace(*end); end++)
4158                         ;
4159
4160                 if (n_words == max_words) {
4161                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4162                                          max_words);
4163                         return -EINVAL; /* ran out of words[] before bytes */
4164                 }
4165
4166                 if (*end)
4167                         *end++ = '\0';
4168                 words[n_words++] = buf;
4169                 buf = end;
4170         }
4171
4172         return n_words;
4173 }
4174
4175 enum intel_pipe_crc_object {
4176         PIPE_CRC_OBJECT_PIPE,
4177 };
4178
4179 static const char * const pipe_crc_objects[] = {
4180         "pipe",
4181 };
4182
4183 static int
4184 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4185 {
4186         int i;
4187
4188         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4189                 if (!strcmp(buf, pipe_crc_objects[i])) {
4190                         *o = i;
4191                         return 0;
4192                     }
4193
4194         return -EINVAL;
4195 }
4196
4197 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4198 {
4199         const char name = buf[0];
4200
4201         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4202                 return -EINVAL;
4203
4204         *pipe = name - 'A';
4205
4206         return 0;
4207 }
4208
4209 static int
4210 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4211 {
4212         int i;
4213
4214         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4215                 if (!strcmp(buf, pipe_crc_sources[i])) {
4216                         *s = i;
4217                         return 0;
4218                     }
4219
4220         return -EINVAL;
4221 }
4222
4223 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4224 {
4225 #define N_WORDS 3
4226         int n_words;
4227         char *words[N_WORDS];
4228         enum pipe pipe;
4229         enum intel_pipe_crc_object object;
4230         enum intel_pipe_crc_source source;
4231
4232         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4233         if (n_words != N_WORDS) {
4234                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4235                                  N_WORDS);
4236                 return -EINVAL;
4237         }
4238
4239         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4240                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4241                 return -EINVAL;
4242         }
4243
4244         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4245                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4246                 return -EINVAL;
4247         }
4248
4249         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4250                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4251                 return -EINVAL;
4252         }
4253
4254         return pipe_crc_set_source(dev, pipe, source);
4255 }
4256
4257 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4258                                      size_t len, loff_t *offp)
4259 {
4260         struct seq_file *m = file->private_data;
4261         struct drm_device *dev = m->private;
4262         char *tmpbuf;
4263         int ret;
4264
4265         if (len == 0)
4266                 return 0;
4267
4268         if (len > PAGE_SIZE - 1) {
4269                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4270                                  PAGE_SIZE);
4271                 return -E2BIG;
4272         }
4273
4274         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4275         if (!tmpbuf)
4276                 return -ENOMEM;
4277
4278         if (copy_from_user(tmpbuf, ubuf, len)) {
4279                 ret = -EFAULT;
4280                 goto out;
4281         }
4282         tmpbuf[len] = '\0';
4283
4284         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4285
4286 out:
4287         kfree(tmpbuf);
4288         if (ret < 0)
4289                 return ret;
4290
4291         *offp += len;
4292         return len;
4293 }
4294
4295 static const struct file_operations i915_display_crc_ctl_fops = {
4296         .owner = THIS_MODULE,
4297         .open = display_crc_ctl_open,
4298         .read = seq_read,
4299         .llseek = seq_lseek,
4300         .release = single_release,
4301         .write = display_crc_ctl_write
4302 };
4303
4304 static ssize_t i915_displayport_test_active_write(struct file *file,
4305                                             const char __user *ubuf,
4306                                             size_t len, loff_t *offp)
4307 {
4308         char *input_buffer;
4309         int status = 0;
4310         struct drm_device *dev;
4311         struct drm_connector *connector;
4312         struct list_head *connector_list;
4313         struct intel_dp *intel_dp;
4314         int val = 0;
4315
4316         dev = ((struct seq_file *)file->private_data)->private;
4317
4318         connector_list = &dev->mode_config.connector_list;
4319
4320         if (len == 0)
4321                 return 0;
4322
4323         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4324         if (!input_buffer)
4325                 return -ENOMEM;
4326
4327         if (copy_from_user(input_buffer, ubuf, len)) {
4328                 status = -EFAULT;
4329                 goto out;
4330         }
4331
4332         input_buffer[len] = '\0';
4333         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4334
4335         list_for_each_entry(connector, connector_list, head) {
4336
4337                 if (connector->connector_type !=
4338                     DRM_MODE_CONNECTOR_DisplayPort)
4339                         continue;
4340
4341                 if (connector->status == connector_status_connected &&
4342                     connector->encoder != NULL) {
4343                         intel_dp = enc_to_intel_dp(connector->encoder);
4344                         status = kstrtoint(input_buffer, 10, &val);
4345                         if (status < 0)
4346                                 goto out;
4347                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4348                         /* To prevent erroneous activation of the compliance
4349                          * testing code, only accept an actual value of 1 here
4350                          */
4351                         if (val == 1)
4352                                 intel_dp->compliance_test_active = 1;
4353                         else
4354                                 intel_dp->compliance_test_active = 0;
4355                 }
4356         }
4357 out:
4358         kfree(input_buffer);
4359         if (status < 0)
4360                 return status;
4361
4362         *offp += len;
4363         return len;
4364 }
4365
4366 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4367 {
4368         struct drm_device *dev = m->private;
4369         struct drm_connector *connector;
4370         struct list_head *connector_list = &dev->mode_config.connector_list;
4371         struct intel_dp *intel_dp;
4372
4373         list_for_each_entry(connector, connector_list, head) {
4374
4375                 if (connector->connector_type !=
4376                     DRM_MODE_CONNECTOR_DisplayPort)
4377                         continue;
4378
4379                 if (connector->status == connector_status_connected &&
4380                     connector->encoder != NULL) {
4381                         intel_dp = enc_to_intel_dp(connector->encoder);
4382                         if (intel_dp->compliance_test_active)
4383                                 seq_puts(m, "1");
4384                         else
4385                                 seq_puts(m, "0");
4386                 } else
4387                         seq_puts(m, "0");
4388         }
4389
4390         return 0;
4391 }
4392
4393 static int i915_displayport_test_active_open(struct inode *inode,
4394                                        struct file *file)
4395 {
4396         struct drm_device *dev = inode->i_private;
4397
4398         return single_open(file, i915_displayport_test_active_show, dev);
4399 }
4400
4401 static const struct file_operations i915_displayport_test_active_fops = {
4402         .owner = THIS_MODULE,
4403         .open = i915_displayport_test_active_open,
4404         .read = seq_read,
4405         .llseek = seq_lseek,
4406         .release = single_release,
4407         .write = i915_displayport_test_active_write
4408 };
4409
4410 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4411 {
4412         struct drm_device *dev = m->private;
4413         struct drm_connector *connector;
4414         struct list_head *connector_list = &dev->mode_config.connector_list;
4415         struct intel_dp *intel_dp;
4416
4417         list_for_each_entry(connector, connector_list, head) {
4418
4419                 if (connector->connector_type !=
4420                     DRM_MODE_CONNECTOR_DisplayPort)
4421                         continue;
4422
4423                 if (connector->status == connector_status_connected &&
4424                     connector->encoder != NULL) {
4425                         intel_dp = enc_to_intel_dp(connector->encoder);
4426                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4427                 } else
4428                         seq_puts(m, "0");
4429         }
4430
4431         return 0;
4432 }
4433 static int i915_displayport_test_data_open(struct inode *inode,
4434                                        struct file *file)
4435 {
4436         struct drm_device *dev = inode->i_private;
4437
4438         return single_open(file, i915_displayport_test_data_show, dev);
4439 }
4440
4441 static const struct file_operations i915_displayport_test_data_fops = {
4442         .owner = THIS_MODULE,
4443         .open = i915_displayport_test_data_open,
4444         .read = seq_read,
4445         .llseek = seq_lseek,
4446         .release = single_release
4447 };
4448
4449 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4450 {
4451         struct drm_device *dev = m->private;
4452         struct drm_connector *connector;
4453         struct list_head *connector_list = &dev->mode_config.connector_list;
4454         struct intel_dp *intel_dp;
4455
4456         list_for_each_entry(connector, connector_list, head) {
4457
4458                 if (connector->connector_type !=
4459                     DRM_MODE_CONNECTOR_DisplayPort)
4460                         continue;
4461
4462                 if (connector->status == connector_status_connected &&
4463                     connector->encoder != NULL) {
4464                         intel_dp = enc_to_intel_dp(connector->encoder);
4465                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4466                 } else
4467                         seq_puts(m, "0");
4468         }
4469
4470         return 0;
4471 }
4472
4473 static int i915_displayport_test_type_open(struct inode *inode,
4474                                        struct file *file)
4475 {
4476         struct drm_device *dev = inode->i_private;
4477
4478         return single_open(file, i915_displayport_test_type_show, dev);
4479 }
4480
4481 static const struct file_operations i915_displayport_test_type_fops = {
4482         .owner = THIS_MODULE,
4483         .open = i915_displayport_test_type_open,
4484         .read = seq_read,
4485         .llseek = seq_lseek,
4486         .release = single_release
4487 };
4488
4489 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4490 {
4491         struct drm_device *dev = m->private;
4492         int level;
4493         int num_levels;
4494
4495         if (IS_CHERRYVIEW(dev))
4496                 num_levels = 3;
4497         else if (IS_VALLEYVIEW(dev))
4498                 num_levels = 1;
4499         else
4500                 num_levels = ilk_wm_max_level(dev) + 1;
4501
4502         drm_modeset_lock_all(dev);
4503
4504         for (level = 0; level < num_levels; level++) {
4505                 unsigned int latency = wm[level];
4506
4507                 /*
4508                  * - WM1+ latency values in 0.5us units
4509                  * - latencies are in us on gen9/vlv/chv
4510                  */
4511                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4512                         latency *= 10;
4513                 else if (level > 0)
4514                         latency *= 5;
4515
4516                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4517                            level, wm[level], latency / 10, latency % 10);
4518         }
4519
4520         drm_modeset_unlock_all(dev);
4521 }
4522
4523 static int pri_wm_latency_show(struct seq_file *m, void *data)
4524 {
4525         struct drm_device *dev = m->private;
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         const uint16_t *latencies;
4528
4529         if (INTEL_INFO(dev)->gen >= 9)
4530                 latencies = dev_priv->wm.skl_latency;
4531         else
4532                 latencies = to_i915(dev)->wm.pri_latency;
4533
4534         wm_latency_show(m, latencies);
4535
4536         return 0;
4537 }
4538
4539 static int spr_wm_latency_show(struct seq_file *m, void *data)
4540 {
4541         struct drm_device *dev = m->private;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         const uint16_t *latencies;
4544
4545         if (INTEL_INFO(dev)->gen >= 9)
4546                 latencies = dev_priv->wm.skl_latency;
4547         else
4548                 latencies = to_i915(dev)->wm.spr_latency;
4549
4550         wm_latency_show(m, latencies);
4551
4552         return 0;
4553 }
4554
4555 static int cur_wm_latency_show(struct seq_file *m, void *data)
4556 {
4557         struct drm_device *dev = m->private;
4558         struct drm_i915_private *dev_priv = dev->dev_private;
4559         const uint16_t *latencies;
4560
4561         if (INTEL_INFO(dev)->gen >= 9)
4562                 latencies = dev_priv->wm.skl_latency;
4563         else
4564                 latencies = to_i915(dev)->wm.cur_latency;
4565
4566         wm_latency_show(m, latencies);
4567
4568         return 0;
4569 }
4570
4571 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4572 {
4573         struct drm_device *dev = inode->i_private;
4574
4575         if (INTEL_INFO(dev)->gen < 5)
4576                 return -ENODEV;
4577
4578         return single_open(file, pri_wm_latency_show, dev);
4579 }
4580
4581 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4582 {
4583         struct drm_device *dev = inode->i_private;
4584
4585         if (HAS_GMCH_DISPLAY(dev))
4586                 return -ENODEV;
4587
4588         return single_open(file, spr_wm_latency_show, dev);
4589 }
4590
4591 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4592 {
4593         struct drm_device *dev = inode->i_private;
4594
4595         if (HAS_GMCH_DISPLAY(dev))
4596                 return -ENODEV;
4597
4598         return single_open(file, cur_wm_latency_show, dev);
4599 }
4600
4601 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4602                                 size_t len, loff_t *offp, uint16_t wm[8])
4603 {
4604         struct seq_file *m = file->private_data;
4605         struct drm_device *dev = m->private;
4606         uint16_t new[8] = { 0 };
4607         int num_levels;
4608         int level;
4609         int ret;
4610         char tmp[32];
4611
4612         if (IS_CHERRYVIEW(dev))
4613                 num_levels = 3;
4614         else if (IS_VALLEYVIEW(dev))
4615                 num_levels = 1;
4616         else
4617                 num_levels = ilk_wm_max_level(dev) + 1;
4618
4619         if (len >= sizeof(tmp))
4620                 return -EINVAL;
4621
4622         if (copy_from_user(tmp, ubuf, len))
4623                 return -EFAULT;
4624
4625         tmp[len] = '\0';
4626
4627         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4628                      &new[0], &new[1], &new[2], &new[3],
4629                      &new[4], &new[5], &new[6], &new[7]);
4630         if (ret != num_levels)
4631                 return -EINVAL;
4632
4633         drm_modeset_lock_all(dev);
4634
4635         for (level = 0; level < num_levels; level++)
4636                 wm[level] = new[level];
4637
4638         drm_modeset_unlock_all(dev);
4639
4640         return len;
4641 }
4642
4643
4644 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4645                                     size_t len, loff_t *offp)
4646 {
4647         struct seq_file *m = file->private_data;
4648         struct drm_device *dev = m->private;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         uint16_t *latencies;
4651
4652         if (INTEL_INFO(dev)->gen >= 9)
4653                 latencies = dev_priv->wm.skl_latency;
4654         else
4655                 latencies = to_i915(dev)->wm.pri_latency;
4656
4657         return wm_latency_write(file, ubuf, len, offp, latencies);
4658 }
4659
4660 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4661                                     size_t len, loff_t *offp)
4662 {
4663         struct seq_file *m = file->private_data;
4664         struct drm_device *dev = m->private;
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         uint16_t *latencies;
4667
4668         if (INTEL_INFO(dev)->gen >= 9)
4669                 latencies = dev_priv->wm.skl_latency;
4670         else
4671                 latencies = to_i915(dev)->wm.spr_latency;
4672
4673         return wm_latency_write(file, ubuf, len, offp, latencies);
4674 }
4675
4676 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4677                                     size_t len, loff_t *offp)
4678 {
4679         struct seq_file *m = file->private_data;
4680         struct drm_device *dev = m->private;
4681         struct drm_i915_private *dev_priv = dev->dev_private;
4682         uint16_t *latencies;
4683
4684         if (INTEL_INFO(dev)->gen >= 9)
4685                 latencies = dev_priv->wm.skl_latency;
4686         else
4687                 latencies = to_i915(dev)->wm.cur_latency;
4688
4689         return wm_latency_write(file, ubuf, len, offp, latencies);
4690 }
4691
4692 static const struct file_operations i915_pri_wm_latency_fops = {
4693         .owner = THIS_MODULE,
4694         .open = pri_wm_latency_open,
4695         .read = seq_read,
4696         .llseek = seq_lseek,
4697         .release = single_release,
4698         .write = pri_wm_latency_write
4699 };
4700
4701 static const struct file_operations i915_spr_wm_latency_fops = {
4702         .owner = THIS_MODULE,
4703         .open = spr_wm_latency_open,
4704         .read = seq_read,
4705         .llseek = seq_lseek,
4706         .release = single_release,
4707         .write = spr_wm_latency_write
4708 };
4709
4710 static const struct file_operations i915_cur_wm_latency_fops = {
4711         .owner = THIS_MODULE,
4712         .open = cur_wm_latency_open,
4713         .read = seq_read,
4714         .llseek = seq_lseek,
4715         .release = single_release,
4716         .write = cur_wm_latency_write
4717 };
4718
4719 static int
4720 i915_wedged_get(void *data, u64 *val)
4721 {
4722         struct drm_device *dev = data;
4723         struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4726
4727         return 0;
4728 }
4729
4730 static int
4731 i915_wedged_set(void *data, u64 val)
4732 {
4733         struct drm_device *dev = data;
4734         struct drm_i915_private *dev_priv = dev->dev_private;
4735
4736         /*
4737          * There is no safeguard against this debugfs entry colliding
4738          * with the hangcheck calling same i915_handle_error() in
4739          * parallel, causing an explosion. For now we assume that the
4740          * test harness is responsible enough not to inject gpu hangs
4741          * while it is writing to 'i915_wedged'
4742          */
4743
4744         if (i915_reset_in_progress(&dev_priv->gpu_error))
4745                 return -EAGAIN;
4746
4747         intel_runtime_pm_get(dev_priv);
4748
4749         i915_handle_error(dev, val,
4750                           "Manually setting wedged to %llu", val);
4751
4752         intel_runtime_pm_put(dev_priv);
4753
4754         return 0;
4755 }
4756
4757 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4758                         i915_wedged_get, i915_wedged_set,
4759                         "%llu\n");
4760
4761 static int
4762 i915_ring_stop_get(void *data, u64 *val)
4763 {
4764         struct drm_device *dev = data;
4765         struct drm_i915_private *dev_priv = dev->dev_private;
4766
4767         *val = dev_priv->gpu_error.stop_rings;
4768
4769         return 0;
4770 }
4771
4772 static int
4773 i915_ring_stop_set(void *data, u64 val)
4774 {
4775         struct drm_device *dev = data;
4776         struct drm_i915_private *dev_priv = dev->dev_private;
4777         int ret;
4778
4779         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4780
4781         ret = mutex_lock_interruptible(&dev->struct_mutex);
4782         if (ret)
4783                 return ret;
4784
4785         dev_priv->gpu_error.stop_rings = val;
4786         mutex_unlock(&dev->struct_mutex);
4787
4788         return 0;
4789 }
4790
4791 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4792                         i915_ring_stop_get, i915_ring_stop_set,
4793                         "0x%08llx\n");
4794
4795 static int
4796 i915_ring_missed_irq_get(void *data, u64 *val)
4797 {
4798         struct drm_device *dev = data;
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800
4801         *val = dev_priv->gpu_error.missed_irq_rings;
4802         return 0;
4803 }
4804
4805 static int
4806 i915_ring_missed_irq_set(void *data, u64 val)
4807 {
4808         struct drm_device *dev = data;
4809         struct drm_i915_private *dev_priv = dev->dev_private;
4810         int ret;
4811
4812         /* Lock against concurrent debugfs callers */
4813         ret = mutex_lock_interruptible(&dev->struct_mutex);
4814         if (ret)
4815                 return ret;
4816         dev_priv->gpu_error.missed_irq_rings = val;
4817         mutex_unlock(&dev->struct_mutex);
4818
4819         return 0;
4820 }
4821
4822 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4823                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4824                         "0x%08llx\n");
4825
4826 static int
4827 i915_ring_test_irq_get(void *data, u64 *val)
4828 {
4829         struct drm_device *dev = data;
4830         struct drm_i915_private *dev_priv = dev->dev_private;
4831
4832         *val = dev_priv->gpu_error.test_irq_rings;
4833
4834         return 0;
4835 }
4836
4837 static int
4838 i915_ring_test_irq_set(void *data, u64 val)
4839 {
4840         struct drm_device *dev = data;
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         int ret;
4843
4844         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4845
4846         /* Lock against concurrent debugfs callers */
4847         ret = mutex_lock_interruptible(&dev->struct_mutex);
4848         if (ret)
4849                 return ret;
4850
4851         dev_priv->gpu_error.test_irq_rings = val;
4852         mutex_unlock(&dev->struct_mutex);
4853
4854         return 0;
4855 }
4856
4857 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4858                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4859                         "0x%08llx\n");
4860
4861 #define DROP_UNBOUND 0x1
4862 #define DROP_BOUND 0x2
4863 #define DROP_RETIRE 0x4
4864 #define DROP_ACTIVE 0x8
4865 #define DROP_ALL (DROP_UNBOUND | \
4866                   DROP_BOUND | \
4867                   DROP_RETIRE | \
4868                   DROP_ACTIVE)
4869 static int
4870 i915_drop_caches_get(void *data, u64 *val)
4871 {
4872         *val = DROP_ALL;
4873
4874         return 0;
4875 }
4876
4877 static int
4878 i915_drop_caches_set(void *data, u64 val)
4879 {
4880         struct drm_device *dev = data;
4881         struct drm_i915_private *dev_priv = dev->dev_private;
4882         int ret;
4883
4884         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4885
4886         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4887          * on ioctls on -EAGAIN. */
4888         ret = mutex_lock_interruptible(&dev->struct_mutex);
4889         if (ret)
4890                 return ret;
4891
4892         if (val & DROP_ACTIVE) {
4893                 ret = i915_gpu_idle(dev);
4894                 if (ret)
4895                         goto unlock;
4896         }
4897
4898         if (val & (DROP_RETIRE | DROP_ACTIVE))
4899                 i915_gem_retire_requests(dev);
4900
4901         if (val & DROP_BOUND)
4902                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4903
4904         if (val & DROP_UNBOUND)
4905                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4906
4907 unlock:
4908         mutex_unlock(&dev->struct_mutex);
4909
4910         return ret;
4911 }
4912
4913 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4914                         i915_drop_caches_get, i915_drop_caches_set,
4915                         "0x%08llx\n");
4916
4917 static int
4918 i915_max_freq_get(void *data, u64 *val)
4919 {
4920         struct drm_device *dev = data;
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         int ret;
4923
4924         if (INTEL_INFO(dev)->gen < 6)
4925                 return -ENODEV;
4926
4927         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4928
4929         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4930         if (ret)
4931                 return ret;
4932
4933         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4934         mutex_unlock(&dev_priv->rps.hw_lock);
4935
4936         return 0;
4937 }
4938
4939 static int
4940 i915_max_freq_set(void *data, u64 val)
4941 {
4942         struct drm_device *dev = data;
4943         struct drm_i915_private *dev_priv = dev->dev_private;
4944         u32 hw_max, hw_min;
4945         int ret;
4946
4947         if (INTEL_INFO(dev)->gen < 6)
4948                 return -ENODEV;
4949
4950         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4951
4952         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4953
4954         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4955         if (ret)
4956                 return ret;
4957
4958         /*
4959          * Turbo will still be enabled, but won't go above the set value.
4960          */
4961         val = intel_freq_opcode(dev_priv, val);
4962
4963         hw_max = dev_priv->rps.max_freq;
4964         hw_min = dev_priv->rps.min_freq;
4965
4966         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4967                 mutex_unlock(&dev_priv->rps.hw_lock);
4968                 return -EINVAL;
4969         }
4970
4971         dev_priv->rps.max_freq_softlimit = val;
4972
4973         intel_set_rps(dev, val);
4974
4975         mutex_unlock(&dev_priv->rps.hw_lock);
4976
4977         return 0;
4978 }
4979
4980 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4981                         i915_max_freq_get, i915_max_freq_set,
4982                         "%llu\n");
4983
4984 static int
4985 i915_min_freq_get(void *data, u64 *val)
4986 {
4987         struct drm_device *dev = data;
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         int ret;
4990
4991         if (INTEL_INFO(dev)->gen < 6)
4992                 return -ENODEV;
4993
4994         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4995
4996         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4997         if (ret)
4998                 return ret;
4999
5000         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5001         mutex_unlock(&dev_priv->rps.hw_lock);
5002
5003         return 0;
5004 }
5005
5006 static int
5007 i915_min_freq_set(void *data, u64 val)
5008 {
5009         struct drm_device *dev = data;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         u32 hw_max, hw_min;
5012         int ret;
5013
5014         if (INTEL_INFO(dev)->gen < 6)
5015                 return -ENODEV;
5016
5017         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5018
5019         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5020
5021         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5022         if (ret)
5023                 return ret;
5024
5025         /*
5026          * Turbo will still be enabled, but won't go below the set value.
5027          */
5028         val = intel_freq_opcode(dev_priv, val);
5029
5030         hw_max = dev_priv->rps.max_freq;
5031         hw_min = dev_priv->rps.min_freq;
5032
5033         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5034                 mutex_unlock(&dev_priv->rps.hw_lock);
5035                 return -EINVAL;
5036         }
5037
5038         dev_priv->rps.min_freq_softlimit = val;
5039
5040         intel_set_rps(dev, val);
5041
5042         mutex_unlock(&dev_priv->rps.hw_lock);
5043
5044         return 0;
5045 }
5046
5047 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5048                         i915_min_freq_get, i915_min_freq_set,
5049                         "%llu\n");
5050
5051 static int
5052 i915_cache_sharing_get(void *data, u64 *val)
5053 {
5054         struct drm_device *dev = data;
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         u32 snpcr;
5057         int ret;
5058
5059         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5060                 return -ENODEV;
5061
5062         ret = mutex_lock_interruptible(&dev->struct_mutex);
5063         if (ret)
5064                 return ret;
5065         intel_runtime_pm_get(dev_priv);
5066
5067         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5068
5069         intel_runtime_pm_put(dev_priv);
5070         mutex_unlock(&dev_priv->dev->struct_mutex);
5071
5072         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5073
5074         return 0;
5075 }
5076
5077 static int
5078 i915_cache_sharing_set(void *data, u64 val)
5079 {
5080         struct drm_device *dev = data;
5081         struct drm_i915_private *dev_priv = dev->dev_private;
5082         u32 snpcr;
5083
5084         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5085                 return -ENODEV;
5086
5087         if (val > 3)
5088                 return -EINVAL;
5089
5090         intel_runtime_pm_get(dev_priv);
5091         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5092
5093         /* Update the cache sharing policy here as well */
5094         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5095         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5096         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5097         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5098
5099         intel_runtime_pm_put(dev_priv);
5100         return 0;
5101 }
5102
5103 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5104                         i915_cache_sharing_get, i915_cache_sharing_set,
5105                         "%llu\n");
5106
5107 struct sseu_dev_status {
5108         unsigned int slice_total;
5109         unsigned int subslice_total;
5110         unsigned int subslice_per_slice;
5111         unsigned int eu_total;
5112         unsigned int eu_per_subslice;
5113 };
5114
5115 static void cherryview_sseu_device_status(struct drm_device *dev,
5116                                           struct sseu_dev_status *stat)
5117 {
5118         struct drm_i915_private *dev_priv = dev->dev_private;
5119         int ss_max = 2;
5120         int ss;
5121         u32 sig1[ss_max], sig2[ss_max];
5122
5123         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5124         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5125         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5126         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5127
5128         for (ss = 0; ss < ss_max; ss++) {
5129                 unsigned int eu_cnt;
5130
5131                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5132                         /* skip disabled subslice */
5133                         continue;
5134
5135                 stat->slice_total = 1;
5136                 stat->subslice_per_slice++;
5137                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5138                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5139                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5140                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5141                 stat->eu_total += eu_cnt;
5142                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5143         }
5144         stat->subslice_total = stat->subslice_per_slice;
5145 }
5146
5147 static void gen9_sseu_device_status(struct drm_device *dev,
5148                                     struct sseu_dev_status *stat)
5149 {
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         int s_max = 3, ss_max = 4;
5152         int s, ss;
5153         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5154
5155         /* BXT has a single slice and at most 3 subslices. */
5156         if (IS_BROXTON(dev)) {
5157                 s_max = 1;
5158                 ss_max = 3;
5159         }
5160
5161         for (s = 0; s < s_max; s++) {
5162                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5163                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5164                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5165         }
5166
5167         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5168                      GEN9_PGCTL_SSA_EU19_ACK |
5169                      GEN9_PGCTL_SSA_EU210_ACK |
5170                      GEN9_PGCTL_SSA_EU311_ACK;
5171         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5172                      GEN9_PGCTL_SSB_EU19_ACK |
5173                      GEN9_PGCTL_SSB_EU210_ACK |
5174                      GEN9_PGCTL_SSB_EU311_ACK;
5175
5176         for (s = 0; s < s_max; s++) {
5177                 unsigned int ss_cnt = 0;
5178
5179                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5180                         /* skip disabled slice */
5181                         continue;
5182
5183                 stat->slice_total++;
5184
5185                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5186                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5187
5188                 for (ss = 0; ss < ss_max; ss++) {
5189                         unsigned int eu_cnt;
5190
5191                         if (IS_BROXTON(dev) &&
5192                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5193                                 /* skip disabled subslice */
5194                                 continue;
5195
5196                         if (IS_BROXTON(dev))
5197                                 ss_cnt++;
5198
5199                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5200                                                eu_mask[ss%2]);
5201                         stat->eu_total += eu_cnt;
5202                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5203                                                     eu_cnt);
5204                 }
5205
5206                 stat->subslice_total += ss_cnt;
5207                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5208                                                ss_cnt);
5209         }
5210 }
5211
5212 static void broadwell_sseu_device_status(struct drm_device *dev,
5213                                          struct sseu_dev_status *stat)
5214 {
5215         struct drm_i915_private *dev_priv = dev->dev_private;
5216         int s;
5217         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5218
5219         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5220
5221         if (stat->slice_total) {
5222                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5223                 stat->subslice_total = stat->slice_total *
5224                                        stat->subslice_per_slice;
5225                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5226                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5227
5228                 /* subtract fused off EU(s) from enabled slice(s) */
5229                 for (s = 0; s < stat->slice_total; s++) {
5230                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5231
5232                         stat->eu_total -= hweight8(subslice_7eu);
5233                 }
5234         }
5235 }
5236
5237 static int i915_sseu_status(struct seq_file *m, void *unused)
5238 {
5239         struct drm_info_node *node = (struct drm_info_node *) m->private;
5240         struct drm_device *dev = node->minor->dev;
5241         struct sseu_dev_status stat;
5242
5243         if (INTEL_INFO(dev)->gen < 8)
5244                 return -ENODEV;
5245
5246         seq_puts(m, "SSEU Device Info\n");
5247         seq_printf(m, "  Available Slice Total: %u\n",
5248                    INTEL_INFO(dev)->slice_total);
5249         seq_printf(m, "  Available Subslice Total: %u\n",
5250                    INTEL_INFO(dev)->subslice_total);
5251         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5252                    INTEL_INFO(dev)->subslice_per_slice);
5253         seq_printf(m, "  Available EU Total: %u\n",
5254                    INTEL_INFO(dev)->eu_total);
5255         seq_printf(m, "  Available EU Per Subslice: %u\n",
5256                    INTEL_INFO(dev)->eu_per_subslice);
5257         seq_printf(m, "  Has Slice Power Gating: %s\n",
5258                    yesno(INTEL_INFO(dev)->has_slice_pg));
5259         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5260                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5261         seq_printf(m, "  Has EU Power Gating: %s\n",
5262                    yesno(INTEL_INFO(dev)->has_eu_pg));
5263
5264         seq_puts(m, "SSEU Device Status\n");
5265         memset(&stat, 0, sizeof(stat));
5266         if (IS_CHERRYVIEW(dev)) {
5267                 cherryview_sseu_device_status(dev, &stat);
5268         } else if (IS_BROADWELL(dev)) {
5269                 broadwell_sseu_device_status(dev, &stat);
5270         } else if (INTEL_INFO(dev)->gen >= 9) {
5271                 gen9_sseu_device_status(dev, &stat);
5272         }
5273         seq_printf(m, "  Enabled Slice Total: %u\n",
5274                    stat.slice_total);
5275         seq_printf(m, "  Enabled Subslice Total: %u\n",
5276                    stat.subslice_total);
5277         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5278                    stat.subslice_per_slice);
5279         seq_printf(m, "  Enabled EU Total: %u\n",
5280                    stat.eu_total);
5281         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5282                    stat.eu_per_subslice);
5283
5284         return 0;
5285 }
5286
5287 static int i915_forcewake_open(struct inode *inode, struct file *file)
5288 {
5289         struct drm_device *dev = inode->i_private;
5290         struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292         if (INTEL_INFO(dev)->gen < 6)
5293                 return 0;
5294
5295         intel_runtime_pm_get(dev_priv);
5296         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5297
5298         return 0;
5299 }
5300
5301 static int i915_forcewake_release(struct inode *inode, struct file *file)
5302 {
5303         struct drm_device *dev = inode->i_private;
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305
5306         if (INTEL_INFO(dev)->gen < 6)
5307                 return 0;
5308
5309         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5310         intel_runtime_pm_put(dev_priv);
5311
5312         return 0;
5313 }
5314
5315 static const struct file_operations i915_forcewake_fops = {
5316         .owner = THIS_MODULE,
5317         .open = i915_forcewake_open,
5318         .release = i915_forcewake_release,
5319 };
5320
5321 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5322 {
5323         struct drm_device *dev = minor->dev;
5324         struct dentry *ent;
5325
5326         ent = debugfs_create_file("i915_forcewake_user",
5327                                   S_IRUSR,
5328                                   root, dev,
5329                                   &i915_forcewake_fops);
5330         if (!ent)
5331                 return -ENOMEM;
5332
5333         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5334 }
5335
5336 static int i915_debugfs_create(struct dentry *root,
5337                                struct drm_minor *minor,
5338                                const char *name,
5339                                const struct file_operations *fops)
5340 {
5341         struct drm_device *dev = minor->dev;
5342         struct dentry *ent;
5343
5344         ent = debugfs_create_file(name,
5345                                   S_IRUGO | S_IWUSR,
5346                                   root, dev,
5347                                   fops);
5348         if (!ent)
5349                 return -ENOMEM;
5350
5351         return drm_add_fake_info_node(minor, ent, fops);
5352 }
5353
5354 static const struct drm_info_list i915_debugfs_list[] = {
5355         {"i915_capabilities", i915_capabilities, 0},
5356         {"i915_gem_objects", i915_gem_object_info, 0},
5357         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5358         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5359         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5360         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5361         {"i915_gem_stolen", i915_gem_stolen_list_info },
5362         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5363         {"i915_gem_request", i915_gem_request_info, 0},
5364         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5365         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5366         {"i915_gem_interrupt", i915_interrupt_info, 0},
5367         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5368         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5369         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5370         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5371         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5372         {"i915_guc_info", i915_guc_info, 0},
5373         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5374         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5375         {"i915_frequency_info", i915_frequency_info, 0},
5376         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5377         {"i915_drpc_info", i915_drpc_info, 0},
5378         {"i915_emon_status", i915_emon_status, 0},
5379         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5380         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5381         {"i915_fbc_status", i915_fbc_status, 0},
5382         {"i915_ips_status", i915_ips_status, 0},
5383         {"i915_sr_status", i915_sr_status, 0},
5384         {"i915_opregion", i915_opregion, 0},
5385         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5386         {"i915_context_status", i915_context_status, 0},
5387         {"i915_dump_lrc", i915_dump_lrc, 0},
5388         {"i915_execlists", i915_execlists, 0},
5389         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5390         {"i915_swizzle_info", i915_swizzle_info, 0},
5391         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5392         {"i915_llc", i915_llc, 0},
5393         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5394         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5395         {"i915_energy_uJ", i915_energy_uJ, 0},
5396         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5397         {"i915_power_domain_info", i915_power_domain_info, 0},
5398         {"i915_dmc_info", i915_dmc_info, 0},
5399         {"i915_display_info", i915_display_info, 0},
5400         {"i915_semaphore_status", i915_semaphore_status, 0},
5401         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5402         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5403         {"i915_wa_registers", i915_wa_registers, 0},
5404         {"i915_ddb_info", i915_ddb_info, 0},
5405         {"i915_sseu_status", i915_sseu_status, 0},
5406         {"i915_drrs_status", i915_drrs_status, 0},
5407         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5408 };
5409 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5410
5411 static const struct i915_debugfs_files {
5412         const char *name;
5413         const struct file_operations *fops;
5414 } i915_debugfs_files[] = {
5415         {"i915_wedged", &i915_wedged_fops},
5416         {"i915_max_freq", &i915_max_freq_fops},
5417         {"i915_min_freq", &i915_min_freq_fops},
5418         {"i915_cache_sharing", &i915_cache_sharing_fops},
5419         {"i915_ring_stop", &i915_ring_stop_fops},
5420         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5421         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5422         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5423         {"i915_error_state", &i915_error_state_fops},
5424         {"i915_next_seqno", &i915_next_seqno_fops},
5425         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5426         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5427         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5428         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5429         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5430         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5431         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5432         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5433 };
5434
5435 void intel_display_crc_init(struct drm_device *dev)
5436 {
5437         struct drm_i915_private *dev_priv = dev->dev_private;
5438         enum pipe pipe;
5439
5440         for_each_pipe(dev_priv, pipe) {
5441                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5442
5443                 pipe_crc->opened = false;
5444                 spin_lock_init(&pipe_crc->lock);
5445                 init_waitqueue_head(&pipe_crc->wq);
5446         }
5447 }
5448
5449 int i915_debugfs_init(struct drm_minor *minor)
5450 {
5451         int ret, i;
5452
5453         ret = i915_forcewake_create(minor->debugfs_root, minor);
5454         if (ret)
5455                 return ret;
5456
5457         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5458                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5459                 if (ret)
5460                         return ret;
5461         }
5462
5463         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5464                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5465                                           i915_debugfs_files[i].name,
5466                                           i915_debugfs_files[i].fops);
5467                 if (ret)
5468                         return ret;
5469         }
5470
5471         return drm_debugfs_create_files(i915_debugfs_list,
5472                                         I915_DEBUGFS_ENTRIES,
5473                                         minor->debugfs_root, minor);
5474 }
5475
5476 void i915_debugfs_cleanup(struct drm_minor *minor)
5477 {
5478         int i;
5479
5480         drm_debugfs_remove_files(i915_debugfs_list,
5481                                  I915_DEBUGFS_ENTRIES, minor);
5482
5483         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5484                                  1, minor);
5485
5486         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5487                 struct drm_info_list *info_list =
5488                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5489
5490                 drm_debugfs_remove_files(info_list, 1, minor);
5491         }
5492
5493         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5494                 struct drm_info_list *info_list =
5495                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5496
5497                 drm_debugfs_remove_files(info_list, 1, minor);
5498         }
5499 }
5500
5501 struct dpcd_block {
5502         /* DPCD dump start address. */
5503         unsigned int offset;
5504         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5505         unsigned int end;
5506         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5507         size_t size;
5508         /* Only valid for eDP. */
5509         bool edp;
5510 };
5511
5512 static const struct dpcd_block i915_dpcd_debug[] = {
5513         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5514         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5515         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5516         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5517         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5518         { .offset = DP_SET_POWER },
5519         { .offset = DP_EDP_DPCD_REV },
5520         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5521         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5522         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5523 };
5524
5525 static int i915_dpcd_show(struct seq_file *m, void *data)
5526 {
5527         struct drm_connector *connector = m->private;
5528         struct intel_dp *intel_dp =
5529                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5530         uint8_t buf[16];
5531         ssize_t err;
5532         int i;
5533
5534         if (connector->status != connector_status_connected)
5535                 return -ENODEV;
5536
5537         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5538                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5539                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5540
5541                 if (b->edp &&
5542                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5543                         continue;
5544
5545                 /* low tech for now */
5546                 if (WARN_ON(size > sizeof(buf)))
5547                         continue;
5548
5549                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5550                 if (err <= 0) {
5551                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5552                                   size, b->offset, err);
5553                         continue;
5554                 }
5555
5556                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5557         }
5558
5559         return 0;
5560 }
5561
5562 static int i915_dpcd_open(struct inode *inode, struct file *file)
5563 {
5564         return single_open(file, i915_dpcd_show, inode->i_private);
5565 }
5566
5567 static const struct file_operations i915_dpcd_fops = {
5568         .owner = THIS_MODULE,
5569         .open = i915_dpcd_open,
5570         .read = seq_read,
5571         .llseek = seq_lseek,
5572         .release = single_release,
5573 };
5574
5575 /**
5576  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5577  * @connector: pointer to a registered drm_connector
5578  *
5579  * Cleanup will be done by drm_connector_unregister() through a call to
5580  * drm_debugfs_connector_remove().
5581  *
5582  * Returns 0 on success, negative error codes on error.
5583  */
5584 int i915_debugfs_connector_add(struct drm_connector *connector)
5585 {
5586         struct dentry *root = connector->debugfs_entry;
5587
5588         /* The connector must have been registered beforehands. */
5589         if (!root)
5590                 return -ENODEV;
5591
5592         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5593             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5594                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5595                                     &i915_dpcd_fops);
5596
5597         return 0;
5598 }