2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #include <linux/kthread.h>
38 #include "gem/i915_gem_context.h"
39 #include "gem/i915_gem_pm.h"
40 #include "gt/intel_context.h"
45 #define RING_CTX_OFF(x) \
46 offsetof(struct execlist_ring_context, x)
48 static void set_context_pdp_root_pointer(
49 struct execlist_ring_context *ring_context,
54 for (i = 0; i < 8; i++)
55 ring_context->pdps[i].val = pdp[7 - i];
58 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
60 struct drm_i915_gem_object *ctx_obj =
61 workload->req->hw_context->state->obj;
62 struct execlist_ring_context *shadow_ring_context;
65 if (WARN_ON(!workload->shadow_mm))
68 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
71 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
72 shadow_ring_context = kmap(page);
73 set_context_pdp_root_pointer(shadow_ring_context,
74 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
79 * when populating shadow ctx from guest, we should not overrride oa related
80 * registers, so that they will not be overlapped by guest oa configs. Thus
81 * made it possible to capture oa data from host for both host and guests.
83 static void sr_oa_regs(struct intel_vgpu_workload *workload,
84 u32 *reg_state, bool save)
86 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
87 u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
88 u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
91 i915_mmio_reg_offset(EU_PERF_CNTL0),
92 i915_mmio_reg_offset(EU_PERF_CNTL1),
93 i915_mmio_reg_offset(EU_PERF_CNTL2),
94 i915_mmio_reg_offset(EU_PERF_CNTL3),
95 i915_mmio_reg_offset(EU_PERF_CNTL4),
96 i915_mmio_reg_offset(EU_PERF_CNTL5),
97 i915_mmio_reg_offset(EU_PERF_CNTL6),
100 if (workload->ring_id != RCS0)
104 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
106 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
107 u32 state_offset = ctx_flexeu0 + i * 2;
109 workload->flex_mmio[i] = reg_state[state_offset + 1];
112 reg_state[ctx_oactxctrl] =
113 i915_mmio_reg_offset(GEN8_OACTXCONTROL);
114 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
116 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
117 u32 state_offset = ctx_flexeu0 + i * 2;
118 u32 mmio = flex_mmio[i];
120 reg_state[state_offset] = mmio;
121 reg_state[state_offset + 1] = workload->flex_mmio[i];
126 static int populate_shadow_context(struct intel_vgpu_workload *workload)
128 struct intel_vgpu *vgpu = workload->vgpu;
129 struct intel_gvt *gvt = vgpu->gvt;
130 int ring_id = workload->ring_id;
131 struct drm_i915_gem_object *ctx_obj =
132 workload->req->hw_context->state->obj;
133 struct execlist_ring_context *shadow_ring_context;
136 unsigned long context_gpa, context_page_num;
139 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
140 shadow_ring_context = kmap(page);
142 sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
143 #define COPY_REG(name) \
144 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
145 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
146 #define COPY_REG_MASKED(name) {\
147 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
148 + RING_CTX_OFF(name.val),\
149 &shadow_ring_context->name.val, 4);\
150 shadow_ring_context->name.val |= 0xffff << 16;\
153 COPY_REG_MASKED(ctx_ctrl);
154 COPY_REG(ctx_timestamp);
156 if (ring_id == RCS0) {
157 COPY_REG(bb_per_ctx_ptr);
158 COPY_REG(rcs_indirect_ctx);
159 COPY_REG(rcs_indirect_ctx_offset);
162 #undef COPY_REG_MASKED
164 intel_gvt_hypervisor_read_gpa(vgpu,
165 workload->ring_context_gpa +
166 sizeof(*shadow_ring_context),
167 (void *)shadow_ring_context +
168 sizeof(*shadow_ring_context),
169 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
171 sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
174 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
177 gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
178 workload->ctx_desc.lrca);
180 context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
182 context_page_num = context_page_num >> PAGE_SHIFT;
184 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
185 context_page_num = 19;
188 while (i < context_page_num) {
189 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
190 (u32)((workload->ctx_desc.lrca + i) <<
191 I915_GTT_PAGE_SHIFT));
192 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
193 gvt_vgpu_err("Invalid guest context descriptor\n");
197 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
199 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
207 static inline bool is_gvt_request(struct i915_request *req)
209 return i915_gem_context_force_single_submission(req->gem_context);
212 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
214 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
215 u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
218 reg = RING_INSTDONE(ring_base);
219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
220 reg = RING_ACTHD(ring_base);
221 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
222 reg = RING_ACTHD_UDW(ring_base);
223 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
226 static int shadow_context_status_change(struct notifier_block *nb,
227 unsigned long action, void *data)
229 struct i915_request *req = data;
230 struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
231 shadow_ctx_notifier_block[req->engine->id]);
232 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
233 enum intel_engine_id ring_id = req->engine->id;
234 struct intel_vgpu_workload *workload;
237 if (!is_gvt_request(req)) {
238 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
239 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
240 scheduler->engine_owner[ring_id]) {
241 /* Switch ring from vGPU to host. */
242 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
244 scheduler->engine_owner[ring_id] = NULL;
246 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
251 workload = scheduler->current_workload[ring_id];
252 if (unlikely(!workload))
256 case INTEL_CONTEXT_SCHEDULE_IN:
257 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
258 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
259 /* Switch ring from host to vGPU or vGPU to vGPU. */
260 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
261 workload->vgpu, ring_id);
262 scheduler->engine_owner[ring_id] = workload->vgpu;
264 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
265 ring_id, workload->vgpu->id);
266 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
267 atomic_set(&workload->shadow_ctx_active, 1);
269 case INTEL_CONTEXT_SCHEDULE_OUT:
270 save_ring_hw_state(workload->vgpu, ring_id);
271 atomic_set(&workload->shadow_ctx_active, 0);
273 case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
274 save_ring_hw_state(workload->vgpu, ring_id);
280 wake_up(&workload->shadow_ctx_status_wq);
285 shadow_context_descriptor_update(struct intel_context *ce,
286 struct intel_vgpu_workload *workload)
288 u64 desc = ce->lrc_desc;
291 * Update bits 0-11 of the context descriptor which includes flags
292 * like GEN8_CTX_* cached in desc_template
294 desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
295 desc |= workload->ctx_desc.addressing_mode <<
296 GEN8_CTX_ADDRESSING_MODE_SHIFT;
301 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
303 struct intel_vgpu *vgpu = workload->vgpu;
304 struct i915_request *req = workload->req;
305 void *shadow_ring_buffer_va;
309 if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context))
310 intel_vgpu_restore_inhibit_context(vgpu, req);
313 * To track whether a request has started on HW, we can emit a
314 * breadcrumb at the beginning of the request and check its
315 * timeline's HWSP to see if the breadcrumb has advanced past the
316 * start of this request. Actually, the request must have the
317 * init_breadcrumb if its timeline set has_init_bread_crumb, or the
318 * scheduler might get a wrong state of it during reset. Since the
319 * requests from gvt always set the has_init_breadcrumb flag, here
320 * need to do the emit_init_breadcrumb for all the requests.
322 if (req->engine->emit_init_breadcrumb) {
323 err = req->engine->emit_init_breadcrumb(req);
325 gvt_vgpu_err("fail to emit init breadcrumb\n");
330 /* allocate shadow ring buffer */
331 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
333 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
338 shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
340 /* get shadow ring buffer va */
341 workload->shadow_ring_buffer_va = cs;
343 memcpy(cs, shadow_ring_buffer_va,
346 cs += workload->rb_len / sizeof(u32);
347 intel_ring_advance(workload->req, cs);
352 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
354 if (!wa_ctx->indirect_ctx.obj)
357 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
358 i915_gem_object_put(wa_ctx->indirect_ctx.obj);
360 wa_ctx->indirect_ctx.obj = NULL;
361 wa_ctx->indirect_ctx.shadow_va = NULL;
364 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
365 struct i915_gem_context *ctx)
367 struct intel_vgpu_mm *mm = workload->shadow_mm;
368 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm);
371 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
372 px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
374 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
375 struct i915_page_directory * const pd =
376 i915_pd_entry(ppgtt->pd, i);
378 px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
384 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
386 struct intel_vgpu *vgpu = workload->vgpu;
387 struct intel_vgpu_submission *s = &vgpu->submission;
388 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
389 struct i915_request *rq;
391 lockdep_assert_held(&dev_priv->drm.struct_mutex);
396 rq = i915_request_create(s->shadow[workload->ring_id]);
398 gvt_vgpu_err("fail to allocate gem request\n");
402 workload->req = i915_request_get(rq);
407 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
408 * shadow it as well, include ringbuffer,wa_ctx and ctx.
409 * @workload: an abstract entity for each execlist submission.
411 * This function is called before the workload submitting to i915, to make
412 * sure the content of the workload is valid.
414 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
416 struct intel_vgpu *vgpu = workload->vgpu;
417 struct intel_vgpu_submission *s = &vgpu->submission;
418 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
421 lockdep_assert_held(&dev_priv->drm.struct_mutex);
423 if (workload->shadow)
426 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
427 shadow_context_descriptor_update(s->shadow[workload->ring_id],
430 ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
434 if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
435 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
440 workload->shadow = true;
443 release_shadow_wa_ctx(&workload->wa_ctx);
447 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
449 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
451 struct intel_gvt *gvt = workload->vgpu->gvt;
452 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
453 struct intel_vgpu_shadow_bb *bb;
456 list_for_each_entry(bb, &workload->shadow_bb, list) {
457 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
458 * is only updated into ring_scan_buffer, not real ring address
459 * allocated in later copy_workload_to_ring_buffer. pls be noted
460 * shadow_ring_buffer_va is now pointed to real ring buffer va
461 * in copy_workload_to_ring_buffer.
465 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
469 /* for non-priv bb, scan&shadow is only for
470 * debugging purpose, so the content of shadow bb
471 * is the same as original bb. Therefore,
472 * here, rather than switch to shadow bb's gma
473 * address, we directly use original batch buffer's
474 * gma address, and send original bb to hardware
477 if (bb->clflush & CLFLUSH_AFTER) {
478 drm_clflush_virt_range(bb->va,
480 bb->clflush &= ~CLFLUSH_AFTER;
482 i915_gem_object_finish_access(bb->obj);
483 bb->accessing = false;
486 bb->vma = i915_gem_object_ggtt_pin(bb->obj,
488 if (IS_ERR(bb->vma)) {
489 ret = PTR_ERR(bb->vma);
493 /* relocate shadow batch buffer */
494 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
495 if (gmadr_bytes == 8)
496 bb->bb_start_cmd_va[2] = 0;
498 /* No one is going to touch shadow bb from now on. */
499 if (bb->clflush & CLFLUSH_AFTER) {
500 drm_clflush_virt_range(bb->va,
502 bb->clflush &= ~CLFLUSH_AFTER;
505 ret = i915_gem_object_set_to_gtt_domain(bb->obj,
510 ret = i915_vma_move_to_active(bb->vma,
516 i915_gem_object_finish_access(bb->obj);
517 bb->accessing = false;
522 release_shadow_batch_buffer(workload);
526 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
528 struct intel_vgpu_workload *workload =
529 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
530 struct i915_request *rq = workload->req;
531 struct execlist_ring_context *shadow_ring_context =
532 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
534 shadow_ring_context->bb_per_ctx_ptr.val =
535 (shadow_ring_context->bb_per_ctx_ptr.val &
536 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
537 shadow_ring_context->rcs_indirect_ctx.val =
538 (shadow_ring_context->rcs_indirect_ctx.val &
539 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
542 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
544 struct i915_vma *vma;
545 unsigned char *per_ctx_va =
546 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
547 wa_ctx->indirect_ctx.size;
549 if (wa_ctx->indirect_ctx.size == 0)
552 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
553 0, CACHELINE_BYTES, 0);
557 /* FIXME: we are not tracking our pinned VMA leaving it
558 * up to the core to fix up the stray pin_count upon
562 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
564 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
565 memset(per_ctx_va, 0, CACHELINE_BYTES);
567 update_wa_ctx_2_shadow_ctx(wa_ctx);
571 static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
573 struct intel_vgpu *vgpu = workload->vgpu;
574 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
577 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
578 vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start;
581 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
583 struct intel_vgpu *vgpu = workload->vgpu;
584 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
585 struct intel_vgpu_shadow_bb *bb, *pos;
587 if (list_empty(&workload->shadow_bb))
590 bb = list_first_entry(&workload->shadow_bb,
591 struct intel_vgpu_shadow_bb, list);
593 mutex_lock(&dev_priv->drm.struct_mutex);
595 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
598 i915_gem_object_finish_access(bb->obj);
600 if (bb->va && !IS_ERR(bb->va))
601 i915_gem_object_unpin_map(bb->obj);
603 if (bb->vma && !IS_ERR(bb->vma)) {
604 i915_vma_unpin(bb->vma);
605 i915_vma_close(bb->vma);
607 i915_gem_object_put(bb->obj);
613 mutex_unlock(&dev_priv->drm.struct_mutex);
616 static int prepare_workload(struct intel_vgpu_workload *workload)
618 struct intel_vgpu *vgpu = workload->vgpu;
619 struct intel_vgpu_submission *s = &vgpu->submission;
620 int ring = workload->ring_id;
623 ret = intel_vgpu_pin_mm(workload->shadow_mm);
625 gvt_vgpu_err("fail to vgpu pin mm\n");
629 if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
630 !workload->shadow_mm->ppgtt_mm.shadowed) {
631 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
635 update_shadow_pdps(workload);
637 set_context_ppgtt_from_shadow(workload, s->shadow[ring]->gem_context);
639 ret = intel_vgpu_sync_oos_pages(workload->vgpu);
641 gvt_vgpu_err("fail to vgpu sync oos pages\n");
645 ret = intel_vgpu_flush_post_shadow(workload->vgpu);
647 gvt_vgpu_err("fail to flush post shadow\n");
651 ret = copy_workload_to_ring_buffer(workload);
653 gvt_vgpu_err("fail to generate request\n");
657 ret = prepare_shadow_batch_buffer(workload);
659 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
663 ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
665 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
666 goto err_shadow_batch;
669 if (workload->prepare) {
670 ret = workload->prepare(workload);
672 goto err_shadow_wa_ctx;
677 release_shadow_wa_ctx(&workload->wa_ctx);
679 release_shadow_batch_buffer(workload);
681 intel_vgpu_unpin_mm(workload->shadow_mm);
685 static int dispatch_workload(struct intel_vgpu_workload *workload)
687 struct intel_vgpu *vgpu = workload->vgpu;
688 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
689 struct i915_request *rq;
690 int ring_id = workload->ring_id;
693 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
696 mutex_lock(&vgpu->vgpu_lock);
697 mutex_lock(&dev_priv->drm.struct_mutex);
699 ret = intel_gvt_workload_req_alloc(workload);
703 ret = intel_gvt_scan_and_shadow_workload(workload);
707 ret = populate_shadow_context(workload);
709 release_shadow_wa_ctx(&workload->wa_ctx);
713 ret = prepare_workload(workload);
716 /* We might still need to add request with
717 * clean ctx to retire it properly..
719 rq = fetch_and_zero(&workload->req);
720 i915_request_put(rq);
723 if (!IS_ERR_OR_NULL(workload->req)) {
724 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
725 ring_id, workload->req);
726 i915_request_add(workload->req);
727 workload->dispatched = true;
731 workload->status = ret;
732 mutex_unlock(&dev_priv->drm.struct_mutex);
733 mutex_unlock(&vgpu->vgpu_lock);
737 static struct intel_vgpu_workload *pick_next_workload(
738 struct intel_gvt *gvt, int ring_id)
740 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
741 struct intel_vgpu_workload *workload = NULL;
743 mutex_lock(&gvt->sched_lock);
746 * no current vgpu / will be scheduled out / no workload
749 if (!scheduler->current_vgpu) {
750 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
754 if (scheduler->need_reschedule) {
755 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
759 if (!scheduler->current_vgpu->active ||
760 list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
764 * still have current workload, maybe the workload disptacher
765 * fail to submit it for some reason, resubmit it.
767 if (scheduler->current_workload[ring_id]) {
768 workload = scheduler->current_workload[ring_id];
769 gvt_dbg_sched("ring id %d still have current workload %p\n",
775 * pick a workload as current workload
776 * once current workload is set, schedule policy routines
777 * will wait the current workload is finished when trying to
778 * schedule out a vgpu.
780 scheduler->current_workload[ring_id] = container_of(
781 workload_q_head(scheduler->current_vgpu, ring_id)->next,
782 struct intel_vgpu_workload, list);
784 workload = scheduler->current_workload[ring_id];
786 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
788 atomic_inc(&workload->vgpu->submission.running_workload_num);
790 mutex_unlock(&gvt->sched_lock);
794 static void update_guest_context(struct intel_vgpu_workload *workload)
796 struct i915_request *rq = workload->req;
797 struct intel_vgpu *vgpu = workload->vgpu;
798 struct intel_gvt *gvt = vgpu->gvt;
799 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
800 struct execlist_ring_context *shadow_ring_context;
803 unsigned long context_gpa, context_page_num;
805 struct drm_i915_private *dev_priv = gvt->dev_priv;
810 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
811 workload->ctx_desc.lrca);
813 head = workload->rb_head;
814 tail = workload->rb_tail;
815 wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
818 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
824 head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
826 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
827 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
828 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
830 context_page_num = rq->engine->context_size;
831 context_page_num = context_page_num >> PAGE_SHIFT;
833 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
834 context_page_num = 19;
838 while (i < context_page_num) {
839 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
840 (u32)((workload->ctx_desc.lrca + i) <<
841 I915_GTT_PAGE_SHIFT));
842 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
843 gvt_vgpu_err("invalid guest context descriptor\n");
847 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
849 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
855 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
856 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
858 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
859 shadow_ring_context = kmap(page);
861 #define COPY_REG(name) \
862 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
863 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
866 COPY_REG(ctx_timestamp);
870 intel_gvt_hypervisor_write_gpa(vgpu,
871 workload->ring_context_gpa +
872 sizeof(*shadow_ring_context),
873 (void *)shadow_ring_context +
874 sizeof(*shadow_ring_context),
875 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
880 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
881 intel_engine_mask_t engine_mask)
883 struct intel_vgpu_submission *s = &vgpu->submission;
884 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
885 struct intel_engine_cs *engine;
886 struct intel_vgpu_workload *pos, *n;
887 intel_engine_mask_t tmp;
889 /* free the unsubmited workloads in the queues. */
890 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
891 list_for_each_entry_safe(pos, n,
892 &s->workload_q_head[engine->id], list) {
893 list_del_init(&pos->list);
894 intel_vgpu_destroy_workload(pos);
896 clear_bit(engine->id, s->shadow_ctx_desc_updated);
900 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
902 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
903 struct intel_vgpu_workload *workload =
904 scheduler->current_workload[ring_id];
905 struct intel_vgpu *vgpu = workload->vgpu;
906 struct intel_vgpu_submission *s = &vgpu->submission;
907 struct i915_request *rq = workload->req;
910 mutex_lock(&vgpu->vgpu_lock);
911 mutex_lock(&gvt->sched_lock);
913 /* For the workload w/ request, needs to wait for the context
914 * switch to make sure request is completed.
915 * For the workload w/o request, directly complete the workload.
918 wait_event(workload->shadow_ctx_status_wq,
919 !atomic_read(&workload->shadow_ctx_active));
921 /* If this request caused GPU hang, req->fence.error will
922 * be set to -EIO. Use -EIO to set workload status so
923 * that when this request caused GPU hang, didn't trigger
924 * context switch interrupt to guest.
926 if (likely(workload->status == -EINPROGRESS)) {
927 if (workload->req->fence.error == -EIO)
928 workload->status = -EIO;
930 workload->status = 0;
933 if (!workload->status &&
934 !(vgpu->resetting_eng & BIT(ring_id))) {
935 update_guest_context(workload);
937 for_each_set_bit(event, workload->pending_events,
939 intel_vgpu_trigger_virtual_event(vgpu, event);
942 i915_request_put(fetch_and_zero(&workload->req));
945 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
946 ring_id, workload, workload->status);
948 scheduler->current_workload[ring_id] = NULL;
950 list_del_init(&workload->list);
952 if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
953 /* if workload->status is not successful means HW GPU
954 * has occurred GPU hang or something wrong with i915/GVT,
955 * and GVT won't inject context switch interrupt to guest.
956 * So this error is a vGPU hang actually to the guest.
957 * According to this we should emunlate a vGPU hang. If
958 * there are pending workloads which are already submitted
959 * from guest, we should clean them up like HW GPU does.
961 * if it is in middle of engine resetting, the pending
962 * workloads won't be submitted to HW GPU and will be
963 * cleaned up during the resetting process later, so doing
964 * the workload clean up here doesn't have any impact.
966 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
969 workload->complete(workload);
971 atomic_dec(&s->running_workload_num);
972 wake_up(&scheduler->workload_complete_wq);
974 if (gvt->scheduler.need_reschedule)
975 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
977 mutex_unlock(&gvt->sched_lock);
978 mutex_unlock(&vgpu->vgpu_lock);
981 struct workload_thread_param {
982 struct intel_gvt *gvt;
986 static int workload_thread(void *priv)
988 struct workload_thread_param *p = (struct workload_thread_param *)priv;
989 struct intel_gvt *gvt = p->gvt;
990 int ring_id = p->ring_id;
991 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
992 struct intel_vgpu_workload *workload = NULL;
993 struct intel_vgpu *vgpu = NULL;
995 bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
996 DEFINE_WAIT_FUNC(wait, woken_wake_function);
997 struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm;
1001 gvt_dbg_core("workload thread for ring %d started\n", ring_id);
1003 while (!kthread_should_stop()) {
1004 add_wait_queue(&scheduler->waitq[ring_id], &wait);
1006 workload = pick_next_workload(gvt, ring_id);
1009 wait_woken(&wait, TASK_INTERRUPTIBLE,
1010 MAX_SCHEDULE_TIMEOUT);
1011 } while (!kthread_should_stop());
1012 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
1017 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
1018 workload->ring_id, workload,
1019 workload->vgpu->id);
1021 intel_runtime_pm_get(rpm);
1023 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1024 workload->ring_id, workload);
1026 if (need_force_wake)
1027 intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
1030 * Update the vReg of the vGPU which submitted this
1031 * workload. The vGPU may use these registers for checking
1032 * the context state. The value comes from GPU commands
1035 update_vreg_in_ctx(workload);
1037 ret = dispatch_workload(workload);
1040 vgpu = workload->vgpu;
1041 gvt_vgpu_err("fail to dispatch workload, skip\n");
1045 gvt_dbg_sched("ring id %d wait workload %p\n",
1046 workload->ring_id, workload);
1047 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1050 gvt_dbg_sched("will complete workload %p, status: %d\n",
1051 workload, workload->status);
1053 complete_current_workload(gvt, ring_id);
1055 if (need_force_wake)
1056 intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1059 intel_runtime_pm_put_unchecked(rpm);
1060 if (ret && (vgpu_is_vm_unhealthy(ret)))
1061 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1066 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1068 struct intel_vgpu_submission *s = &vgpu->submission;
1069 struct intel_gvt *gvt = vgpu->gvt;
1070 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1072 if (atomic_read(&s->running_workload_num)) {
1073 gvt_dbg_sched("wait vgpu idle\n");
1075 wait_event(scheduler->workload_complete_wq,
1076 !atomic_read(&s->running_workload_num));
1080 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1082 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1083 struct intel_engine_cs *engine;
1084 enum intel_engine_id i;
1086 gvt_dbg_core("clean workload scheduler\n");
1088 for_each_engine(engine, gvt->dev_priv, i) {
1089 atomic_notifier_chain_unregister(
1090 &engine->context_status_notifier,
1091 &gvt->shadow_ctx_notifier_block[i]);
1092 kthread_stop(scheduler->thread[i]);
1096 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1098 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1099 struct workload_thread_param *param = NULL;
1100 struct intel_engine_cs *engine;
1101 enum intel_engine_id i;
1104 gvt_dbg_core("init workload scheduler\n");
1106 init_waitqueue_head(&scheduler->workload_complete_wq);
1108 for_each_engine(engine, gvt->dev_priv, i) {
1109 init_waitqueue_head(&scheduler->waitq[i]);
1111 param = kzalloc(sizeof(*param), GFP_KERNEL);
1120 scheduler->thread[i] = kthread_run(workload_thread, param,
1121 "gvt workload %d", i);
1122 if (IS_ERR(scheduler->thread[i])) {
1123 gvt_err("fail to create workload thread\n");
1124 ret = PTR_ERR(scheduler->thread[i]);
1128 gvt->shadow_ctx_notifier_block[i].notifier_call =
1129 shadow_context_status_change;
1130 atomic_notifier_chain_register(&engine->context_status_notifier,
1131 &gvt->shadow_ctx_notifier_block[i]);
1135 intel_gvt_clean_workload_scheduler(gvt);
1142 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1143 struct i915_ppgtt *ppgtt)
1147 if (i915_vm_is_4lvl(&ppgtt->vm)) {
1148 px_dma(ppgtt->pd) = s->i915_context_pml4;
1150 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1151 struct i915_page_directory * const pd =
1152 i915_pd_entry(ppgtt->pd, i);
1154 px_dma(pd) = s->i915_context_pdps[i];
1160 * intel_vgpu_clean_submission - free submission-related resource for vGPU
1163 * This function is called when a vGPU is being destroyed.
1166 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1168 struct intel_vgpu_submission *s = &vgpu->submission;
1169 struct intel_engine_cs *engine;
1170 enum intel_engine_id id;
1172 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1174 i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1175 for_each_engine(engine, vgpu->gvt->dev_priv, id)
1176 intel_context_unpin(s->shadow[id]);
1178 kmem_cache_destroy(s->workloads);
1183 * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1185 * @engine_mask: engines expected to be reset
1187 * This function is called when a vGPU is being destroyed.
1190 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1191 intel_engine_mask_t engine_mask)
1193 struct intel_vgpu_submission *s = &vgpu->submission;
1198 intel_vgpu_clean_workloads(vgpu, engine_mask);
1199 s->ops->reset(vgpu, engine_mask);
1203 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1204 struct i915_ppgtt *ppgtt)
1208 if (i915_vm_is_4lvl(&ppgtt->vm)) {
1209 s->i915_context_pml4 = px_dma(ppgtt->pd);
1211 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1212 struct i915_page_directory * const pd =
1213 i915_pd_entry(ppgtt->pd, i);
1215 s->i915_context_pdps[i] = px_dma(pd);
1221 * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1224 * This function is called when a vGPU is being created.
1227 * Zero on success, negative error code if failed.
1230 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1232 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
1233 struct intel_vgpu_submission *s = &vgpu->submission;
1234 struct intel_engine_cs *engine;
1235 struct i915_gem_context *ctx;
1236 enum intel_engine_id i;
1239 mutex_lock(&i915->drm.struct_mutex);
1241 ctx = i915_gem_context_create_kernel(i915, I915_PRIORITY_MAX);
1247 i915_gem_context_set_force_single_submission(ctx);
1249 i915_context_ppgtt_root_save(s, i915_vm_to_ppgtt(ctx->vm));
1251 for_each_engine(engine, i915, i) {
1252 struct intel_context *ce;
1254 INIT_LIST_HEAD(&s->workload_q_head[i]);
1255 s->shadow[i] = ERR_PTR(-EINVAL);
1257 ce = intel_context_create(ctx, engine);
1260 goto out_shadow_ctx;
1263 if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
1264 const unsigned int ring_size = 512 * SZ_4K;
1266 ce->ring = __intel_context_ring_size(ring_size);
1269 ret = intel_context_pin(ce);
1270 intel_context_put(ce);
1272 goto out_shadow_ctx;
1277 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1279 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1280 sizeof(struct intel_vgpu_workload), 0,
1282 offsetof(struct intel_vgpu_workload, rb_tail),
1283 sizeof_field(struct intel_vgpu_workload, rb_tail),
1286 if (!s->workloads) {
1288 goto out_shadow_ctx;
1291 atomic_set(&s->running_workload_num, 0);
1292 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1294 i915_gem_context_put(ctx);
1295 mutex_unlock(&i915->drm.struct_mutex);
1299 i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(ctx->vm));
1300 for_each_engine(engine, i915, i) {
1301 if (IS_ERR(s->shadow[i]))
1304 intel_context_unpin(s->shadow[i]);
1305 intel_context_put(s->shadow[i]);
1307 i915_gem_context_put(ctx);
1309 mutex_unlock(&i915->drm.struct_mutex);
1314 * intel_vgpu_select_submission_ops - select virtual submission interface
1316 * @engine_mask: either ALL_ENGINES or target engine mask
1317 * @interface: expected vGPU virtual submission interface
1319 * This function is called when guest configures submission interface.
1322 * Zero on success, negative error code if failed.
1325 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1326 intel_engine_mask_t engine_mask,
1327 unsigned int interface)
1329 struct intel_vgpu_submission *s = &vgpu->submission;
1330 const struct intel_vgpu_submission_ops *ops[] = {
1331 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1332 &intel_vgpu_execlist_submission_ops,
1336 if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1339 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1343 s->ops->clean(vgpu, engine_mask);
1345 if (interface == 0) {
1347 s->virtual_submission_interface = 0;
1349 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1353 ret = ops[interface]->init(vgpu, engine_mask);
1357 s->ops = ops[interface];
1358 s->virtual_submission_interface = interface;
1361 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1362 vgpu->id, s->ops->name);
1368 * intel_vgpu_destroy_workload - destroy a vGPU workload
1369 * @workload: workload to destroy
1371 * This function is called when destroy a vGPU workload.
1374 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1376 struct intel_vgpu_submission *s = &workload->vgpu->submission;
1378 release_shadow_batch_buffer(workload);
1379 release_shadow_wa_ctx(&workload->wa_ctx);
1381 if (workload->shadow_mm)
1382 intel_vgpu_mm_put(workload->shadow_mm);
1384 kmem_cache_free(s->workloads, workload);
1387 static struct intel_vgpu_workload *
1388 alloc_workload(struct intel_vgpu *vgpu)
1390 struct intel_vgpu_submission *s = &vgpu->submission;
1391 struct intel_vgpu_workload *workload;
1393 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1395 return ERR_PTR(-ENOMEM);
1397 INIT_LIST_HEAD(&workload->list);
1398 INIT_LIST_HEAD(&workload->shadow_bb);
1400 init_waitqueue_head(&workload->shadow_ctx_status_wq);
1401 atomic_set(&workload->shadow_ctx_active, 0);
1403 workload->status = -EINPROGRESS;
1404 workload->vgpu = vgpu;
1409 #define RING_CTX_OFF(x) \
1410 offsetof(struct execlist_ring_context, x)
1412 static void read_guest_pdps(struct intel_vgpu *vgpu,
1413 u64 ring_context_gpa, u32 pdp[8])
1418 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1420 for (i = 0; i < 8; i++)
1421 intel_gvt_hypervisor_read_gpa(vgpu,
1422 gpa + i * 8, &pdp[7 - i], 4);
1425 static int prepare_mm(struct intel_vgpu_workload *workload)
1427 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1428 struct intel_vgpu_mm *mm;
1429 struct intel_vgpu *vgpu = workload->vgpu;
1430 enum intel_gvt_gtt_type root_entry_type;
1431 u64 pdps[GVT_RING_CTX_NR_PDPS];
1433 switch (desc->addressing_mode) {
1434 case 1: /* legacy 32-bit */
1435 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1437 case 3: /* legacy 64-bit */
1438 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1441 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1445 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1447 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1451 workload->shadow_mm = mm;
1455 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1456 ((a)->lrca == (b)->lrca))
1459 * intel_vgpu_create_workload - create a vGPU workload
1461 * @ring_id: ring index
1462 * @desc: a guest context descriptor
1464 * This function is called when creating a vGPU workload.
1467 * struct intel_vgpu_workload * on success, negative error code in
1468 * pointer if failed.
1471 struct intel_vgpu_workload *
1472 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1473 struct execlist_ctx_descriptor_format *desc)
1475 struct intel_vgpu_submission *s = &vgpu->submission;
1476 struct list_head *q = workload_q_head(vgpu, ring_id);
1477 struct intel_vgpu_workload *last_workload = NULL;
1478 struct intel_vgpu_workload *workload = NULL;
1479 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1480 u64 ring_context_gpa;
1481 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1485 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1486 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1487 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1488 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1489 return ERR_PTR(-EINVAL);
1492 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1493 RING_CTX_OFF(ring_header.val), &head, 4);
1495 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1496 RING_CTX_OFF(ring_tail.val), &tail, 4);
1500 head &= RB_HEAD_OFF_MASK;
1501 tail &= RB_TAIL_OFF_MASK;
1503 list_for_each_entry_reverse(last_workload, q, list) {
1505 if (same_context(&last_workload->ctx_desc, desc)) {
1506 gvt_dbg_el("ring id %d cur workload == last\n",
1508 gvt_dbg_el("ctx head %x real head %lx\n", head,
1509 last_workload->rb_tail);
1511 * cannot use guest context head pointer here,
1512 * as it might not be updated at this time
1514 head = last_workload->rb_tail;
1519 gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1521 /* record some ring buffer register values for scan and shadow */
1522 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1523 RING_CTX_OFF(rb_start.val), &start, 4);
1524 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1525 RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1526 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1527 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1529 if (!intel_gvt_ggtt_validate_range(vgpu, start,
1530 _RING_CTL_BUF_SIZE(ctl))) {
1531 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1532 return ERR_PTR(-EINVAL);
1535 workload = alloc_workload(vgpu);
1536 if (IS_ERR(workload))
1539 workload->ring_id = ring_id;
1540 workload->ctx_desc = *desc;
1541 workload->ring_context_gpa = ring_context_gpa;
1542 workload->rb_head = head;
1543 workload->guest_rb_head = guest_head;
1544 workload->rb_tail = tail;
1545 workload->rb_start = start;
1546 workload->rb_ctl = ctl;
1548 if (ring_id == RCS0) {
1549 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1550 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1551 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1552 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1554 workload->wa_ctx.indirect_ctx.guest_gma =
1555 indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1556 workload->wa_ctx.indirect_ctx.size =
1557 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1560 if (workload->wa_ctx.indirect_ctx.size != 0) {
1561 if (!intel_gvt_ggtt_validate_range(vgpu,
1562 workload->wa_ctx.indirect_ctx.guest_gma,
1563 workload->wa_ctx.indirect_ctx.size)) {
1564 kmem_cache_free(s->workloads, workload);
1565 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1566 workload->wa_ctx.indirect_ctx.guest_gma);
1567 return ERR_PTR(-EINVAL);
1571 workload->wa_ctx.per_ctx.guest_gma =
1572 per_ctx & PER_CTX_ADDR_MASK;
1573 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1574 if (workload->wa_ctx.per_ctx.valid) {
1575 if (!intel_gvt_ggtt_validate_range(vgpu,
1576 workload->wa_ctx.per_ctx.guest_gma,
1578 kmem_cache_free(s->workloads, workload);
1579 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1580 workload->wa_ctx.per_ctx.guest_gma);
1581 return ERR_PTR(-EINVAL);
1586 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1587 workload, ring_id, head, tail, start, ctl);
1589 ret = prepare_mm(workload);
1591 kmem_cache_free(s->workloads, workload);
1592 return ERR_PTR(ret);
1595 /* Only scan and shadow the first workload in the queue
1596 * as there is only one pre-allocated buf-obj for shadow.
1598 if (list_empty(workload_q_head(vgpu, ring_id))) {
1599 intel_runtime_pm_get(&dev_priv->runtime_pm);
1600 mutex_lock(&dev_priv->drm.struct_mutex);
1601 ret = intel_gvt_scan_and_shadow_workload(workload);
1602 mutex_unlock(&dev_priv->drm.struct_mutex);
1603 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
1607 if (vgpu_is_vm_unhealthy(ret))
1608 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1609 intel_vgpu_destroy_workload(workload);
1610 return ERR_PTR(ret);
1617 * intel_vgpu_queue_workload - Qeue a vGPU workload
1618 * @workload: the workload to queue in
1620 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1622 list_add_tail(&workload->list,
1623 workload_q_head(workload->vgpu, workload->ring_id));
1624 intel_gvt_kick_schedule(workload->vgpu->gvt);
1625 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);