drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "gem/i915_gem_pm.h"
  39 #include "gt/intel_context.h"
  40 #include "gt/intel_ring.h"
  41
  42 #include "i915_drv.h"
  43 #include "i915_gem_gtt.h"
  44 #include "gvt.h"
  45
  46 #define RING_CTX_OFF(x) \
  47         offsetof(struct execlist_ring_context, x)
  48
  49 static void set_context_pdp_root_pointer(
  50                 struct execlist_ring_context *ring_context,
  51                 u32 pdp[8])
  52 {
  53         int i;
  54
  55         for (i = 0; i < 8; i++)
  56                 ring_context->pdps[i].val = pdp[7 - i];
  57 }
  58
  59 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  60 {
  61         struct drm_i915_gem_object *ctx_obj =
  62                 workload->req->context->state->obj;
  63         struct execlist_ring_context *shadow_ring_context;
  64         struct page *page;
  65
  66         if (WARN_ON(!workload->shadow_mm))
  67                 return;
  68
  69         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  70                 return;
  71
  72         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
  73         shadow_ring_context = kmap(page);
  74         set_context_pdp_root_pointer(shadow_ring_context,
  75                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  76         kunmap(page);
  77 }
  78
  79 /*
  80  * when populating shadow ctx from guest, we should not overrride oa related
  81  * registers, so that they will not be overlapped by guest oa configs. Thus
  82  * made it possible to capture oa data from host for both host and guests.
  83  */
  84 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  85                 u32 *reg_state, bool save)
  86 {
  87         struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;
  88         u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
  89         u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
  90         int i = 0;
  91         u32 flex_mmio[] = {
  92                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  94                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  95                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  96                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  97                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  98                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  99         };
 100
 101         if (workload->engine->id != RCS0)
 102                 return;
 103
 104         if (save) {
 105                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 106
 107                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 108                         u32 state_offset = ctx_flexeu0 + i * 2;
 109
 110                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 111                 }
 112         } else {
 113                 reg_state[ctx_oactxctrl] =
 114                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 115                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 116
 117                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 118                         u32 state_offset = ctx_flexeu0 + i * 2;
 119                         u32 mmio = flex_mmio[i];
 120
 121                         reg_state[state_offset] = mmio;
 122                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 123                 }
 124         }
 125 }
 126
 127 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 128 {
 129         struct intel_vgpu *vgpu = workload->vgpu;
 130         struct intel_gvt *gvt = vgpu->gvt;
 131         struct intel_context *ctx = workload->req->context;
 132         struct execlist_ring_context *shadow_ring_context;
 133         void *dst;
 134         void *context_base;
 135         unsigned long context_gpa, context_page_num;
 136         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 137         unsigned long gpa_size; /* size of consecutive GPAs */
 138         struct intel_vgpu_submission *s = &vgpu->submission;
 139         int i;
 140         bool skip = false;
 141         int ring_id = workload->engine->id;
 142
 143         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 144
 145         context_base = (void *) ctx->lrc_reg_state -
 146                                 (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 147
 148         shadow_ring_context = (void *) ctx->lrc_reg_state;
 149
 150         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 151 #define COPY_REG(name) \
 152         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 153                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 154 #define COPY_REG_MASKED(name) {\
 155                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 156                                               + RING_CTX_OFF(name.val),\
 157                                               &shadow_ring_context->name.val, 4);\
 158                 shadow_ring_context->name.val |= 0xffff << 16;\
 159         }
 160
 161         COPY_REG_MASKED(ctx_ctrl);
 162         COPY_REG(ctx_timestamp);
 163
 164         if (workload->engine->id == RCS0) {
 165                 COPY_REG(bb_per_ctx_ptr);
 166                 COPY_REG(rcs_indirect_ctx);
 167                 COPY_REG(rcs_indirect_ctx_offset);
 168         }
 169 #undef COPY_REG
 170 #undef COPY_REG_MASKED
 171
 172         intel_gvt_hypervisor_read_gpa(vgpu,
 173                         workload->ring_context_gpa +
 174                         sizeof(*shadow_ring_context),
 175                         (void *)shadow_ring_context +
 176                         sizeof(*shadow_ring_context),
 177                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 178
 179         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 180
 181         gvt_dbg_sched("ring %s workload lrca %x, ctx_id %x, ctx gpa %llx",
 182                         workload->engine->name, workload->ctx_desc.lrca,
 183                         workload->ctx_desc.context_id,
 184                         workload->ring_context_gpa);
 185
 186         /* only need to ensure this context is not pinned/unpinned during the
 187          * period from last submission to this this submission.
 188          * Upon reaching this function, the currently submitted context is not
 189          * supposed to get unpinned. If a misbehaving guest driver ever does
 190          * this, it would corrupt itself.
 191          */
 192         if (s->last_ctx[ring_id].valid &&
 193                         (s->last_ctx[ring_id].lrca ==
 194                                 workload->ctx_desc.lrca) &&
 195                         (s->last_ctx[ring_id].ring_context_gpa ==
 196                                 workload->ring_context_gpa))
 197                 skip = true;
 198
 199         s->last_ctx[ring_id].lrca = workload->ctx_desc.lrca;
 200         s->last_ctx[ring_id].ring_context_gpa = workload->ring_context_gpa;
 201
 202         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) || skip)
 203                 return 0;
 204
 205         s->last_ctx[ring_id].valid = false;
 206         context_page_num = workload->engine->context_size;
 207         context_page_num = context_page_num >> PAGE_SHIFT;
 208
 209         if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
 210                 context_page_num = 19;
 211
 212         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 213          * read from the continuous GPAs into dst virtual address
 214          */
 215         gpa_size = 0;
 216         for (i = 2; i < context_page_num; i++) {
 217                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 218                                 (u32)((workload->ctx_desc.lrca + i) <<
 219                                 I915_GTT_PAGE_SHIFT));
 220                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 221                         gvt_vgpu_err("Invalid guest context descriptor\n");
 222                         return -EFAULT;
 223                 }
 224
 225                 if (gpa_size == 0) {
 226                         gpa_base = context_gpa;
 227                         dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 228                 } else if (context_gpa != gpa_base + gpa_size)
 229                         goto read;
 230
 231                 gpa_size += I915_GTT_PAGE_SIZE;
 232
 233                 if (i == context_page_num - 1)
 234                         goto read;
 235
 236                 continue;
 237
 238 read:
 239                 intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size);
 240                 gpa_base = context_gpa;
 241                 gpa_size = I915_GTT_PAGE_SIZE;
 242                 dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 243         }
 244         s->last_ctx[ring_id].valid = true;
 245         return 0;
 246 }
 247
 248 static inline bool is_gvt_request(struct i915_request *rq)
 249 {
 250         return intel_context_force_single_submission(rq->context);
 251 }
 252
 253 static void save_ring_hw_state(struct intel_vgpu *vgpu,
 254                                const struct intel_engine_cs *engine)
 255 {
 256         struct intel_uncore *uncore = engine->uncore;
 257         i915_reg_t reg;
 258
 259         reg = RING_INSTDONE(engine->mmio_base);
 260         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 261                 intel_uncore_read(uncore, reg);
 262
 263         reg = RING_ACTHD(engine->mmio_base);
 264         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 265                 intel_uncore_read(uncore, reg);
 266
 267         reg = RING_ACTHD_UDW(engine->mmio_base);
 268         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 269                 intel_uncore_read(uncore, reg);
 270 }
 271
 272 static int shadow_context_status_change(struct notifier_block *nb,
 273                 unsigned long action, void *data)
 274 {
 275         struct i915_request *rq = data;
 276         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 277                                 shadow_ctx_notifier_block[rq->engine->id]);
 278         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 279         enum intel_engine_id ring_id = rq->engine->id;
 280         struct intel_vgpu_workload *workload;
 281         unsigned long flags;
 282
 283         if (!is_gvt_request(rq)) {
 284                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 285                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 286                     scheduler->engine_owner[ring_id]) {
 287                         /* Switch ring from vGPU to host. */
 288                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 289                                               NULL, rq->engine);
 290                         scheduler->engine_owner[ring_id] = NULL;
 291                 }
 292                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 293
 294                 return NOTIFY_OK;
 295         }
 296
 297         workload = scheduler->current_workload[ring_id];
 298         if (unlikely(!workload))
 299                 return NOTIFY_OK;
 300
 301         switch (action) {
 302         case INTEL_CONTEXT_SCHEDULE_IN:
 303                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 304                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 305                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 306                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 307                                               workload->vgpu, rq->engine);
 308                         scheduler->engine_owner[ring_id] = workload->vgpu;
 309                 } else
 310                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 311                                       ring_id, workload->vgpu->id);
 312                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 313                 atomic_set(&workload->shadow_ctx_active, 1);
 314                 break;
 315         case INTEL_CONTEXT_SCHEDULE_OUT:
 316                 save_ring_hw_state(workload->vgpu, rq->engine);
 317                 atomic_set(&workload->shadow_ctx_active, 0);
 318                 break;
 319         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 320                 save_ring_hw_state(workload->vgpu, rq->engine);
 321                 break;
 322         default:
 323                 WARN_ON(1);
 324                 return NOTIFY_OK;
 325         }
 326         wake_up(&workload->shadow_ctx_status_wq);
 327         return NOTIFY_OK;
 328 }
 329
 330 static void
 331 shadow_context_descriptor_update(struct intel_context *ce,
 332                                  struct intel_vgpu_workload *workload)
 333 {
 334         u64 desc = ce->lrc.desc;
 335
 336         /*
 337          * Update bits 0-11 of the context descriptor which includes flags
 338          * like GEN8_CTX_* cached in desc_template
 339          */
 340         desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 341         desc |= (u64)workload->ctx_desc.addressing_mode <<
 342                 GEN8_CTX_ADDRESSING_MODE_SHIFT;
 343
 344         ce->lrc.desc = desc;
 345 }
 346
 347 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 348 {
 349         struct intel_vgpu *vgpu = workload->vgpu;
 350         struct i915_request *req = workload->req;
 351         void *shadow_ring_buffer_va;
 352         u32 *cs;
 353         int err;
 354
 355         if (IS_GEN(req->i915, 9) && is_inhibit_context(req->context))
 356                 intel_vgpu_restore_inhibit_context(vgpu, req);
 357
 358         /*
 359          * To track whether a request has started on HW, we can emit a
 360          * breadcrumb at the beginning of the request and check its
 361          * timeline's HWSP to see if the breadcrumb has advanced past the
 362          * start of this request. Actually, the request must have the
 363          * init_breadcrumb if its timeline set has_init_bread_crumb, or the
 364          * scheduler might get a wrong state of it during reset. Since the
 365          * requests from gvt always set the has_init_breadcrumb flag, here
 366          * need to do the emit_init_breadcrumb for all the requests.
 367          */
 368         if (req->engine->emit_init_breadcrumb) {
 369                 err = req->engine->emit_init_breadcrumb(req);
 370                 if (err) {
 371                         gvt_vgpu_err("fail to emit init breadcrumb\n");
 372                         return err;
 373                 }
 374         }
 375
 376         /* allocate shadow ring buffer */
 377         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 378         if (IS_ERR(cs)) {
 379                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 380                         workload->rb_len);
 381                 return PTR_ERR(cs);
 382         }
 383
 384         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 385
 386         /* get shadow ring buffer va */
 387         workload->shadow_ring_buffer_va = cs;
 388
 389         memcpy(cs, shadow_ring_buffer_va,
 390                         workload->rb_len);
 391
 392         cs += workload->rb_len / sizeof(u32);
 393         intel_ring_advance(workload->req, cs);
 394
 395         return 0;
 396 }
 397
 398 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 399 {
 400         if (!wa_ctx->indirect_ctx.obj)
 401                 return;
 402
 403         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 404         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 405
 406         wa_ctx->indirect_ctx.obj = NULL;
 407         wa_ctx->indirect_ctx.shadow_va = NULL;
 408 }
 409
 410 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 411                                           struct intel_context *ce)
 412 {
 413         struct intel_vgpu_mm *mm = workload->shadow_mm;
 414         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
 415         int i = 0;
 416
 417         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 418                 px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
 419         } else {
 420                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 421                         struct i915_page_directory * const pd =
 422                                 i915_pd_entry(ppgtt->pd, i);
 423
 424                         px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
 425                 }
 426         }
 427 }
 428
 429 static int
 430 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
 431 {
 432         struct intel_vgpu *vgpu = workload->vgpu;
 433         struct intel_vgpu_submission *s = &vgpu->submission;
 434         struct i915_request *rq;
 435
 436         if (workload->req)
 437                 return 0;
 438
 439         rq = i915_request_create(s->shadow[workload->engine->id]);
 440         if (IS_ERR(rq)) {
 441                 gvt_vgpu_err("fail to allocate gem request\n");
 442                 return PTR_ERR(rq);
 443         }
 444
 445         workload->req = i915_request_get(rq);
 446         return 0;
 447 }
 448
 449 /**
 450  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 451  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 452  * @workload: an abstract entity for each execlist submission.
 453  *
 454  * This function is called before the workload submitting to i915, to make
 455  * sure the content of the workload is valid.
 456  */
 457 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 458 {
 459         struct intel_vgpu *vgpu = workload->vgpu;
 460         struct intel_vgpu_submission *s = &vgpu->submission;
 461         int ret;
 462
 463         lockdep_assert_held(&vgpu->vgpu_lock);
 464
 465         if (workload->shadow)
 466                 return 0;
 467
 468         if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))
 469                 shadow_context_descriptor_update(s->shadow[workload->engine->id],
 470                                                  workload);
 471
 472         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 473         if (ret)
 474                 return ret;
 475
 476         if (workload->engine->id == RCS0 &&
 477             workload->wa_ctx.indirect_ctx.size) {
 478                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 479                 if (ret)
 480                         goto err_shadow;
 481         }
 482
 483         workload->shadow = true;
 484         return 0;
 485
 486 err_shadow:
 487         release_shadow_wa_ctx(&workload->wa_ctx);
 488         return ret;
 489 }
 490
 491 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 492
 493 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 494 {
 495         struct intel_gvt *gvt = workload->vgpu->gvt;
 496         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 497         struct intel_vgpu_shadow_bb *bb;
 498         int ret;
 499
 500         list_for_each_entry(bb, &workload->shadow_bb, list) {
 501                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 502                  * is only updated into ring_scan_buffer, not real ring address
 503                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 504                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 505                  * in copy_workload_to_ring_buffer.
 506                  */
 507
 508                 if (bb->bb_offset)
 509                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 510                                 + bb->bb_offset;
 511
 512                 if (bb->ppgtt) {
 513                         /* for non-priv bb, scan&shadow is only for
 514                          * debugging purpose, so the content of shadow bb
 515                          * is the same as original bb. Therefore,
 516                          * here, rather than switch to shadow bb's gma
 517                          * address, we directly use original batch buffer's
 518                          * gma address, and send original bb to hardware
 519                          * directly
 520                          */
 521                         if (bb->clflush & CLFLUSH_AFTER) {
 522                                 drm_clflush_virt_range(bb->va,
 523                                                 bb->obj->base.size);
 524                                 bb->clflush &= ~CLFLUSH_AFTER;
 525                         }
 526                         i915_gem_object_finish_access(bb->obj);
 527                         bb->accessing = false;
 528
 529                 } else {
 530                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
 531                                         NULL, 0, 0, 0);
 532                         if (IS_ERR(bb->vma)) {
 533                                 ret = PTR_ERR(bb->vma);
 534                                 goto err;
 535                         }
 536
 537                         /* relocate shadow batch buffer */
 538                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 539                         if (gmadr_bytes == 8)
 540                                 bb->bb_start_cmd_va[2] = 0;
 541
 542                         /* No one is going to touch shadow bb from now on. */
 543                         if (bb->clflush & CLFLUSH_AFTER) {
 544                                 drm_clflush_virt_range(bb->va,
 545                                                 bb->obj->base.size);
 546                                 bb->clflush &= ~CLFLUSH_AFTER;
 547                         }
 548
 549                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
 550                                                                 false);
 551                         if (ret)
 552                                 goto err;
 553
 554                         ret = i915_vma_move_to_active(bb->vma,
 555                                                       workload->req,
 556                                                       0);
 557                         if (ret)
 558                                 goto err;
 559
 560                         i915_gem_object_finish_access(bb->obj);
 561                         bb->accessing = false;
 562                 }
 563         }
 564         return 0;
 565 err:
 566         release_shadow_batch_buffer(workload);
 567         return ret;
 568 }
 569
 570 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 571 {
 572         struct intel_vgpu_workload *workload =
 573                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 574         struct i915_request *rq = workload->req;
 575         struct execlist_ring_context *shadow_ring_context =
 576                 (struct execlist_ring_context *)rq->context->lrc_reg_state;
 577
 578         shadow_ring_context->bb_per_ctx_ptr.val =
 579                 (shadow_ring_context->bb_per_ctx_ptr.val &
 580                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 581         shadow_ring_context->rcs_indirect_ctx.val =
 582                 (shadow_ring_context->rcs_indirect_ctx.val &
 583                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 584 }
 585
 586 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 587 {
 588         struct i915_vma *vma;
 589         unsigned char *per_ctx_va =
 590                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 591                 wa_ctx->indirect_ctx.size;
 592
 593         if (wa_ctx->indirect_ctx.size == 0)
 594                 return 0;
 595
 596         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 597                                        0, CACHELINE_BYTES, 0);
 598         if (IS_ERR(vma))
 599                 return PTR_ERR(vma);
 600
 601         /* FIXME: we are not tracking our pinned VMA leaving it
 602          * up to the core to fix up the stray pin_count upon
 603          * free.
 604          */
 605
 606         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 607
 608         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 609         memset(per_ctx_va, 0, CACHELINE_BYTES);
 610
 611         update_wa_ctx_2_shadow_ctx(wa_ctx);
 612         return 0;
 613 }
 614
 615 static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
 616 {
 617         vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
 618                 workload->rb_start;
 619 }
 620
 621 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 622 {
 623         struct intel_vgpu_shadow_bb *bb, *pos;
 624
 625         if (list_empty(&workload->shadow_bb))
 626                 return;
 627
 628         bb = list_first_entry(&workload->shadow_bb,
 629                         struct intel_vgpu_shadow_bb, list);
 630
 631         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 632                 if (bb->obj) {
 633                         if (bb->accessing)
 634                                 i915_gem_object_finish_access(bb->obj);
 635
 636                         if (bb->va && !IS_ERR(bb->va))
 637                                 i915_gem_object_unpin_map(bb->obj);
 638
 639                         if (bb->vma && !IS_ERR(bb->vma))
 640                                 i915_vma_unpin(bb->vma);
 641
 642                         i915_gem_object_put(bb->obj);
 643                 }
 644                 list_del(&bb->list);
 645                 kfree(bb);
 646         }
 647 }
 648
 649 static int prepare_workload(struct intel_vgpu_workload *workload)
 650 {
 651         struct intel_vgpu *vgpu = workload->vgpu;
 652         struct intel_vgpu_submission *s = &vgpu->submission;
 653         int ret = 0;
 654
 655         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 656         if (ret) {
 657                 gvt_vgpu_err("fail to vgpu pin mm\n");
 658                 return ret;
 659         }
 660
 661         if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
 662             !workload->shadow_mm->ppgtt_mm.shadowed) {
 663                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 664                 return -EINVAL;
 665         }
 666
 667         update_shadow_pdps(workload);
 668
 669         set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);
 670
 671         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 672         if (ret) {
 673                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 674                 goto err_unpin_mm;
 675         }
 676
 677         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 678         if (ret) {
 679                 gvt_vgpu_err("fail to flush post shadow\n");
 680                 goto err_unpin_mm;
 681         }
 682
 683         ret = copy_workload_to_ring_buffer(workload);
 684         if (ret) {
 685                 gvt_vgpu_err("fail to generate request\n");
 686                 goto err_unpin_mm;
 687         }
 688
 689         ret = prepare_shadow_batch_buffer(workload);
 690         if (ret) {
 691                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 692                 goto err_unpin_mm;
 693         }
 694
 695         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 696         if (ret) {
 697                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 698                 goto err_shadow_batch;
 699         }
 700
 701         if (workload->prepare) {
 702                 ret = workload->prepare(workload);
 703                 if (ret)
 704                         goto err_shadow_wa_ctx;
 705         }
 706
 707         return 0;
 708 err_shadow_wa_ctx:
 709         release_shadow_wa_ctx(&workload->wa_ctx);
 710 err_shadow_batch:
 711         release_shadow_batch_buffer(workload);
 712 err_unpin_mm:
 713         intel_vgpu_unpin_mm(workload->shadow_mm);
 714         return ret;
 715 }
 716
 717 static int dispatch_workload(struct intel_vgpu_workload *workload)
 718 {
 719         struct intel_vgpu *vgpu = workload->vgpu;
 720         struct i915_request *rq;
 721         int ret;
 722
 723         gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n",
 724                       workload->engine->name, workload);
 725
 726         mutex_lock(&vgpu->vgpu_lock);
 727
 728         ret = intel_gvt_workload_req_alloc(workload);
 729         if (ret)
 730                 goto err_req;
 731
 732         ret = intel_gvt_scan_and_shadow_workload(workload);
 733         if (ret)
 734                 goto out;
 735
 736         ret = populate_shadow_context(workload);
 737         if (ret) {
 738                 release_shadow_wa_ctx(&workload->wa_ctx);
 739                 goto out;
 740         }
 741
 742         ret = prepare_workload(workload);
 743 out:
 744         if (ret) {
 745                 /* We might still need to add request with
 746                  * clean ctx to retire it properly..
 747                  */
 748                 rq = fetch_and_zero(&workload->req);
 749                 i915_request_put(rq);
 750         }
 751
 752         if (!IS_ERR_OR_NULL(workload->req)) {
 753                 gvt_dbg_sched("ring id %s submit workload to i915 %p\n",
 754                               workload->engine->name, workload->req);
 755                 i915_request_add(workload->req);
 756                 workload->dispatched = true;
 757         }
 758 err_req:
 759         if (ret)
 760                 workload->status = ret;
 761         mutex_unlock(&vgpu->vgpu_lock);
 762         return ret;
 763 }
 764
 765 static struct intel_vgpu_workload *
 766 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine)
 767 {
 768         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 769         struct intel_vgpu_workload *workload = NULL;
 770
 771         mutex_lock(&gvt->sched_lock);
 772
 773         /*
 774          * no current vgpu / will be scheduled out / no workload
 775          * bail out
 776          */
 777         if (!scheduler->current_vgpu) {
 778                 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);
 779                 goto out;
 780         }
 781
 782         if (scheduler->need_reschedule) {
 783                 gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);
 784                 goto out;
 785         }
 786
 787         if (!scheduler->current_vgpu->active ||
 788             list_empty(workload_q_head(scheduler->current_vgpu, engine)))
 789                 goto out;
 790
 791         /*
 792          * still have current workload, maybe the workload disptacher
 793          * fail to submit it for some reason, resubmit it.
 794          */
 795         if (scheduler->current_workload[engine->id]) {
 796                 workload = scheduler->current_workload[engine->id];
 797                 gvt_dbg_sched("ring %s still have current workload %p\n",
 798                               engine->name, workload);
 799                 goto out;
 800         }
 801
 802         /*
 803          * pick a workload as current workload
 804          * once current workload is set, schedule policy routines
 805          * will wait the current workload is finished when trying to
 806          * schedule out a vgpu.
 807          */
 808         scheduler->current_workload[engine->id] =
 809                 list_first_entry(workload_q_head(scheduler->current_vgpu,
 810                                                  engine),
 811                                  struct intel_vgpu_workload, list);
 812
 813         workload = scheduler->current_workload[engine->id];
 814
 815         gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);
 816
 817         atomic_inc(&workload->vgpu->submission.running_workload_num);
 818 out:
 819         mutex_unlock(&gvt->sched_lock);
 820         return workload;
 821 }
 822
 823 static void update_guest_context(struct intel_vgpu_workload *workload)
 824 {
 825         struct i915_request *rq = workload->req;
 826         struct intel_vgpu *vgpu = workload->vgpu;
 827         struct execlist_ring_context *shadow_ring_context;
 828         struct intel_context *ctx = workload->req->context;
 829         void *context_base;
 830         void *src;
 831         unsigned long context_gpa, context_page_num;
 832         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 833         unsigned long gpa_size; /* size of consecutive GPAs*/
 834         int i;
 835         u32 ring_base;
 836         u32 head, tail;
 837         u16 wrap_count;
 838
 839         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 840                       workload->ctx_desc.lrca);
 841
 842         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 843
 844         head = workload->rb_head;
 845         tail = workload->rb_tail;
 846         wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
 847
 848         if (tail < head) {
 849                 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
 850                         wrap_count = 0;
 851                 else
 852                         wrap_count += 1;
 853         }
 854
 855         head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
 856
 857         ring_base = rq->engine->mmio_base;
 858         vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
 859         vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
 860
 861         context_page_num = rq->engine->context_size;
 862         context_page_num = context_page_num >> PAGE_SHIFT;
 863
 864         if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
 865                 context_page_num = 19;
 866
 867         context_base = (void *) ctx->lrc_reg_state -
 868                         (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 869
 870         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 871          * write to the consecutive GPAs from src virtual address
 872          */
 873         gpa_size = 0;
 874         for (i = 2; i < context_page_num; i++) {
 875                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 876                                 (u32)((workload->ctx_desc.lrca + i) <<
 877                                         I915_GTT_PAGE_SHIFT));
 878                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 879                         gvt_vgpu_err("invalid guest context descriptor\n");
 880                         return;
 881                 }
 882
 883                 if (gpa_size == 0) {
 884                         gpa_base = context_gpa;
 885                         src = context_base + (i << I915_GTT_PAGE_SHIFT);
 886                 } else if (context_gpa != gpa_base + gpa_size)
 887                         goto write;
 888
 889                 gpa_size += I915_GTT_PAGE_SIZE;
 890
 891                 if (i == context_page_num - 1)
 892                         goto write;
 893
 894                 continue;
 895
 896 write:
 897                 intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size);
 898                 gpa_base = context_gpa;
 899                 gpa_size = I915_GTT_PAGE_SIZE;
 900                 src = context_base + (i << I915_GTT_PAGE_SHIFT);
 901         }
 902
 903         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 904                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 905
 906         shadow_ring_context = (void *) ctx->lrc_reg_state;
 907
 908 #define COPY_REG(name) \
 909         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 910                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 911
 912         COPY_REG(ctx_ctrl);
 913         COPY_REG(ctx_timestamp);
 914
 915 #undef COPY_REG
 916
 917         intel_gvt_hypervisor_write_gpa(vgpu,
 918                         workload->ring_context_gpa +
 919                         sizeof(*shadow_ring_context),
 920                         (void *)shadow_ring_context +
 921                         sizeof(*shadow_ring_context),
 922                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 923 }
 924
 925 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
 926                                 intel_engine_mask_t engine_mask)
 927 {
 928         struct intel_vgpu_submission *s = &vgpu->submission;
 929         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 930         struct intel_engine_cs *engine;
 931         struct intel_vgpu_workload *pos, *n;
 932         intel_engine_mask_t tmp;
 933
 934         /* free the unsubmited workloads in the queues. */
 935         for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
 936                 list_for_each_entry_safe(pos, n,
 937                         &s->workload_q_head[engine->id], list) {
 938                         list_del_init(&pos->list);
 939                         intel_vgpu_destroy_workload(pos);
 940                 }
 941                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
 942         }
 943 }
 944
 945 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 946 {
 947         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 948         struct intel_vgpu_workload *workload =
 949                 scheduler->current_workload[ring_id];
 950         struct intel_vgpu *vgpu = workload->vgpu;
 951         struct intel_vgpu_submission *s = &vgpu->submission;
 952         struct i915_request *rq = workload->req;
 953         int event;
 954
 955         mutex_lock(&vgpu->vgpu_lock);
 956         mutex_lock(&gvt->sched_lock);
 957
 958         /* For the workload w/ request, needs to wait for the context
 959          * switch to make sure request is completed.
 960          * For the workload w/o request, directly complete the workload.
 961          */
 962         if (rq) {
 963                 wait_event(workload->shadow_ctx_status_wq,
 964                            !atomic_read(&workload->shadow_ctx_active));
 965
 966                 /* If this request caused GPU hang, req->fence.error will
 967                  * be set to -EIO. Use -EIO to set workload status so
 968                  * that when this request caused GPU hang, didn't trigger
 969                  * context switch interrupt to guest.
 970                  */
 971                 if (likely(workload->status == -EINPROGRESS)) {
 972                         if (workload->req->fence.error == -EIO)
 973                                 workload->status = -EIO;
 974                         else
 975                                 workload->status = 0;
 976                 }
 977
 978                 if (!workload->status &&
 979                     !(vgpu->resetting_eng & BIT(ring_id))) {
 980                         update_guest_context(workload);
 981
 982                         for_each_set_bit(event, workload->pending_events,
 983                                          INTEL_GVT_EVENT_MAX)
 984                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 985                 }
 986
 987                 i915_request_put(fetch_and_zero(&workload->req));
 988         }
 989
 990         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 991                         ring_id, workload, workload->status);
 992
 993         scheduler->current_workload[ring_id] = NULL;
 994
 995         list_del_init(&workload->list);
 996
 997         if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
 998                 /* if workload->status is not successful means HW GPU
 999                  * has occurred GPU hang or something wrong with i915/GVT,
1000                  * and GVT won't inject context switch interrupt to guest.
1001                  * So this error is a vGPU hang actually to the guest.
1002                  * According to this we should emunlate a vGPU hang. If
1003                  * there are pending workloads which are already submitted
1004                  * from guest, we should clean them up like HW GPU does.
1005                  *
1006                  * if it is in middle of engine resetting, the pending
1007                  * workloads won't be submitted to HW GPU and will be
1008                  * cleaned up during the resetting process later, so doing
1009                  * the workload clean up here doesn't have any impact.
1010                  **/
1011                 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
1012         }
1013
1014         workload->complete(workload);
1015
1016         atomic_dec(&s->running_workload_num);
1017         wake_up(&scheduler->workload_complete_wq);
1018
1019         if (gvt->scheduler.need_reschedule)
1020                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
1021
1022         mutex_unlock(&gvt->sched_lock);
1023         mutex_unlock(&vgpu->vgpu_lock);
1024 }
1025
1026 static int workload_thread(void *arg)
1027 {
1028         struct intel_engine_cs *engine = arg;
1029         const bool need_force_wake = INTEL_GEN(engine->i915) >= 9;
1030         struct intel_gvt *gvt = engine->i915->gvt;
1031         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1032         struct intel_vgpu_workload *workload = NULL;
1033         struct intel_vgpu *vgpu = NULL;
1034         int ret;
1035         DEFINE_WAIT_FUNC(wait, woken_wake_function);
1036
1037         gvt_dbg_core("workload thread for ring %s started\n", engine->name);
1038
1039         while (!kthread_should_stop()) {
1040                 intel_wakeref_t wakeref;
1041
1042                 add_wait_queue(&scheduler->waitq[engine->id], &wait);
1043                 do {
1044                         workload = pick_next_workload(gvt, engine);
1045                         if (workload)
1046                                 break;
1047                         wait_woken(&wait, TASK_INTERRUPTIBLE,
1048                                    MAX_SCHEDULE_TIMEOUT);
1049                 } while (!kthread_should_stop());
1050                 remove_wait_queue(&scheduler->waitq[engine->id], &wait);
1051
1052                 if (!workload)
1053                         break;
1054
1055                 gvt_dbg_sched("ring %s next workload %p vgpu %d\n",
1056                               engine->name, workload,
1057                               workload->vgpu->id);
1058
1059                 wakeref = intel_runtime_pm_get(engine->uncore->rpm);
1060
1061                 gvt_dbg_sched("ring %s will dispatch workload %p\n",
1062                               engine->name, workload);
1063
1064                 if (need_force_wake)
1065                         intel_uncore_forcewake_get(engine->uncore,
1066                                                    FORCEWAKE_ALL);
1067                 /*
1068                  * Update the vReg of the vGPU which submitted this
1069                  * workload. The vGPU may use these registers for checking
1070                  * the context state. The value comes from GPU commands
1071                  * in this workload.
1072                  */
1073                 update_vreg_in_ctx(workload);
1074
1075                 ret = dispatch_workload(workload);
1076
1077                 if (ret) {
1078                         vgpu = workload->vgpu;
1079                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1080                         goto complete;
1081                 }
1082
1083                 gvt_dbg_sched("ring %s wait workload %p\n",
1084                               engine->name, workload);
1085                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1086
1087 complete:
1088                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1089                               workload, workload->status);
1090
1091                 complete_current_workload(gvt, engine->id);
1092
1093                 if (need_force_wake)
1094                         intel_uncore_forcewake_put(engine->uncore,
1095                                                    FORCEWAKE_ALL);
1096
1097                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1098                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1099                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1100         }
1101         return 0;
1102 }
1103
1104 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1105 {
1106         struct intel_vgpu_submission *s = &vgpu->submission;
1107         struct intel_gvt *gvt = vgpu->gvt;
1108         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1109
1110         if (atomic_read(&s->running_workload_num)) {
1111                 gvt_dbg_sched("wait vgpu idle\n");
1112
1113                 wait_event(scheduler->workload_complete_wq,
1114                                 !atomic_read(&s->running_workload_num));
1115         }
1116 }
1117
1118 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1119 {
1120         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1121         struct intel_engine_cs *engine;
1122         enum intel_engine_id i;
1123
1124         gvt_dbg_core("clean workload scheduler\n");
1125
1126         for_each_engine(engine, gvt->gt, i) {
1127                 atomic_notifier_chain_unregister(
1128                                         &engine->context_status_notifier,
1129                                         &gvt->shadow_ctx_notifier_block[i]);
1130                 kthread_stop(scheduler->thread[i]);
1131         }
1132 }
1133
1134 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1135 {
1136         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1137         struct intel_engine_cs *engine;
1138         enum intel_engine_id i;
1139         int ret;
1140
1141         gvt_dbg_core("init workload scheduler\n");
1142
1143         init_waitqueue_head(&scheduler->workload_complete_wq);
1144
1145         for_each_engine(engine, gvt->gt, i) {
1146                 init_waitqueue_head(&scheduler->waitq[i]);
1147
1148                 scheduler->thread[i] = kthread_run(workload_thread, engine,
1149                                                    "gvt:%s", engine->name);
1150                 if (IS_ERR(scheduler->thread[i])) {
1151                         gvt_err("fail to create workload thread\n");
1152                         ret = PTR_ERR(scheduler->thread[i]);
1153                         goto err;
1154                 }
1155
1156                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1157                                         shadow_context_status_change;
1158                 atomic_notifier_chain_register(&engine->context_status_notifier,
1159                                         &gvt->shadow_ctx_notifier_block[i]);
1160         }
1161
1162         return 0;
1163
1164 err:
1165         intel_gvt_clean_workload_scheduler(gvt);
1166         return ret;
1167 }
1168
1169 static void
1170 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1171                                 struct i915_ppgtt *ppgtt)
1172 {
1173         int i;
1174
1175         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1176                 px_dma(ppgtt->pd) = s->i915_context_pml4;
1177         } else {
1178                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1179                         struct i915_page_directory * const pd =
1180                                 i915_pd_entry(ppgtt->pd, i);
1181
1182                         px_dma(pd) = s->i915_context_pdps[i];
1183                 }
1184         }
1185 }
1186
1187 /**
1188  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1189  * @vgpu: a vGPU
1190  *
1191  * This function is called when a vGPU is being destroyed.
1192  *
1193  */
1194 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1195 {
1196         struct intel_vgpu_submission *s = &vgpu->submission;
1197         struct intel_engine_cs *engine;
1198         enum intel_engine_id id;
1199
1200         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1201
1202         i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1203         for_each_engine(engine, vgpu->gvt->gt, id)
1204                 intel_context_unpin(s->shadow[id]);
1205
1206         kmem_cache_destroy(s->workloads);
1207 }
1208
1209
1210 /**
1211  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1212  * @vgpu: a vGPU
1213  * @engine_mask: engines expected to be reset
1214  *
1215  * This function is called when a vGPU is being destroyed.
1216  *
1217  */
1218 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1219                                  intel_engine_mask_t engine_mask)
1220 {
1221         struct intel_vgpu_submission *s = &vgpu->submission;
1222
1223         if (!s->active)
1224                 return;
1225
1226         intel_vgpu_clean_workloads(vgpu, engine_mask);
1227         s->ops->reset(vgpu, engine_mask);
1228 }
1229
1230 static void
1231 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1232                              struct i915_ppgtt *ppgtt)
1233 {
1234         int i;
1235
1236         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1237                 s->i915_context_pml4 = px_dma(ppgtt->pd);
1238         } else {
1239                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1240                         struct i915_page_directory * const pd =
1241                                 i915_pd_entry(ppgtt->pd, i);
1242
1243                         s->i915_context_pdps[i] = px_dma(pd);
1244                 }
1245         }
1246 }
1247
1248 /**
1249  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1250  * @vgpu: a vGPU
1251  *
1252  * This function is called when a vGPU is being created.
1253  *
1254  * Returns:
1255  * Zero on success, negative error code if failed.
1256  *
1257  */
1258 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1259 {
1260         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1261         struct intel_vgpu_submission *s = &vgpu->submission;
1262         struct intel_engine_cs *engine;
1263         struct i915_ppgtt *ppgtt;
1264         enum intel_engine_id i;
1265         int ret;
1266
1267         ppgtt = i915_ppgtt_create(&i915->gt);
1268         if (IS_ERR(ppgtt))
1269                 return PTR_ERR(ppgtt);
1270
1271         i915_context_ppgtt_root_save(s, ppgtt);
1272
1273         for_each_engine(engine, vgpu->gvt->gt, i) {
1274                 struct intel_context *ce;
1275
1276                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1277                 s->shadow[i] = ERR_PTR(-EINVAL);
1278
1279                 ce = intel_context_create(engine);
1280                 if (IS_ERR(ce)) {
1281                         ret = PTR_ERR(ce);
1282                         goto out_shadow_ctx;
1283                 }
1284
1285                 i915_vm_put(ce->vm);
1286                 ce->vm = i915_vm_get(&ppgtt->vm);
1287                 intel_context_set_single_submission(ce);
1288
1289                 /* Max ring buffer size */
1290                 if (!intel_uc_wants_guc_submission(&engine->gt->uc)) {
1291                         const unsigned int ring_size = 512 * SZ_4K;
1292
1293                         ce->ring = __intel_context_ring_size(ring_size);
1294                 }
1295
1296                 ret = intel_context_pin(ce);
1297                 intel_context_put(ce);
1298                 if (ret)
1299                         goto out_shadow_ctx;
1300
1301                 s->shadow[i] = ce;
1302         }
1303
1304         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1305
1306         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1307                                                   sizeof(struct intel_vgpu_workload), 0,
1308                                                   SLAB_HWCACHE_ALIGN,
1309                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1310                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1311                                                   NULL);
1312
1313         if (!s->workloads) {
1314                 ret = -ENOMEM;
1315                 goto out_shadow_ctx;
1316         }
1317
1318         atomic_set(&s->running_workload_num, 0);
1319         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1320
1321         memset(s->last_ctx, 0, sizeof(s->last_ctx));
1322
1323         i915_vm_put(&ppgtt->vm);
1324         return 0;
1325
1326 out_shadow_ctx:
1327         i915_context_ppgtt_root_restore(s, ppgtt);
1328         for_each_engine(engine, vgpu->gvt->gt, i) {
1329                 if (IS_ERR(s->shadow[i]))
1330                         break;
1331
1332                 intel_context_unpin(s->shadow[i]);
1333                 intel_context_put(s->shadow[i]);
1334         }
1335         i915_vm_put(&ppgtt->vm);
1336         return ret;
1337 }
1338
1339 /**
1340  * intel_vgpu_select_submission_ops - select virtual submission interface
1341  * @vgpu: a vGPU
1342  * @engine_mask: either ALL_ENGINES or target engine mask
1343  * @interface: expected vGPU virtual submission interface
1344  *
1345  * This function is called when guest configures submission interface.
1346  *
1347  * Returns:
1348  * Zero on success, negative error code if failed.
1349  *
1350  */
1351 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1352                                      intel_engine_mask_t engine_mask,
1353                                      unsigned int interface)
1354 {
1355         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1356         struct intel_vgpu_submission *s = &vgpu->submission;
1357         const struct intel_vgpu_submission_ops *ops[] = {
1358                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1359                         &intel_vgpu_execlist_submission_ops,
1360         };
1361         int ret;
1362
1363         if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
1364                 return -EINVAL;
1365
1366         if (drm_WARN_ON(&i915->drm,
1367                         interface == 0 && engine_mask != ALL_ENGINES))
1368                 return -EINVAL;
1369
1370         if (s->active)
1371                 s->ops->clean(vgpu, engine_mask);
1372
1373         if (interface == 0) {
1374                 s->ops = NULL;
1375                 s->virtual_submission_interface = 0;
1376                 s->active = false;
1377                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1378                 return 0;
1379         }
1380
1381         ret = ops[interface]->init(vgpu, engine_mask);
1382         if (ret)
1383                 return ret;
1384
1385         s->ops = ops[interface];
1386         s->virtual_submission_interface = interface;
1387         s->active = true;
1388
1389         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1390                         vgpu->id, s->ops->name);
1391
1392         return 0;
1393 }
1394
1395 /**
1396  * intel_vgpu_destroy_workload - destroy a vGPU workload
1397  * @workload: workload to destroy
1398  *
1399  * This function is called when destroy a vGPU workload.
1400  *
1401  */
1402 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1403 {
1404         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1405
1406         release_shadow_batch_buffer(workload);
1407         release_shadow_wa_ctx(&workload->wa_ctx);
1408
1409         if (workload->shadow_mm)
1410                 intel_vgpu_mm_put(workload->shadow_mm);
1411
1412         kmem_cache_free(s->workloads, workload);
1413 }
1414
1415 static struct intel_vgpu_workload *
1416 alloc_workload(struct intel_vgpu *vgpu)
1417 {
1418         struct intel_vgpu_submission *s = &vgpu->submission;
1419         struct intel_vgpu_workload *workload;
1420
1421         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1422         if (!workload)
1423                 return ERR_PTR(-ENOMEM);
1424
1425         INIT_LIST_HEAD(&workload->list);
1426         INIT_LIST_HEAD(&workload->shadow_bb);
1427
1428         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1429         atomic_set(&workload->shadow_ctx_active, 0);
1430
1431         workload->status = -EINPROGRESS;
1432         workload->vgpu = vgpu;
1433
1434         return workload;
1435 }
1436
1437 #define RING_CTX_OFF(x) \
1438         offsetof(struct execlist_ring_context, x)
1439
1440 static void read_guest_pdps(struct intel_vgpu *vgpu,
1441                 u64 ring_context_gpa, u32 pdp[8])
1442 {
1443         u64 gpa;
1444         int i;
1445
1446         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1447
1448         for (i = 0; i < 8; i++)
1449                 intel_gvt_hypervisor_read_gpa(vgpu,
1450                                 gpa + i * 8, &pdp[7 - i], 4);
1451 }
1452
1453 static int prepare_mm(struct intel_vgpu_workload *workload)
1454 {
1455         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1456         struct intel_vgpu_mm *mm;
1457         struct intel_vgpu *vgpu = workload->vgpu;
1458         enum intel_gvt_gtt_type root_entry_type;
1459         u64 pdps[GVT_RING_CTX_NR_PDPS];
1460
1461         switch (desc->addressing_mode) {
1462         case 1: /* legacy 32-bit */
1463                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1464                 break;
1465         case 3: /* legacy 64-bit */
1466                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1467                 break;
1468         default:
1469                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1470                 return -EINVAL;
1471         }
1472
1473         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1474
1475         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1476         if (IS_ERR(mm))
1477                 return PTR_ERR(mm);
1478
1479         workload->shadow_mm = mm;
1480         return 0;
1481 }
1482
1483 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1484                 ((a)->lrca == (b)->lrca))
1485
1486 /**
1487  * intel_vgpu_create_workload - create a vGPU workload
1488  * @vgpu: a vGPU
1489  * @engine: the engine
1490  * @desc: a guest context descriptor
1491  *
1492  * This function is called when creating a vGPU workload.
1493  *
1494  * Returns:
1495  * struct intel_vgpu_workload * on success, negative error code in
1496  * pointer if failed.
1497  *
1498  */
1499 struct intel_vgpu_workload *
1500 intel_vgpu_create_workload(struct intel_vgpu *vgpu,
1501                            const struct intel_engine_cs *engine,
1502                            struct execlist_ctx_descriptor_format *desc)
1503 {
1504         struct intel_vgpu_submission *s = &vgpu->submission;
1505         struct list_head *q = workload_q_head(vgpu, engine);
1506         struct intel_vgpu_workload *last_workload = NULL;
1507         struct intel_vgpu_workload *workload = NULL;
1508         u64 ring_context_gpa;
1509         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1510         u32 guest_head;
1511         int ret;
1512
1513         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1514                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1515         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1516                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1517                 return ERR_PTR(-EINVAL);
1518         }
1519
1520         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1521                         RING_CTX_OFF(ring_header.val), &head, 4);
1522
1523         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1524                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1525
1526         guest_head = head;
1527
1528         head &= RB_HEAD_OFF_MASK;
1529         tail &= RB_TAIL_OFF_MASK;
1530
1531         list_for_each_entry_reverse(last_workload, q, list) {
1532
1533                 if (same_context(&last_workload->ctx_desc, desc)) {
1534                         gvt_dbg_el("ring %s cur workload == last\n",
1535                                    engine->name);
1536                         gvt_dbg_el("ctx head %x real head %lx\n", head,
1537                                    last_workload->rb_tail);
1538                         /*
1539                          * cannot use guest context head pointer here,
1540                          * as it might not be updated at this time
1541                          */
1542                         head = last_workload->rb_tail;
1543                         break;
1544                 }
1545         }
1546
1547         gvt_dbg_el("ring %s begin a new workload\n", engine->name);
1548
1549         /* record some ring buffer register values for scan and shadow */
1550         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1551                         RING_CTX_OFF(rb_start.val), &start, 4);
1552         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1553                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1554         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1555                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1556
1557         if (!intel_gvt_ggtt_validate_range(vgpu, start,
1558                                 _RING_CTL_BUF_SIZE(ctl))) {
1559                 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1560                 return ERR_PTR(-EINVAL);
1561         }
1562
1563         workload = alloc_workload(vgpu);
1564         if (IS_ERR(workload))
1565                 return workload;
1566
1567         workload->engine = engine;
1568         workload->ctx_desc = *desc;
1569         workload->ring_context_gpa = ring_context_gpa;
1570         workload->rb_head = head;
1571         workload->guest_rb_head = guest_head;
1572         workload->rb_tail = tail;
1573         workload->rb_start = start;
1574         workload->rb_ctl = ctl;
1575
1576         if (engine->id == RCS0) {
1577                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1578                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1579                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1580                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1581
1582                 workload->wa_ctx.indirect_ctx.guest_gma =
1583                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1584                 workload->wa_ctx.indirect_ctx.size =
1585                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1586                         CACHELINE_BYTES;
1587
1588                 if (workload->wa_ctx.indirect_ctx.size != 0) {
1589                         if (!intel_gvt_ggtt_validate_range(vgpu,
1590                                 workload->wa_ctx.indirect_ctx.guest_gma,
1591                                 workload->wa_ctx.indirect_ctx.size)) {
1592                                 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1593                                     workload->wa_ctx.indirect_ctx.guest_gma);
1594                                 kmem_cache_free(s->workloads, workload);
1595                                 return ERR_PTR(-EINVAL);
1596                         }
1597                 }
1598
1599                 workload->wa_ctx.per_ctx.guest_gma =
1600                         per_ctx & PER_CTX_ADDR_MASK;
1601                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1602                 if (workload->wa_ctx.per_ctx.valid) {
1603                         if (!intel_gvt_ggtt_validate_range(vgpu,
1604                                 workload->wa_ctx.per_ctx.guest_gma,
1605                                 CACHELINE_BYTES)) {
1606                                 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1607                                         workload->wa_ctx.per_ctx.guest_gma);
1608                                 kmem_cache_free(s->workloads, workload);
1609                                 return ERR_PTR(-EINVAL);
1610                         }
1611                 }
1612         }
1613
1614         gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n",
1615                    workload, engine->name, head, tail, start, ctl);
1616
1617         ret = prepare_mm(workload);
1618         if (ret) {
1619                 kmem_cache_free(s->workloads, workload);
1620                 return ERR_PTR(ret);
1621         }
1622
1623         /* Only scan and shadow the first workload in the queue
1624          * as there is only one pre-allocated buf-obj for shadow.
1625          */
1626         if (list_empty(q)) {
1627                 intel_wakeref_t wakeref;
1628
1629                 with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)
1630                         ret = intel_gvt_scan_and_shadow_workload(workload);
1631         }
1632
1633         if (ret) {
1634                 if (vgpu_is_vm_unhealthy(ret))
1635                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1636                 intel_vgpu_destroy_workload(workload);
1637                 return ERR_PTR(ret);
1638         }
1639
1640         return workload;
1641 }
1642
1643 /**
1644  * intel_vgpu_queue_workload - Qeue a vGPU workload
1645  * @workload: the workload to queue in
1646  */
1647 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1648 {
1649         list_add_tail(&workload->list,
1650                       workload_q_head(workload->vgpu, workload->engine));
1651         intel_gvt_kick_schedule(workload->vgpu->gvt);
1652         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);
1653 }