drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "gem/i915_gem_pm.h"
  39 #include "gt/intel_context.h"
  40 #include "gt/intel_execlists_submission.h"
  41 #include "gt/intel_lrc.h"
  42 #include "gt/intel_ring.h"
  43
  44 #include "i915_drv.h"
  45 #include "i915_gem_gtt.h"
  46 #include "gvt.h"
  47
  48 #define RING_CTX_OFF(x) \
  49         offsetof(struct execlist_ring_context, x)
  50
  51 static void set_context_pdp_root_pointer(
  52                 struct execlist_ring_context *ring_context,
  53                 u32 pdp[8])
  54 {
  55         int i;
  56
  57         for (i = 0; i < 8; i++)
  58                 ring_context->pdps[i].val = pdp[7 - i];
  59 }
  60
  61 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  62 {
  63         struct execlist_ring_context *shadow_ring_context;
  64         struct intel_context *ctx = workload->req->context;
  65
  66         if (WARN_ON(!workload->shadow_mm))
  67                 return;
  68
  69         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  70                 return;
  71
  72         shadow_ring_context = (struct execlist_ring_context *)ctx->lrc_reg_state;
  73         set_context_pdp_root_pointer(shadow_ring_context,
  74                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  75 }
  76
  77 /*
  78  * when populating shadow ctx from guest, we should not overrride oa related
  79  * registers, so that they will not be overlapped by guest oa configs. Thus
  80  * made it possible to capture oa data from host for both host and guests.
  81  */
  82 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  83                 u32 *reg_state, bool save)
  84 {
  85         struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;
  86         u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
  87         u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
  88         int i = 0;
  89         u32 flex_mmio[] = {
  90                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  91                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  92                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  94                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  95                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  96                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  97         };
  98
  99         if (workload->engine->id != RCS0)
 100                 return;
 101
 102         if (save) {
 103                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 104
 105                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 106                         u32 state_offset = ctx_flexeu0 + i * 2;
 107
 108                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 109                 }
 110         } else {
 111                 reg_state[ctx_oactxctrl] =
 112                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 113                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 114
 115                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 116                         u32 state_offset = ctx_flexeu0 + i * 2;
 117                         u32 mmio = flex_mmio[i];
 118
 119                         reg_state[state_offset] = mmio;
 120                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 121                 }
 122         }
 123 }
 124
 125 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 126 {
 127         struct intel_vgpu *vgpu = workload->vgpu;
 128         struct intel_gvt *gvt = vgpu->gvt;
 129         struct intel_context *ctx = workload->req->context;
 130         struct execlist_ring_context *shadow_ring_context;
 131         void *dst;
 132         void *context_base;
 133         unsigned long context_gpa, context_page_num;
 134         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 135         unsigned long gpa_size; /* size of consecutive GPAs */
 136         struct intel_vgpu_submission *s = &vgpu->submission;
 137         int i;
 138         bool skip = false;
 139         int ring_id = workload->engine->id;
 140         int ret;
 141
 142         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 143
 144         context_base = (void *) ctx->lrc_reg_state -
 145                                 (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 146
 147         shadow_ring_context = (void *) ctx->lrc_reg_state;
 148
 149         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 150 #define COPY_REG(name) \
 151         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 152                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 153 #define COPY_REG_MASKED(name) {\
 154                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 155                                               + RING_CTX_OFF(name.val),\
 156                                               &shadow_ring_context->name.val, 4);\
 157                 shadow_ring_context->name.val |= 0xffff << 16;\
 158         }
 159
 160         COPY_REG_MASKED(ctx_ctrl);
 161         COPY_REG(ctx_timestamp);
 162
 163         if (workload->engine->id == RCS0) {
 164                 COPY_REG(bb_per_ctx_ptr);
 165                 COPY_REG(rcs_indirect_ctx);
 166                 COPY_REG(rcs_indirect_ctx_offset);
 167         } else if (workload->engine->id == BCS0)
 168                 intel_gvt_hypervisor_read_gpa(vgpu,
 169                                 workload->ring_context_gpa +
 170                                 BCS_TILE_REGISTER_VAL_OFFSET,
 171                                 (void *)shadow_ring_context +
 172                                 BCS_TILE_REGISTER_VAL_OFFSET, 4);
 173 #undef COPY_REG
 174 #undef COPY_REG_MASKED
 175
 176         /* don't copy Ring Context (the first 0x50 dwords),
 177          * only copy the Engine Context part from guest
 178          */
 179         intel_gvt_hypervisor_read_gpa(vgpu,
 180                         workload->ring_context_gpa +
 181                         RING_CTX_SIZE,
 182                         (void *)shadow_ring_context +
 183                         RING_CTX_SIZE,
 184                         I915_GTT_PAGE_SIZE - RING_CTX_SIZE);
 185
 186         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 187
 188         gvt_dbg_sched("ring %s workload lrca %x, ctx_id %x, ctx gpa %llx",
 189                         workload->engine->name, workload->ctx_desc.lrca,
 190                         workload->ctx_desc.context_id,
 191                         workload->ring_context_gpa);
 192
 193         /* only need to ensure this context is not pinned/unpinned during the
 194          * period from last submission to this this submission.
 195          * Upon reaching this function, the currently submitted context is not
 196          * supposed to get unpinned. If a misbehaving guest driver ever does
 197          * this, it would corrupt itself.
 198          */
 199         if (s->last_ctx[ring_id].valid &&
 200                         (s->last_ctx[ring_id].lrca ==
 201                                 workload->ctx_desc.lrca) &&
 202                         (s->last_ctx[ring_id].ring_context_gpa ==
 203                                 workload->ring_context_gpa))
 204                 skip = true;
 205
 206         s->last_ctx[ring_id].lrca = workload->ctx_desc.lrca;
 207         s->last_ctx[ring_id].ring_context_gpa = workload->ring_context_gpa;
 208
 209         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) || skip)
 210                 return 0;
 211
 212         s->last_ctx[ring_id].valid = false;
 213         context_page_num = workload->engine->context_size;
 214         context_page_num = context_page_num >> PAGE_SHIFT;
 215
 216         if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
 217                 context_page_num = 19;
 218
 219         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 220          * read from the continuous GPAs into dst virtual address
 221          */
 222         gpa_size = 0;
 223         for (i = 2; i < context_page_num; i++) {
 224                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 225                                 (u32)((workload->ctx_desc.lrca + i) <<
 226                                 I915_GTT_PAGE_SHIFT));
 227                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 228                         gvt_vgpu_err("Invalid guest context descriptor\n");
 229                         return -EFAULT;
 230                 }
 231
 232                 if (gpa_size == 0) {
 233                         gpa_base = context_gpa;
 234                         dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 235                 } else if (context_gpa != gpa_base + gpa_size)
 236                         goto read;
 237
 238                 gpa_size += I915_GTT_PAGE_SIZE;
 239
 240                 if (i == context_page_num - 1)
 241                         goto read;
 242
 243                 continue;
 244
 245 read:
 246                 intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size);
 247                 gpa_base = context_gpa;
 248                 gpa_size = I915_GTT_PAGE_SIZE;
 249                 dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 250         }
 251         ret = intel_gvt_scan_engine_context(workload);
 252         if (ret) {
 253                 gvt_vgpu_err("invalid cmd found in guest context pages\n");
 254                 return ret;
 255         }
 256         s->last_ctx[ring_id].valid = true;
 257         return 0;
 258 }
 259
 260 static inline bool is_gvt_request(struct i915_request *rq)
 261 {
 262         return intel_context_force_single_submission(rq->context);
 263 }
 264
 265 static void save_ring_hw_state(struct intel_vgpu *vgpu,
 266                                const struct intel_engine_cs *engine)
 267 {
 268         struct intel_uncore *uncore = engine->uncore;
 269         i915_reg_t reg;
 270
 271         reg = RING_INSTDONE(engine->mmio_base);
 272         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 273                 intel_uncore_read(uncore, reg);
 274
 275         reg = RING_ACTHD(engine->mmio_base);
 276         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 277                 intel_uncore_read(uncore, reg);
 278
 279         reg = RING_ACTHD_UDW(engine->mmio_base);
 280         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 281                 intel_uncore_read(uncore, reg);
 282 }
 283
 284 static int shadow_context_status_change(struct notifier_block *nb,
 285                 unsigned long action, void *data)
 286 {
 287         struct i915_request *rq = data;
 288         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 289                                 shadow_ctx_notifier_block[rq->engine->id]);
 290         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 291         enum intel_engine_id ring_id = rq->engine->id;
 292         struct intel_vgpu_workload *workload;
 293         unsigned long flags;
 294
 295         if (!is_gvt_request(rq)) {
 296                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 297                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 298                     scheduler->engine_owner[ring_id]) {
 299                         /* Switch ring from vGPU to host. */
 300                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 301                                               NULL, rq->engine);
 302                         scheduler->engine_owner[ring_id] = NULL;
 303                 }
 304                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 305
 306                 return NOTIFY_OK;
 307         }
 308
 309         workload = scheduler->current_workload[ring_id];
 310         if (unlikely(!workload))
 311                 return NOTIFY_OK;
 312
 313         switch (action) {
 314         case INTEL_CONTEXT_SCHEDULE_IN:
 315                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 316                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 317                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 318                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 319                                               workload->vgpu, rq->engine);
 320                         scheduler->engine_owner[ring_id] = workload->vgpu;
 321                 } else
 322                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 323                                       ring_id, workload->vgpu->id);
 324                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 325                 atomic_set(&workload->shadow_ctx_active, 1);
 326                 break;
 327         case INTEL_CONTEXT_SCHEDULE_OUT:
 328                 save_ring_hw_state(workload->vgpu, rq->engine);
 329                 atomic_set(&workload->shadow_ctx_active, 0);
 330                 break;
 331         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 332                 save_ring_hw_state(workload->vgpu, rq->engine);
 333                 break;
 334         default:
 335                 WARN_ON(1);
 336                 return NOTIFY_OK;
 337         }
 338         wake_up(&workload->shadow_ctx_status_wq);
 339         return NOTIFY_OK;
 340 }
 341
 342 static void
 343 shadow_context_descriptor_update(struct intel_context *ce,
 344                                  struct intel_vgpu_workload *workload)
 345 {
 346         u64 desc = ce->lrc.desc;
 347
 348         /*
 349          * Update bits 0-11 of the context descriptor which includes flags
 350          * like GEN8_CTX_* cached in desc_template
 351          */
 352         desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 353         desc |= (u64)workload->ctx_desc.addressing_mode <<
 354                 GEN8_CTX_ADDRESSING_MODE_SHIFT;
 355
 356         ce->lrc.desc = desc;
 357 }
 358
 359 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 360 {
 361         struct intel_vgpu *vgpu = workload->vgpu;
 362         struct i915_request *req = workload->req;
 363         void *shadow_ring_buffer_va;
 364         u32 *cs;
 365         int err;
 366
 367         if (GRAPHICS_VER(req->engine->i915) == 9 && is_inhibit_context(req->context))
 368                 intel_vgpu_restore_inhibit_context(vgpu, req);
 369
 370         /*
 371          * To track whether a request has started on HW, we can emit a
 372          * breadcrumb at the beginning of the request and check its
 373          * timeline's HWSP to see if the breadcrumb has advanced past the
 374          * start of this request. Actually, the request must have the
 375          * init_breadcrumb if its timeline set has_init_bread_crumb, or the
 376          * scheduler might get a wrong state of it during reset. Since the
 377          * requests from gvt always set the has_init_breadcrumb flag, here
 378          * need to do the emit_init_breadcrumb for all the requests.
 379          */
 380         if (req->engine->emit_init_breadcrumb) {
 381                 err = req->engine->emit_init_breadcrumb(req);
 382                 if (err) {
 383                         gvt_vgpu_err("fail to emit init breadcrumb\n");
 384                         return err;
 385                 }
 386         }
 387
 388         /* allocate shadow ring buffer */
 389         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 390         if (IS_ERR(cs)) {
 391                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 392                         workload->rb_len);
 393                 return PTR_ERR(cs);
 394         }
 395
 396         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 397
 398         /* get shadow ring buffer va */
 399         workload->shadow_ring_buffer_va = cs;
 400
 401         memcpy(cs, shadow_ring_buffer_va,
 402                         workload->rb_len);
 403
 404         cs += workload->rb_len / sizeof(u32);
 405         intel_ring_advance(workload->req, cs);
 406
 407         return 0;
 408 }
 409
 410 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 411 {
 412         if (!wa_ctx->indirect_ctx.obj)
 413                 return;
 414
 415         i915_gem_object_lock(wa_ctx->indirect_ctx.obj, NULL);
 416         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 417         i915_gem_object_unlock(wa_ctx->indirect_ctx.obj);
 418         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 419
 420         wa_ctx->indirect_ctx.obj = NULL;
 421         wa_ctx->indirect_ctx.shadow_va = NULL;
 422 }
 423
 424 static void set_dma_address(struct i915_page_directory *pd, dma_addr_t addr)
 425 {
 426         struct scatterlist *sg = pd->pt.base->mm.pages->sgl;
 427
 428         /* This is not a good idea */
 429         sg->dma_address = addr;
 430 }
 431
 432 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 433                                           struct intel_context *ce)
 434 {
 435         struct intel_vgpu_mm *mm = workload->shadow_mm;
 436         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
 437         int i = 0;
 438
 439         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 440                 set_dma_address(ppgtt->pd, mm->ppgtt_mm.shadow_pdps[0]);
 441         } else {
 442                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 443                         struct i915_page_directory * const pd =
 444                                 i915_pd_entry(ppgtt->pd, i);
 445                         /* skip now as current i915 ppgtt alloc won't allocate
 446                            top level pdp for non 4-level table, won't impact
 447                            shadow ppgtt. */
 448                         if (!pd)
 449                                 break;
 450
 451                         set_dma_address(pd, mm->ppgtt_mm.shadow_pdps[i]);
 452                 }
 453         }
 454 }
 455
 456 static int
 457 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
 458 {
 459         struct intel_vgpu *vgpu = workload->vgpu;
 460         struct intel_vgpu_submission *s = &vgpu->submission;
 461         struct i915_request *rq;
 462
 463         if (workload->req)
 464                 return 0;
 465
 466         rq = i915_request_create(s->shadow[workload->engine->id]);
 467         if (IS_ERR(rq)) {
 468                 gvt_vgpu_err("fail to allocate gem request\n");
 469                 return PTR_ERR(rq);
 470         }
 471
 472         workload->req = i915_request_get(rq);
 473         return 0;
 474 }
 475
 476 /**
 477  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 478  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 479  * @workload: an abstract entity for each execlist submission.
 480  *
 481  * This function is called before the workload submitting to i915, to make
 482  * sure the content of the workload is valid.
 483  */
 484 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 485 {
 486         struct intel_vgpu *vgpu = workload->vgpu;
 487         struct intel_vgpu_submission *s = &vgpu->submission;
 488         int ret;
 489
 490         lockdep_assert_held(&vgpu->vgpu_lock);
 491
 492         if (workload->shadow)
 493                 return 0;
 494
 495         if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))
 496                 shadow_context_descriptor_update(s->shadow[workload->engine->id],
 497                                                  workload);
 498
 499         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 500         if (ret)
 501                 return ret;
 502
 503         if (workload->engine->id == RCS0 &&
 504             workload->wa_ctx.indirect_ctx.size) {
 505                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 506                 if (ret)
 507                         goto err_shadow;
 508         }
 509
 510         workload->shadow = true;
 511         return 0;
 512
 513 err_shadow:
 514         release_shadow_wa_ctx(&workload->wa_ctx);
 515         return ret;
 516 }
 517
 518 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 519
 520 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 521 {
 522         struct intel_gvt *gvt = workload->vgpu->gvt;
 523         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 524         struct intel_vgpu_shadow_bb *bb;
 525         struct i915_gem_ww_ctx ww;
 526         int ret;
 527
 528         list_for_each_entry(bb, &workload->shadow_bb, list) {
 529                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 530                  * is only updated into ring_scan_buffer, not real ring address
 531                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 532                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 533                  * in copy_workload_to_ring_buffer.
 534                  */
 535
 536                 if (bb->bb_offset)
 537                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 538                                 + bb->bb_offset;
 539
 540                 /*
 541                  * For non-priv bb, scan&shadow is only for
 542                  * debugging purpose, so the content of shadow bb
 543                  * is the same as original bb. Therefore,
 544                  * here, rather than switch to shadow bb's gma
 545                  * address, we directly use original batch buffer's
 546                  * gma address, and send original bb to hardware
 547                  * directly
 548                  */
 549                 if (!bb->ppgtt) {
 550                         i915_gem_ww_ctx_init(&ww, false);
 551 retry:
 552                         i915_gem_object_lock(bb->obj, &ww);
 553
 554                         bb->vma = i915_gem_object_ggtt_pin_ww(bb->obj, &ww,
 555                                                               NULL, 0, 0, 0);
 556                         if (IS_ERR(bb->vma)) {
 557                                 ret = PTR_ERR(bb->vma);
 558                                 if (ret == -EDEADLK) {
 559                                         ret = i915_gem_ww_ctx_backoff(&ww);
 560                                         if (!ret)
 561                                                 goto retry;
 562                                 }
 563                                 goto err;
 564                         }
 565
 566                         /* relocate shadow batch buffer */
 567                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 568                         if (gmadr_bytes == 8)
 569                                 bb->bb_start_cmd_va[2] = 0;
 570
 571                         ret = i915_vma_move_to_active(bb->vma,
 572                                                       workload->req,
 573                                                       0);
 574                         if (ret)
 575                                 goto err;
 576
 577                         /* No one is going to touch shadow bb from now on. */
 578                         i915_gem_object_flush_map(bb->obj);
 579                         i915_gem_ww_ctx_fini(&ww);
 580                 }
 581         }
 582         return 0;
 583 err:
 584         i915_gem_ww_ctx_fini(&ww);
 585         release_shadow_batch_buffer(workload);
 586         return ret;
 587 }
 588
 589 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 590 {
 591         struct intel_vgpu_workload *workload =
 592                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 593         struct i915_request *rq = workload->req;
 594         struct execlist_ring_context *shadow_ring_context =
 595                 (struct execlist_ring_context *)rq->context->lrc_reg_state;
 596
 597         shadow_ring_context->bb_per_ctx_ptr.val =
 598                 (shadow_ring_context->bb_per_ctx_ptr.val &
 599                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 600         shadow_ring_context->rcs_indirect_ctx.val =
 601                 (shadow_ring_context->rcs_indirect_ctx.val &
 602                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 603 }
 604
 605 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 606 {
 607         struct i915_vma *vma;
 608         unsigned char *per_ctx_va =
 609                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 610                 wa_ctx->indirect_ctx.size;
 611         struct i915_gem_ww_ctx ww;
 612         int ret;
 613
 614         if (wa_ctx->indirect_ctx.size == 0)
 615                 return 0;
 616
 617         i915_gem_ww_ctx_init(&ww, false);
 618 retry:
 619         i915_gem_object_lock(wa_ctx->indirect_ctx.obj, &ww);
 620
 621         vma = i915_gem_object_ggtt_pin_ww(wa_ctx->indirect_ctx.obj, &ww, NULL,
 622                                           0, CACHELINE_BYTES, 0);
 623         if (IS_ERR(vma)) {
 624                 ret = PTR_ERR(vma);
 625                 if (ret == -EDEADLK) {
 626                         ret = i915_gem_ww_ctx_backoff(&ww);
 627                         if (!ret)
 628                                 goto retry;
 629                 }
 630                 return ret;
 631         }
 632
 633         i915_gem_ww_ctx_fini(&ww);
 634
 635         /* FIXME: we are not tracking our pinned VMA leaving it
 636          * up to the core to fix up the stray pin_count upon
 637          * free.
 638          */
 639
 640         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 641
 642         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 643         memset(per_ctx_va, 0, CACHELINE_BYTES);
 644
 645         update_wa_ctx_2_shadow_ctx(wa_ctx);
 646         return 0;
 647 }
 648
 649 static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
 650 {
 651         vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
 652                 workload->rb_start;
 653 }
 654
 655 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 656 {
 657         struct intel_vgpu_shadow_bb *bb, *pos;
 658
 659         if (list_empty(&workload->shadow_bb))
 660                 return;
 661
 662         bb = list_first_entry(&workload->shadow_bb,
 663                         struct intel_vgpu_shadow_bb, list);
 664
 665         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 666                 if (bb->obj) {
 667                         i915_gem_object_lock(bb->obj, NULL);
 668                         if (bb->va && !IS_ERR(bb->va))
 669                                 i915_gem_object_unpin_map(bb->obj);
 670
 671                         if (bb->vma && !IS_ERR(bb->vma))
 672                                 i915_vma_unpin(bb->vma);
 673
 674                         i915_gem_object_unlock(bb->obj);
 675                         i915_gem_object_put(bb->obj);
 676                 }
 677                 list_del(&bb->list);
 678                 kfree(bb);
 679         }
 680 }
 681
 682 static int
 683 intel_vgpu_shadow_mm_pin(struct intel_vgpu_workload *workload)
 684 {
 685         struct intel_vgpu *vgpu = workload->vgpu;
 686         struct intel_vgpu_mm *m;
 687         int ret = 0;
 688
 689         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 690         if (ret) {
 691                 gvt_vgpu_err("fail to vgpu pin mm\n");
 692                 return ret;
 693         }
 694
 695         if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
 696             !workload->shadow_mm->ppgtt_mm.shadowed) {
 697                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 698                 return -EINVAL;
 699         }
 700
 701         if (!list_empty(&workload->lri_shadow_mm)) {
 702                 list_for_each_entry(m, &workload->lri_shadow_mm,
 703                                     ppgtt_mm.link) {
 704                         ret = intel_vgpu_pin_mm(m);
 705                         if (ret) {
 706                                 list_for_each_entry_from_reverse(m,
 707                                                                  &workload->lri_shadow_mm,
 708                                                                  ppgtt_mm.link)
 709                                         intel_vgpu_unpin_mm(m);
 710                                 gvt_vgpu_err("LRI shadow ppgtt fail to pin\n");
 711                                 break;
 712                         }
 713                 }
 714         }
 715
 716         if (ret)
 717                 intel_vgpu_unpin_mm(workload->shadow_mm);
 718
 719         return ret;
 720 }
 721
 722 static void
 723 intel_vgpu_shadow_mm_unpin(struct intel_vgpu_workload *workload)
 724 {
 725         struct intel_vgpu_mm *m;
 726
 727         if (!list_empty(&workload->lri_shadow_mm)) {
 728                 list_for_each_entry(m, &workload->lri_shadow_mm,
 729                                     ppgtt_mm.link)
 730                         intel_vgpu_unpin_mm(m);
 731         }
 732         intel_vgpu_unpin_mm(workload->shadow_mm);
 733 }
 734
 735 static int prepare_workload(struct intel_vgpu_workload *workload)
 736 {
 737         struct intel_vgpu *vgpu = workload->vgpu;
 738         struct intel_vgpu_submission *s = &vgpu->submission;
 739         int ret = 0;
 740
 741         ret = intel_vgpu_shadow_mm_pin(workload);
 742         if (ret) {
 743                 gvt_vgpu_err("fail to pin shadow mm\n");
 744                 return ret;
 745         }
 746
 747         update_shadow_pdps(workload);
 748
 749         set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);
 750
 751         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 752         if (ret) {
 753                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 754                 goto err_unpin_mm;
 755         }
 756
 757         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 758         if (ret) {
 759                 gvt_vgpu_err("fail to flush post shadow\n");
 760                 goto err_unpin_mm;
 761         }
 762
 763         ret = copy_workload_to_ring_buffer(workload);
 764         if (ret) {
 765                 gvt_vgpu_err("fail to generate request\n");
 766                 goto err_unpin_mm;
 767         }
 768
 769         ret = prepare_shadow_batch_buffer(workload);
 770         if (ret) {
 771                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 772                 goto err_unpin_mm;
 773         }
 774
 775         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 776         if (ret) {
 777                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 778                 goto err_shadow_batch;
 779         }
 780
 781         if (workload->prepare) {
 782                 ret = workload->prepare(workload);
 783                 if (ret)
 784                         goto err_shadow_wa_ctx;
 785         }
 786
 787         return 0;
 788 err_shadow_wa_ctx:
 789         release_shadow_wa_ctx(&workload->wa_ctx);
 790 err_shadow_batch:
 791         release_shadow_batch_buffer(workload);
 792 err_unpin_mm:
 793         intel_vgpu_shadow_mm_unpin(workload);
 794         return ret;
 795 }
 796
 797 static int dispatch_workload(struct intel_vgpu_workload *workload)
 798 {
 799         struct intel_vgpu *vgpu = workload->vgpu;
 800         struct i915_request *rq;
 801         int ret;
 802
 803         gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n",
 804                       workload->engine->name, workload);
 805
 806         mutex_lock(&vgpu->vgpu_lock);
 807
 808         ret = intel_gvt_workload_req_alloc(workload);
 809         if (ret)
 810                 goto err_req;
 811
 812         ret = intel_gvt_scan_and_shadow_workload(workload);
 813         if (ret)
 814                 goto out;
 815
 816         ret = populate_shadow_context(workload);
 817         if (ret) {
 818                 release_shadow_wa_ctx(&workload->wa_ctx);
 819                 goto out;
 820         }
 821
 822         ret = prepare_workload(workload);
 823 out:
 824         if (ret) {
 825                 /* We might still need to add request with
 826                  * clean ctx to retire it properly..
 827                  */
 828                 rq = fetch_and_zero(&workload->req);
 829                 i915_request_put(rq);
 830         }
 831
 832         if (!IS_ERR_OR_NULL(workload->req)) {
 833                 gvt_dbg_sched("ring id %s submit workload to i915 %p\n",
 834                               workload->engine->name, workload->req);
 835                 i915_request_add(workload->req);
 836                 workload->dispatched = true;
 837         }
 838 err_req:
 839         if (ret)
 840                 workload->status = ret;
 841         mutex_unlock(&vgpu->vgpu_lock);
 842         return ret;
 843 }
 844
 845 static struct intel_vgpu_workload *
 846 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine)
 847 {
 848         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 849         struct intel_vgpu_workload *workload = NULL;
 850
 851         mutex_lock(&gvt->sched_lock);
 852
 853         /*
 854          * no current vgpu / will be scheduled out / no workload
 855          * bail out
 856          */
 857         if (!scheduler->current_vgpu) {
 858                 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);
 859                 goto out;
 860         }
 861
 862         if (scheduler->need_reschedule) {
 863                 gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);
 864                 goto out;
 865         }
 866
 867         if (!scheduler->current_vgpu->active ||
 868             list_empty(workload_q_head(scheduler->current_vgpu, engine)))
 869                 goto out;
 870
 871         /*
 872          * still have current workload, maybe the workload disptacher
 873          * fail to submit it for some reason, resubmit it.
 874          */
 875         if (scheduler->current_workload[engine->id]) {
 876                 workload = scheduler->current_workload[engine->id];
 877                 gvt_dbg_sched("ring %s still have current workload %p\n",
 878                               engine->name, workload);
 879                 goto out;
 880         }
 881
 882         /*
 883          * pick a workload as current workload
 884          * once current workload is set, schedule policy routines
 885          * will wait the current workload is finished when trying to
 886          * schedule out a vgpu.
 887          */
 888         scheduler->current_workload[engine->id] =
 889                 list_first_entry(workload_q_head(scheduler->current_vgpu,
 890                                                  engine),
 891                                  struct intel_vgpu_workload, list);
 892
 893         workload = scheduler->current_workload[engine->id];
 894
 895         gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);
 896
 897         atomic_inc(&workload->vgpu->submission.running_workload_num);
 898 out:
 899         mutex_unlock(&gvt->sched_lock);
 900         return workload;
 901 }
 902
 903 static void update_guest_pdps(struct intel_vgpu *vgpu,
 904                               u64 ring_context_gpa, u32 pdp[8])
 905 {
 906         u64 gpa;
 907         int i;
 908
 909         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
 910
 911         for (i = 0; i < 8; i++)
 912                 intel_gvt_hypervisor_write_gpa(vgpu,
 913                                 gpa + i * 8, &pdp[7 - i], 4);
 914 }
 915
 916 static __maybe_unused bool
 917 check_shadow_context_ppgtt(struct execlist_ring_context *c, struct intel_vgpu_mm *m)
 918 {
 919         if (m->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 920                 u64 shadow_pdp = c->pdps[7].val | (u64) c->pdps[6].val << 32;
 921
 922                 if (shadow_pdp != m->ppgtt_mm.shadow_pdps[0]) {
 923                         gvt_dbg_mm("4-level context ppgtt not match LRI command\n");
 924                         return false;
 925                 }
 926                 return true;
 927         } else {
 928                 /* see comment in LRI handler in cmd_parser.c */
 929                 gvt_dbg_mm("invalid shadow mm type\n");
 930                 return false;
 931         }
 932 }
 933
 934 static void update_guest_context(struct intel_vgpu_workload *workload)
 935 {
 936         struct i915_request *rq = workload->req;
 937         struct intel_vgpu *vgpu = workload->vgpu;
 938         struct execlist_ring_context *shadow_ring_context;
 939         struct intel_context *ctx = workload->req->context;
 940         void *context_base;
 941         void *src;
 942         unsigned long context_gpa, context_page_num;
 943         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 944         unsigned long gpa_size; /* size of consecutive GPAs*/
 945         int i;
 946         u32 ring_base;
 947         u32 head, tail;
 948         u16 wrap_count;
 949
 950         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 951                       workload->ctx_desc.lrca);
 952
 953         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 954
 955         head = workload->rb_head;
 956         tail = workload->rb_tail;
 957         wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
 958
 959         if (tail < head) {
 960                 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
 961                         wrap_count = 0;
 962                 else
 963                         wrap_count += 1;
 964         }
 965
 966         head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
 967
 968         ring_base = rq->engine->mmio_base;
 969         vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
 970         vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
 971
 972         context_page_num = rq->engine->context_size;
 973         context_page_num = context_page_num >> PAGE_SHIFT;
 974
 975         if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
 976                 context_page_num = 19;
 977
 978         context_base = (void *) ctx->lrc_reg_state -
 979                         (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 980
 981         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 982          * write to the consecutive GPAs from src virtual address
 983          */
 984         gpa_size = 0;
 985         for (i = 2; i < context_page_num; i++) {
 986                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 987                                 (u32)((workload->ctx_desc.lrca + i) <<
 988                                         I915_GTT_PAGE_SHIFT));
 989                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 990                         gvt_vgpu_err("invalid guest context descriptor\n");
 991                         return;
 992                 }
 993
 994                 if (gpa_size == 0) {
 995                         gpa_base = context_gpa;
 996                         src = context_base + (i << I915_GTT_PAGE_SHIFT);
 997                 } else if (context_gpa != gpa_base + gpa_size)
 998                         goto write;
 999
1000                 gpa_size += I915_GTT_PAGE_SIZE;
1001
1002                 if (i == context_page_num - 1)
1003                         goto write;
1004
1005                 continue;
1006
1007 write:
1008                 intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size);
1009                 gpa_base = context_gpa;
1010                 gpa_size = I915_GTT_PAGE_SIZE;
1011                 src = context_base + (i << I915_GTT_PAGE_SHIFT);
1012         }
1013
1014         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
1015                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
1016
1017         shadow_ring_context = (void *) ctx->lrc_reg_state;
1018
1019         if (!list_empty(&workload->lri_shadow_mm)) {
1020                 struct intel_vgpu_mm *m = list_last_entry(&workload->lri_shadow_mm,
1021                                                           struct intel_vgpu_mm,
1022                                                           ppgtt_mm.link);
1023                 GEM_BUG_ON(!check_shadow_context_ppgtt(shadow_ring_context, m));
1024                 update_guest_pdps(vgpu, workload->ring_context_gpa,
1025                                   (void *)m->ppgtt_mm.guest_pdps);
1026         }
1027
1028 #define COPY_REG(name) \
1029         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
1030                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
1031
1032         COPY_REG(ctx_ctrl);
1033         COPY_REG(ctx_timestamp);
1034
1035 #undef COPY_REG
1036
1037         intel_gvt_hypervisor_write_gpa(vgpu,
1038                         workload->ring_context_gpa +
1039                         sizeof(*shadow_ring_context),
1040                         (void *)shadow_ring_context +
1041                         sizeof(*shadow_ring_context),
1042                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
1043 }
1044
1045 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
1046                                 intel_engine_mask_t engine_mask)
1047 {
1048         struct intel_vgpu_submission *s = &vgpu->submission;
1049         struct intel_engine_cs *engine;
1050         struct intel_vgpu_workload *pos, *n;
1051         intel_engine_mask_t tmp;
1052
1053         /* free the unsubmited workloads in the queues. */
1054         for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
1055                 list_for_each_entry_safe(pos, n,
1056                         &s->workload_q_head[engine->id], list) {
1057                         list_del_init(&pos->list);
1058                         intel_vgpu_destroy_workload(pos);
1059                 }
1060                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
1061         }
1062 }
1063
1064 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
1065 {
1066         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1067         struct intel_vgpu_workload *workload =
1068                 scheduler->current_workload[ring_id];
1069         struct intel_vgpu *vgpu = workload->vgpu;
1070         struct intel_vgpu_submission *s = &vgpu->submission;
1071         struct i915_request *rq = workload->req;
1072         int event;
1073
1074         mutex_lock(&vgpu->vgpu_lock);
1075         mutex_lock(&gvt->sched_lock);
1076
1077         /* For the workload w/ request, needs to wait for the context
1078          * switch to make sure request is completed.
1079          * For the workload w/o request, directly complete the workload.
1080          */
1081         if (rq) {
1082                 wait_event(workload->shadow_ctx_status_wq,
1083                            !atomic_read(&workload->shadow_ctx_active));
1084
1085                 /* If this request caused GPU hang, req->fence.error will
1086                  * be set to -EIO. Use -EIO to set workload status so
1087                  * that when this request caused GPU hang, didn't trigger
1088                  * context switch interrupt to guest.
1089                  */
1090                 if (likely(workload->status == -EINPROGRESS)) {
1091                         if (workload->req->fence.error == -EIO)
1092                                 workload->status = -EIO;
1093                         else
1094                                 workload->status = 0;
1095                 }
1096
1097                 if (!workload->status &&
1098                     !(vgpu->resetting_eng & BIT(ring_id))) {
1099                         update_guest_context(workload);
1100
1101                         for_each_set_bit(event, workload->pending_events,
1102                                          INTEL_GVT_EVENT_MAX)
1103                                 intel_vgpu_trigger_virtual_event(vgpu, event);
1104                 }
1105
1106                 i915_request_put(fetch_and_zero(&workload->req));
1107         }
1108
1109         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
1110                         ring_id, workload, workload->status);
1111
1112         scheduler->current_workload[ring_id] = NULL;
1113
1114         list_del_init(&workload->list);
1115
1116         if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
1117                 /* if workload->status is not successful means HW GPU
1118                  * has occurred GPU hang or something wrong with i915/GVT,
1119                  * and GVT won't inject context switch interrupt to guest.
1120                  * So this error is a vGPU hang actually to the guest.
1121                  * According to this we should emunlate a vGPU hang. If
1122                  * there are pending workloads which are already submitted
1123                  * from guest, we should clean them up like HW GPU does.
1124                  *
1125                  * if it is in middle of engine resetting, the pending
1126                  * workloads won't be submitted to HW GPU and will be
1127                  * cleaned up during the resetting process later, so doing
1128                  * the workload clean up here doesn't have any impact.
1129                  **/
1130                 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
1131         }
1132
1133         workload->complete(workload);
1134
1135         intel_vgpu_shadow_mm_unpin(workload);
1136         intel_vgpu_destroy_workload(workload);
1137
1138         atomic_dec(&s->running_workload_num);
1139         wake_up(&scheduler->workload_complete_wq);
1140
1141         if (gvt->scheduler.need_reschedule)
1142                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
1143
1144         mutex_unlock(&gvt->sched_lock);
1145         mutex_unlock(&vgpu->vgpu_lock);
1146 }
1147
1148 static int workload_thread(void *arg)
1149 {
1150         struct intel_engine_cs *engine = arg;
1151         const bool need_force_wake = GRAPHICS_VER(engine->i915) >= 9;
1152         struct intel_gvt *gvt = engine->i915->gvt;
1153         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1154         struct intel_vgpu_workload *workload = NULL;
1155         struct intel_vgpu *vgpu = NULL;
1156         int ret;
1157         DEFINE_WAIT_FUNC(wait, woken_wake_function);
1158
1159         gvt_dbg_core("workload thread for ring %s started\n", engine->name);
1160
1161         while (!kthread_should_stop()) {
1162                 intel_wakeref_t wakeref;
1163
1164                 add_wait_queue(&scheduler->waitq[engine->id], &wait);
1165                 do {
1166                         workload = pick_next_workload(gvt, engine);
1167                         if (workload)
1168                                 break;
1169                         wait_woken(&wait, TASK_INTERRUPTIBLE,
1170                                    MAX_SCHEDULE_TIMEOUT);
1171                 } while (!kthread_should_stop());
1172                 remove_wait_queue(&scheduler->waitq[engine->id], &wait);
1173
1174                 if (!workload)
1175                         break;
1176
1177                 gvt_dbg_sched("ring %s next workload %p vgpu %d\n",
1178                               engine->name, workload,
1179                               workload->vgpu->id);
1180
1181                 wakeref = intel_runtime_pm_get(engine->uncore->rpm);
1182
1183                 gvt_dbg_sched("ring %s will dispatch workload %p\n",
1184                               engine->name, workload);
1185
1186                 if (need_force_wake)
1187                         intel_uncore_forcewake_get(engine->uncore,
1188                                                    FORCEWAKE_ALL);
1189                 /*
1190                  * Update the vReg of the vGPU which submitted this
1191                  * workload. The vGPU may use these registers for checking
1192                  * the context state. The value comes from GPU commands
1193                  * in this workload.
1194                  */
1195                 update_vreg_in_ctx(workload);
1196
1197                 ret = dispatch_workload(workload);
1198
1199                 if (ret) {
1200                         vgpu = workload->vgpu;
1201                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1202                         goto complete;
1203                 }
1204
1205                 gvt_dbg_sched("ring %s wait workload %p\n",
1206                               engine->name, workload);
1207                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1208
1209 complete:
1210                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1211                               workload, workload->status);
1212
1213                 complete_current_workload(gvt, engine->id);
1214
1215                 if (need_force_wake)
1216                         intel_uncore_forcewake_put(engine->uncore,
1217                                                    FORCEWAKE_ALL);
1218
1219                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1220                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1221                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1222         }
1223         return 0;
1224 }
1225
1226 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1227 {
1228         struct intel_vgpu_submission *s = &vgpu->submission;
1229         struct intel_gvt *gvt = vgpu->gvt;
1230         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1231
1232         if (atomic_read(&s->running_workload_num)) {
1233                 gvt_dbg_sched("wait vgpu idle\n");
1234
1235                 wait_event(scheduler->workload_complete_wq,
1236                                 !atomic_read(&s->running_workload_num));
1237         }
1238 }
1239
1240 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1241 {
1242         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1243         struct intel_engine_cs *engine;
1244         enum intel_engine_id i;
1245
1246         gvt_dbg_core("clean workload scheduler\n");
1247
1248         for_each_engine(engine, gvt->gt, i) {
1249                 atomic_notifier_chain_unregister(
1250                                         &engine->context_status_notifier,
1251                                         &gvt->shadow_ctx_notifier_block[i]);
1252                 kthread_stop(scheduler->thread[i]);
1253         }
1254 }
1255
1256 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1257 {
1258         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1259         struct intel_engine_cs *engine;
1260         enum intel_engine_id i;
1261         int ret;
1262
1263         gvt_dbg_core("init workload scheduler\n");
1264
1265         init_waitqueue_head(&scheduler->workload_complete_wq);
1266
1267         for_each_engine(engine, gvt->gt, i) {
1268                 init_waitqueue_head(&scheduler->waitq[i]);
1269
1270                 scheduler->thread[i] = kthread_run(workload_thread, engine,
1271                                                    "gvt:%s", engine->name);
1272                 if (IS_ERR(scheduler->thread[i])) {
1273                         gvt_err("fail to create workload thread\n");
1274                         ret = PTR_ERR(scheduler->thread[i]);
1275                         goto err;
1276                 }
1277
1278                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1279                                         shadow_context_status_change;
1280                 atomic_notifier_chain_register(&engine->context_status_notifier,
1281                                         &gvt->shadow_ctx_notifier_block[i]);
1282         }
1283
1284         return 0;
1285
1286 err:
1287         intel_gvt_clean_workload_scheduler(gvt);
1288         return ret;
1289 }
1290
1291 static void
1292 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1293                                 struct i915_ppgtt *ppgtt)
1294 {
1295         int i;
1296
1297         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1298                 set_dma_address(ppgtt->pd, s->i915_context_pml4);
1299         } else {
1300                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1301                         struct i915_page_directory * const pd =
1302                                 i915_pd_entry(ppgtt->pd, i);
1303
1304                         set_dma_address(pd, s->i915_context_pdps[i]);
1305                 }
1306         }
1307 }
1308
1309 /**
1310  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1311  * @vgpu: a vGPU
1312  *
1313  * This function is called when a vGPU is being destroyed.
1314  *
1315  */
1316 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1317 {
1318         struct intel_vgpu_submission *s = &vgpu->submission;
1319         struct intel_engine_cs *engine;
1320         enum intel_engine_id id;
1321
1322         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1323
1324         i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1325         for_each_engine(engine, vgpu->gvt->gt, id)
1326                 intel_context_put(s->shadow[id]);
1327
1328         kmem_cache_destroy(s->workloads);
1329 }
1330
1331
1332 /**
1333  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1334  * @vgpu: a vGPU
1335  * @engine_mask: engines expected to be reset
1336  *
1337  * This function is called when a vGPU is being destroyed.
1338  *
1339  */
1340 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1341                                  intel_engine_mask_t engine_mask)
1342 {
1343         struct intel_vgpu_submission *s = &vgpu->submission;
1344
1345         if (!s->active)
1346                 return;
1347
1348         intel_vgpu_clean_workloads(vgpu, engine_mask);
1349         s->ops->reset(vgpu, engine_mask);
1350 }
1351
1352 static void
1353 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1354                              struct i915_ppgtt *ppgtt)
1355 {
1356         int i;
1357
1358         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1359                 s->i915_context_pml4 = px_dma(ppgtt->pd);
1360         } else {
1361                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1362                         struct i915_page_directory * const pd =
1363                                 i915_pd_entry(ppgtt->pd, i);
1364
1365                         s->i915_context_pdps[i] = px_dma(pd);
1366                 }
1367         }
1368 }
1369
1370 /**
1371  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1372  * @vgpu: a vGPU
1373  *
1374  * This function is called when a vGPU is being created.
1375  *
1376  * Returns:
1377  * Zero on success, negative error code if failed.
1378  *
1379  */
1380 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1381 {
1382         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1383         struct intel_vgpu_submission *s = &vgpu->submission;
1384         struct intel_engine_cs *engine;
1385         struct i915_ppgtt *ppgtt;
1386         enum intel_engine_id i;
1387         int ret;
1388
1389         ppgtt = i915_ppgtt_create(&i915->gt);
1390         if (IS_ERR(ppgtt))
1391                 return PTR_ERR(ppgtt);
1392
1393         i915_context_ppgtt_root_save(s, ppgtt);
1394
1395         for_each_engine(engine, vgpu->gvt->gt, i) {
1396                 struct intel_context *ce;
1397
1398                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1399                 s->shadow[i] = ERR_PTR(-EINVAL);
1400
1401                 ce = intel_context_create(engine);
1402                 if (IS_ERR(ce)) {
1403                         ret = PTR_ERR(ce);
1404                         goto out_shadow_ctx;
1405                 }
1406
1407                 i915_vm_put(ce->vm);
1408                 ce->vm = i915_vm_get(&ppgtt->vm);
1409                 intel_context_set_single_submission(ce);
1410
1411                 /* Max ring buffer size */
1412                 if (!intel_uc_wants_guc_submission(&engine->gt->uc))
1413                         ce->ring_size = SZ_2M;
1414
1415                 s->shadow[i] = ce;
1416         }
1417
1418         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1419
1420         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1421                                                   sizeof(struct intel_vgpu_workload), 0,
1422                                                   SLAB_HWCACHE_ALIGN,
1423                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1424                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1425                                                   NULL);
1426
1427         if (!s->workloads) {
1428                 ret = -ENOMEM;
1429                 goto out_shadow_ctx;
1430         }
1431
1432         atomic_set(&s->running_workload_num, 0);
1433         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1434
1435         memset(s->last_ctx, 0, sizeof(s->last_ctx));
1436
1437         i915_vm_put(&ppgtt->vm);
1438         return 0;
1439
1440 out_shadow_ctx:
1441         i915_context_ppgtt_root_restore(s, ppgtt);
1442         for_each_engine(engine, vgpu->gvt->gt, i) {
1443                 if (IS_ERR(s->shadow[i]))
1444                         break;
1445
1446                 intel_context_put(s->shadow[i]);
1447         }
1448         i915_vm_put(&ppgtt->vm);
1449         return ret;
1450 }
1451
1452 /**
1453  * intel_vgpu_select_submission_ops - select virtual submission interface
1454  * @vgpu: a vGPU
1455  * @engine_mask: either ALL_ENGINES or target engine mask
1456  * @interface: expected vGPU virtual submission interface
1457  *
1458  * This function is called when guest configures submission interface.
1459  *
1460  * Returns:
1461  * Zero on success, negative error code if failed.
1462  *
1463  */
1464 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1465                                      intel_engine_mask_t engine_mask,
1466                                      unsigned int interface)
1467 {
1468         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1469         struct intel_vgpu_submission *s = &vgpu->submission;
1470         const struct intel_vgpu_submission_ops *ops[] = {
1471                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1472                         &intel_vgpu_execlist_submission_ops,
1473         };
1474         int ret;
1475
1476         if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
1477                 return -EINVAL;
1478
1479         if (drm_WARN_ON(&i915->drm,
1480                         interface == 0 && engine_mask != ALL_ENGINES))
1481                 return -EINVAL;
1482
1483         if (s->active)
1484                 s->ops->clean(vgpu, engine_mask);
1485
1486         if (interface == 0) {
1487                 s->ops = NULL;
1488                 s->virtual_submission_interface = 0;
1489                 s->active = false;
1490                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1491                 return 0;
1492         }
1493
1494         ret = ops[interface]->init(vgpu, engine_mask);
1495         if (ret)
1496                 return ret;
1497
1498         s->ops = ops[interface];
1499         s->virtual_submission_interface = interface;
1500         s->active = true;
1501
1502         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1503                         vgpu->id, s->ops->name);
1504
1505         return 0;
1506 }
1507
1508 /**
1509  * intel_vgpu_destroy_workload - destroy a vGPU workload
1510  * @workload: workload to destroy
1511  *
1512  * This function is called when destroy a vGPU workload.
1513  *
1514  */
1515 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1516 {
1517         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1518
1519         intel_context_unpin(s->shadow[workload->engine->id]);
1520         release_shadow_batch_buffer(workload);
1521         release_shadow_wa_ctx(&workload->wa_ctx);
1522
1523         if (!list_empty(&workload->lri_shadow_mm)) {
1524                 struct intel_vgpu_mm *m, *mm;
1525                 list_for_each_entry_safe(m, mm, &workload->lri_shadow_mm,
1526                                          ppgtt_mm.link) {
1527                         list_del(&m->ppgtt_mm.link);
1528                         intel_vgpu_mm_put(m);
1529                 }
1530         }
1531
1532         GEM_BUG_ON(!list_empty(&workload->lri_shadow_mm));
1533         if (workload->shadow_mm)
1534                 intel_vgpu_mm_put(workload->shadow_mm);
1535
1536         kmem_cache_free(s->workloads, workload);
1537 }
1538
1539 static struct intel_vgpu_workload *
1540 alloc_workload(struct intel_vgpu *vgpu)
1541 {
1542         struct intel_vgpu_submission *s = &vgpu->submission;
1543         struct intel_vgpu_workload *workload;
1544
1545         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1546         if (!workload)
1547                 return ERR_PTR(-ENOMEM);
1548
1549         INIT_LIST_HEAD(&workload->list);
1550         INIT_LIST_HEAD(&workload->shadow_bb);
1551         INIT_LIST_HEAD(&workload->lri_shadow_mm);
1552
1553         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1554         atomic_set(&workload->shadow_ctx_active, 0);
1555
1556         workload->status = -EINPROGRESS;
1557         workload->vgpu = vgpu;
1558
1559         return workload;
1560 }
1561
1562 #define RING_CTX_OFF(x) \
1563         offsetof(struct execlist_ring_context, x)
1564
1565 static void read_guest_pdps(struct intel_vgpu *vgpu,
1566                 u64 ring_context_gpa, u32 pdp[8])
1567 {
1568         u64 gpa;
1569         int i;
1570
1571         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1572
1573         for (i = 0; i < 8; i++)
1574                 intel_gvt_hypervisor_read_gpa(vgpu,
1575                                 gpa + i * 8, &pdp[7 - i], 4);
1576 }
1577
1578 static int prepare_mm(struct intel_vgpu_workload *workload)
1579 {
1580         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1581         struct intel_vgpu_mm *mm;
1582         struct intel_vgpu *vgpu = workload->vgpu;
1583         enum intel_gvt_gtt_type root_entry_type;
1584         u64 pdps[GVT_RING_CTX_NR_PDPS];
1585
1586         switch (desc->addressing_mode) {
1587         case 1: /* legacy 32-bit */
1588                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1589                 break;
1590         case 3: /* legacy 64-bit */
1591                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1592                 break;
1593         default:
1594                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1595                 return -EINVAL;
1596         }
1597
1598         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1599
1600         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1601         if (IS_ERR(mm))
1602                 return PTR_ERR(mm);
1603
1604         workload->shadow_mm = mm;
1605         return 0;
1606 }
1607
1608 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1609                 ((a)->lrca == (b)->lrca))
1610
1611 /**
1612  * intel_vgpu_create_workload - create a vGPU workload
1613  * @vgpu: a vGPU
1614  * @engine: the engine
1615  * @desc: a guest context descriptor
1616  *
1617  * This function is called when creating a vGPU workload.
1618  *
1619  * Returns:
1620  * struct intel_vgpu_workload * on success, negative error code in
1621  * pointer if failed.
1622  *
1623  */
1624 struct intel_vgpu_workload *
1625 intel_vgpu_create_workload(struct intel_vgpu *vgpu,
1626                            const struct intel_engine_cs *engine,
1627                            struct execlist_ctx_descriptor_format *desc)
1628 {
1629         struct intel_vgpu_submission *s = &vgpu->submission;
1630         struct list_head *q = workload_q_head(vgpu, engine);
1631         struct intel_vgpu_workload *last_workload = NULL;
1632         struct intel_vgpu_workload *workload = NULL;
1633         u64 ring_context_gpa;
1634         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1635         u32 guest_head;
1636         int ret;
1637
1638         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1639                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1640         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1641                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1642                 return ERR_PTR(-EINVAL);
1643         }
1644
1645         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1646                         RING_CTX_OFF(ring_header.val), &head, 4);
1647
1648         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1649                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1650
1651         guest_head = head;
1652
1653         head &= RB_HEAD_OFF_MASK;
1654         tail &= RB_TAIL_OFF_MASK;
1655
1656         list_for_each_entry_reverse(last_workload, q, list) {
1657
1658                 if (same_context(&last_workload->ctx_desc, desc)) {
1659                         gvt_dbg_el("ring %s cur workload == last\n",
1660                                    engine->name);
1661                         gvt_dbg_el("ctx head %x real head %lx\n", head,
1662                                    last_workload->rb_tail);
1663                         /*
1664                          * cannot use guest context head pointer here,
1665                          * as it might not be updated at this time
1666                          */
1667                         head = last_workload->rb_tail;
1668                         break;
1669                 }
1670         }
1671
1672         gvt_dbg_el("ring %s begin a new workload\n", engine->name);
1673
1674         /* record some ring buffer register values for scan and shadow */
1675         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1676                         RING_CTX_OFF(rb_start.val), &start, 4);
1677         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1678                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1679         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1680                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1681
1682         if (!intel_gvt_ggtt_validate_range(vgpu, start,
1683                                 _RING_CTL_BUF_SIZE(ctl))) {
1684                 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1685                 return ERR_PTR(-EINVAL);
1686         }
1687
1688         workload = alloc_workload(vgpu);
1689         if (IS_ERR(workload))
1690                 return workload;
1691
1692         workload->engine = engine;
1693         workload->ctx_desc = *desc;
1694         workload->ring_context_gpa = ring_context_gpa;
1695         workload->rb_head = head;
1696         workload->guest_rb_head = guest_head;
1697         workload->rb_tail = tail;
1698         workload->rb_start = start;
1699         workload->rb_ctl = ctl;
1700
1701         if (engine->id == RCS0) {
1702                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1703                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1704                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1705                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1706
1707                 workload->wa_ctx.indirect_ctx.guest_gma =
1708                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1709                 workload->wa_ctx.indirect_ctx.size =
1710                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1711                         CACHELINE_BYTES;
1712
1713                 if (workload->wa_ctx.indirect_ctx.size != 0) {
1714                         if (!intel_gvt_ggtt_validate_range(vgpu,
1715                                 workload->wa_ctx.indirect_ctx.guest_gma,
1716                                 workload->wa_ctx.indirect_ctx.size)) {
1717                                 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1718                                     workload->wa_ctx.indirect_ctx.guest_gma);
1719                                 kmem_cache_free(s->workloads, workload);
1720                                 return ERR_PTR(-EINVAL);
1721                         }
1722                 }
1723
1724                 workload->wa_ctx.per_ctx.guest_gma =
1725                         per_ctx & PER_CTX_ADDR_MASK;
1726                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1727                 if (workload->wa_ctx.per_ctx.valid) {
1728                         if (!intel_gvt_ggtt_validate_range(vgpu,
1729                                 workload->wa_ctx.per_ctx.guest_gma,
1730                                 CACHELINE_BYTES)) {
1731                                 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1732                                         workload->wa_ctx.per_ctx.guest_gma);
1733                                 kmem_cache_free(s->workloads, workload);
1734                                 return ERR_PTR(-EINVAL);
1735                         }
1736                 }
1737         }
1738
1739         gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n",
1740                    workload, engine->name, head, tail, start, ctl);
1741
1742         ret = prepare_mm(workload);
1743         if (ret) {
1744                 kmem_cache_free(s->workloads, workload);
1745                 return ERR_PTR(ret);
1746         }
1747
1748         /* Only scan and shadow the first workload in the queue
1749          * as there is only one pre-allocated buf-obj for shadow.
1750          */
1751         if (list_empty(q)) {
1752                 intel_wakeref_t wakeref;
1753
1754                 with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)
1755                         ret = intel_gvt_scan_and_shadow_workload(workload);
1756         }
1757
1758         if (ret) {
1759                 if (vgpu_is_vm_unhealthy(ret))
1760                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1761                 intel_vgpu_destroy_workload(workload);
1762                 return ERR_PTR(ret);
1763         }
1764
1765         ret = intel_context_pin(s->shadow[engine->id]);
1766         if (ret) {
1767                 intel_vgpu_destroy_workload(workload);
1768                 return ERR_PTR(ret);
1769         }
1770
1771         return workload;
1772 }
1773
1774 /**
1775  * intel_vgpu_queue_workload - Qeue a vGPU workload
1776  * @workload: the workload to queue in
1777  */
1778 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1779 {
1780         list_add_tail(&workload->list,
1781                       workload_q_head(workload->vgpu, workload->engine));
1782         intel_gvt_kick_schedule(workload->vgpu->gvt);
1783         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);
1784 }