drivers/gpu/drm/i915/gvt/gtt.c

   1 /*
   2  * GTT virtualization
   3  *
   4  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Zhi Wang <zhi.a.wang@intel.com>
  27  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  28  *    Xiao Zheng <xiao.zheng@intel.com>
  29  *
  30  * Contributors:
  31  *    Min He <min.he@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gvt.h"
  38 #include "i915_pvinfo.h"
  39 #include "trace.h"
  40
  41 #include "gt/intel_gt_regs.h"
  42
  43 #if defined(VERBOSE_DEBUG)
  44 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
  45 #else
  46 #define gvt_vdbg_mm(fmt, args...)
  47 #endif
  48
  49 static bool enable_out_of_sync = false;
  50 static int preallocated_oos_pages = 8192;
  51
  52 /*
  53  * validate a gm address and related range size,
  54  * translate it to host gm address
  55  */
  56 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
  57 {
  58         if (size == 0)
  59                 return vgpu_gmadr_is_valid(vgpu, addr);
  60
  61         if (vgpu_gmadr_is_aperture(vgpu, addr) &&
  62             vgpu_gmadr_is_aperture(vgpu, addr + size - 1))
  63                 return true;
  64         else if (vgpu_gmadr_is_hidden(vgpu, addr) &&
  65                  vgpu_gmadr_is_hidden(vgpu, addr + size - 1))
  66                 return true;
  67
  68         gvt_dbg_mm("Invalid ggtt range at 0x%llx, size: 0x%x\n",
  69                      addr, size);
  70         return false;
  71 }
  72
  73 /* translate a guest gmadr to host gmadr */
  74 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
  75 {
  76         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
  77
  78         if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
  79                      "invalid guest gmadr %llx\n", g_addr))
  80                 return -EACCES;
  81
  82         if (vgpu_gmadr_is_aperture(vgpu, g_addr))
  83                 *h_addr = vgpu_aperture_gmadr_base(vgpu)
  84                           + (g_addr - vgpu_aperture_offset(vgpu));
  85         else
  86                 *h_addr = vgpu_hidden_gmadr_base(vgpu)
  87                           + (g_addr - vgpu_hidden_offset(vgpu));
  88         return 0;
  89 }
  90
  91 /* translate a host gmadr to guest gmadr */
  92 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
  93 {
  94         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
  95
  96         if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
  97                      "invalid host gmadr %llx\n", h_addr))
  98                 return -EACCES;
  99
 100         if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
 101                 *g_addr = vgpu_aperture_gmadr_base(vgpu)
 102                         + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
 103         else
 104                 *g_addr = vgpu_hidden_gmadr_base(vgpu)
 105                         + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
 106         return 0;
 107 }
 108
 109 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
 110                              unsigned long *h_index)
 111 {
 112         u64 h_addr;
 113         int ret;
 114
 115         ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
 116                                        &h_addr);
 117         if (ret)
 118                 return ret;
 119
 120         *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
 121         return 0;
 122 }
 123
 124 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
 125                              unsigned long *g_index)
 126 {
 127         u64 g_addr;
 128         int ret;
 129
 130         ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
 131                                        &g_addr);
 132         if (ret)
 133                 return ret;
 134
 135         *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
 136         return 0;
 137 }
 138
 139 #define gtt_type_is_entry(type) \
 140         (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
 141          && type != GTT_TYPE_PPGTT_PTE_ENTRY \
 142          && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
 143
 144 #define gtt_type_is_pt(type) \
 145         (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
 146
 147 #define gtt_type_is_pte_pt(type) \
 148         (type == GTT_TYPE_PPGTT_PTE_PT)
 149
 150 #define gtt_type_is_root_pointer(type) \
 151         (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
 152
 153 #define gtt_init_entry(e, t, p, v) do { \
 154         (e)->type = t; \
 155         (e)->pdev = p; \
 156         memcpy(&(e)->val64, &v, sizeof(v)); \
 157 } while (0)
 158
 159 /*
 160  * Mappings between GTT_TYPE* enumerations.
 161  * Following information can be found according to the given type:
 162  * - type of next level page table
 163  * - type of entry inside this level page table
 164  * - type of entry with PSE set
 165  *
 166  * If the given type doesn't have such a kind of information,
 167  * e.g. give a l4 root entry type, then request to get its PSE type,
 168  * give a PTE page table type, then request to get its next level page
 169  * table type, as we know l4 root entry doesn't have a PSE bit,
 170  * and a PTE page table doesn't have a next level page table type,
 171  * GTT_TYPE_INVALID will be returned. This is useful when traversing a
 172  * page table.
 173  */
 174
 175 struct gtt_type_table_entry {
 176         int entry_type;
 177         int pt_type;
 178         int next_pt_type;
 179         int pse_entry_type;
 180 };
 181
 182 #define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
 183         [type] = { \
 184                 .entry_type = e_type, \
 185                 .pt_type = cpt_type, \
 186                 .next_pt_type = npt_type, \
 187                 .pse_entry_type = pse_type, \
 188         }
 189
 190 static const struct gtt_type_table_entry gtt_type_table[] = {
 191         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
 192                         GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
 193                         GTT_TYPE_INVALID,
 194                         GTT_TYPE_PPGTT_PML4_PT,
 195                         GTT_TYPE_INVALID),
 196         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
 197                         GTT_TYPE_PPGTT_PML4_ENTRY,
 198                         GTT_TYPE_PPGTT_PML4_PT,
 199                         GTT_TYPE_PPGTT_PDP_PT,
 200                         GTT_TYPE_INVALID),
 201         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
 202                         GTT_TYPE_PPGTT_PML4_ENTRY,
 203                         GTT_TYPE_PPGTT_PML4_PT,
 204                         GTT_TYPE_PPGTT_PDP_PT,
 205                         GTT_TYPE_INVALID),
 206         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
 207                         GTT_TYPE_PPGTT_PDP_ENTRY,
 208                         GTT_TYPE_PPGTT_PDP_PT,
 209                         GTT_TYPE_PPGTT_PDE_PT,
 210                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 211         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
 212                         GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
 213                         GTT_TYPE_INVALID,
 214                         GTT_TYPE_PPGTT_PDE_PT,
 215                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 216         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
 217                         GTT_TYPE_PPGTT_PDP_ENTRY,
 218                         GTT_TYPE_PPGTT_PDP_PT,
 219                         GTT_TYPE_PPGTT_PDE_PT,
 220                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 221         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
 222                         GTT_TYPE_PPGTT_PDE_ENTRY,
 223                         GTT_TYPE_PPGTT_PDE_PT,
 224                         GTT_TYPE_PPGTT_PTE_PT,
 225                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 226         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
 227                         GTT_TYPE_PPGTT_PDE_ENTRY,
 228                         GTT_TYPE_PPGTT_PDE_PT,
 229                         GTT_TYPE_PPGTT_PTE_PT,
 230                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 231         /* We take IPS bit as 'PSE' for PTE level. */
 232         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
 233                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 234                         GTT_TYPE_PPGTT_PTE_PT,
 235                         GTT_TYPE_INVALID,
 236                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 237         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 238                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 239                         GTT_TYPE_PPGTT_PTE_PT,
 240                         GTT_TYPE_INVALID,
 241                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 242         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
 243                         GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 244                         GTT_TYPE_PPGTT_PTE_PT,
 245                         GTT_TYPE_INVALID,
 246                         GTT_TYPE_PPGTT_PTE_64K_ENTRY),
 247         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
 248                         GTT_TYPE_PPGTT_PDE_ENTRY,
 249                         GTT_TYPE_PPGTT_PDE_PT,
 250                         GTT_TYPE_INVALID,
 251                         GTT_TYPE_PPGTT_PTE_2M_ENTRY),
 252         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
 253                         GTT_TYPE_PPGTT_PDP_ENTRY,
 254                         GTT_TYPE_PPGTT_PDP_PT,
 255                         GTT_TYPE_INVALID,
 256                         GTT_TYPE_PPGTT_PTE_1G_ENTRY),
 257         GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
 258                         GTT_TYPE_GGTT_PTE,
 259                         GTT_TYPE_INVALID,
 260                         GTT_TYPE_INVALID,
 261                         GTT_TYPE_INVALID),
 262 };
 263
 264 static inline int get_next_pt_type(int type)
 265 {
 266         return gtt_type_table[type].next_pt_type;
 267 }
 268
 269 static inline int get_entry_type(int type)
 270 {
 271         return gtt_type_table[type].entry_type;
 272 }
 273
 274 static inline int get_pse_type(int type)
 275 {
 276         return gtt_type_table[type].pse_entry_type;
 277 }
 278
 279 static u64 read_pte64(struct i915_ggtt *ggtt, unsigned long index)
 280 {
 281         void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
 282
 283         return readq(addr);
 284 }
 285
 286 static void ggtt_invalidate(struct intel_gt *gt)
 287 {
 288         mmio_hw_access_pre(gt);
 289         intel_uncore_write(gt->uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 290         mmio_hw_access_post(gt);
 291 }
 292
 293 static void write_pte64(struct i915_ggtt *ggtt, unsigned long index, u64 pte)
 294 {
 295         void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
 296
 297         writeq(pte, addr);
 298 }
 299
 300 static inline int gtt_get_entry64(void *pt,
 301                 struct intel_gvt_gtt_entry *e,
 302                 unsigned long index, bool hypervisor_access, unsigned long gpa,
 303                 struct intel_vgpu *vgpu)
 304 {
 305         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 306         int ret;
 307
 308         if (WARN_ON(info->gtt_entry_size != 8))
 309                 return -EINVAL;
 310
 311         if (hypervisor_access) {
 312                 ret = intel_gvt_read_gpa(vgpu, gpa +
 313                                 (index << info->gtt_entry_size_shift),
 314                                 &e->val64, 8);
 315                 if (WARN_ON(ret))
 316                         return ret;
 317         } else if (!pt) {
 318                 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
 319         } else {
 320                 e->val64 = *((u64 *)pt + index);
 321         }
 322         return 0;
 323 }
 324
 325 static inline int gtt_set_entry64(void *pt,
 326                 struct intel_gvt_gtt_entry *e,
 327                 unsigned long index, bool hypervisor_access, unsigned long gpa,
 328                 struct intel_vgpu *vgpu)
 329 {
 330         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 331         int ret;
 332
 333         if (WARN_ON(info->gtt_entry_size != 8))
 334                 return -EINVAL;
 335
 336         if (hypervisor_access) {
 337                 ret = intel_gvt_write_gpa(vgpu, gpa +
 338                                 (index << info->gtt_entry_size_shift),
 339                                 &e->val64, 8);
 340                 if (WARN_ON(ret))
 341                         return ret;
 342         } else if (!pt) {
 343                 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
 344         } else {
 345                 *((u64 *)pt + index) = e->val64;
 346         }
 347         return 0;
 348 }
 349
 350 #define GTT_HAW 46
 351
 352 #define ADDR_1G_MASK    GENMASK_ULL(GTT_HAW - 1, 30)
 353 #define ADDR_2M_MASK    GENMASK_ULL(GTT_HAW - 1, 21)
 354 #define ADDR_64K_MASK   GENMASK_ULL(GTT_HAW - 1, 16)
 355 #define ADDR_4K_MASK    GENMASK_ULL(GTT_HAW - 1, 12)
 356
 357 #define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
 358 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
 359
 360 #define GTT_64K_PTE_STRIDE 16
 361
 362 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
 363 {
 364         unsigned long pfn;
 365
 366         if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
 367                 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
 368         else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
 369                 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
 370         else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
 371                 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
 372         else
 373                 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
 374         return pfn;
 375 }
 376
 377 static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
 378 {
 379         if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
 380                 e->val64 &= ~ADDR_1G_MASK;
 381                 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
 382         } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
 383                 e->val64 &= ~ADDR_2M_MASK;
 384                 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
 385         } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
 386                 e->val64 &= ~ADDR_64K_MASK;
 387                 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
 388         } else {
 389                 e->val64 &= ~ADDR_4K_MASK;
 390                 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
 391         }
 392
 393         e->val64 |= (pfn << PAGE_SHIFT);
 394 }
 395
 396 static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
 397 {
 398         return !!(e->val64 & _PAGE_PSE);
 399 }
 400
 401 static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
 402 {
 403         if (gen8_gtt_test_pse(e)) {
 404                 switch (e->type) {
 405                 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
 406                         e->val64 &= ~_PAGE_PSE;
 407                         e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
 408                         break;
 409                 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
 410                         e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
 411                         e->val64 &= ~_PAGE_PSE;
 412                         break;
 413                 default:
 414                         WARN_ON(1);
 415                 }
 416         }
 417 }
 418
 419 static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
 420 {
 421         if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
 422                 return false;
 423
 424         return !!(e->val64 & GEN8_PDE_IPS_64K);
 425 }
 426
 427 static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
 428 {
 429         if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
 430                 return;
 431
 432         e->val64 &= ~GEN8_PDE_IPS_64K;
 433 }
 434
 435 static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
 436 {
 437         /*
 438          * i915 writes PDP root pointer registers without present bit,
 439          * it also works, so we need to treat root pointer entry
 440          * specifically.
 441          */
 442         if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
 443                         || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
 444                 return (e->val64 != 0);
 445         else
 446                 return (e->val64 & GEN8_PAGE_PRESENT);
 447 }
 448
 449 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
 450 {
 451         e->val64 &= ~GEN8_PAGE_PRESENT;
 452 }
 453
 454 static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
 455 {
 456         e->val64 |= GEN8_PAGE_PRESENT;
 457 }
 458
 459 static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
 460 {
 461         return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
 462 }
 463
 464 static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
 465 {
 466         e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
 467 }
 468
 469 static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
 470 {
 471         e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
 472 }
 473
 474 /*
 475  * Per-platform GMA routines.
 476  */
 477 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
 478 {
 479         unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
 480
 481         trace_gma_index(__func__, gma, x);
 482         return x;
 483 }
 484
 485 #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
 486 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
 487 { \
 488         unsigned long x = (exp); \
 489         trace_gma_index(__func__, gma, x); \
 490         return x; \
 491 }
 492
 493 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
 494 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
 495 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
 496 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
 497 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
 498
 499 static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 500         .get_entry = gtt_get_entry64,
 501         .set_entry = gtt_set_entry64,
 502         .clear_present = gtt_entry_clear_present,
 503         .set_present = gtt_entry_set_present,
 504         .test_present = gen8_gtt_test_present,
 505         .test_pse = gen8_gtt_test_pse,
 506         .clear_pse = gen8_gtt_clear_pse,
 507         .clear_ips = gen8_gtt_clear_ips,
 508         .test_ips = gen8_gtt_test_ips,
 509         .clear_64k_splited = gen8_gtt_clear_64k_splited,
 510         .set_64k_splited = gen8_gtt_set_64k_splited,
 511         .test_64k_splited = gen8_gtt_test_64k_splited,
 512         .get_pfn = gen8_gtt_get_pfn,
 513         .set_pfn = gen8_gtt_set_pfn,
 514 };
 515
 516 static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
 517         .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
 518         .gma_to_pte_index = gen8_gma_to_pte_index,
 519         .gma_to_pde_index = gen8_gma_to_pde_index,
 520         .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
 521         .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
 522         .gma_to_pml4_index = gen8_gma_to_pml4_index,
 523 };
 524
 525 /* Update entry type per pse and ips bit. */
 526 static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops,
 527         struct intel_gvt_gtt_entry *entry, bool ips)
 528 {
 529         switch (entry->type) {
 530         case GTT_TYPE_PPGTT_PDE_ENTRY:
 531         case GTT_TYPE_PPGTT_PDP_ENTRY:
 532                 if (pte_ops->test_pse(entry))
 533                         entry->type = get_pse_type(entry->type);
 534                 break;
 535         case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
 536                 if (ips)
 537                         entry->type = get_pse_type(entry->type);
 538                 break;
 539         default:
 540                 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
 541         }
 542
 543         GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
 544 }
 545
 546 /*
 547  * MM helpers.
 548  */
 549 static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
 550                 struct intel_gvt_gtt_entry *entry, unsigned long index,
 551                 bool guest)
 552 {
 553         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 554
 555         GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
 556
 557         entry->type = mm->ppgtt_mm.root_entry_type;
 558         pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
 559                            mm->ppgtt_mm.shadow_pdps,
 560                            entry, index, false, 0, mm->vgpu);
 561         update_entry_type_for_real(pte_ops, entry, false);
 562 }
 563
 564 static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
 565                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 566 {
 567         _ppgtt_get_root_entry(mm, entry, index, true);
 568 }
 569
 570 static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
 571                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 572 {
 573         _ppgtt_get_root_entry(mm, entry, index, false);
 574 }
 575
 576 static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
 577                 struct intel_gvt_gtt_entry *entry, unsigned long index,
 578                 bool guest)
 579 {
 580         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 581
 582         pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
 583                            mm->ppgtt_mm.shadow_pdps,
 584                            entry, index, false, 0, mm->vgpu);
 585 }
 586
 587 static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
 588                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 589 {
 590         _ppgtt_set_root_entry(mm, entry, index, false);
 591 }
 592
 593 static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
 594                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 595 {
 596         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 597
 598         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 599
 600         entry->type = GTT_TYPE_GGTT_PTE;
 601         pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
 602                            false, 0, mm->vgpu);
 603 }
 604
 605 static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
 606                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 607 {
 608         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 609
 610         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 611
 612         pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
 613                            false, 0, mm->vgpu);
 614 }
 615
 616 static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
 617                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 618 {
 619         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 620
 621         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 622
 623         pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
 624 }
 625
 626 static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
 627                 struct intel_gvt_gtt_entry *entry, unsigned long index)
 628 {
 629         const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
 630         unsigned long offset = index;
 631
 632         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
 633
 634         if (vgpu_gmadr_is_aperture(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
 635                 offset -= (vgpu_aperture_gmadr_base(mm->vgpu) >> PAGE_SHIFT);
 636                 mm->ggtt_mm.host_ggtt_aperture[offset] = entry->val64;
 637         } else if (vgpu_gmadr_is_hidden(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
 638                 offset -= (vgpu_hidden_gmadr_base(mm->vgpu) >> PAGE_SHIFT);
 639                 mm->ggtt_mm.host_ggtt_hidden[offset] = entry->val64;
 640         }
 641
 642         pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
 643 }
 644
 645 /*
 646  * PPGTT shadow page table helpers.
 647  */
 648 static inline int ppgtt_spt_get_entry(
 649                 struct intel_vgpu_ppgtt_spt *spt,
 650                 void *page_table, int type,
 651                 struct intel_gvt_gtt_entry *e, unsigned long index,
 652                 bool guest)
 653 {
 654         struct intel_gvt *gvt = spt->vgpu->gvt;
 655         const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
 656         int ret;
 657
 658         e->type = get_entry_type(type);
 659
 660         if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
 661                 return -EINVAL;
 662
 663         ret = ops->get_entry(page_table, e, index, guest,
 664                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
 665                         spt->vgpu);
 666         if (ret)
 667                 return ret;
 668
 669         update_entry_type_for_real(ops, e, guest ?
 670                                    spt->guest_page.pde_ips : false);
 671
 672         gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
 673                     type, e->type, index, e->val64);
 674         return 0;
 675 }
 676
 677 static inline int ppgtt_spt_set_entry(
 678                 struct intel_vgpu_ppgtt_spt *spt,
 679                 void *page_table, int type,
 680                 struct intel_gvt_gtt_entry *e, unsigned long index,
 681                 bool guest)
 682 {
 683         struct intel_gvt *gvt = spt->vgpu->gvt;
 684         const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
 685
 686         if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
 687                 return -EINVAL;
 688
 689         gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
 690                     type, e->type, index, e->val64);
 691
 692         return ops->set_entry(page_table, e, index, guest,
 693                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
 694                         spt->vgpu);
 695 }
 696
 697 #define ppgtt_get_guest_entry(spt, e, index) \
 698         ppgtt_spt_get_entry(spt, NULL, \
 699                 spt->guest_page.type, e, index, true)
 700
 701 #define ppgtt_set_guest_entry(spt, e, index) \
 702         ppgtt_spt_set_entry(spt, NULL, \
 703                 spt->guest_page.type, e, index, true)
 704
 705 #define ppgtt_get_shadow_entry(spt, e, index) \
 706         ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
 707                 spt->shadow_page.type, e, index, false)
 708
 709 #define ppgtt_set_shadow_entry(spt, e, index) \
 710         ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
 711                 spt->shadow_page.type, e, index, false)
 712
 713 static void *alloc_spt(gfp_t gfp_mask)
 714 {
 715         struct intel_vgpu_ppgtt_spt *spt;
 716
 717         spt = kzalloc(sizeof(*spt), gfp_mask);
 718         if (!spt)
 719                 return NULL;
 720
 721         spt->shadow_page.page = alloc_page(gfp_mask);
 722         if (!spt->shadow_page.page) {
 723                 kfree(spt);
 724                 return NULL;
 725         }
 726         return spt;
 727 }
 728
 729 static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
 730 {
 731         __free_page(spt->shadow_page.page);
 732         kfree(spt);
 733 }
 734
 735 static int detach_oos_page(struct intel_vgpu *vgpu,
 736                 struct intel_vgpu_oos_page *oos_page);
 737
 738 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
 739 {
 740         struct device *kdev = spt->vgpu->gvt->gt->i915->drm.dev;
 741
 742         trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
 743
 744         dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
 745                        DMA_BIDIRECTIONAL);
 746
 747         radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
 748
 749         if (spt->guest_page.gfn) {
 750                 if (spt->guest_page.oos_page)
 751                         detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
 752
 753                 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
 754         }
 755
 756         list_del_init(&spt->post_shadow_list);
 757         free_spt(spt);
 758 }
 759
 760 static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
 761 {
 762         struct intel_vgpu_ppgtt_spt *spt, *spn;
 763         struct radix_tree_iter iter;
 764         LIST_HEAD(all_spt);
 765         void __rcu **slot;
 766
 767         rcu_read_lock();
 768         radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
 769                 spt = radix_tree_deref_slot(slot);
 770                 list_move(&spt->post_shadow_list, &all_spt);
 771         }
 772         rcu_read_unlock();
 773
 774         list_for_each_entry_safe(spt, spn, &all_spt, post_shadow_list)
 775                 ppgtt_free_spt(spt);
 776 }
 777
 778 static int ppgtt_handle_guest_write_page_table_bytes(
 779                 struct intel_vgpu_ppgtt_spt *spt,
 780                 u64 pa, void *p_data, int bytes);
 781
 782 static int ppgtt_write_protection_handler(
 783                 struct intel_vgpu_page_track *page_track,
 784                 u64 gpa, void *data, int bytes)
 785 {
 786         struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
 787
 788         int ret;
 789
 790         if (bytes != 4 && bytes != 8)
 791                 return -EINVAL;
 792
 793         ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
 794         if (ret)
 795                 return ret;
 796         return ret;
 797 }
 798
 799 /* Find a spt by guest gfn. */
 800 static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
 801                 struct intel_vgpu *vgpu, unsigned long gfn)
 802 {
 803         struct intel_vgpu_page_track *track;
 804
 805         track = intel_vgpu_find_page_track(vgpu, gfn);
 806         if (track && track->handler == ppgtt_write_protection_handler)
 807                 return track->priv_data;
 808
 809         return NULL;
 810 }
 811
 812 /* Find the spt by shadow page mfn. */
 813 static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
 814                 struct intel_vgpu *vgpu, unsigned long mfn)
 815 {
 816         return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
 817 }
 818
 819 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
 820
 821 /* Allocate shadow page table without guest page. */
 822 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
 823                 struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type)
 824 {
 825         struct device *kdev = vgpu->gvt->gt->i915->drm.dev;
 826         struct intel_vgpu_ppgtt_spt *spt = NULL;
 827         dma_addr_t daddr;
 828         int ret;
 829
 830 retry:
 831         spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
 832         if (!spt) {
 833                 if (reclaim_one_ppgtt_mm(vgpu->gvt))
 834                         goto retry;
 835
 836                 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
 837                 return ERR_PTR(-ENOMEM);
 838         }
 839
 840         spt->vgpu = vgpu;
 841         atomic_set(&spt->refcount, 1);
 842         INIT_LIST_HEAD(&spt->post_shadow_list);
 843
 844         /*
 845          * Init shadow_page.
 846          */
 847         spt->shadow_page.type = type;
 848         daddr = dma_map_page(kdev, spt->shadow_page.page,
 849                              0, 4096, DMA_BIDIRECTIONAL);
 850         if (dma_mapping_error(kdev, daddr)) {
 851                 gvt_vgpu_err("fail to map dma addr\n");
 852                 ret = -EINVAL;
 853                 goto err_free_spt;
 854         }
 855         spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
 856         spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
 857
 858         ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
 859         if (ret)
 860                 goto err_unmap_dma;
 861
 862         return spt;
 863
 864 err_unmap_dma:
 865         dma_unmap_page(kdev, daddr, PAGE_SIZE, DMA_BIDIRECTIONAL);
 866 err_free_spt:
 867         free_spt(spt);
 868         return ERR_PTR(ret);
 869 }
 870
 871 /* Allocate shadow page table associated with specific gfn. */
 872 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
 873                 struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type,
 874                 unsigned long gfn, bool guest_pde_ips)
 875 {
 876         struct intel_vgpu_ppgtt_spt *spt;
 877         int ret;
 878
 879         spt = ppgtt_alloc_spt(vgpu, type);
 880         if (IS_ERR(spt))
 881                 return spt;
 882
 883         /*
 884          * Init guest_page.
 885          */
 886         ret = intel_vgpu_register_page_track(vgpu, gfn,
 887                         ppgtt_write_protection_handler, spt);
 888         if (ret) {
 889                 ppgtt_free_spt(spt);
 890                 return ERR_PTR(ret);
 891         }
 892
 893         spt->guest_page.type = type;
 894         spt->guest_page.gfn = gfn;
 895         spt->guest_page.pde_ips = guest_pde_ips;
 896
 897         trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
 898
 899         return spt;
 900 }
 901
 902 #define pt_entry_size_shift(spt) \
 903         ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
 904
 905 #define pt_entries(spt) \
 906         (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
 907
 908 #define for_each_present_guest_entry(spt, e, i) \
 909         for (i = 0; i < pt_entries(spt); \
 910              i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 911                 if (!ppgtt_get_guest_entry(spt, e, i) && \
 912                     spt->vgpu->gvt->gtt.pte_ops->test_present(e))
 913
 914 #define for_each_present_shadow_entry(spt, e, i) \
 915         for (i = 0; i < pt_entries(spt); \
 916              i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 917                 if (!ppgtt_get_shadow_entry(spt, e, i) && \
 918                     spt->vgpu->gvt->gtt.pte_ops->test_present(e))
 919
 920 #define for_each_shadow_entry(spt, e, i) \
 921         for (i = 0; i < pt_entries(spt); \
 922              i += (spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1)) \
 923                 if (!ppgtt_get_shadow_entry(spt, e, i))
 924
 925 static inline void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
 926 {
 927         int v = atomic_read(&spt->refcount);
 928
 929         trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
 930         atomic_inc(&spt->refcount);
 931 }
 932
 933 static inline int ppgtt_put_spt(struct intel_vgpu_ppgtt_spt *spt)
 934 {
 935         int v = atomic_read(&spt->refcount);
 936
 937         trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
 938         return atomic_dec_return(&spt->refcount);
 939 }
 940
 941 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
 942
 943 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
 944                 struct intel_gvt_gtt_entry *e)
 945 {
 946         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
 947         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 948         struct intel_vgpu_ppgtt_spt *s;
 949         enum intel_gvt_gtt_type cur_pt_type;
 950
 951         GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
 952
 953         if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
 954                 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 955                 cur_pt_type = get_next_pt_type(e->type);
 956
 957                 if (!gtt_type_is_pt(cur_pt_type) ||
 958                                 !gtt_type_is_pt(cur_pt_type + 1)) {
 959                         drm_WARN(&i915->drm, 1,
 960                                  "Invalid page table type, cur_pt_type is: %d\n",
 961                                  cur_pt_type);
 962                         return -EINVAL;
 963                 }
 964
 965                 cur_pt_type += 1;
 966
 967                 if (ops->get_pfn(e) ==
 968                         vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
 969                         return 0;
 970         }
 971         s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
 972         if (!s) {
 973                 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
 974                                 ops->get_pfn(e));
 975                 return -ENXIO;
 976         }
 977         return ppgtt_invalidate_spt(s);
 978 }
 979
 980 static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
 981                 struct intel_gvt_gtt_entry *entry)
 982 {
 983         struct intel_vgpu *vgpu = spt->vgpu;
 984         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
 985         unsigned long pfn;
 986         int type;
 987
 988         pfn = ops->get_pfn(entry);
 989         type = spt->shadow_page.type;
 990
 991         /* Uninitialized spte or unshadowed spte. */
 992         if (!pfn || pfn == vgpu->gtt.scratch_pt[type].page_mfn)
 993                 return;
 994
 995         intel_gvt_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
 996 }
 997
 998 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
 999 {
1000         struct intel_vgpu *vgpu = spt->vgpu;
1001         struct intel_gvt_gtt_entry e;
1002         unsigned long index;
1003         int ret;
1004
1005         trace_spt_change(spt->vgpu->id, "die", spt,
1006                         spt->guest_page.gfn, spt->shadow_page.type);
1007
1008         if (ppgtt_put_spt(spt) > 0)
1009                 return 0;
1010
1011         for_each_present_shadow_entry(spt, &e, index) {
1012                 switch (e.type) {
1013                 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1014                         gvt_vdbg_mm("invalidate 4K entry\n");
1015                         ppgtt_invalidate_pte(spt, &e);
1016                         break;
1017                 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1018                         /* We don't setup 64K shadow entry so far. */
1019                         WARN(1, "suspicious 64K gtt entry\n");
1020                         continue;
1021                 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1022                         gvt_vdbg_mm("invalidate 2M entry\n");
1023                         continue;
1024                 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1025                         WARN(1, "GVT doesn't support 1GB page\n");
1026                         continue;
1027                 case GTT_TYPE_PPGTT_PML4_ENTRY:
1028                 case GTT_TYPE_PPGTT_PDP_ENTRY:
1029                 case GTT_TYPE_PPGTT_PDE_ENTRY:
1030                         gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
1031                         ret = ppgtt_invalidate_spt_by_shadow_entry(
1032                                         spt->vgpu, &e);
1033                         if (ret)
1034                                 goto fail;
1035                         break;
1036                 default:
1037                         GEM_BUG_ON(1);
1038                 }
1039         }
1040
1041         trace_spt_change(spt->vgpu->id, "release", spt,
1042                          spt->guest_page.gfn, spt->shadow_page.type);
1043         ppgtt_free_spt(spt);
1044         return 0;
1045 fail:
1046         gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1047                         spt, e.val64, e.type);
1048         return ret;
1049 }
1050
1051 static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
1052 {
1053         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1054
1055         if (GRAPHICS_VER(dev_priv) == 9) {
1056                 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
1057                         GAMW_ECO_ENABLE_64K_IPS_FIELD;
1058
1059                 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
1060         } else if (GRAPHICS_VER(dev_priv) >= 11) {
1061                 /* 64K paging only controlled by IPS bit in PTE now. */
1062                 return true;
1063         } else
1064                 return false;
1065 }
1066
1067 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
1068
1069 static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
1070                 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1071 {
1072         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1073         struct intel_vgpu_ppgtt_spt *spt = NULL;
1074         bool ips = false;
1075         int ret;
1076
1077         GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
1078
1079         if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1080                 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1081
1082         spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
1083         if (spt) {
1084                 ppgtt_get_spt(spt);
1085
1086                 if (ips != spt->guest_page.pde_ips) {
1087                         spt->guest_page.pde_ips = ips;
1088
1089                         gvt_dbg_mm("reshadow PDE since ips changed\n");
1090                         clear_page(spt->shadow_page.vaddr);
1091                         ret = ppgtt_populate_spt(spt);
1092                         if (ret) {
1093                                 ppgtt_put_spt(spt);
1094                                 goto err;
1095                         }
1096                 }
1097         } else {
1098                 int type = get_next_pt_type(we->type);
1099
1100                 if (!gtt_type_is_pt(type)) {
1101                         ret = -EINVAL;
1102                         goto err;
1103                 }
1104
1105                 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
1106                 if (IS_ERR(spt)) {
1107                         ret = PTR_ERR(spt);
1108                         goto err;
1109                 }
1110
1111                 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
1112                 if (ret)
1113                         goto err_free_spt;
1114
1115                 ret = ppgtt_populate_spt(spt);
1116                 if (ret)
1117                         goto err_free_spt;
1118
1119                 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1120                                  spt->shadow_page.type);
1121         }
1122         return spt;
1123
1124 err_free_spt:
1125         ppgtt_free_spt(spt);
1126         spt = NULL;
1127 err:
1128         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1129                      spt, we->val64, we->type);
1130         return ERR_PTR(ret);
1131 }
1132
1133 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1134                 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1135 {
1136         const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1137
1138         se->type = ge->type;
1139         se->val64 = ge->val64;
1140
1141         /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1142         if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1143                 ops->clear_ips(se);
1144
1145         ops->set_pfn(se, s->shadow_page.mfn);
1146 }
1147
1148 /*
1149  * Check if can do 2M page
1150  * @vgpu: target vgpu
1151  * @entry: target pfn's gtt entry
1152  *
1153  * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
1154  * negative if found err.
1155  */
1156 static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
1157         struct intel_gvt_gtt_entry *entry)
1158 {
1159         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1160         kvm_pfn_t pfn;
1161         int ret;
1162
1163         if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
1164                 return 0;
1165
1166         pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
1167         if (is_error_noslot_pfn(pfn))
1168                 return -EINVAL;
1169
1170         if (!pfn_valid(pfn))
1171                 return -EINVAL;
1172
1173         ret = PageTransHuge(pfn_to_page(pfn));
1174         kvm_release_pfn_clean(pfn);
1175         return ret;
1176 }
1177
1178 static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
1179         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1180         struct intel_gvt_gtt_entry *se)
1181 {
1182         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1183         struct intel_vgpu_ppgtt_spt *sub_spt;
1184         struct intel_gvt_gtt_entry sub_se;
1185         unsigned long start_gfn;
1186         dma_addr_t dma_addr;
1187         unsigned long sub_index;
1188         int ret;
1189
1190         gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1191
1192         start_gfn = ops->get_pfn(se);
1193
1194         sub_spt = ppgtt_alloc_spt(vgpu, GTT_TYPE_PPGTT_PTE_PT);
1195         if (IS_ERR(sub_spt))
1196                 return PTR_ERR(sub_spt);
1197
1198         for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
1199                 ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
1200                                                    PAGE_SIZE, &dma_addr);
1201                 if (ret)
1202                         goto err;
1203                 sub_se.val64 = se->val64;
1204
1205                 /* Copy the PAT field from PDE. */
1206                 sub_se.val64 &= ~_PAGE_PAT;
1207                 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5;
1208
1209                 ops->set_pfn(&sub_se, dma_addr >> PAGE_SHIFT);
1210                 ppgtt_set_shadow_entry(sub_spt, &sub_se, sub_index);
1211         }
1212
1213         /* Clear dirty field. */
1214         se->val64 &= ~_PAGE_DIRTY;
1215
1216         ops->clear_pse(se);
1217         ops->clear_ips(se);
1218         ops->set_pfn(se, sub_spt->shadow_page.mfn);
1219         ppgtt_set_shadow_entry(spt, se, index);
1220         return 0;
1221 err:
1222         /* Cancel the existing addess mappings of DMA addr. */
1223         for_each_present_shadow_entry(sub_spt, &sub_se, sub_index) {
1224                 gvt_vdbg_mm("invalidate 4K entry\n");
1225                 ppgtt_invalidate_pte(sub_spt, &sub_se);
1226         }
1227         /* Release the new allocated spt. */
1228         trace_spt_change(sub_spt->vgpu->id, "release", sub_spt,
1229                 sub_spt->guest_page.gfn, sub_spt->shadow_page.type);
1230         ppgtt_free_spt(sub_spt);
1231         return ret;
1232 }
1233
1234 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
1235         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1236         struct intel_gvt_gtt_entry *se)
1237 {
1238         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1239         struct intel_gvt_gtt_entry entry = *se;
1240         unsigned long start_gfn;
1241         dma_addr_t dma_addr;
1242         int i, ret;
1243
1244         gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1245
1246         GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1247
1248         start_gfn = ops->get_pfn(se);
1249
1250         entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1251         ops->set_64k_splited(&entry);
1252
1253         for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1254                 ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + i,
1255                                                    PAGE_SIZE, &dma_addr);
1256                 if (ret)
1257                         return ret;
1258
1259                 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1260                 ppgtt_set_shadow_entry(spt, &entry, index + i);
1261         }
1262         return 0;
1263 }
1264
1265 static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1266         struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1267         struct intel_gvt_gtt_entry *ge)
1268 {
1269         const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1270         struct intel_gvt_gtt_entry se = *ge;
1271         unsigned long gfn, page_size = PAGE_SIZE;
1272         dma_addr_t dma_addr;
1273         int ret;
1274
1275         if (!pte_ops->test_present(ge))
1276                 return 0;
1277
1278         gfn = pte_ops->get_pfn(ge);
1279
1280         switch (ge->type) {
1281         case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1282                 gvt_vdbg_mm("shadow 4K gtt entry\n");
1283                 break;
1284         case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1285                 gvt_vdbg_mm("shadow 64K gtt entry\n");
1286                 /*
1287                  * The layout of 64K page is special, the page size is
1288                  * controlled by uper PDE. To be simple, we always split
1289                  * 64K page to smaller 4K pages in shadow PT.
1290                  */
1291                 return split_64KB_gtt_entry(vgpu, spt, index, &se);
1292         case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1293                 gvt_vdbg_mm("shadow 2M gtt entry\n");
1294                 ret = is_2MB_gtt_possible(vgpu, ge);
1295                 if (ret == 0)
1296                         return split_2MB_gtt_entry(vgpu, spt, index, &se);
1297                 else if (ret < 0)
1298                         return ret;
1299                 page_size = I915_GTT_PAGE_SIZE_2M;
1300                 break;
1301         case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1302                 gvt_vgpu_err("GVT doesn't support 1GB entry\n");
1303                 return -EINVAL;
1304         default:
1305                 GEM_BUG_ON(1);
1306         }
1307
1308         /* direct shadow */
1309         ret = intel_gvt_dma_map_guest_page(vgpu, gfn, page_size, &dma_addr);
1310         if (ret)
1311                 return -ENXIO;
1312
1313         pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1314         ppgtt_set_shadow_entry(spt, &se, index);
1315         return 0;
1316 }
1317
1318 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1319 {
1320         struct intel_vgpu *vgpu = spt->vgpu;
1321         struct intel_vgpu_ppgtt_spt *s;
1322         struct intel_gvt_gtt_entry se, ge;
1323         unsigned long i;
1324         int ret;
1325
1326         trace_spt_change(spt->vgpu->id, "born", spt,
1327                          spt->guest_page.gfn, spt->shadow_page.type);
1328
1329         for_each_present_guest_entry(spt, &ge, i) {
1330                 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1331                         s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1332                         if (IS_ERR(s)) {
1333                                 ret = PTR_ERR(s);
1334                                 goto fail;
1335                         }
1336                         ppgtt_get_shadow_entry(spt, &se, i);
1337                         ppgtt_generate_shadow_entry(&se, s, &ge);
1338                         ppgtt_set_shadow_entry(spt, &se, i);
1339                 } else {
1340                         ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1341                         if (ret)
1342                                 goto fail;
1343                 }
1344         }
1345         return 0;
1346 fail:
1347         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1348                         spt, ge.val64, ge.type);
1349         return ret;
1350 }
1351
1352 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1353                 struct intel_gvt_gtt_entry *se, unsigned long index)
1354 {
1355         struct intel_vgpu *vgpu = spt->vgpu;
1356         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1357         int ret;
1358
1359         trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1360                                spt->shadow_page.type, se->val64, index);
1361
1362         gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1363                     se->type, index, se->val64);
1364
1365         if (!ops->test_present(se))
1366                 return 0;
1367
1368         if (ops->get_pfn(se) ==
1369             vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1370                 return 0;
1371
1372         if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1373                 struct intel_vgpu_ppgtt_spt *s =
1374                         intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1375                 if (!s) {
1376                         gvt_vgpu_err("fail to find guest page\n");
1377                         ret = -ENXIO;
1378                         goto fail;
1379                 }
1380                 ret = ppgtt_invalidate_spt(s);
1381                 if (ret)
1382                         goto fail;
1383         } else {
1384                 /* We don't setup 64K shadow entry so far. */
1385                 WARN(se->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY,
1386                      "suspicious 64K entry\n");
1387                 ppgtt_invalidate_pte(spt, se);
1388         }
1389
1390         return 0;
1391 fail:
1392         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1393                         spt, se->val64, se->type);
1394         return ret;
1395 }
1396
1397 static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1398                 struct intel_gvt_gtt_entry *we, unsigned long index)
1399 {
1400         struct intel_vgpu *vgpu = spt->vgpu;
1401         struct intel_gvt_gtt_entry m;
1402         struct intel_vgpu_ppgtt_spt *s;
1403         int ret;
1404
1405         trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1406                                we->val64, index);
1407
1408         gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1409                     we->type, index, we->val64);
1410
1411         if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1412                 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1413                 if (IS_ERR(s)) {
1414                         ret = PTR_ERR(s);
1415                         goto fail;
1416                 }
1417                 ppgtt_get_shadow_entry(spt, &m, index);
1418                 ppgtt_generate_shadow_entry(&m, s, we);
1419                 ppgtt_set_shadow_entry(spt, &m, index);
1420         } else {
1421                 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1422                 if (ret)
1423                         goto fail;
1424         }
1425         return 0;
1426 fail:
1427         gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1428                 spt, we->val64, we->type);
1429         return ret;
1430 }
1431
1432 static int sync_oos_page(struct intel_vgpu *vgpu,
1433                 struct intel_vgpu_oos_page *oos_page)
1434 {
1435         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1436         struct intel_gvt *gvt = vgpu->gvt;
1437         const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1438         struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1439         struct intel_gvt_gtt_entry old, new;
1440         int index;
1441         int ret;
1442
1443         trace_oos_change(vgpu->id, "sync", oos_page->id,
1444                          spt, spt->guest_page.type);
1445
1446         old.type = new.type = get_entry_type(spt->guest_page.type);
1447         old.val64 = new.val64 = 0;
1448
1449         for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1450                                 info->gtt_entry_size_shift); index++) {
1451                 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1452                 ops->get_entry(NULL, &new, index, true,
1453                                spt->guest_page.gfn << PAGE_SHIFT, vgpu);
1454
1455                 if (old.val64 == new.val64
1456                         && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1457                         continue;
1458
1459                 trace_oos_sync(vgpu->id, oos_page->id,
1460                                 spt, spt->guest_page.type,
1461                                 new.val64, index);
1462
1463                 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
1464                 if (ret)
1465                         return ret;
1466
1467                 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1468         }
1469
1470         spt->guest_page.write_cnt = 0;
1471         list_del_init(&spt->post_shadow_list);
1472         return 0;
1473 }
1474
1475 static int detach_oos_page(struct intel_vgpu *vgpu,
1476                 struct intel_vgpu_oos_page *oos_page)
1477 {
1478         struct intel_gvt *gvt = vgpu->gvt;
1479         struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1480
1481         trace_oos_change(vgpu->id, "detach", oos_page->id,
1482                          spt, spt->guest_page.type);
1483
1484         spt->guest_page.write_cnt = 0;
1485         spt->guest_page.oos_page = NULL;
1486         oos_page->spt = NULL;
1487
1488         list_del_init(&oos_page->vm_list);
1489         list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1490
1491         return 0;
1492 }
1493
1494 static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1495                 struct intel_vgpu_ppgtt_spt *spt)
1496 {
1497         struct intel_gvt *gvt = spt->vgpu->gvt;
1498         int ret;
1499
1500         ret = intel_gvt_read_gpa(spt->vgpu,
1501                         spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
1502                         oos_page->mem, I915_GTT_PAGE_SIZE);
1503         if (ret)
1504                 return ret;
1505
1506         oos_page->spt = spt;
1507         spt->guest_page.oos_page = oos_page;
1508
1509         list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1510
1511         trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1512                          spt, spt->guest_page.type);
1513         return 0;
1514 }
1515
1516 static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
1517 {
1518         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1519         int ret;
1520
1521         ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
1522         if (ret)
1523                 return ret;
1524
1525         trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1526                          spt, spt->guest_page.type);
1527
1528         list_del_init(&oos_page->vm_list);
1529         return sync_oos_page(spt->vgpu, oos_page);
1530 }
1531
1532 static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
1533 {
1534         struct intel_gvt *gvt = spt->vgpu->gvt;
1535         struct intel_gvt_gtt *gtt = &gvt->gtt;
1536         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1537         int ret;
1538
1539         WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1540
1541         if (list_empty(&gtt->oos_page_free_list_head)) {
1542                 oos_page = container_of(gtt->oos_page_use_list_head.next,
1543                         struct intel_vgpu_oos_page, list);
1544                 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1545                 if (ret)
1546                         return ret;
1547                 ret = detach_oos_page(spt->vgpu, oos_page);
1548                 if (ret)
1549                         return ret;
1550         } else
1551                 oos_page = container_of(gtt->oos_page_free_list_head.next,
1552                         struct intel_vgpu_oos_page, list);
1553         return attach_oos_page(oos_page, spt);
1554 }
1555
1556 static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
1557 {
1558         struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1559
1560         if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1561                 return -EINVAL;
1562
1563         trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1564                          spt, spt->guest_page.type);
1565
1566         list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
1567         return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
1568 }
1569
1570 /**
1571  * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1572  * @vgpu: a vGPU
1573  *
1574  * This function is called before submitting a guest workload to host,
1575  * to sync all the out-of-synced shadow for vGPU
1576  *
1577  * Returns:
1578  * Zero on success, negative error code if failed.
1579  */
1580 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1581 {
1582         struct list_head *pos, *n;
1583         struct intel_vgpu_oos_page *oos_page;
1584         int ret;
1585
1586         if (!enable_out_of_sync)
1587                 return 0;
1588
1589         list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1590                 oos_page = container_of(pos,
1591                                 struct intel_vgpu_oos_page, vm_list);
1592                 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1593                 if (ret)
1594                         return ret;
1595         }
1596         return 0;
1597 }
1598
1599 /*
1600  * The heart of PPGTT shadow page table.
1601  */
1602 static int ppgtt_handle_guest_write_page_table(
1603                 struct intel_vgpu_ppgtt_spt *spt,
1604                 struct intel_gvt_gtt_entry *we, unsigned long index)
1605 {
1606         struct intel_vgpu *vgpu = spt->vgpu;
1607         int type = spt->shadow_page.type;
1608         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1609         struct intel_gvt_gtt_entry old_se;
1610         int new_present;
1611         int i, ret;
1612
1613         new_present = ops->test_present(we);
1614
1615         /*
1616          * Adding the new entry first and then removing the old one, that can
1617          * guarantee the ppgtt table is validated during the window between
1618          * adding and removal.
1619          */
1620         ppgtt_get_shadow_entry(spt, &old_se, index);
1621
1622         if (new_present) {
1623                 ret = ppgtt_handle_guest_entry_add(spt, we, index);
1624                 if (ret)
1625                         goto fail;
1626         }
1627
1628         ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
1629         if (ret)
1630                 goto fail;
1631
1632         if (!new_present) {
1633                 /* For 64KB splited entries, we need clear them all. */
1634                 if (ops->test_64k_splited(&old_se) &&
1635                     !(index % GTT_64K_PTE_STRIDE)) {
1636                         gvt_vdbg_mm("remove splited 64K shadow entries\n");
1637                         for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1638                                 ops->clear_64k_splited(&old_se);
1639                                 ops->set_pfn(&old_se,
1640                                         vgpu->gtt.scratch_pt[type].page_mfn);
1641                                 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1642                         }
1643                 } else if (old_se.type == GTT_TYPE_PPGTT_PTE_2M_ENTRY ||
1644                            old_se.type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
1645                         ops->clear_pse(&old_se);
1646                         ops->set_pfn(&old_se,
1647                                      vgpu->gtt.scratch_pt[type].page_mfn);
1648                         ppgtt_set_shadow_entry(spt, &old_se, index);
1649                 } else {
1650                         ops->set_pfn(&old_se,
1651                                      vgpu->gtt.scratch_pt[type].page_mfn);
1652                         ppgtt_set_shadow_entry(spt, &old_se, index);
1653                 }
1654         }
1655
1656         return 0;
1657 fail:
1658         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1659                         spt, we->val64, we->type);
1660         return ret;
1661 }
1662
1663
1664
1665 static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
1666 {
1667         return enable_out_of_sync
1668                 && gtt_type_is_pte_pt(spt->guest_page.type)
1669                 && spt->guest_page.write_cnt >= 2;
1670 }
1671
1672 static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1673                 unsigned long index)
1674 {
1675         set_bit(index, spt->post_shadow_bitmap);
1676         if (!list_empty(&spt->post_shadow_list))
1677                 return;
1678
1679         list_add_tail(&spt->post_shadow_list,
1680                         &spt->vgpu->gtt.post_shadow_list_head);
1681 }
1682
1683 /**
1684  * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1685  * @vgpu: a vGPU
1686  *
1687  * This function is called before submitting a guest workload to host,
1688  * to flush all the post shadows for a vGPU.
1689  *
1690  * Returns:
1691  * Zero on success, negative error code if failed.
1692  */
1693 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1694 {
1695         struct list_head *pos, *n;
1696         struct intel_vgpu_ppgtt_spt *spt;
1697         struct intel_gvt_gtt_entry ge;
1698         unsigned long index;
1699         int ret;
1700
1701         list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1702                 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1703                                 post_shadow_list);
1704
1705                 for_each_set_bit(index, spt->post_shadow_bitmap,
1706                                 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1707                         ppgtt_get_guest_entry(spt, &ge, index);
1708
1709                         ret = ppgtt_handle_guest_write_page_table(spt,
1710                                                         &ge, index);
1711                         if (ret)
1712                                 return ret;
1713                         clear_bit(index, spt->post_shadow_bitmap);
1714                 }
1715                 list_del_init(&spt->post_shadow_list);
1716         }
1717         return 0;
1718 }
1719
1720 static int ppgtt_handle_guest_write_page_table_bytes(
1721                 struct intel_vgpu_ppgtt_spt *spt,
1722                 u64 pa, void *p_data, int bytes)
1723 {
1724         struct intel_vgpu *vgpu = spt->vgpu;
1725         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1726         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1727         struct intel_gvt_gtt_entry we, se;
1728         unsigned long index;
1729         int ret;
1730
1731         index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1732
1733         ppgtt_get_guest_entry(spt, &we, index);
1734
1735         /*
1736          * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1737          * PTE#32, ... PTE#496 are used. Unused PTEs update should be
1738          * ignored.
1739          */
1740         if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1741             (index % GTT_64K_PTE_STRIDE)) {
1742                 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1743                             index);
1744                 return 0;
1745         }
1746
1747         if (bytes == info->gtt_entry_size) {
1748                 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1749                 if (ret)
1750                         return ret;
1751         } else {
1752                 if (!test_bit(index, spt->post_shadow_bitmap)) {
1753                         int type = spt->shadow_page.type;
1754
1755                         ppgtt_get_shadow_entry(spt, &se, index);
1756                         ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
1757                         if (ret)
1758                                 return ret;
1759                         ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1760                         ppgtt_set_shadow_entry(spt, &se, index);
1761                 }
1762                 ppgtt_set_post_shadow(spt, index);
1763         }
1764
1765         if (!enable_out_of_sync)
1766                 return 0;
1767
1768         spt->guest_page.write_cnt++;
1769
1770         if (spt->guest_page.oos_page)
1771                 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
1772                                 false, 0, vgpu);
1773
1774         if (can_do_out_of_sync(spt)) {
1775                 if (!spt->guest_page.oos_page)
1776                         ppgtt_allocate_oos_page(spt);
1777
1778                 ret = ppgtt_set_guest_page_oos(spt);
1779                 if (ret < 0)
1780                         return ret;
1781         }
1782         return 0;
1783 }
1784
1785 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
1786 {
1787         struct intel_vgpu *vgpu = mm->vgpu;
1788         struct intel_gvt *gvt = vgpu->gvt;
1789         struct intel_gvt_gtt *gtt = &gvt->gtt;
1790         const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1791         struct intel_gvt_gtt_entry se;
1792         int index;
1793
1794         if (!mm->ppgtt_mm.shadowed)
1795                 return;
1796
1797         for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1798                 ppgtt_get_shadow_root_entry(mm, &se, index);
1799
1800                 if (!ops->test_present(&se))
1801                         continue;
1802
1803                 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
1804                 se.val64 = 0;
1805                 ppgtt_set_shadow_root_entry(mm, &se, index);
1806
1807                 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1808                                        NULL, se.type, se.val64, index);
1809         }
1810
1811         mm->ppgtt_mm.shadowed = false;
1812 }
1813
1814
1815 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
1816 {
1817         struct intel_vgpu *vgpu = mm->vgpu;
1818         struct intel_gvt *gvt = vgpu->gvt;
1819         struct intel_gvt_gtt *gtt = &gvt->gtt;
1820         const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1821         struct intel_vgpu_ppgtt_spt *spt;
1822         struct intel_gvt_gtt_entry ge, se;
1823         int index, ret;
1824
1825         if (mm->ppgtt_mm.shadowed)
1826                 return 0;
1827
1828         if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
1829                 return -EINVAL;
1830
1831         mm->ppgtt_mm.shadowed = true;
1832
1833         for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1834                 ppgtt_get_guest_root_entry(mm, &ge, index);
1835
1836                 if (!ops->test_present(&ge))
1837                         continue;
1838
1839                 trace_spt_guest_change(vgpu->id, __func__, NULL,
1840                                        ge.type, ge.val64, index);
1841
1842                 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1843                 if (IS_ERR(spt)) {
1844                         gvt_vgpu_err("fail to populate guest root pointer\n");
1845                         ret = PTR_ERR(spt);
1846                         goto fail;
1847                 }
1848                 ppgtt_generate_shadow_entry(&se, spt, &ge);
1849                 ppgtt_set_shadow_root_entry(mm, &se, index);
1850
1851                 trace_spt_guest_change(vgpu->id, "populate root pointer",
1852                                        NULL, se.type, se.val64, index);
1853         }
1854
1855         return 0;
1856 fail:
1857         invalidate_ppgtt_mm(mm);
1858         return ret;
1859 }
1860
1861 static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1862 {
1863         struct intel_vgpu_mm *mm;
1864
1865         mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1866         if (!mm)
1867                 return NULL;
1868
1869         mm->vgpu = vgpu;
1870         kref_init(&mm->ref);
1871         atomic_set(&mm->pincount, 0);
1872
1873         return mm;
1874 }
1875
1876 static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1877 {
1878         kfree(mm);
1879 }
1880
1881 /**
1882  * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
1883  * @vgpu: a vGPU
1884  * @root_entry_type: ppgtt root entry type
1885  * @pdps: guest pdps.
1886  *
1887  * This function is used to create a ppgtt mm object for a vGPU.
1888  *
1889  * Returns:
1890  * Zero on success, negative error code in pointer if failed.
1891  */
1892 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1893                 enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
1894 {
1895         struct intel_gvt *gvt = vgpu->gvt;
1896         struct intel_vgpu_mm *mm;
1897         int ret;
1898
1899         mm = vgpu_alloc_mm(vgpu);
1900         if (!mm)
1901                 return ERR_PTR(-ENOMEM);
1902
1903         mm->type = INTEL_GVT_MM_PPGTT;
1904
1905         GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1906                    root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1907         mm->ppgtt_mm.root_entry_type = root_entry_type;
1908
1909         INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1910         INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
1911         INIT_LIST_HEAD(&mm->ppgtt_mm.link);
1912
1913         if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1914                 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1915         else
1916                 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1917                        sizeof(mm->ppgtt_mm.guest_pdps));
1918
1919         ret = shadow_ppgtt_mm(mm);
1920         if (ret) {
1921                 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1922                 vgpu_free_mm(mm);
1923                 return ERR_PTR(ret);
1924         }
1925
1926         list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1927
1928         mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1929         list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1930         mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1931
1932         return mm;
1933 }
1934
1935 static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1936 {
1937         struct intel_vgpu_mm *mm;
1938         unsigned long nr_entries;
1939
1940         mm = vgpu_alloc_mm(vgpu);
1941         if (!mm)
1942                 return ERR_PTR(-ENOMEM);
1943
1944         mm->type = INTEL_GVT_MM_GGTT;
1945
1946         nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1947         mm->ggtt_mm.virtual_ggtt =
1948                 vzalloc(array_size(nr_entries,
1949                                    vgpu->gvt->device_info.gtt_entry_size));
1950         if (!mm->ggtt_mm.virtual_ggtt) {
1951                 vgpu_free_mm(mm);
1952                 return ERR_PTR(-ENOMEM);
1953         }
1954
1955         mm->ggtt_mm.host_ggtt_aperture = vzalloc((vgpu_aperture_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));
1956         if (!mm->ggtt_mm.host_ggtt_aperture) {
1957                 vfree(mm->ggtt_mm.virtual_ggtt);
1958                 vgpu_free_mm(mm);
1959                 return ERR_PTR(-ENOMEM);
1960         }
1961
1962         mm->ggtt_mm.host_ggtt_hidden = vzalloc((vgpu_hidden_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));
1963         if (!mm->ggtt_mm.host_ggtt_hidden) {
1964                 vfree(mm->ggtt_mm.host_ggtt_aperture);
1965                 vfree(mm->ggtt_mm.virtual_ggtt);
1966                 vgpu_free_mm(mm);
1967                 return ERR_PTR(-ENOMEM);
1968         }
1969
1970         return mm;
1971 }
1972
1973 /**
1974  * _intel_vgpu_mm_release - destroy a mm object
1975  * @mm_ref: a kref object
1976  *
1977  * This function is used to destroy a mm object for vGPU
1978  *
1979  */
1980 void _intel_vgpu_mm_release(struct kref *mm_ref)
1981 {
1982         struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1983
1984         if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1985                 gvt_err("vgpu mm pin count bug detected\n");
1986
1987         if (mm->type == INTEL_GVT_MM_PPGTT) {
1988                 list_del(&mm->ppgtt_mm.list);
1989
1990                 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1991                 list_del(&mm->ppgtt_mm.lru_list);
1992                 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1993
1994                 invalidate_ppgtt_mm(mm);
1995         } else {
1996                 vfree(mm->ggtt_mm.virtual_ggtt);
1997                 vfree(mm->ggtt_mm.host_ggtt_aperture);
1998                 vfree(mm->ggtt_mm.host_ggtt_hidden);
1999         }
2000
2001         vgpu_free_mm(mm);
2002 }
2003
2004 /**
2005  * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
2006  * @mm: a vGPU mm object
2007  *
2008  * This function is called when user doesn't want to use a vGPU mm object
2009  */
2010 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
2011 {
2012         atomic_dec_if_positive(&mm->pincount);
2013 }
2014
2015 /**
2016  * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
2017  * @mm: target vgpu mm
2018  *
2019  * This function is called when user wants to use a vGPU mm object. If this
2020  * mm object hasn't been shadowed yet, the shadow will be populated at this
2021  * time.
2022  *
2023  * Returns:
2024  * Zero on success, negative error code if failed.
2025  */
2026 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
2027 {
2028         int ret;
2029
2030         atomic_inc(&mm->pincount);
2031
2032         if (mm->type == INTEL_GVT_MM_PPGTT) {
2033                 ret = shadow_ppgtt_mm(mm);
2034                 if (ret)
2035                         return ret;
2036
2037                 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2038                 list_move_tail(&mm->ppgtt_mm.lru_list,
2039                                &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
2040                 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2047 {
2048         struct intel_vgpu_mm *mm;
2049         struct list_head *pos, *n;
2050
2051         mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2052
2053         list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
2054                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
2055
2056                 if (atomic_read(&mm->pincount))
2057                         continue;
2058
2059                 list_del_init(&mm->ppgtt_mm.lru_list);
2060                 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2061                 invalidate_ppgtt_mm(mm);
2062                 return 1;
2063         }
2064         mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2065         return 0;
2066 }
2067
2068 /*
2069  * GMA translation APIs.
2070  */
2071 static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
2072                 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
2073 {
2074         struct intel_vgpu *vgpu = mm->vgpu;
2075         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2076         struct intel_vgpu_ppgtt_spt *s;
2077
2078         s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2079         if (!s)
2080                 return -ENXIO;
2081
2082         if (!guest)
2083                 ppgtt_get_shadow_entry(s, e, index);
2084         else
2085                 ppgtt_get_guest_entry(s, e, index);
2086         return 0;
2087 }
2088
2089 /**
2090  * intel_vgpu_gma_to_gpa - translate a gma to GPA
2091  * @mm: mm object. could be a PPGTT or GGTT mm object
2092  * @gma: graphics memory address in this mm object
2093  *
2094  * This function is used to translate a graphics memory address in specific
2095  * graphics memory space to guest physical address.
2096  *
2097  * Returns:
2098  * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
2099  */
2100 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
2101 {
2102         struct intel_vgpu *vgpu = mm->vgpu;
2103         struct intel_gvt *gvt = vgpu->gvt;
2104         const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2105         const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2106         unsigned long gpa = INTEL_GVT_INVALID_ADDR;
2107         unsigned long gma_index[4];
2108         struct intel_gvt_gtt_entry e;
2109         int i, levels = 0;
2110         int ret;
2111
2112         GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
2113                    mm->type != INTEL_GVT_MM_PPGTT);
2114
2115         if (mm->type == INTEL_GVT_MM_GGTT) {
2116                 if (!vgpu_gmadr_is_valid(vgpu, gma))
2117                         goto err;
2118
2119                 ggtt_get_guest_entry(mm, &e,
2120                         gma_ops->gma_to_ggtt_pte_index(gma));
2121
2122                 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
2123                         + (gma & ~I915_GTT_PAGE_MASK);
2124
2125                 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
2126         } else {
2127                 switch (mm->ppgtt_mm.root_entry_type) {
2128                 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2129                         ppgtt_get_shadow_root_entry(mm, &e, 0);
2130
2131                         gma_index[0] = gma_ops->gma_to_pml4_index(gma);
2132                         gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
2133                         gma_index[2] = gma_ops->gma_to_pde_index(gma);
2134                         gma_index[3] = gma_ops->gma_to_pte_index(gma);
2135                         levels = 4;
2136                         break;
2137                 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2138                         ppgtt_get_shadow_root_entry(mm, &e,
2139                                         gma_ops->gma_to_l3_pdp_index(gma));
2140
2141                         gma_index[0] = gma_ops->gma_to_pde_index(gma);
2142                         gma_index[1] = gma_ops->gma_to_pte_index(gma);
2143                         levels = 2;
2144                         break;
2145                 default:
2146                         GEM_BUG_ON(1);
2147                 }
2148
2149                 /* walk the shadow page table and get gpa from guest entry */
2150                 for (i = 0; i < levels; i++) {
2151                         ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
2152                                 (i == levels - 1));
2153                         if (ret)
2154                                 goto err;
2155
2156                         if (!pte_ops->test_present(&e)) {
2157                                 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
2158                                 goto err;
2159                         }
2160                 }
2161
2162                 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
2163                                         (gma & ~I915_GTT_PAGE_MASK);
2164                 trace_gma_translate(vgpu->id, "ppgtt", 0,
2165                                     mm->ppgtt_mm.root_entry_type, gma, gpa);
2166         }
2167
2168         return gpa;
2169 err:
2170         gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2171         return INTEL_GVT_INVALID_ADDR;
2172 }
2173
2174 static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2175         unsigned int off, void *p_data, unsigned int bytes)
2176 {
2177         struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2178         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2179         unsigned long index = off >> info->gtt_entry_size_shift;
2180         unsigned long gma;
2181         struct intel_gvt_gtt_entry e;
2182
2183         if (bytes != 4 && bytes != 8)
2184                 return -EINVAL;
2185
2186         gma = index << I915_GTT_PAGE_SHIFT;
2187         if (!intel_gvt_ggtt_validate_range(vgpu,
2188                                            gma, 1 << I915_GTT_PAGE_SHIFT)) {
2189                 gvt_dbg_mm("read invalid ggtt at 0x%lx\n", gma);
2190                 memset(p_data, 0, bytes);
2191                 return 0;
2192         }
2193
2194         ggtt_get_guest_entry(ggtt_mm, &e, index);
2195         memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
2196                         bytes);
2197         return 0;
2198 }
2199
2200 /**
2201  * intel_vgpu_emulate_ggtt_mmio_read - emulate GTT MMIO register read
2202  * @vgpu: a vGPU
2203  * @off: register offset
2204  * @p_data: data will be returned to guest
2205  * @bytes: data length
2206  *
2207  * This function is used to emulate the GTT MMIO register read
2208  *
2209  * Returns:
2210  * Zero on success, error code if failed.
2211  */
2212 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2213         void *p_data, unsigned int bytes)
2214 {
2215         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2216         int ret;
2217
2218         if (bytes != 4 && bytes != 8)
2219                 return -EINVAL;
2220
2221         off -= info->gtt_start_offset;
2222         ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2223         return ret;
2224 }
2225
2226 static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
2227                 struct intel_gvt_gtt_entry *entry)
2228 {
2229         const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2230         unsigned long pfn;
2231
2232         pfn = pte_ops->get_pfn(entry);
2233         if (pfn != vgpu->gvt->gtt.scratch_mfn)
2234                 intel_gvt_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
2235 }
2236
2237 static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2238         void *p_data, unsigned int bytes)
2239 {
2240         struct intel_gvt *gvt = vgpu->gvt;
2241         const struct intel_gvt_device_info *info = &gvt->device_info;
2242         struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2243         const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2244         unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
2245         unsigned long gma, gfn;
2246         struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2247         struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2248         dma_addr_t dma_addr;
2249         int ret;
2250         struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2251         bool partial_update = false;
2252
2253         if (bytes != 4 && bytes != 8)
2254                 return -EINVAL;
2255
2256         gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2257
2258         /* the VM may configure the whole GM space when ballooning is used */
2259         if (!vgpu_gmadr_is_valid(vgpu, gma))
2260                 return 0;
2261
2262         e.type = GTT_TYPE_GGTT_PTE;
2263         memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2264                         bytes);
2265
2266         /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2267          * write, save the first 4 bytes in a list and update virtual
2268          * PTE. Only update shadow PTE when the second 4 bytes comes.
2269          */
2270         if (bytes < info->gtt_entry_size) {
2271                 bool found = false;
2272
2273                 list_for_each_entry_safe(pos, n,
2274                                 &ggtt_mm->ggtt_mm.partial_pte_list, list) {
2275                         if (g_gtt_index == pos->offset >>
2276                                         info->gtt_entry_size_shift) {
2277                                 if (off != pos->offset) {
2278                                         /* the second partial part*/
2279                                         int last_off = pos->offset &
2280                                                 (info->gtt_entry_size - 1);
2281
2282                                         memcpy((void *)&e.val64 + last_off,
2283                                                 (void *)&pos->data + last_off,
2284                                                 bytes);
2285
2286                                         list_del(&pos->list);
2287                                         kfree(pos);
2288                                         found = true;
2289                                         break;
2290                                 }
2291
2292                                 /* update of the first partial part */
2293                                 pos->data = e.val64;
2294                                 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2295                                 return 0;
2296                         }
2297                 }
2298
2299                 if (!found) {
2300                         /* the first partial part */
2301                         partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2302                         if (!partial_pte)
2303                                 return -ENOMEM;
2304                         partial_pte->offset = off;
2305                         partial_pte->data = e.val64;
2306                         list_add_tail(&partial_pte->list,
2307                                 &ggtt_mm->ggtt_mm.partial_pte_list);
2308                         partial_update = true;
2309                 }
2310         }
2311
2312         if (!partial_update && (ops->test_present(&e))) {
2313                 gfn = ops->get_pfn(&e);
2314                 m.val64 = e.val64;
2315                 m.type = e.type;
2316
2317                 ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE,
2318                                                    &dma_addr);
2319                 if (ret) {
2320                         gvt_vgpu_err("fail to populate guest ggtt entry\n");
2321                         /* guest driver may read/write the entry when partial
2322                          * update the entry in this situation p2m will fail
2323                          * setting the shadow entry to point to a scratch page
2324                          */
2325                         ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2326                 } else
2327                         ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
2328         } else {
2329                 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2330                 ops->clear_present(&m);
2331         }
2332
2333         ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2334
2335         ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2336         ggtt_invalidate_pte(vgpu, &e);
2337
2338         ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2339         ggtt_invalidate(gvt->gt);
2340         return 0;
2341 }
2342
2343 /*
2344  * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2345  * @vgpu: a vGPU
2346  * @off: register offset
2347  * @p_data: data from guest write
2348  * @bytes: data length
2349  *
2350  * This function is used to emulate the GTT MMIO register write
2351  *
2352  * Returns:
2353  * Zero on success, error code if failed.
2354  */
2355 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2356                 unsigned int off, void *p_data, unsigned int bytes)
2357 {
2358         const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2359         int ret;
2360         struct intel_vgpu_submission *s = &vgpu->submission;
2361         struct intel_engine_cs *engine;
2362         int i;
2363
2364         if (bytes != 4 && bytes != 8)
2365                 return -EINVAL;
2366
2367         off -= info->gtt_start_offset;
2368         ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2369
2370         /* if ggtt of last submitted context is written,
2371          * that context is probably got unpinned.
2372          * Set last shadowed ctx to invalid.
2373          */
2374         for_each_engine(engine, vgpu->gvt->gt, i) {
2375                 if (!s->last_ctx[i].valid)
2376                         continue;
2377
2378                 if (s->last_ctx[i].lrca == (off >> info->gtt_entry_size_shift))
2379                         s->last_ctx[i].valid = false;
2380         }
2381         return ret;
2382 }
2383
2384 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2385                 enum intel_gvt_gtt_type type)
2386 {
2387         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
2388         struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2389         const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2390         int page_entry_num = I915_GTT_PAGE_SIZE >>
2391                                 vgpu->gvt->device_info.gtt_entry_size_shift;
2392         void *scratch_pt;
2393         int i;
2394         struct device *dev = vgpu->gvt->gt->i915->drm.dev;
2395         dma_addr_t daddr;
2396
2397         if (drm_WARN_ON(&i915->drm,
2398                         type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2399                 return -EINVAL;
2400
2401         scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
2402         if (!scratch_pt) {
2403                 gvt_vgpu_err("fail to allocate scratch page\n");
2404                 return -ENOMEM;
2405         }
2406
2407         daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0, 4096, DMA_BIDIRECTIONAL);
2408         if (dma_mapping_error(dev, daddr)) {
2409                 gvt_vgpu_err("fail to dmamap scratch_pt\n");
2410                 __free_page(virt_to_page(scratch_pt));
2411                 return -ENOMEM;
2412         }
2413         gtt->scratch_pt[type].page_mfn =
2414                 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2415         gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
2416         gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
2417                         vgpu->id, type, gtt->scratch_pt[type].page_mfn);
2418
2419         /* Build the tree by full filled the scratch pt with the entries which
2420          * point to the next level scratch pt or scratch page. The
2421          * scratch_pt[type] indicate the scratch pt/scratch page used by the
2422          * 'type' pt.
2423          * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
2424          * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
2425          * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2426          */
2427         if (type > GTT_TYPE_PPGTT_PTE_PT) {
2428                 struct intel_gvt_gtt_entry se;
2429
2430                 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2431                 se.type = get_entry_type(type - 1);
2432                 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2433
2434                 /* The entry parameters like present/writeable/cache type
2435                  * set to the same as i915's scratch page tree.
2436                  */
2437                 se.val64 |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
2438                 if (type == GTT_TYPE_PPGTT_PDE_PT)
2439                         se.val64 |= PPAT_CACHED;
2440
2441                 for (i = 0; i < page_entry_num; i++)
2442                         ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
2443         }
2444
2445         return 0;
2446 }
2447
2448 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2449 {
2450         int i;
2451         struct device *dev = vgpu->gvt->gt->i915->drm.dev;
2452         dma_addr_t daddr;
2453
2454         for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2455                 if (vgpu->gtt.scratch_pt[i].page != NULL) {
2456                         daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
2457                                         I915_GTT_PAGE_SHIFT);
2458                         dma_unmap_page(dev, daddr, 4096, DMA_BIDIRECTIONAL);
2459                         __free_page(vgpu->gtt.scratch_pt[i].page);
2460                         vgpu->gtt.scratch_pt[i].page = NULL;
2461                         vgpu->gtt.scratch_pt[i].page_mfn = 0;
2462                 }
2463         }
2464
2465         return 0;
2466 }
2467
2468 static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2469 {
2470         int i, ret;
2471
2472         for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2473                 ret = alloc_scratch_pages(vgpu, i);
2474                 if (ret)
2475                         goto err;
2476         }
2477
2478         return 0;
2479
2480 err:
2481         release_scratch_page_tree(vgpu);
2482         return ret;
2483 }
2484
2485 /**
2486  * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2487  * @vgpu: a vGPU
2488  *
2489  * This function is used to initialize per-vGPU graphics memory virtualization
2490  * components.
2491  *
2492  * Returns:
2493  * Zero on success, error code if failed.
2494  */
2495 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2496 {
2497         struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2498
2499         INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2500
2501         INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2502         INIT_LIST_HEAD(&gtt->oos_page_list_head);
2503         INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2504
2505         gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2506         if (IS_ERR(gtt->ggtt_mm)) {
2507                 gvt_vgpu_err("fail to create mm for ggtt.\n");
2508                 return PTR_ERR(gtt->ggtt_mm);
2509         }
2510
2511         intel_vgpu_reset_ggtt(vgpu, false);
2512
2513         INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2514
2515         return create_scratch_page_tree(vgpu);
2516 }
2517
2518 void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2519 {
2520         struct list_head *pos, *n;
2521         struct intel_vgpu_mm *mm;
2522
2523         list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2524                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2525                 intel_vgpu_destroy_mm(mm);
2526         }
2527
2528         if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
2529                 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
2530
2531         if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
2532                 gvt_err("Why we still has spt not freed?\n");
2533                 ppgtt_free_all_spt(vgpu);
2534         }
2535 }
2536
2537 static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2538 {
2539         struct intel_gvt_partial_pte *pos, *next;
2540
2541         list_for_each_entry_safe(pos, next,
2542                                  &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2543                                  list) {
2544                 gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2545                         pos->offset, pos->data);
2546                 kfree(pos);
2547         }
2548         intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2549         vgpu->gtt.ggtt_mm = NULL;
2550 }
2551
2552 /**
2553  * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2554  * @vgpu: a vGPU
2555  *
2556  * This function is used to clean up per-vGPU graphics memory virtualization
2557  * components.
2558  *
2559  * Returns:
2560  * Zero on success, error code if failed.
2561  */
2562 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2563 {
2564         intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2565         intel_vgpu_destroy_ggtt_mm(vgpu);
2566         release_scratch_page_tree(vgpu);
2567 }
2568
2569 static void clean_spt_oos(struct intel_gvt *gvt)
2570 {
2571         struct intel_gvt_gtt *gtt = &gvt->gtt;
2572         struct list_head *pos, *n;
2573         struct intel_vgpu_oos_page *oos_page;
2574
2575         WARN(!list_empty(&gtt->oos_page_use_list_head),
2576                 "someone is still using oos page\n");
2577
2578         list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2579                 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2580                 list_del(&oos_page->list);
2581                 free_page((unsigned long)oos_page->mem);
2582                 kfree(oos_page);
2583         }
2584 }
2585
2586 static int setup_spt_oos(struct intel_gvt *gvt)
2587 {
2588         struct intel_gvt_gtt *gtt = &gvt->gtt;
2589         struct intel_vgpu_oos_page *oos_page;
2590         int i;
2591         int ret;
2592
2593         INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2594         INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2595
2596         for (i = 0; i < preallocated_oos_pages; i++) {
2597                 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2598                 if (!oos_page) {
2599                         ret = -ENOMEM;
2600                         goto fail;
2601                 }
2602                 oos_page->mem = (void *)__get_free_pages(GFP_KERNEL, 0);
2603                 if (!oos_page->mem) {
2604                         ret = -ENOMEM;
2605                         kfree(oos_page);
2606                         goto fail;
2607                 }
2608
2609                 INIT_LIST_HEAD(&oos_page->list);
2610                 INIT_LIST_HEAD(&oos_page->vm_list);
2611                 oos_page->id = i;
2612                 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2613         }
2614
2615         gvt_dbg_mm("%d oos pages preallocated\n", i);
2616
2617         return 0;
2618 fail:
2619         clean_spt_oos(gvt);
2620         return ret;
2621 }
2622
2623 /**
2624  * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2625  * @vgpu: a vGPU
2626  * @pdps: pdp root array
2627  *
2628  * This function is used to find a PPGTT mm object from mm object pool
2629  *
2630  * Returns:
2631  * pointer to mm object on success, NULL if failed.
2632  */
2633 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2634                 u64 pdps[])
2635 {
2636         struct intel_vgpu_mm *mm;
2637         struct list_head *pos;
2638
2639         list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2640                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2641
2642                 switch (mm->ppgtt_mm.root_entry_type) {
2643                 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2644                         if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2645                                 return mm;
2646                         break;
2647                 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2648                         if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2649                                     sizeof(mm->ppgtt_mm.guest_pdps)))
2650                                 return mm;
2651                         break;
2652                 default:
2653                         GEM_BUG_ON(1);
2654                 }
2655         }
2656         return NULL;
2657 }
2658
2659 /**
2660  * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2661  * @vgpu: a vGPU
2662  * @root_entry_type: ppgtt root entry type
2663  * @pdps: guest pdps
2664  *
2665  * This function is used to find or create a PPGTT mm object from a guest.
2666  *
2667  * Returns:
2668  * Zero on success, negative error code if failed.
2669  */
2670 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
2671                 enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
2672 {
2673         struct intel_vgpu_mm *mm;
2674
2675         mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2676         if (mm) {
2677                 intel_vgpu_mm_get(mm);
2678         } else {
2679                 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
2680                 if (IS_ERR(mm))
2681                         gvt_vgpu_err("fail to create mm\n");
2682         }
2683         return mm;
2684 }
2685
2686 /**
2687  * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2688  * @vgpu: a vGPU
2689  * @pdps: guest pdps
2690  *
2691  * This function is used to find a PPGTT mm object from a guest and destroy it.
2692  *
2693  * Returns:
2694  * Zero on success, negative error code if failed.
2695  */
2696 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2697 {
2698         struct intel_vgpu_mm *mm;
2699
2700         mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2701         if (!mm) {
2702                 gvt_vgpu_err("fail to find ppgtt instance.\n");
2703                 return -EINVAL;
2704         }
2705         intel_vgpu_mm_put(mm);
2706         return 0;
2707 }
2708
2709 /**
2710  * intel_gvt_init_gtt - initialize mm components of a GVT device
2711  * @gvt: GVT device
2712  *
2713  * This function is called at the initialization stage, to initialize
2714  * the mm components of a GVT device.
2715  *
2716  * Returns:
2717  * zero on success, negative error code if failed.
2718  */
2719 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2720 {
2721         int ret;
2722         void *page;
2723         struct device *dev = gvt->gt->i915->drm.dev;
2724         dma_addr_t daddr;
2725
2726         gvt_dbg_core("init gtt\n");
2727
2728         gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2729         gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2730
2731         page = (void *)get_zeroed_page(GFP_KERNEL);
2732         if (!page) {
2733                 gvt_err("fail to allocate scratch ggtt page\n");
2734                 return -ENOMEM;
2735         }
2736
2737         daddr = dma_map_page(dev, virt_to_page(page), 0,
2738                         4096, DMA_BIDIRECTIONAL);
2739         if (dma_mapping_error(dev, daddr)) {
2740                 gvt_err("fail to dmamap scratch ggtt page\n");
2741                 __free_page(virt_to_page(page));
2742                 return -ENOMEM;
2743         }
2744
2745         gvt->gtt.scratch_page = virt_to_page(page);
2746         gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2747
2748         if (enable_out_of_sync) {
2749                 ret = setup_spt_oos(gvt);
2750                 if (ret) {
2751                         gvt_err("fail to initialize SPT oos\n");
2752                         dma_unmap_page(dev, daddr, 4096, DMA_BIDIRECTIONAL);
2753                         __free_page(gvt->gtt.scratch_page);
2754                         return ret;
2755                 }
2756         }
2757         INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2758         mutex_init(&gvt->gtt.ppgtt_mm_lock);
2759         return 0;
2760 }
2761
2762 /**
2763  * intel_gvt_clean_gtt - clean up mm components of a GVT device
2764  * @gvt: GVT device
2765  *
2766  * This function is called at the driver unloading stage, to clean up
2767  * the mm components of a GVT device.
2768  *
2769  */
2770 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2771 {
2772         struct device *dev = gvt->gt->i915->drm.dev;
2773         dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2774                                         I915_GTT_PAGE_SHIFT);
2775
2776         dma_unmap_page(dev, daddr, 4096, DMA_BIDIRECTIONAL);
2777
2778         __free_page(gvt->gtt.scratch_page);
2779
2780         if (enable_out_of_sync)
2781                 clean_spt_oos(gvt);
2782 }
2783
2784 /**
2785  * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2786  * @vgpu: a vGPU
2787  *
2788  * This function is called when invalidate all PPGTT instances of a vGPU.
2789  *
2790  */
2791 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2792 {
2793         struct list_head *pos, *n;
2794         struct intel_vgpu_mm *mm;
2795
2796         list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2797                 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2798                 if (mm->type == INTEL_GVT_MM_PPGTT) {
2799                         mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2800                         list_del_init(&mm->ppgtt_mm.lru_list);
2801                         mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2802                         if (mm->ppgtt_mm.shadowed)
2803                                 invalidate_ppgtt_mm(mm);
2804                 }
2805         }
2806 }
2807
2808 /**
2809  * intel_vgpu_reset_ggtt - reset the GGTT entry
2810  * @vgpu: a vGPU
2811  * @invalidate_old: invalidate old entries
2812  *
2813  * This function is called at the vGPU create stage
2814  * to reset all the GGTT entries.
2815  *
2816  */
2817 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
2818 {
2819         struct intel_gvt *gvt = vgpu->gvt;
2820         const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2821         struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
2822         struct intel_gvt_gtt_entry old_entry;
2823         u32 index;
2824         u32 num_entries;
2825
2826         pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2827         pte_ops->set_present(&entry);
2828
2829         index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2830         num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2831         while (num_entries--) {
2832                 if (invalidate_old) {
2833                         ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2834                         ggtt_invalidate_pte(vgpu, &old_entry);
2835                 }
2836                 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2837         }
2838
2839         index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2840         num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2841         while (num_entries--) {
2842                 if (invalidate_old) {
2843                         ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2844                         ggtt_invalidate_pte(vgpu, &old_entry);
2845                 }
2846                 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2847         }
2848
2849         ggtt_invalidate(gvt->gt);
2850 }
2851
2852 /**
2853  * intel_vgpu_reset_gtt - reset the all GTT related status
2854  * @vgpu: a vGPU
2855  *
2856  * This function is called from vfio core to reset reset all
2857  * GTT related status, including GGTT, PPGTT, scratch page.
2858  *
2859  */
2860 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
2861 {
2862         /* Shadow pages are only created when there is no page
2863          * table tracking data, so remove page tracking data after
2864          * removing the shadow pages.
2865          */
2866         intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2867         intel_vgpu_reset_ggtt(vgpu, true);
2868 }
2869
2870 /**
2871  * intel_gvt_restore_ggtt - restore all vGPU's ggtt entries
2872  * @gvt: intel gvt device
2873  *
2874  * This function is called at driver resume stage to restore
2875  * GGTT entries of every vGPU.
2876  *
2877  */
2878 void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
2879 {
2880         struct intel_vgpu *vgpu;
2881         struct intel_vgpu_mm *mm;
2882         int id;
2883         gen8_pte_t pte;
2884         u32 idx, num_low, num_hi, offset;
2885
2886         /* Restore dirty host ggtt for all vGPUs */
2887         idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
2888                 mm = vgpu->gtt.ggtt_mm;
2889
2890                 num_low = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2891                 offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2892                 for (idx = 0; idx < num_low; idx++) {
2893                         pte = mm->ggtt_mm.host_ggtt_aperture[idx];
2894                         if (pte & GEN8_PAGE_PRESENT)
2895                                 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2896                 }
2897
2898                 num_hi = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2899                 offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2900                 for (idx = 0; idx < num_hi; idx++) {
2901                         pte = mm->ggtt_mm.host_ggtt_hidden[idx];
2902                         if (pte & GEN8_PAGE_PRESENT)
2903                                 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2904                 }
2905         }
2906 }