drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38
  39 #include "i915_drv.h"
  40 #include "gt/intel_gpu_commands.h"
  41 #include "gt/intel_lrc.h"
  42 #include "gt/intel_ring.h"
  43 #include "gt/intel_gt_requests.h"
  44 #include "gt/shmem_utils.h"
  45 #include "gvt.h"
  46 #include "i915_pvinfo.h"
  47 #include "trace.h"
  48
  49 #include "gem/i915_gem_context.h"
  50 #include "gem/i915_gem_pm.h"
  51 #include "gt/intel_context.h"
  52
  53 #define INVALID_OP    (~0U)
  54
  55 #define OP_LEN_MI           9
  56 #define OP_LEN_2D           10
  57 #define OP_LEN_3D_MEDIA     16
  58 #define OP_LEN_MFX_VC       16
  59 #define OP_LEN_VEBOX        16
  60
  61 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  62
  63 struct sub_op_bits {
  64         int hi;
  65         int low;
  66 };
  67 struct decode_info {
  68         const char *name;
  69         int op_len;
  70         int nr_sub_op;
  71         const struct sub_op_bits *sub_op;
  72 };
  73
  74 #define   MAX_CMD_BUDGET                        0x7fffffff
  75 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  76 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  77 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  78
  79 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  80 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  81 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  82
  83 /* Render Command Map */
  84
  85 /* MI_* command Opcode (28:23) */
  86 #define OP_MI_NOOP                          0x0
  87 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  88 #define OP_MI_USER_INTERRUPT                0x2
  89 #define OP_MI_WAIT_FOR_EVENT                0x3
  90 #define OP_MI_FLUSH                         0x4
  91 #define OP_MI_ARB_CHECK                     0x5
  92 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  93 #define OP_MI_REPORT_HEAD                   0x7
  94 #define OP_MI_ARB_ON_OFF                    0x8
  95 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  96 #define OP_MI_BATCH_BUFFER_END              0xA
  97 #define OP_MI_SUSPEND_FLUSH                 0xB
  98 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  99 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
 100 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
 101 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
 102 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
 103 #define OP_MI_DISPLAY_FLIP                  0x14
 104 #define OP_MI_SEMAPHORE_MBOX                0x16
 105 #define OP_MI_SET_CONTEXT                   0x18
 106 #define OP_MI_MATH                          0x1A
 107 #define OP_MI_URB_CLEAR                     0x19
 108 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
 109 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 110
 111 #define OP_MI_STORE_DATA_IMM                0x20
 112 #define OP_MI_STORE_DATA_INDEX              0x21
 113 #define OP_MI_LOAD_REGISTER_IMM             0x22
 114 #define OP_MI_UPDATE_GTT                    0x23
 115 #define OP_MI_STORE_REGISTER_MEM            0x24
 116 #define OP_MI_FLUSH_DW                      0x26
 117 #define OP_MI_CLFLUSH                       0x27
 118 #define OP_MI_REPORT_PERF_COUNT             0x28
 119 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 120 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 121 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 122 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 123 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 124 #define OP_MI_2E                            0x2E  /* BDW+ */
 125 #define OP_MI_2F                            0x2F  /* BDW+ */
 126 #define OP_MI_BATCH_BUFFER_START            0x31
 127
 128 /* Bit definition for dword 0 */
 129 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 130
 131 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 132
 133 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 134 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 135 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 136 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 137
 138 /* 2D command: Opcode (28:22) */
 139 #define OP_2D(x)    ((2<<7) | x)
 140
 141 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 142 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 143 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 144 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 145 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 146 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 147 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 148 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 149 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 150 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 151 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 152 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 153 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 154 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 155 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 156 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 157 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 158 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 159 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 160 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 161 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 162 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 163 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 164 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 165
 166 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 167 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 168         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 169
 170 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 171
 172 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 173 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 174 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 175 #define OP_SWTESS_BASE_ADDRESS                  OP_3D_MEDIA(0x0, 0x1, 0x03)
 176
 177 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 178
 179 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 180
 181 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 182 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 183 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 184 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 185 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 186 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 187
 188 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 189 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 190 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 191 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 192
 193 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 194 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 195 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 196 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 197 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 198 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 199 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 200 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 201 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 202 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 203 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 204 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 205 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 206 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 207 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 208 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 209 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 210 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 211 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 212 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 213 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 214 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 215 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 216 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 217 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 218 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 219 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 220 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 221 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 222 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 223 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 224 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 225 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 226 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 227 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 228 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 229 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 230 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 231 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 232 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 233 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 234 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 235 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 236 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 237 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 238 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 239 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 240 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 241 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 242 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 243 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 244 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 245 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 246 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 247 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 248 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 249 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 250 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 251 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 252 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 253 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 254 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 255 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 256 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 257 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 258 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 259
 260 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 261 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 262 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 263 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 264 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 265 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 266 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 267 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 268 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 269 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 270 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 271
 272 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 273 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 274 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 275 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 276 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 277 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 278 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 279 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 280 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 281 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 282 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 283 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 284 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 285 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 286 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 287 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 288 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 289 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 290 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 291 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 292 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 293 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 294 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 295 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 296 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 297 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 298 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 299 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 300
 301 /* VCCP Command Parser */
 302
 303 /*
 304  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 305  * git://anongit.freedesktop.org/vaapi/intel-driver
 306  * src/i965_defines.h
 307  *
 308  */
 309
 310 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 311         (3 << 13 | \
 312          (pipeline) << 11 | \
 313          (op) << 8 | \
 314          (sub_opa) << 5 | \
 315          (sub_opb))
 316
 317 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 318 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 319 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 320 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 321 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 322 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 323 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 324 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 325 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 326 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 327 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 328
 329 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 330
 331 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 332 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 333 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 334 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 335 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 336 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 337 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 338 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 339 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 340 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 341 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 342 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 343
 344 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 345 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 346 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 347 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 348 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 349
 350 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 351 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 352 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 353 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 354 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 355
 356 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 357 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 358 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 359
 360 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 361 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 362 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 363
 364 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 365         (3 << 13 | \
 366          (pipeline) << 11 | \
 367          (op) << 8 | \
 368          (sub_opa) << 5 | \
 369          (sub_opb))
 370
 371 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 372 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 373 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 374
 375 struct parser_exec_state;
 376
 377 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 378
 379 #define GVT_CMD_HASH_BITS   7
 380
 381 /* which DWords need address fix */
 382 #define ADDR_FIX_1(x1)                  (1 << (x1))
 383 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 384 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 385 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 386 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 387
 388 #define DWORD_FIELD(dword, end, start) \
 389         FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 390
 391 #define OP_LENGTH_BIAS 2
 392 #define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 393
 394 static int gvt_check_valid_cmd_length(int len, int valid_len)
 395 {
 396         if (valid_len != len) {
 397                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 398                         len, valid_len);
 399                 return -EFAULT;
 400         }
 401         return 0;
 402 }
 403
 404 struct cmd_info {
 405         const char *name;
 406         u32 opcode;
 407
 408 #define F_LEN_MASK      3U
 409 #define F_LEN_CONST  1U
 410 #define F_LEN_VAR    0U
 411 /* value is const although LEN maybe variable */
 412 #define F_LEN_VAR_FIXED    (1<<1)
 413
 414 /*
 415  * command has its own ip advance logic
 416  * e.g. MI_BATCH_START, MI_BATCH_END
 417  */
 418 #define F_IP_ADVANCE_CUSTOM (1<<2)
 419         u32 flag;
 420
 421 #define R_RCS   BIT(RCS0)
 422 #define R_VCS1  BIT(VCS0)
 423 #define R_VCS2  BIT(VCS1)
 424 #define R_VCS   (R_VCS1 | R_VCS2)
 425 #define R_BCS   BIT(BCS0)
 426 #define R_VECS  BIT(VECS0)
 427 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 428         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 429         u16 rings;
 430
 431         /* devices that support this cmd: SNB/IVB/HSW/... */
 432         u16 devices;
 433
 434         /* which DWords are address that need fix up.
 435          * bit 0 means a 32-bit non address operand in command
 436          * bit 1 means address operand, which could be 32-bit
 437          * or 64-bit depending on different architectures.(
 438          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 439          * No matter the address length, each address only takes
 440          * one bit in the bitmap.
 441          */
 442         u16 addr_bitmap;
 443
 444         /* flag == F_LEN_CONST : command length
 445          * flag == F_LEN_VAR : length bias bits
 446          * Note: length is in DWord
 447          */
 448         u32 len;
 449
 450         parser_cmd_handler handler;
 451
 452         /* valid length in DWord */
 453         u32 valid_len;
 454 };
 455
 456 struct cmd_entry {
 457         struct hlist_node hlist;
 458         const struct cmd_info *info;
 459 };
 460
 461 enum {
 462         RING_BUFFER_INSTRUCTION,
 463         BATCH_BUFFER_INSTRUCTION,
 464         BATCH_BUFFER_2ND_LEVEL,
 465         RING_BUFFER_CTX,
 466 };
 467
 468 enum {
 469         GTT_BUFFER,
 470         PPGTT_BUFFER
 471 };
 472
 473 struct parser_exec_state {
 474         struct intel_vgpu *vgpu;
 475         const struct intel_engine_cs *engine;
 476
 477         int buf_type;
 478
 479         /* batch buffer address type */
 480         int buf_addr_type;
 481
 482         /* graphics memory address of ring buffer start */
 483         unsigned long ring_start;
 484         unsigned long ring_size;
 485         unsigned long ring_head;
 486         unsigned long ring_tail;
 487
 488         /* instruction graphics memory address */
 489         unsigned long ip_gma;
 490
 491         /* mapped va of the instr_gma */
 492         void *ip_va;
 493         void *rb_va;
 494
 495         void *ret_bb_va;
 496         /* next instruction when return from  batch buffer to ring buffer */
 497         unsigned long ret_ip_gma_ring;
 498
 499         /* next instruction when return from 2nd batch buffer to batch buffer */
 500         unsigned long ret_ip_gma_bb;
 501
 502         /* batch buffer address type (GTT or PPGTT)
 503          * used when ret from 2nd level batch buffer
 504          */
 505         int saved_buf_addr_type;
 506         bool is_ctx_wa;
 507         bool is_init_ctx;
 508
 509         const struct cmd_info *info;
 510
 511         struct intel_vgpu_workload *workload;
 512 };
 513
 514 #define gmadr_dw_number(s)      \
 515         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 516
 517 static unsigned long bypass_scan_mask = 0;
 518
 519 /* ring ALL, type = 0 */
 520 static const struct sub_op_bits sub_op_mi[] = {
 521         {31, 29},
 522         {28, 23},
 523 };
 524
 525 static const struct decode_info decode_info_mi = {
 526         "MI",
 527         OP_LEN_MI,
 528         ARRAY_SIZE(sub_op_mi),
 529         sub_op_mi,
 530 };
 531
 532 /* ring RCS, command type 2 */
 533 static const struct sub_op_bits sub_op_2d[] = {
 534         {31, 29},
 535         {28, 22},
 536 };
 537
 538 static const struct decode_info decode_info_2d = {
 539         "2D",
 540         OP_LEN_2D,
 541         ARRAY_SIZE(sub_op_2d),
 542         sub_op_2d,
 543 };
 544
 545 /* ring RCS, command type 3 */
 546 static const struct sub_op_bits sub_op_3d_media[] = {
 547         {31, 29},
 548         {28, 27},
 549         {26, 24},
 550         {23, 16},
 551 };
 552
 553 static const struct decode_info decode_info_3d_media = {
 554         "3D_Media",
 555         OP_LEN_3D_MEDIA,
 556         ARRAY_SIZE(sub_op_3d_media),
 557         sub_op_3d_media,
 558 };
 559
 560 /* ring VCS, command type 3 */
 561 static const struct sub_op_bits sub_op_mfx_vc[] = {
 562         {31, 29},
 563         {28, 27},
 564         {26, 24},
 565         {23, 21},
 566         {20, 16},
 567 };
 568
 569 static const struct decode_info decode_info_mfx_vc = {
 570         "MFX_VC",
 571         OP_LEN_MFX_VC,
 572         ARRAY_SIZE(sub_op_mfx_vc),
 573         sub_op_mfx_vc,
 574 };
 575
 576 /* ring VECS, command type 3 */
 577 static const struct sub_op_bits sub_op_vebox[] = {
 578         {31, 29},
 579         {28, 27},
 580         {26, 24},
 581         {23, 21},
 582         {20, 16},
 583 };
 584
 585 static const struct decode_info decode_info_vebox = {
 586         "VEBOX",
 587         OP_LEN_VEBOX,
 588         ARRAY_SIZE(sub_op_vebox),
 589         sub_op_vebox,
 590 };
 591
 592 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 593         [RCS0] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_3d_media,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [VCS0] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 NULL,
 608                 &decode_info_mfx_vc,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614
 615         [BCS0] = {
 616                 &decode_info_mi,
 617                 NULL,
 618                 &decode_info_2d,
 619                 NULL,
 620                 NULL,
 621                 NULL,
 622                 NULL,
 623                 NULL,
 624         },
 625
 626         [VECS0] = {
 627                 &decode_info_mi,
 628                 NULL,
 629                 NULL,
 630                 &decode_info_vebox,
 631                 NULL,
 632                 NULL,
 633                 NULL,
 634                 NULL,
 635         },
 636
 637         [VCS1] = {
 638                 &decode_info_mi,
 639                 NULL,
 640                 NULL,
 641                 &decode_info_mfx_vc,
 642                 NULL,
 643                 NULL,
 644                 NULL,
 645                 NULL,
 646         },
 647 };
 648
 649 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
 650 {
 651         const struct decode_info *d_info;
 652
 653         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 654         if (d_info == NULL)
 655                 return INVALID_OP;
 656
 657         return cmd >> (32 - d_info->op_len);
 658 }
 659
 660 static inline const struct cmd_info *
 661 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
 662                const struct intel_engine_cs *engine)
 663 {
 664         struct cmd_entry *e;
 665
 666         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 667                 if (opcode == e->info->opcode &&
 668                     e->info->rings & engine->mask)
 669                         return e->info;
 670         }
 671         return NULL;
 672 }
 673
 674 static inline const struct cmd_info *
 675 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
 676              const struct intel_engine_cs *engine)
 677 {
 678         u32 opcode;
 679
 680         opcode = get_opcode(cmd, engine);
 681         if (opcode == INVALID_OP)
 682                 return NULL;
 683
 684         return find_cmd_entry(gvt, opcode, engine);
 685 }
 686
 687 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 688 {
 689         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 690 }
 691
 692 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
 693 {
 694         const struct decode_info *d_info;
 695         int i;
 696
 697         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 698         if (d_info == NULL)
 699                 return;
 700
 701         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 702                         cmd >> (32 - d_info->op_len), d_info->name);
 703
 704         for (i = 0; i < d_info->nr_sub_op; i++)
 705                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 706                                         d_info->sub_op[i].low));
 707
 708         pr_err("\n");
 709 }
 710
 711 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 712 {
 713         return s->ip_va + (index << 2);
 714 }
 715
 716 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 717 {
 718         return *cmd_ptr(s, index);
 719 }
 720
 721 static inline bool is_init_ctx(struct parser_exec_state *s)
 722 {
 723         return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
 724 }
 725
 726 static void parser_exec_state_dump(struct parser_exec_state *s)
 727 {
 728         int cnt = 0;
 729         int i;
 730
 731         gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
 732                     " ring_head(%08lx) ring_tail(%08lx)\n",
 733                     s->vgpu->id, s->engine->name,
 734                     s->ring_start, s->ring_start + s->ring_size,
 735                     s->ring_head, s->ring_tail);
 736
 737         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 738                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 739                         "RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
 740                                 "CTX_BUFFER" : "BATCH_BUFFER"),
 741                         s->buf_addr_type == GTT_BUFFER ?
 742                         "GTT" : "PPGTT", s->ip_gma);
 743
 744         if (s->ip_va == NULL) {
 745                 gvt_dbg_cmd(" ip_va(NULL)");
 746                 return;
 747         }
 748
 749         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 750                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 751                         cmd_val(s, 2), cmd_val(s, 3));
 752
 753         print_opcode(cmd_val(s, 0), s->engine);
 754
 755         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 756
 757         while (cnt < 1024) {
 758                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 759                 for (i = 0; i < 8; i++)
 760                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 761                 gvt_dbg_cmd("\n");
 762
 763                 s->ip_va += 8 * sizeof(u32);
 764                 cnt += 8;
 765         }
 766 }
 767
 768 static inline void update_ip_va(struct parser_exec_state *s)
 769 {
 770         unsigned long len = 0;
 771
 772         if (WARN_ON(s->ring_head == s->ring_tail))
 773                 return;
 774
 775         if (s->buf_type == RING_BUFFER_INSTRUCTION ||
 776                         s->buf_type == RING_BUFFER_CTX) {
 777                 unsigned long ring_top = s->ring_start + s->ring_size;
 778
 779                 if (s->ring_head > s->ring_tail) {
 780                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 781                                 len = (s->ip_gma - s->ring_head);
 782                         else if (s->ip_gma >= s->ring_start &&
 783                                         s->ip_gma <= s->ring_tail)
 784                                 len = (ring_top - s->ring_head) +
 785                                         (s->ip_gma - s->ring_start);
 786                 } else
 787                         len = (s->ip_gma - s->ring_head);
 788
 789                 s->ip_va = s->rb_va + len;
 790         } else {/* shadow batch buffer */
 791                 s->ip_va = s->ret_bb_va;
 792         }
 793 }
 794
 795 static inline int ip_gma_set(struct parser_exec_state *s,
 796                 unsigned long ip_gma)
 797 {
 798         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 799
 800         s->ip_gma = ip_gma;
 801         update_ip_va(s);
 802         return 0;
 803 }
 804
 805 static inline int ip_gma_advance(struct parser_exec_state *s,
 806                 unsigned int dw_len)
 807 {
 808         s->ip_gma += (dw_len << 2);
 809
 810         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 811                 if (s->ip_gma >= s->ring_start + s->ring_size)
 812                         s->ip_gma -= s->ring_size;
 813                 update_ip_va(s);
 814         } else {
 815                 s->ip_va += (dw_len << 2);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 822 {
 823         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 824                 return info->len;
 825         else
 826                 return (cmd & ((1U << info->len) - 1)) + 2;
 827         return 0;
 828 }
 829
 830 static inline int cmd_length(struct parser_exec_state *s)
 831 {
 832         return get_cmd_length(s->info, cmd_val(s, 0));
 833 }
 834
 835 /* do not remove this, some platform may need clflush here */
 836 #define patch_value(s, addr, val) do { \
 837         *addr = val; \
 838 } while (0)
 839
 840 static inline bool is_mocs_mmio(unsigned int offset)
 841 {
 842         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 843                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 844 }
 845
 846 static int is_cmd_update_pdps(unsigned int offset,
 847                               struct parser_exec_state *s)
 848 {
 849         u32 base = s->workload->engine->mmio_base;
 850         return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
 851 }
 852
 853 static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
 854                                        unsigned int offset, unsigned int index)
 855 {
 856         struct intel_vgpu *vgpu = s->vgpu;
 857         struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
 858         struct intel_vgpu_mm *mm;
 859         u64 pdps[GEN8_3LVL_PDPES];
 860
 861         if (shadow_mm->ppgtt_mm.root_entry_type ==
 862             GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 863                 pdps[0] = (u64)cmd_val(s, 2) << 32;
 864                 pdps[0] |= cmd_val(s, 4);
 865
 866                 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
 867                 if (!mm) {
 868                         gvt_vgpu_err("failed to get the 4-level shadow vm\n");
 869                         return -EINVAL;
 870                 }
 871                 intel_vgpu_mm_get(mm);
 872                 list_add_tail(&mm->ppgtt_mm.link,
 873                               &s->workload->lri_shadow_mm);
 874                 *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 875                 *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 876         } else {
 877                 /* Currently all guests use PML4 table and now can't
 878                  * have a guest with 3-level table but uses LRI for
 879                  * PPGTT update. So this is simply un-testable. */
 880                 GEM_BUG_ON(1);
 881                 gvt_vgpu_err("invalid shared shadow vm type\n");
 882                 return -EINVAL;
 883         }
 884         return 0;
 885 }
 886
 887 static int cmd_reg_handler(struct parser_exec_state *s,
 888         unsigned int offset, unsigned int index, char *cmd)
 889 {
 890         struct intel_vgpu *vgpu = s->vgpu;
 891         struct intel_gvt *gvt = vgpu->gvt;
 892         u32 ctx_sr_ctl;
 893         u32 *vreg, vreg_old;
 894
 895         if (offset + 4 > gvt->device_info.mmio_size) {
 896                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 897                                 cmd, offset);
 898                 return -EFAULT;
 899         }
 900
 901         if (is_init_ctx(s)) {
 902                 struct intel_gvt_mmio_info *mmio_info;
 903
 904                 intel_gvt_mmio_set_cmd_accessible(gvt, offset);
 905                 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 906                 if (mmio_info && mmio_info->write)
 907                         intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
 908                 return 0;
 909         }
 910
 911         if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
 912                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 913                                 cmd, offset);
 914                 return -EBADRQC;
 915         }
 916
 917         if (!strncmp(cmd, "srm", 3) ||
 918                         !strncmp(cmd, "lrm", 3)) {
 919                 if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
 920                                 offset != 0x21f0) {
 921                         gvt_vgpu_err("%s access to register (%x)\n",
 922                                         cmd, offset);
 923                         return -EPERM;
 924                 } else
 925                         return 0;
 926         }
 927
 928         if (!strncmp(cmd, "lrr-src", 7) ||
 929                         !strncmp(cmd, "lrr-dst", 7)) {
 930                 gvt_vgpu_err("not allowed cmd %s\n", cmd);
 931                 return -EPERM;
 932         }
 933
 934         if (!strncmp(cmd, "pipe_ctrl", 9)) {
 935                 /* TODO: add LRI POST logic here */
 936                 return 0;
 937         }
 938
 939         if (strncmp(cmd, "lri", 3))
 940                 return -EPERM;
 941
 942         /* below are all lri handlers */
 943         vreg = &vgpu_vreg(s->vgpu, offset);
 944
 945         if (is_cmd_update_pdps(offset, s) &&
 946             cmd_pdp_mmio_update_handler(s, offset, index))
 947                 return -EINVAL;
 948
 949         if (offset == i915_mmio_reg_offset(DERRMR) ||
 950                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 951                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 952                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 953         }
 954
 955         if (is_mocs_mmio(offset))
 956                 *vreg = cmd_val(s, index + 1);
 957
 958         vreg_old = *vreg;
 959
 960         if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
 961                 u32 cmdval_new, cmdval;
 962                 struct intel_gvt_mmio_info *mmio_info;
 963
 964                 cmdval = cmd_val(s, index + 1);
 965
 966                 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 967                 if (!mmio_info) {
 968                         cmdval_new = cmdval;
 969                 } else {
 970                         u64 ro_mask = mmio_info->ro_mask;
 971                         int ret;
 972
 973                         if (likely(!ro_mask))
 974                                 ret = mmio_info->write(s->vgpu, offset,
 975                                                 &cmdval, 4);
 976                         else {
 977                                 gvt_vgpu_err("try to write RO reg %x\n",
 978                                                 offset);
 979                                 ret = -EBADRQC;
 980                         }
 981                         if (ret)
 982                                 return ret;
 983                         cmdval_new = *vreg;
 984                 }
 985                 if (cmdval_new != cmdval)
 986                         patch_value(s, cmd_ptr(s, index+1), cmdval_new);
 987         }
 988
 989         /* only patch cmd. restore vreg value if changed in mmio write handler*/
 990         *vreg = vreg_old;
 991
 992         /* TODO
 993          * In order to let workload with inhibit context to generate
 994          * correct image data into memory, vregs values will be loaded to
 995          * hw via LRIs in the workload with inhibit context. But as
 996          * indirect context is loaded prior to LRIs in workload, we don't
 997          * want reg values specified in indirect context overwritten by
 998          * LRIs in workloads. So, when scanning an indirect context, we
 999          * update reg values in it into vregs, so LRIs in workload with
1000          * inhibit context will restore with correct values
1001          */
1002         if (IS_GEN(s->engine->i915, 9) &&
1003             intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1004             !strncmp(cmd, "lri", 3)) {
1005                 intel_gvt_hypervisor_read_gpa(s->vgpu,
1006                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1007                 /* check inhibit context */
1008                 if (ctx_sr_ctl & 1) {
1009                         u32 data = cmd_val(s, index + 1);
1010
1011                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1012                                 intel_vgpu_mask_mmio_write(vgpu,
1013                                                         offset, &data, 4);
1014                         else
1015                                 vgpu_vreg(vgpu, offset) = data;
1016                 }
1017         }
1018
1019         return 0;
1020 }
1021
1022 #define cmd_reg(s, i) \
1023         (cmd_val(s, i) & GENMASK(22, 2))
1024
1025 #define cmd_reg_inhibit(s, i) \
1026         (cmd_val(s, i) & GENMASK(22, 18))
1027
1028 #define cmd_gma(s, i) \
1029         (cmd_val(s, i) & GENMASK(31, 2))
1030
1031 #define cmd_gma_hi(s, i) \
1032         (cmd_val(s, i) & GENMASK(15, 0))
1033
1034 static int cmd_handler_lri(struct parser_exec_state *s)
1035 {
1036         int i, ret = 0;
1037         int cmd_len = cmd_length(s);
1038
1039         for (i = 1; i < cmd_len; i += 2) {
1040                 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1041                         if (s->engine->id == BCS0 &&
1042                             cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1043                                 ret |= 0;
1044                         else
1045                                 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1046                 }
1047                 if (ret)
1048                         break;
1049                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1050                 if (ret)
1051                         break;
1052         }
1053         return ret;
1054 }
1055
1056 static int cmd_handler_lrr(struct parser_exec_state *s)
1057 {
1058         int i, ret = 0;
1059         int cmd_len = cmd_length(s);
1060
1061         for (i = 1; i < cmd_len; i += 2) {
1062                 if (IS_BROADWELL(s->engine->i915))
1063                         ret |= ((cmd_reg_inhibit(s, i) ||
1064                                  (cmd_reg_inhibit(s, i + 1)))) ?
1065                                 -EBADRQC : 0;
1066                 if (ret)
1067                         break;
1068                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1069                 if (ret)
1070                         break;
1071                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1072                 if (ret)
1073                         break;
1074         }
1075         return ret;
1076 }
1077
1078 static inline int cmd_address_audit(struct parser_exec_state *s,
1079                 unsigned long guest_gma, int op_size, bool index_mode);
1080
1081 static int cmd_handler_lrm(struct parser_exec_state *s)
1082 {
1083         struct intel_gvt *gvt = s->vgpu->gvt;
1084         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1085         unsigned long gma;
1086         int i, ret = 0;
1087         int cmd_len = cmd_length(s);
1088
1089         for (i = 1; i < cmd_len;) {
1090                 if (IS_BROADWELL(s->engine->i915))
1091                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1092                 if (ret)
1093                         break;
1094                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1095                 if (ret)
1096                         break;
1097                 if (cmd_val(s, 0) & (1 << 22)) {
1098                         gma = cmd_gma(s, i + 1);
1099                         if (gmadr_bytes == 8)
1100                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1101                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1102                         if (ret)
1103                                 break;
1104                 }
1105                 i += gmadr_dw_number(s) + 1;
1106         }
1107         return ret;
1108 }
1109
1110 static int cmd_handler_srm(struct parser_exec_state *s)
1111 {
1112         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1113         unsigned long gma;
1114         int i, ret = 0;
1115         int cmd_len = cmd_length(s);
1116
1117         for (i = 1; i < cmd_len;) {
1118                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1119                 if (ret)
1120                         break;
1121                 if (cmd_val(s, 0) & (1 << 22)) {
1122                         gma = cmd_gma(s, i + 1);
1123                         if (gmadr_bytes == 8)
1124                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1125                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1126                         if (ret)
1127                                 break;
1128                 }
1129                 i += gmadr_dw_number(s) + 1;
1130         }
1131         return ret;
1132 }
1133
1134 struct cmd_interrupt_event {
1135         int pipe_control_notify;
1136         int mi_flush_dw;
1137         int mi_user_interrupt;
1138 };
1139
1140 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1141         [RCS0] = {
1142                 .pipe_control_notify = RCS_PIPE_CONTROL,
1143                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1144                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1145         },
1146         [BCS0] = {
1147                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1148                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1149                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1150         },
1151         [VCS0] = {
1152                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1153                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1154                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1155         },
1156         [VCS1] = {
1157                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1158                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1159                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1160         },
1161         [VECS0] = {
1162                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1163                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1164                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1165         },
1166 };
1167
1168 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1169 {
1170         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1171         unsigned long gma;
1172         bool index_mode = false;
1173         unsigned int post_sync;
1174         int ret = 0;
1175         u32 hws_pga, val;
1176
1177         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1178
1179         /* LRI post sync */
1180         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1181                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1182         /* post sync */
1183         else if (post_sync) {
1184                 if (post_sync == 2)
1185                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1186                 else if (post_sync == 3)
1187                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1188                 else if (post_sync == 1) {
1189                         /* check ggtt*/
1190                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1191                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1192                                 if (gmadr_bytes == 8)
1193                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1194                                 /* Store Data Index */
1195                                 if (cmd_val(s, 1) & (1 << 21))
1196                                         index_mode = true;
1197                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1198                                                 index_mode);
1199                                 if (ret)
1200                                         return ret;
1201                                 if (index_mode) {
1202                                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1203                                         gma = hws_pga + gma;
1204                                         patch_value(s, cmd_ptr(s, 2), gma);
1205                                         val = cmd_val(s, 1) & (~(1 << 21));
1206                                         patch_value(s, cmd_ptr(s, 1), val);
1207                                 }
1208                         }
1209                 }
1210         }
1211
1212         if (ret)
1213                 return ret;
1214
1215         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1216                 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1217                         s->workload->pending_events);
1218         return 0;
1219 }
1220
1221 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1222 {
1223         set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1224                 s->workload->pending_events);
1225         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1226         return 0;
1227 }
1228
1229 static int cmd_advance_default(struct parser_exec_state *s)
1230 {
1231         return ip_gma_advance(s, cmd_length(s));
1232 }
1233
1234 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1235 {
1236         int ret;
1237
1238         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1239                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1240                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1241                 s->buf_addr_type = s->saved_buf_addr_type;
1242         } else if (s->buf_type == RING_BUFFER_CTX) {
1243                 ret = ip_gma_set(s, s->ring_tail);
1244         } else {
1245                 s->buf_type = RING_BUFFER_INSTRUCTION;
1246                 s->buf_addr_type = GTT_BUFFER;
1247                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1248                         s->ret_ip_gma_ring -= s->ring_size;
1249                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1250         }
1251         return ret;
1252 }
1253
1254 struct mi_display_flip_command_info {
1255         int pipe;
1256         int plane;
1257         int event;
1258         i915_reg_t stride_reg;
1259         i915_reg_t ctrl_reg;
1260         i915_reg_t surf_reg;
1261         u64 stride_val;
1262         u64 tile_val;
1263         u64 surf_val;
1264         bool async_flip;
1265 };
1266
1267 struct plane_code_mapping {
1268         int pipe;
1269         int plane;
1270         int event;
1271 };
1272
1273 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1274                 struct mi_display_flip_command_info *info)
1275 {
1276         struct drm_i915_private *dev_priv = s->engine->i915;
1277         struct plane_code_mapping gen8_plane_code[] = {
1278                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1279                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1280                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1281                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1282                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1283                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1284         };
1285         u32 dword0, dword1, dword2;
1286         u32 v;
1287
1288         dword0 = cmd_val(s, 0);
1289         dword1 = cmd_val(s, 1);
1290         dword2 = cmd_val(s, 2);
1291
1292         v = (dword0 & GENMASK(21, 19)) >> 19;
1293         if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1294                 return -EBADRQC;
1295
1296         info->pipe = gen8_plane_code[v].pipe;
1297         info->plane = gen8_plane_code[v].plane;
1298         info->event = gen8_plane_code[v].event;
1299         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1300         info->tile_val = (dword1 & 0x1);
1301         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1302         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1303
1304         if (info->plane == PLANE_A) {
1305                 info->ctrl_reg = DSPCNTR(info->pipe);
1306                 info->stride_reg = DSPSTRIDE(info->pipe);
1307                 info->surf_reg = DSPSURF(info->pipe);
1308         } else if (info->plane == PLANE_B) {
1309                 info->ctrl_reg = SPRCTL(info->pipe);
1310                 info->stride_reg = SPRSTRIDE(info->pipe);
1311                 info->surf_reg = SPRSURF(info->pipe);
1312         } else {
1313                 drm_WARN_ON(&dev_priv->drm, 1);
1314                 return -EBADRQC;
1315         }
1316         return 0;
1317 }
1318
1319 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1320                 struct mi_display_flip_command_info *info)
1321 {
1322         struct drm_i915_private *dev_priv = s->engine->i915;
1323         struct intel_vgpu *vgpu = s->vgpu;
1324         u32 dword0 = cmd_val(s, 0);
1325         u32 dword1 = cmd_val(s, 1);
1326         u32 dword2 = cmd_val(s, 2);
1327         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1328
1329         info->plane = PRIMARY_PLANE;
1330
1331         switch (plane) {
1332         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1333                 info->pipe = PIPE_A;
1334                 info->event = PRIMARY_A_FLIP_DONE;
1335                 break;
1336         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1337                 info->pipe = PIPE_B;
1338                 info->event = PRIMARY_B_FLIP_DONE;
1339                 break;
1340         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1341                 info->pipe = PIPE_C;
1342                 info->event = PRIMARY_C_FLIP_DONE;
1343                 break;
1344
1345         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1346                 info->pipe = PIPE_A;
1347                 info->event = SPRITE_A_FLIP_DONE;
1348                 info->plane = SPRITE_PLANE;
1349                 break;
1350         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1351                 info->pipe = PIPE_B;
1352                 info->event = SPRITE_B_FLIP_DONE;
1353                 info->plane = SPRITE_PLANE;
1354                 break;
1355         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1356                 info->pipe = PIPE_C;
1357                 info->event = SPRITE_C_FLIP_DONE;
1358                 info->plane = SPRITE_PLANE;
1359                 break;
1360
1361         default:
1362                 gvt_vgpu_err("unknown plane code %d\n", plane);
1363                 return -EBADRQC;
1364         }
1365
1366         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1367         info->tile_val = (dword1 & GENMASK(2, 0));
1368         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1369         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1370
1371         info->ctrl_reg = DSPCNTR(info->pipe);
1372         info->stride_reg = DSPSTRIDE(info->pipe);
1373         info->surf_reg = DSPSURF(info->pipe);
1374
1375         return 0;
1376 }
1377
1378 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1379                 struct mi_display_flip_command_info *info)
1380 {
1381         u32 stride, tile;
1382
1383         if (!info->async_flip)
1384                 return 0;
1385
1386         if (INTEL_GEN(s->engine->i915) >= 9) {
1387                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1388                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1389                                 GENMASK(12, 10)) >> 10;
1390         } else {
1391                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1392                                 GENMASK(15, 6)) >> 6;
1393                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1394         }
1395
1396         if (stride != info->stride_val)
1397                 gvt_dbg_cmd("cannot change stride during async flip\n");
1398
1399         if (tile != info->tile_val)
1400                 gvt_dbg_cmd("cannot change tile during async flip\n");
1401
1402         return 0;
1403 }
1404
1405 static int gen8_update_plane_mmio_from_mi_display_flip(
1406                 struct parser_exec_state *s,
1407                 struct mi_display_flip_command_info *info)
1408 {
1409         struct drm_i915_private *dev_priv = s->engine->i915;
1410         struct intel_vgpu *vgpu = s->vgpu;
1411
1412         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1413                       info->surf_val << 12);
1414         if (INTEL_GEN(dev_priv) >= 9) {
1415                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1416                               info->stride_val);
1417                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1418                               info->tile_val << 10);
1419         } else {
1420                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1421                               info->stride_val << 6);
1422                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1423                               info->tile_val << 10);
1424         }
1425
1426         if (info->plane == PLANE_PRIMARY)
1427                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1428
1429         if (info->async_flip)
1430                 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1431         else
1432                 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1433
1434         return 0;
1435 }
1436
1437 static int decode_mi_display_flip(struct parser_exec_state *s,
1438                 struct mi_display_flip_command_info *info)
1439 {
1440         if (IS_BROADWELL(s->engine->i915))
1441                 return gen8_decode_mi_display_flip(s, info);
1442         if (INTEL_GEN(s->engine->i915) >= 9)
1443                 return skl_decode_mi_display_flip(s, info);
1444
1445         return -ENODEV;
1446 }
1447
1448 static int check_mi_display_flip(struct parser_exec_state *s,
1449                 struct mi_display_flip_command_info *info)
1450 {
1451         return gen8_check_mi_display_flip(s, info);
1452 }
1453
1454 static int update_plane_mmio_from_mi_display_flip(
1455                 struct parser_exec_state *s,
1456                 struct mi_display_flip_command_info *info)
1457 {
1458         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1459 }
1460
1461 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1462 {
1463         struct mi_display_flip_command_info info;
1464         struct intel_vgpu *vgpu = s->vgpu;
1465         int ret;
1466         int i;
1467         int len = cmd_length(s);
1468         u32 valid_len = CMD_LEN(1);
1469
1470         /* Flip Type == Stereo 3D Flip */
1471         if (DWORD_FIELD(2, 1, 0) == 2)
1472                 valid_len++;
1473         ret = gvt_check_valid_cmd_length(cmd_length(s),
1474                         valid_len);
1475         if (ret)
1476                 return ret;
1477
1478         ret = decode_mi_display_flip(s, &info);
1479         if (ret) {
1480                 gvt_vgpu_err("fail to decode MI display flip command\n");
1481                 return ret;
1482         }
1483
1484         ret = check_mi_display_flip(s, &info);
1485         if (ret) {
1486                 gvt_vgpu_err("invalid MI display flip command\n");
1487                 return ret;
1488         }
1489
1490         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1491         if (ret) {
1492                 gvt_vgpu_err("fail to update plane mmio\n");
1493                 return ret;
1494         }
1495
1496         for (i = 0; i < len; i++)
1497                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1498         return 0;
1499 }
1500
1501 static bool is_wait_for_flip_pending(u32 cmd)
1502 {
1503         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1504                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1505                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1506                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1507                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1508                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1509 }
1510
1511 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1512 {
1513         u32 cmd = cmd_val(s, 0);
1514
1515         if (!is_wait_for_flip_pending(cmd))
1516                 return 0;
1517
1518         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1519         return 0;
1520 }
1521
1522 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1523 {
1524         unsigned long addr;
1525         unsigned long gma_high, gma_low;
1526         struct intel_vgpu *vgpu = s->vgpu;
1527         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1528
1529         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1530                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1531                 return INTEL_GVT_INVALID_ADDR;
1532         }
1533
1534         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1535         if (gmadr_bytes == 4) {
1536                 addr = gma_low;
1537         } else {
1538                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1539                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1540         }
1541         return addr;
1542 }
1543
1544 static inline int cmd_address_audit(struct parser_exec_state *s,
1545                 unsigned long guest_gma, int op_size, bool index_mode)
1546 {
1547         struct intel_vgpu *vgpu = s->vgpu;
1548         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1549         int i;
1550         int ret;
1551
1552         if (op_size > max_surface_size) {
1553                 gvt_vgpu_err("command address audit fail name %s\n",
1554                         s->info->name);
1555                 return -EFAULT;
1556         }
1557
1558         if (index_mode) {
1559                 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1560                         ret = -EFAULT;
1561                         goto err;
1562                 }
1563         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1564                 ret = -EFAULT;
1565                 goto err;
1566         }
1567
1568         return 0;
1569
1570 err:
1571         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1572                         s->info->name, guest_gma, op_size);
1573
1574         pr_err("cmd dump: ");
1575         for (i = 0; i < cmd_length(s); i++) {
1576                 if (!(i % 4))
1577                         pr_err("\n%08x ", cmd_val(s, i));
1578                 else
1579                         pr_err("%08x ", cmd_val(s, i));
1580         }
1581         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1582                         vgpu->id,
1583                         vgpu_aperture_gmadr_base(vgpu),
1584                         vgpu_aperture_gmadr_end(vgpu),
1585                         vgpu_hidden_gmadr_base(vgpu),
1586                         vgpu_hidden_gmadr_end(vgpu));
1587         return ret;
1588 }
1589
1590 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1591 {
1592         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1593         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1594         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1595         unsigned long gma, gma_low, gma_high;
1596         u32 valid_len = CMD_LEN(2);
1597         int ret = 0;
1598
1599         /* check ppggt */
1600         if (!(cmd_val(s, 0) & (1 << 22)))
1601                 return 0;
1602
1603         /* check if QWORD */
1604         if (DWORD_FIELD(0, 21, 21))
1605                 valid_len++;
1606         ret = gvt_check_valid_cmd_length(cmd_length(s),
1607                         valid_len);
1608         if (ret)
1609                 return ret;
1610
1611         gma = cmd_val(s, 2) & GENMASK(31, 2);
1612
1613         if (gmadr_bytes == 8) {
1614                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1615                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1616                 gma = (gma_high << 32) | gma_low;
1617                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1618         }
1619         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1620         return ret;
1621 }
1622
1623 static inline int unexpected_cmd(struct parser_exec_state *s)
1624 {
1625         struct intel_vgpu *vgpu = s->vgpu;
1626
1627         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1628
1629         return -EBADRQC;
1630 }
1631
1632 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1633 {
1634         return unexpected_cmd(s);
1635 }
1636
1637 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1638 {
1639         return unexpected_cmd(s);
1640 }
1641
1642 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1643 {
1644         return unexpected_cmd(s);
1645 }
1646
1647 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1648 {
1649         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1650         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1651                         sizeof(u32);
1652         unsigned long gma, gma_high;
1653         u32 valid_len = CMD_LEN(1);
1654         int ret = 0;
1655
1656         if (!(cmd_val(s, 0) & (1 << 22)))
1657                 return ret;
1658
1659         /* check inline data */
1660         if (cmd_val(s, 0) & BIT(18))
1661                 valid_len = CMD_LEN(9);
1662         ret = gvt_check_valid_cmd_length(cmd_length(s),
1663                         valid_len);
1664         if (ret)
1665                 return ret;
1666
1667         gma = cmd_val(s, 1) & GENMASK(31, 2);
1668         if (gmadr_bytes == 8) {
1669                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1670                 gma = (gma_high << 32) | gma;
1671         }
1672         ret = cmd_address_audit(s, gma, op_size, false);
1673         return ret;
1674 }
1675
1676 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1677 {
1678         return unexpected_cmd(s);
1679 }
1680
1681 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1682 {
1683         return unexpected_cmd(s);
1684 }
1685
1686 static int cmd_handler_mi_conditional_batch_buffer_end(
1687                 struct parser_exec_state *s)
1688 {
1689         return unexpected_cmd(s);
1690 }
1691
1692 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1693 {
1694         return unexpected_cmd(s);
1695 }
1696
1697 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1698 {
1699         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1700         unsigned long gma;
1701         bool index_mode = false;
1702         int ret = 0;
1703         u32 hws_pga, val;
1704         u32 valid_len = CMD_LEN(2);
1705
1706         ret = gvt_check_valid_cmd_length(cmd_length(s),
1707                         valid_len);
1708         if (ret) {
1709                 /* Check again for Qword */
1710                 ret = gvt_check_valid_cmd_length(cmd_length(s),
1711                         ++valid_len);
1712                 return ret;
1713         }
1714
1715         /* Check post-sync and ppgtt bit */
1716         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1717                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1718                 if (gmadr_bytes == 8)
1719                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1720                 /* Store Data Index */
1721                 if (cmd_val(s, 0) & (1 << 21))
1722                         index_mode = true;
1723                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1724                 if (ret)
1725                         return ret;
1726                 if (index_mode) {
1727                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1728                         gma = hws_pga + gma;
1729                         patch_value(s, cmd_ptr(s, 1), gma);
1730                         val = cmd_val(s, 0) & (~(1 << 21));
1731                         patch_value(s, cmd_ptr(s, 0), val);
1732                 }
1733         }
1734         /* Check notify bit */
1735         if ((cmd_val(s, 0) & (1 << 8)))
1736                 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1737                         s->workload->pending_events);
1738         return ret;
1739 }
1740
1741 static void addr_type_update_snb(struct parser_exec_state *s)
1742 {
1743         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1744                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1745                 s->buf_addr_type = PPGTT_BUFFER;
1746         }
1747 }
1748
1749
1750 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1751                 unsigned long gma, unsigned long end_gma, void *va)
1752 {
1753         unsigned long copy_len, offset;
1754         unsigned long len = 0;
1755         unsigned long gpa;
1756
1757         while (gma != end_gma) {
1758                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1759                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1760                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1761                         return -EFAULT;
1762                 }
1763
1764                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1765
1766                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1767                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1768
1769                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1770
1771                 len += copy_len;
1772                 gma += copy_len;
1773         }
1774         return len;
1775 }
1776
1777
1778 /*
1779  * Check whether a batch buffer needs to be scanned. Currently
1780  * the only criteria is based on privilege.
1781  */
1782 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1783 {
1784         /* Decide privilege based on address space */
1785         if (cmd_val(s, 0) & BIT(8) &&
1786             !(s->vgpu->scan_nonprivbb & s->engine->mask))
1787                 return 0;
1788
1789         return 1;
1790 }
1791
1792 static const char *repr_addr_type(unsigned int type)
1793 {
1794         return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1795 }
1796
1797 static int find_bb_size(struct parser_exec_state *s,
1798                         unsigned long *bb_size,
1799                         unsigned long *bb_end_cmd_offset)
1800 {
1801         unsigned long gma = 0;
1802         const struct cmd_info *info;
1803         u32 cmd_len = 0;
1804         bool bb_end = false;
1805         struct intel_vgpu *vgpu = s->vgpu;
1806         u32 cmd;
1807         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1808                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1809
1810         *bb_size = 0;
1811         *bb_end_cmd_offset = 0;
1812
1813         /* get the start gm address of the batch buffer */
1814         gma = get_gma_bb_from_cmd(s, 1);
1815         if (gma == INTEL_GVT_INVALID_ADDR)
1816                 return -EFAULT;
1817
1818         cmd = cmd_val(s, 0);
1819         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1820         if (info == NULL) {
1821                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1822                              cmd, get_opcode(cmd, s->engine),
1823                              repr_addr_type(s->buf_addr_type),
1824                              s->engine->name, s->workload);
1825                 return -EBADRQC;
1826         }
1827         do {
1828                 if (copy_gma_to_hva(s->vgpu, mm,
1829                                     gma, gma + 4, &cmd) < 0)
1830                         return -EFAULT;
1831                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1832                 if (info == NULL) {
1833                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1834                                      cmd, get_opcode(cmd, s->engine),
1835                                      repr_addr_type(s->buf_addr_type),
1836                                      s->engine->name, s->workload);
1837                         return -EBADRQC;
1838                 }
1839
1840                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1841                         bb_end = true;
1842                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1843                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1844                                 /* chained batch buffer */
1845                                 bb_end = true;
1846                 }
1847
1848                 if (bb_end)
1849                         *bb_end_cmd_offset = *bb_size;
1850
1851                 cmd_len = get_cmd_length(info, cmd) << 2;
1852                 *bb_size += cmd_len;
1853                 gma += cmd_len;
1854         } while (!bb_end);
1855
1856         return 0;
1857 }
1858
1859 static int audit_bb_end(struct parser_exec_state *s, void *va)
1860 {
1861         struct intel_vgpu *vgpu = s->vgpu;
1862         u32 cmd = *(u32 *)va;
1863         const struct cmd_info *info;
1864
1865         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1866         if (info == NULL) {
1867                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1868                              cmd, get_opcode(cmd, s->engine),
1869                              repr_addr_type(s->buf_addr_type),
1870                              s->engine->name, s->workload);
1871                 return -EBADRQC;
1872         }
1873
1874         if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1875             ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1876              (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1877                 return 0;
1878
1879         return -EBADRQC;
1880 }
1881
1882 static int perform_bb_shadow(struct parser_exec_state *s)
1883 {
1884         struct intel_vgpu *vgpu = s->vgpu;
1885         struct intel_vgpu_shadow_bb *bb;
1886         unsigned long gma = 0;
1887         unsigned long bb_size;
1888         unsigned long bb_end_cmd_offset;
1889         int ret = 0;
1890         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1891                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1892         unsigned long start_offset = 0;
1893
1894         /* get the start gm address of the batch buffer */
1895         gma = get_gma_bb_from_cmd(s, 1);
1896         if (gma == INTEL_GVT_INVALID_ADDR)
1897                 return -EFAULT;
1898
1899         ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1900         if (ret)
1901                 return ret;
1902
1903         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1904         if (!bb)
1905                 return -ENOMEM;
1906
1907         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1908
1909         /* the start_offset stores the batch buffer's start gma's
1910          * offset relative to page boundary. so for non-privileged batch
1911          * buffer, the shadowed gem object holds exactly the same page
1912          * layout as original gem object. This is for the convience of
1913          * replacing the whole non-privilged batch buffer page to this
1914          * shadowed one in PPGTT at the same gma address. (this replacing
1915          * action is not implemented yet now, but may be necessary in
1916          * future).
1917          * for prileged batch buffer, we just change start gma address to
1918          * that of shadowed page.
1919          */
1920         if (bb->ppgtt)
1921                 start_offset = gma & ~I915_GTT_PAGE_MASK;
1922
1923         bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1924                                                round_up(bb_size + start_offset,
1925                                                         PAGE_SIZE));
1926         if (IS_ERR(bb->obj)) {
1927                 ret = PTR_ERR(bb->obj);
1928                 goto err_free_bb;
1929         }
1930
1931         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1932         if (IS_ERR(bb->va)) {
1933                 ret = PTR_ERR(bb->va);
1934                 goto err_free_obj;
1935         }
1936
1937         ret = copy_gma_to_hva(s->vgpu, mm,
1938                               gma, gma + bb_size,
1939                               bb->va + start_offset);
1940         if (ret < 0) {
1941                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1942                 ret = -EFAULT;
1943                 goto err_unmap;
1944         }
1945
1946         ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1947         if (ret)
1948                 goto err_unmap;
1949
1950         i915_gem_object_unlock(bb->obj);
1951         INIT_LIST_HEAD(&bb->list);
1952         list_add(&bb->list, &s->workload->shadow_bb);
1953
1954         bb->bb_start_cmd_va = s->ip_va;
1955
1956         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1957                 bb->bb_offset = s->ip_va - s->rb_va;
1958         else
1959                 bb->bb_offset = 0;
1960
1961         /*
1962          * ip_va saves the virtual address of the shadow batch buffer, while
1963          * ip_gma saves the graphics address of the original batch buffer.
1964          * As the shadow batch buffer is just a copy from the originial one,
1965          * it should be right to use shadow batch buffer'va and original batch
1966          * buffer's gma in pair. After all, we don't want to pin the shadow
1967          * buffer here (too early).
1968          */
1969         s->ip_va = bb->va + start_offset;
1970         s->ip_gma = gma;
1971         return 0;
1972 err_unmap:
1973         i915_gem_object_unpin_map(bb->obj);
1974 err_free_obj:
1975         i915_gem_object_put(bb->obj);
1976 err_free_bb:
1977         kfree(bb);
1978         return ret;
1979 }
1980
1981 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1982 {
1983         bool second_level;
1984         int ret = 0;
1985         struct intel_vgpu *vgpu = s->vgpu;
1986
1987         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1988                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1989                 return -EFAULT;
1990         }
1991
1992         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1993         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1994                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1995                 return -EFAULT;
1996         }
1997
1998         s->saved_buf_addr_type = s->buf_addr_type;
1999         addr_type_update_snb(s);
2000         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2001                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2002                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
2003         } else if (second_level) {
2004                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2005                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2006                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2007         }
2008
2009         if (batch_buffer_needs_scan(s)) {
2010                 ret = perform_bb_shadow(s);
2011                 if (ret < 0)
2012                         gvt_vgpu_err("invalid shadow batch buffer\n");
2013         } else {
2014                 /* emulate a batch buffer end to do return right */
2015                 ret = cmd_handler_mi_batch_buffer_end(s);
2016                 if (ret < 0)
2017                         return ret;
2018         }
2019         return ret;
2020 }
2021
2022 static int mi_noop_index;
2023
2024 static const struct cmd_info cmd_info[] = {
2025         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2026
2027         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2028                 0, 1, NULL},
2029
2030         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2031                 0, 1, cmd_handler_mi_user_interrupt},
2032
2033         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2034                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2035
2036         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2037
2038         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2039                 NULL},
2040
2041         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2042                 NULL},
2043
2044         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2045                 NULL},
2046
2047         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2048                 NULL},
2049
2050         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2051                 D_ALL, 0, 1, NULL},
2052
2053         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2054                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2055                 cmd_handler_mi_batch_buffer_end},
2056
2057         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2058                 0, 1, NULL},
2059
2060         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2061                 NULL},
2062
2063         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2064                 D_ALL, 0, 1, NULL},
2065
2066         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2067                 NULL},
2068
2069         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2070                 NULL},
2071
2072         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2073                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2074
2075         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2076                 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2077
2078         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2079
2080         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2081                 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2082
2083         {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2084                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2085                 NULL, CMD_LEN(0)},
2086
2087         {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2088                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2089                 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2090
2091         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2092                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2093
2094         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2095                 0, 8, cmd_handler_mi_store_data_index},
2096
2097         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2098                 D_ALL, 0, 8, cmd_handler_lri},
2099
2100         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2101                 cmd_handler_mi_update_gtt},
2102
2103         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2104                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2105                 cmd_handler_srm, CMD_LEN(2)},
2106
2107         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2108                 cmd_handler_mi_flush_dw},
2109
2110         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2111                 10, cmd_handler_mi_clflush},
2112
2113         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2114                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2115                 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2116
2117         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2118                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2119                 cmd_handler_lrm, CMD_LEN(2)},
2120
2121         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2122                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2123                 cmd_handler_lrr, CMD_LEN(1)},
2124
2125         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2126                 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2127                 8, NULL, CMD_LEN(2)},
2128
2129         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2130                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2131
2132         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2133                 ADDR_FIX_1(2), 8, NULL},
2134
2135         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2136                 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2137
2138         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2139                 8, cmd_handler_mi_op_2f},
2140
2141         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2142                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2143                 cmd_handler_mi_batch_buffer_start},
2144
2145         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2146                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2147                 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2148
2149         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2150                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2151
2152         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2153                 ADDR_FIX_2(4, 7), 8, NULL},
2154
2155         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2156                 0, 8, NULL},
2157
2158         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2159                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2160
2161         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2162
2163         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2164                 0, 8, NULL},
2165
2166         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2167                 ADDR_FIX_1(3), 8, NULL},
2168
2169         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2170                 D_ALL, 0, 8, NULL},
2171
2172         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2173                 ADDR_FIX_1(4), 8, NULL},
2174
2175         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2176                 ADDR_FIX_2(4, 5), 8, NULL},
2177
2178         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2179                 ADDR_FIX_1(4), 8, NULL},
2180
2181         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2182                 ADDR_FIX_2(4, 7), 8, NULL},
2183
2184         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2185                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2186
2187         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2188
2189         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2190                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2191
2192         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2193                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2194
2195         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2196                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2197                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2198
2199         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2200                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2201
2202         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2203                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2204
2205         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2206                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2207
2208         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2209                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2210
2211         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2212                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2213
2214         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2215                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2216                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2217
2218         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2219                 ADDR_FIX_2(4, 5), 8, NULL},
2220
2221         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2222                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2223
2224         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2225                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2226                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2227
2228         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2229                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2230                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2231
2232         {"3DSTATE_BLEND_STATE_POINTERS",
2233                 OP_3DSTATE_BLEND_STATE_POINTERS,
2234                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2235
2236         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2237                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2238                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2241                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2242                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2243
2244         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2245                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2246                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2249                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2250                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2251
2252         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2253                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2254                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2255
2256         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2257                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2258                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2259
2260         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2261                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2262                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263
2264         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2265                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2266                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2267
2268         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2269                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2270                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2273                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2274                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2277                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2278                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2279
2280         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2281                 0, 8, NULL},
2282
2283         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2284                 0, 8, NULL},
2285
2286         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2287                 0, 8, NULL},
2288
2289         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2290                 0, 8, NULL},
2291
2292         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2293                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2294
2295         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2296                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2297
2298         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2299                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2300
2301         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2302                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2303
2304         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2305                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2306
2307         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2308                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2309
2310         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2311                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2312
2313         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2314                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2315
2316         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2317                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2318
2319         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2320                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2321
2322         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2323                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324
2325         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2326                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2327
2328         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2329                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2330
2331         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2332                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2333
2334         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2335                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2336
2337         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2338                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2339
2340         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2341                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2342
2343         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2344                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2345
2346         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2347                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2348
2349         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2350                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2351
2352         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2353                 D_BDW_PLUS, 0, 8, NULL},
2354
2355         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2356                 NULL},
2357
2358         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2359                 D_BDW_PLUS, 0, 8, NULL},
2360
2361         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2362                 D_BDW_PLUS, 0, 8, NULL},
2363
2364         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2365                 8, NULL},
2366
2367         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2368                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2369
2370         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2371                 8, NULL},
2372
2373         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2374                 NULL},
2375
2376         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2377                 NULL},
2378
2379         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2380                 NULL},
2381
2382         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2383                 D_BDW_PLUS, 0, 8, NULL},
2384
2385         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2386                 R_RCS, D_ALL, 0, 8, NULL},
2387
2388         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2389                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2390
2391         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2392                 R_RCS, D_ALL, 0, 1, NULL},
2393
2394         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2395
2396         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2397                 R_RCS, D_ALL, 0, 8, NULL},
2398
2399         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2400                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2401
2402         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2403
2404         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2405
2406         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2407
2408         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2409                 D_BDW_PLUS, 0, 8, NULL},
2410
2411         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2412                 D_BDW_PLUS, 0, 8, NULL},
2413
2414         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2415                 D_ALL, 0, 8, NULL},
2416
2417         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2418                 D_BDW_PLUS, 0, 8, NULL},
2419
2420         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2421                 D_BDW_PLUS, 0, 8, NULL},
2422
2423         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2424
2425         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2426
2427         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2428
2429         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2430                 D_ALL, 0, 8, NULL},
2431
2432         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2433
2434         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2435
2436         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2437                 R_RCS, D_ALL, 0, 8, NULL},
2438
2439         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2440                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2441
2442         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2443                 0, 8, NULL},
2444
2445         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2446                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2447
2448         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2449                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2450
2451         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2452                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2453
2454         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2455                 D_ALL, 0, 8, NULL},
2456
2457         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2458                 D_ALL, 0, 8, NULL},
2459
2460         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2461                 D_ALL, 0, 8, NULL},
2462
2463         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2464                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2465
2466         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2467                 D_BDW_PLUS, 0, 8, NULL},
2468
2469         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2470                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2471
2472         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2473                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2474
2475         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2476                 R_RCS, D_ALL, 0, 8, NULL},
2477
2478         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2479                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2480
2481         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2482                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2483
2484         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2485                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2486
2487         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2488                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2489
2490         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2491                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2492
2493         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2494                 R_RCS, D_ALL, 0, 8, NULL},
2495
2496         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2497                 D_ALL, 0, 9, NULL},
2498
2499         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2500                 ADDR_FIX_2(2, 4), 8, NULL},
2501
2502         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2503                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2504                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2505
2506         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2507                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2508
2509         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2510                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2511                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2512
2513         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2514                 D_BDW_PLUS, 0, 8, NULL},
2515
2516         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2517                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2518
2519         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2520
2521         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2522                 1, NULL},
2523
2524         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2525                 ADDR_FIX_1(1), 8, NULL},
2526
2527         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2528
2529         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2530                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2531
2532         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2533                 ADDR_FIX_1(1), 8, NULL},
2534
2535         {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2536                 F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2537
2538         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2539
2540         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2541
2542         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2543                 0, 8, NULL},
2544
2545         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2546                 D_SKL_PLUS, 0, 8, NULL},
2547
2548         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2549                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2550
2551         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2552                 0, 16, NULL},
2553
2554         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2555                 0, 16, NULL},
2556
2557         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2558                 0, 16, NULL},
2559
2560         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2561
2562         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2563                 0, 16, NULL},
2564
2565         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2566                 0, 16, NULL},
2567
2568         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2569                 0, 16, NULL},
2570
2571         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2572                 0, 8, NULL},
2573
2574         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2575                 NULL},
2576
2577         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2578                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2579
2580         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2581                 R_VCS, D_ALL, 0, 12, NULL},
2582
2583         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2584                 R_VCS, D_ALL, 0, 12, NULL},
2585
2586         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2587                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2588
2589         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2590                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2591
2592         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2593                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2594
2595         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2596
2597         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2598                 R_VCS, D_ALL, 0, 12, NULL},
2599
2600         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2601                 R_VCS, D_ALL, 0, 12, NULL},
2602
2603         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2604                 R_VCS, D_ALL, 0, 12, NULL},
2605
2606         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2607                 R_VCS, D_ALL, 0, 12, NULL},
2608
2609         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2610                 R_VCS, D_ALL, 0, 12, NULL},
2611
2612         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2613                 R_VCS, D_ALL, 0, 12, NULL},
2614
2615         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2616                 R_VCS, D_ALL, 0, 6, NULL},
2617
2618         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2619                 R_VCS, D_ALL, 0, 12, NULL},
2620
2621         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2622                 R_VCS, D_ALL, 0, 12, NULL},
2623
2624         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2625                 R_VCS, D_ALL, 0, 12, NULL},
2626
2627         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2628                 R_VCS, D_ALL, 0, 12, NULL},
2629
2630         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2631                 R_VCS, D_ALL, 0, 12, NULL},
2632
2633         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2634                 R_VCS, D_ALL, 0, 12, NULL},
2635
2636         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2637                 R_VCS, D_ALL, 0, 12, NULL},
2638         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2639                 R_VCS, D_ALL, 0, 12, NULL},
2640
2641         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2642                 R_VCS, D_ALL, 0, 12, NULL},
2643
2644         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2645                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2646
2647         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2648                 R_VCS, D_ALL, 0, 12, NULL},
2649
2650         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2651                 R_VCS, D_ALL, 0, 12, NULL},
2652
2653         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2654                 R_VCS, D_ALL, 0, 12, NULL},
2655
2656         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2657                 R_VCS, D_ALL, 0, 12, NULL},
2658
2659         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2660                 R_VCS, D_ALL, 0, 12, NULL},
2661
2662         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2663                 R_VCS, D_ALL, 0, 12, NULL},
2664
2665         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2666                 R_VCS, D_ALL, 0, 12, NULL},
2667
2668         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2669                 R_VCS, D_ALL, 0, 12, NULL},
2670
2671         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2672                 R_VCS, D_ALL, 0, 12, NULL},
2673
2674         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2675                 R_VCS, D_ALL, 0, 12, NULL},
2676
2677         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2678                 R_VCS, D_ALL, 0, 12, NULL},
2679
2680         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2681                 0, 16, NULL},
2682
2683         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2684
2685         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2686
2687         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2688                 R_VCS, D_ALL, 0, 12, NULL},
2689
2690         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2691                 R_VCS, D_ALL, 0, 12, NULL},
2692
2693         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2694                 R_VCS, D_ALL, 0, 12, NULL},
2695
2696         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2697
2698         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2699                 0, 12, NULL},
2700
2701         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2702                 0, 12, NULL},
2703 };
2704
2705 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2706 {
2707         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2708 }
2709
2710 /* call the cmd handler, and advance ip */
2711 static int cmd_parser_exec(struct parser_exec_state *s)
2712 {
2713         struct intel_vgpu *vgpu = s->vgpu;
2714         const struct cmd_info *info;
2715         u32 cmd;
2716         int ret = 0;
2717
2718         cmd = cmd_val(s, 0);
2719
2720         /* fastpath for MI_NOOP */
2721         if (cmd == MI_NOOP)
2722                 info = &cmd_info[mi_noop_index];
2723         else
2724                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2725
2726         if (info == NULL) {
2727                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2728                              cmd, get_opcode(cmd, s->engine),
2729                              repr_addr_type(s->buf_addr_type),
2730                              s->engine->name, s->workload);
2731                 return -EBADRQC;
2732         }
2733
2734         s->info = info;
2735
2736         trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2737                           cmd_length(s), s->buf_type, s->buf_addr_type,
2738                           s->workload, info->name);
2739
2740         if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2741                 ret = gvt_check_valid_cmd_length(cmd_length(s),
2742                                                  info->valid_len);
2743                 if (ret)
2744                         return ret;
2745         }
2746
2747         if (info->handler) {
2748                 ret = info->handler(s);
2749                 if (ret < 0) {
2750                         gvt_vgpu_err("%s handler error\n", info->name);
2751                         return ret;
2752                 }
2753         }
2754
2755         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2756                 ret = cmd_advance_default(s);
2757                 if (ret) {
2758                         gvt_vgpu_err("%s IP advance error\n", info->name);
2759                         return ret;
2760                 }
2761         }
2762         return 0;
2763 }
2764
2765 static inline bool gma_out_of_range(unsigned long gma,
2766                 unsigned long gma_head, unsigned int gma_tail)
2767 {
2768         if (gma_tail >= gma_head)
2769                 return (gma < gma_head) || (gma > gma_tail);
2770         else
2771                 return (gma > gma_tail) && (gma < gma_head);
2772 }
2773
2774 /* Keep the consistent return type, e.g EBADRQC for unknown
2775  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2776  * works as the input of VM healthy status.
2777  */
2778 static int command_scan(struct parser_exec_state *s,
2779                 unsigned long rb_head, unsigned long rb_tail,
2780                 unsigned long rb_start, unsigned long rb_len)
2781 {
2782
2783         unsigned long gma_head, gma_tail, gma_bottom;
2784         int ret = 0;
2785         struct intel_vgpu *vgpu = s->vgpu;
2786
2787         gma_head = rb_start + rb_head;
2788         gma_tail = rb_start + rb_tail;
2789         gma_bottom = rb_start +  rb_len;
2790
2791         while (s->ip_gma != gma_tail) {
2792                 if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2793                                 s->buf_type == RING_BUFFER_CTX) {
2794                         if (!(s->ip_gma >= rb_start) ||
2795                                 !(s->ip_gma < gma_bottom)) {
2796                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2797                                         "(base:0x%lx, bottom: 0x%lx)\n",
2798                                         s->ip_gma, rb_start,
2799                                         gma_bottom);
2800                                 parser_exec_state_dump(s);
2801                                 return -EFAULT;
2802                         }
2803                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2804                                 gvt_vgpu_err("ip_gma %lx out of range."
2805                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2806                                         s->ip_gma, rb_start,
2807                                         rb_head, rb_tail);
2808                                 parser_exec_state_dump(s);
2809                                 break;
2810                         }
2811                 }
2812                 ret = cmd_parser_exec(s);
2813                 if (ret) {
2814                         gvt_vgpu_err("cmd parser error\n");
2815                         parser_exec_state_dump(s);
2816                         break;
2817                 }
2818         }
2819
2820         return ret;
2821 }
2822
2823 static int scan_workload(struct intel_vgpu_workload *workload)
2824 {
2825         unsigned long gma_head, gma_tail, gma_bottom;
2826         struct parser_exec_state s;
2827         int ret = 0;
2828
2829         /* ring base is page aligned */
2830         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2831                 return -EINVAL;
2832
2833         gma_head = workload->rb_start + workload->rb_head;
2834         gma_tail = workload->rb_start + workload->rb_tail;
2835         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2836
2837         s.buf_type = RING_BUFFER_INSTRUCTION;
2838         s.buf_addr_type = GTT_BUFFER;
2839         s.vgpu = workload->vgpu;
2840         s.engine = workload->engine;
2841         s.ring_start = workload->rb_start;
2842         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2843         s.ring_head = gma_head;
2844         s.ring_tail = gma_tail;
2845         s.rb_va = workload->shadow_ring_buffer_va;
2846         s.workload = workload;
2847         s.is_ctx_wa = false;
2848
2849         if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2850                 return 0;
2851
2852         ret = ip_gma_set(&s, gma_head);
2853         if (ret)
2854                 goto out;
2855
2856         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2857                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2858
2859 out:
2860         return ret;
2861 }
2862
2863 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2864 {
2865
2866         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2867         struct parser_exec_state s;
2868         int ret = 0;
2869         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2870                                 struct intel_vgpu_workload,
2871                                 wa_ctx);
2872
2873         /* ring base is page aligned */
2874         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2875                                         I915_GTT_PAGE_SIZE)))
2876                 return -EINVAL;
2877
2878         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2879         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2880                         PAGE_SIZE);
2881         gma_head = wa_ctx->indirect_ctx.guest_gma;
2882         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2883         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2884
2885         s.buf_type = RING_BUFFER_INSTRUCTION;
2886         s.buf_addr_type = GTT_BUFFER;
2887         s.vgpu = workload->vgpu;
2888         s.engine = workload->engine;
2889         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2890         s.ring_size = ring_size;
2891         s.ring_head = gma_head;
2892         s.ring_tail = gma_tail;
2893         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2894         s.workload = workload;
2895         s.is_ctx_wa = true;
2896
2897         ret = ip_gma_set(&s, gma_head);
2898         if (ret)
2899                 goto out;
2900
2901         ret = command_scan(&s, 0, ring_tail,
2902                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2903 out:
2904         return ret;
2905 }
2906
2907 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2908 {
2909         struct intel_vgpu *vgpu = workload->vgpu;
2910         struct intel_vgpu_submission *s = &vgpu->submission;
2911         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2912         void *shadow_ring_buffer_va;
2913         int ret;
2914
2915         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2916
2917         /* calculate workload ring buffer size */
2918         workload->rb_len = (workload->rb_tail + guest_rb_size -
2919                         workload->rb_head) % guest_rb_size;
2920
2921         gma_head = workload->rb_start + workload->rb_head;
2922         gma_tail = workload->rb_start + workload->rb_tail;
2923         gma_top = workload->rb_start + guest_rb_size;
2924
2925         if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2926                 void *p;
2927
2928                 /* realloc the new ring buffer if needed */
2929                 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2930                              workload->rb_len, GFP_KERNEL);
2931                 if (!p) {
2932                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2933                         return -ENOMEM;
2934                 }
2935                 s->ring_scan_buffer[workload->engine->id] = p;
2936                 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2937         }
2938
2939         shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2940
2941         /* get shadow ring buffer va */
2942         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2943
2944         /* head > tail --> copy head <-> top */
2945         if (gma_head > gma_tail) {
2946                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2947                                       gma_head, gma_top, shadow_ring_buffer_va);
2948                 if (ret < 0) {
2949                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2950                         return ret;
2951                 }
2952                 shadow_ring_buffer_va += ret;
2953                 gma_head = workload->rb_start;
2954         }
2955
2956         /* copy head or start <-> tail */
2957         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2958                                 shadow_ring_buffer_va);
2959         if (ret < 0) {
2960                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2961                 return ret;
2962         }
2963         return 0;
2964 }
2965
2966 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2967 {
2968         int ret;
2969         struct intel_vgpu *vgpu = workload->vgpu;
2970
2971         ret = shadow_workload_ring_buffer(workload);
2972         if (ret) {
2973                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2974                 return ret;
2975         }
2976
2977         ret = scan_workload(workload);
2978         if (ret) {
2979                 gvt_vgpu_err("scan workload error\n");
2980                 return ret;
2981         }
2982         return 0;
2983 }
2984
2985 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2986 {
2987         int ctx_size = wa_ctx->indirect_ctx.size;
2988         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2989         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2990                                         struct intel_vgpu_workload,
2991                                         wa_ctx);
2992         struct intel_vgpu *vgpu = workload->vgpu;
2993         struct drm_i915_gem_object *obj;
2994         int ret = 0;
2995         void *map;
2996
2997         obj = i915_gem_object_create_shmem(workload->engine->i915,
2998                                            roundup(ctx_size + CACHELINE_BYTES,
2999                                                    PAGE_SIZE));
3000         if (IS_ERR(obj))
3001                 return PTR_ERR(obj);
3002
3003         /* get the va of the shadow batch buffer */
3004         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3005         if (IS_ERR(map)) {
3006                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3007                 ret = PTR_ERR(map);
3008                 goto put_obj;
3009         }
3010
3011         i915_gem_object_lock(obj, NULL);
3012         ret = i915_gem_object_set_to_cpu_domain(obj, false);
3013         i915_gem_object_unlock(obj);
3014         if (ret) {
3015                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3016                 goto unmap_src;
3017         }
3018
3019         ret = copy_gma_to_hva(workload->vgpu,
3020                                 workload->vgpu->gtt.ggtt_mm,
3021                                 guest_gma, guest_gma + ctx_size,
3022                                 map);
3023         if (ret < 0) {
3024                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
3025                 goto unmap_src;
3026         }
3027
3028         wa_ctx->indirect_ctx.obj = obj;
3029         wa_ctx->indirect_ctx.shadow_va = map;
3030         return 0;
3031
3032 unmap_src:
3033         i915_gem_object_unpin_map(obj);
3034 put_obj:
3035         i915_gem_object_put(obj);
3036         return ret;
3037 }
3038
3039 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3040 {
3041         u32 per_ctx_start[CACHELINE_DWORDS] = {0};
3042         unsigned char *bb_start_sva;
3043
3044         if (!wa_ctx->per_ctx.valid)
3045                 return 0;
3046
3047         per_ctx_start[0] = 0x18800001;
3048         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3049
3050         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3051                                 wa_ctx->indirect_ctx.size;
3052
3053         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3054
3055         return 0;
3056 }
3057
3058 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3059 {
3060         int ret;
3061         struct intel_vgpu_workload *workload = container_of(wa_ctx,
3062                                         struct intel_vgpu_workload,
3063                                         wa_ctx);
3064         struct intel_vgpu *vgpu = workload->vgpu;
3065
3066         if (wa_ctx->indirect_ctx.size == 0)
3067                 return 0;
3068
3069         ret = shadow_indirect_ctx(wa_ctx);
3070         if (ret) {
3071                 gvt_vgpu_err("fail to shadow indirect ctx\n");
3072                 return ret;
3073         }
3074
3075         combine_wa_ctx(wa_ctx);
3076
3077         ret = scan_wa_ctx(wa_ctx);
3078         if (ret) {
3079                 gvt_vgpu_err("scan wa ctx error\n");
3080                 return ret;
3081         }
3082
3083         return 0;
3084 }
3085
3086 /* generate dummy contexts by sending empty requests to HW, and let
3087  * the HW to fill Engine Contexts. This dummy contexts are used for
3088  * initialization purpose (update reg whitelist), so referred to as
3089  * init context here
3090  */
3091 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3092 {
3093         const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3094         struct intel_gvt *gvt = vgpu->gvt;
3095         struct intel_engine_cs *engine;
3096         enum intel_engine_id id;
3097
3098         if (gvt->is_reg_whitelist_updated)
3099                 return;
3100
3101         /* scan init ctx to update cmd accessible list */
3102         for_each_engine(engine, gvt->gt, id) {
3103                 struct parser_exec_state s;
3104                 void *vaddr;
3105                 int ret;
3106
3107                 if (!engine->default_state)
3108                         continue;
3109
3110                 vaddr = shmem_pin_map(engine->default_state);
3111                 if (IS_ERR(vaddr)) {
3112                         gvt_err("failed to map %s->default state, err:%zd\n",
3113                                 engine->name, PTR_ERR(vaddr));
3114                         return;
3115                 }
3116
3117                 s.buf_type = RING_BUFFER_CTX;
3118                 s.buf_addr_type = GTT_BUFFER;
3119                 s.vgpu = vgpu;
3120                 s.engine = engine;
3121                 s.ring_start = 0;
3122                 s.ring_size = engine->context_size - start;
3123                 s.ring_head = 0;
3124                 s.ring_tail = s.ring_size;
3125                 s.rb_va = vaddr + start;
3126                 s.workload = NULL;
3127                 s.is_ctx_wa = false;
3128                 s.is_init_ctx = true;
3129
3130                 /* skipping the first RING_CTX_SIZE(0x50) dwords */
3131                 ret = ip_gma_set(&s, RING_CTX_SIZE);
3132                 if (ret == 0) {
3133                         ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3134                         if (ret)
3135                                 gvt_err("Scan init ctx error\n");
3136                 }
3137
3138                 shmem_unpin_map(engine->default_state, vaddr);
3139                 if (ret)
3140                         return;
3141         }
3142
3143         gvt->is_reg_whitelist_updated = true;
3144 }
3145
3146 int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3147 {
3148         struct intel_vgpu *vgpu = workload->vgpu;
3149         unsigned long gma_head, gma_tail, gma_start, ctx_size;
3150         struct parser_exec_state s;
3151         int ring_id = workload->engine->id;
3152         struct intel_context *ce = vgpu->submission.shadow[ring_id];
3153         int ret;
3154
3155         GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3156
3157         ctx_size = workload->engine->context_size - PAGE_SIZE;
3158
3159         /* Only ring contxt is loaded to HW for inhibit context, no need to
3160          * scan engine context
3161          */
3162         if (is_inhibit_context(ce))
3163                 return 0;
3164
3165         gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3166         gma_head = 0;
3167         gma_tail = ctx_size;
3168
3169         s.buf_type = RING_BUFFER_CTX;
3170         s.buf_addr_type = GTT_BUFFER;
3171         s.vgpu = workload->vgpu;
3172         s.engine = workload->engine;
3173         s.ring_start = gma_start;
3174         s.ring_size = ctx_size;
3175         s.ring_head = gma_start + gma_head;
3176         s.ring_tail = gma_start + gma_tail;
3177         s.rb_va = ce->lrc_reg_state;
3178         s.workload = workload;
3179         s.is_ctx_wa = false;
3180         s.is_init_ctx = false;
3181
3182         /* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3183          * context
3184          */
3185         ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3186         if (ret)
3187                 goto out;
3188
3189         ret = command_scan(&s, gma_head, gma_tail,
3190                 gma_start, ctx_size);
3191 out:
3192         if (ret)
3193                 gvt_vgpu_err("scan shadow ctx error\n");
3194
3195         return ret;
3196 }
3197
3198 static int init_cmd_table(struct intel_gvt *gvt)
3199 {
3200         unsigned int gen_type = intel_gvt_get_device_type(gvt);
3201         int i;
3202
3203         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3204                 struct cmd_entry *e;
3205
3206                 if (!(cmd_info[i].devices & gen_type))
3207                         continue;
3208
3209                 e = kzalloc(sizeof(*e), GFP_KERNEL);
3210                 if (!e)
3211                         return -ENOMEM;
3212
3213                 e->info = &cmd_info[i];
3214                 if (cmd_info[i].opcode == OP_MI_NOOP)
3215                         mi_noop_index = i;
3216
3217                 INIT_HLIST_NODE(&e->hlist);
3218                 add_cmd_entry(gvt, e);
3219                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3220                             e->info->name, e->info->opcode, e->info->flag,
3221                             e->info->devices, e->info->rings);
3222         }
3223
3224         return 0;
3225 }
3226
3227 static void clean_cmd_table(struct intel_gvt *gvt)
3228 {
3229         struct hlist_node *tmp;
3230         struct cmd_entry *e;
3231         int i;
3232
3233         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3234                 kfree(e);
3235
3236         hash_init(gvt->cmd_table);
3237 }
3238
3239 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3240 {
3241         clean_cmd_table(gvt);
3242 }
3243
3244 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3245 {
3246         int ret;
3247
3248         ret = init_cmd_table(gvt);
3249         if (ret) {
3250                 intel_gvt_clean_cmd_parser(gvt);
3251                 return ret;
3252         }
3253         return 0;
3254 }