drivers/gpu/drm/i915/gt/uc/intel_uc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #include "gt/intel_gt.h"
   7 #include "gt/intel_reset.h"
   8 #include "intel_guc.h"
   9 #include "intel_guc_ads.h"
  10 #include "intel_guc_submission.h"
  11 #include "intel_uc.h"
  12
  13 #include "i915_drv.h"
  14
  15 static const struct intel_uc_ops uc_ops_off;
  16 static const struct intel_uc_ops uc_ops_on;
  17
  18 static void uc_expand_default_options(struct intel_uc *uc)
  19 {
  20         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  21
  22         if (i915->params.enable_guc != -1)
  23                 return;
  24
  25         /* Don't enable GuC/HuC on pre-Gen12 */
  26         if (GRAPHICS_VER(i915) < 12) {
  27                 i915->params.enable_guc = 0;
  28                 return;
  29         }
  30
  31         /* Don't enable GuC/HuC on older Gen12 platforms */
  32         if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
  33                 i915->params.enable_guc = 0;
  34                 return;
  35         }
  36
  37         /* Intermediate platforms are HuC authentication only */
  38         if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) {
  39                 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
  40                 return;
  41         }
  42
  43         /* Default: enable HuC authentication and GuC submission */
  44         i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
  45 }
  46
  47 /* Reset GuC providing us with fresh state for both GuC and HuC.
  48  */
  49 static int __intel_uc_reset_hw(struct intel_uc *uc)
  50 {
  51         struct intel_gt *gt = uc_to_gt(uc);
  52         int ret;
  53         u32 guc_status;
  54
  55         ret = i915_inject_probe_error(gt->i915, -ENXIO);
  56         if (ret)
  57                 return ret;
  58
  59         ret = intel_reset_guc(gt);
  60         if (ret) {
  61                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  62                 return ret;
  63         }
  64
  65         guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
  66         WARN(!(guc_status & GS_MIA_IN_RESET),
  67              "GuC status: 0x%x, MIA core expected to be in reset\n",
  68              guc_status);
  69
  70         return ret;
  71 }
  72
  73 static void __confirm_options(struct intel_uc *uc)
  74 {
  75         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  76
  77         drm_dbg(&i915->drm,
  78                 "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
  79                 i915->params.enable_guc,
  80                 yesno(intel_uc_wants_guc(uc)),
  81                 yesno(intel_uc_wants_guc_submission(uc)),
  82                 yesno(intel_uc_wants_huc(uc)),
  83                 yesno(intel_uc_wants_guc_slpc(uc)));
  84
  85         if (i915->params.enable_guc == 0) {
  86                 GEM_BUG_ON(intel_uc_wants_guc(uc));
  87                 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
  88                 GEM_BUG_ON(intel_uc_wants_huc(uc));
  89                 GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
  90                 return;
  91         }
  92
  93         if (!intel_uc_supports_guc(uc))
  94                 drm_info(&i915->drm,
  95                          "Incompatible option enable_guc=%d - %s\n",
  96                          i915->params.enable_guc, "GuC is not supported!");
  97
  98         if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
  99             !intel_uc_supports_huc(uc))
 100                 drm_info(&i915->drm,
 101                          "Incompatible option enable_guc=%d - %s\n",
 102                          i915->params.enable_guc, "HuC is not supported!");
 103
 104         if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
 105             !intel_uc_supports_guc_submission(uc))
 106                 drm_info(&i915->drm,
 107                          "Incompatible option enable_guc=%d - %s\n",
 108                          i915->params.enable_guc, "GuC submission is N/A");
 109
 110         if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
 111                 drm_info(&i915->drm,
 112                          "Incompatible option enable_guc=%d - %s\n",
 113                          i915->params.enable_guc, "undocumented flag");
 114 }
 115
 116 void intel_uc_init_early(struct intel_uc *uc)
 117 {
 118         uc_expand_default_options(uc);
 119
 120         intel_guc_init_early(&uc->guc);
 121         intel_huc_init_early(&uc->huc);
 122
 123         __confirm_options(uc);
 124
 125         if (intel_uc_wants_guc(uc))
 126                 uc->ops = &uc_ops_on;
 127         else
 128                 uc->ops = &uc_ops_off;
 129 }
 130
 131 void intel_uc_init_late(struct intel_uc *uc)
 132 {
 133         intel_guc_init_late(&uc->guc);
 134 }
 135
 136 void intel_uc_driver_late_release(struct intel_uc *uc)
 137 {
 138 }
 139
 140 /**
 141  * intel_uc_init_mmio - setup uC MMIO access
 142  * @uc: the intel_uc structure
 143  *
 144  * Setup minimal state necessary for MMIO accesses later in the
 145  * initialization sequence.
 146  */
 147 void intel_uc_init_mmio(struct intel_uc *uc)
 148 {
 149         intel_guc_init_send_regs(&uc->guc);
 150 }
 151
 152 static void __uc_capture_load_err_log(struct intel_uc *uc)
 153 {
 154         struct intel_guc *guc = &uc->guc;
 155
 156         if (guc->log.vma && !uc->load_err_log)
 157                 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 158 }
 159
 160 static void __uc_free_load_err_log(struct intel_uc *uc)
 161 {
 162         struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
 163
 164         if (log)
 165                 i915_gem_object_put(log);
 166 }
 167
 168 void intel_uc_driver_remove(struct intel_uc *uc)
 169 {
 170         intel_uc_fini_hw(uc);
 171         intel_uc_fini(uc);
 172         __uc_free_load_err_log(uc);
 173 }
 174
 175 static inline bool guc_communication_enabled(struct intel_guc *guc)
 176 {
 177         return intel_guc_ct_enabled(&guc->ct);
 178 }
 179
 180 /*
 181  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
 182  * register using the same bits used in the CT message payload. Since our
 183  * communication channel with guc is turned off at this point, we can save the
 184  * message and handle it after we turn it back on.
 185  */
 186 static void guc_clear_mmio_msg(struct intel_guc *guc)
 187 {
 188         intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
 189 }
 190
 191 static void guc_get_mmio_msg(struct intel_guc *guc)
 192 {
 193         u32 val;
 194
 195         spin_lock_irq(&guc->irq_lock);
 196
 197         val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
 198         guc->mmio_msg |= val & guc->msg_enabled_mask;
 199
 200         /*
 201          * clear all events, including the ones we're not currently servicing,
 202          * to make sure we don't try to process a stale message if we enable
 203          * handling of more events later.
 204          */
 205         guc_clear_mmio_msg(guc);
 206
 207         spin_unlock_irq(&guc->irq_lock);
 208 }
 209
 210 static void guc_handle_mmio_msg(struct intel_guc *guc)
 211 {
 212         /* we need communication to be enabled to reply to GuC */
 213         GEM_BUG_ON(!guc_communication_enabled(guc));
 214
 215         spin_lock_irq(&guc->irq_lock);
 216         if (guc->mmio_msg) {
 217                 intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
 218                 guc->mmio_msg = 0;
 219         }
 220         spin_unlock_irq(&guc->irq_lock);
 221 }
 222
 223 static int guc_enable_communication(struct intel_guc *guc)
 224 {
 225         struct intel_gt *gt = guc_to_gt(guc);
 226         struct drm_i915_private *i915 = gt->i915;
 227         int ret;
 228
 229         GEM_BUG_ON(guc_communication_enabled(guc));
 230
 231         ret = i915_inject_probe_error(i915, -ENXIO);
 232         if (ret)
 233                 return ret;
 234
 235         ret = intel_guc_ct_enable(&guc->ct);
 236         if (ret)
 237                 return ret;
 238
 239         /* check for mmio messages received before/during the CT enable */
 240         guc_get_mmio_msg(guc);
 241         guc_handle_mmio_msg(guc);
 242
 243         intel_guc_enable_interrupts(guc);
 244
 245         /* check for CT messages received before we enabled interrupts */
 246         spin_lock_irq(&gt->irq_lock);
 247         intel_guc_ct_event_handler(&guc->ct);
 248         spin_unlock_irq(&gt->irq_lock);
 249
 250         drm_dbg(&i915->drm, "GuC communication enabled\n");
 251
 252         return 0;
 253 }
 254
 255 static void guc_disable_communication(struct intel_guc *guc)
 256 {
 257         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 258
 259         /*
 260          * Events generated during or after CT disable are logged by guc in
 261          * via mmio. Make sure the register is clear before disabling CT since
 262          * all events we cared about have already been processed via CT.
 263          */
 264         guc_clear_mmio_msg(guc);
 265
 266         intel_guc_disable_interrupts(guc);
 267
 268         intel_guc_ct_disable(&guc->ct);
 269
 270         /*
 271          * Check for messages received during/after the CT disable. We do not
 272          * expect any messages to have arrived via CT between the interrupt
 273          * disable and the CT disable because GuC should've been idle until we
 274          * triggered the CT disable protocol.
 275          */
 276         guc_get_mmio_msg(guc);
 277
 278         drm_dbg(&i915->drm, "GuC communication disabled\n");
 279 }
 280
 281 static void __uc_fetch_firmwares(struct intel_uc *uc)
 282 {
 283         int err;
 284
 285         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 286
 287         err = intel_uc_fw_fetch(&uc->guc.fw);
 288         if (err) {
 289                 /* Make sure we transition out of transient "SELECTED" state */
 290                 if (intel_uc_wants_huc(uc)) {
 291                         drm_dbg(&uc_to_gt(uc)->i915->drm,
 292                                 "Failed to fetch GuC: %d disabling HuC\n", err);
 293                         intel_uc_fw_change_status(&uc->huc.fw,
 294                                                   INTEL_UC_FIRMWARE_ERROR);
 295                 }
 296
 297                 return;
 298         }
 299
 300         if (intel_uc_wants_huc(uc))
 301                 intel_uc_fw_fetch(&uc->huc.fw);
 302 }
 303
 304 static void __uc_cleanup_firmwares(struct intel_uc *uc)
 305 {
 306         intel_uc_fw_cleanup_fetch(&uc->huc.fw);
 307         intel_uc_fw_cleanup_fetch(&uc->guc.fw);
 308 }
 309
 310 static int __uc_init(struct intel_uc *uc)
 311 {
 312         struct intel_guc *guc = &uc->guc;
 313         struct intel_huc *huc = &uc->huc;
 314         int ret;
 315
 316         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 317
 318         if (!intel_uc_uses_guc(uc))
 319                 return 0;
 320
 321         if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
 322                 return -ENOMEM;
 323
 324         ret = intel_guc_init(guc);
 325         if (ret)
 326                 return ret;
 327
 328         if (intel_uc_uses_huc(uc)) {
 329                 ret = intel_huc_init(huc);
 330                 if (ret)
 331                         goto out_guc;
 332         }
 333
 334         return 0;
 335
 336 out_guc:
 337         intel_guc_fini(guc);
 338         return ret;
 339 }
 340
 341 static void __uc_fini(struct intel_uc *uc)
 342 {
 343         intel_huc_fini(&uc->huc);
 344         intel_guc_fini(&uc->guc);
 345 }
 346
 347 static int __uc_sanitize(struct intel_uc *uc)
 348 {
 349         struct intel_guc *guc = &uc->guc;
 350         struct intel_huc *huc = &uc->huc;
 351
 352         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 353
 354         intel_huc_sanitize(huc);
 355         intel_guc_sanitize(guc);
 356
 357         return __intel_uc_reset_hw(uc);
 358 }
 359
 360 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
 361 static int uc_init_wopcm(struct intel_uc *uc)
 362 {
 363         struct intel_gt *gt = uc_to_gt(uc);
 364         struct intel_uncore *uncore = gt->uncore;
 365         u32 base = intel_wopcm_guc_base(&gt->i915->wopcm);
 366         u32 size = intel_wopcm_guc_size(&gt->i915->wopcm);
 367         u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
 368         u32 mask;
 369         int err;
 370
 371         if (unlikely(!base || !size)) {
 372                 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
 373                 return -E2BIG;
 374         }
 375
 376         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 377         GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
 378         GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
 379         GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
 380         GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
 381
 382         err = i915_inject_probe_error(gt->i915, -ENXIO);
 383         if (err)
 384                 return err;
 385
 386         mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
 387         err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
 388                                             size | GUC_WOPCM_SIZE_LOCKED);
 389         if (err)
 390                 goto err_out;
 391
 392         mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
 393         err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
 394                                             base | huc_agent, mask,
 395                                             base | huc_agent |
 396                                             GUC_WOPCM_OFFSET_VALID);
 397         if (err)
 398                 goto err_out;
 399
 400         return 0;
 401
 402 err_out:
 403         i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
 404         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
 405                          i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
 406                          intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
 407         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
 408                          i915_mmio_reg_offset(GUC_WOPCM_SIZE),
 409                          intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 410
 411         return err;
 412 }
 413
 414 static bool uc_is_wopcm_locked(struct intel_uc *uc)
 415 {
 416         struct intel_gt *gt = uc_to_gt(uc);
 417         struct intel_uncore *uncore = gt->uncore;
 418
 419         return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
 420                (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
 421 }
 422
 423 static int __uc_check_hw(struct intel_uc *uc)
 424 {
 425         if (!intel_uc_supports_guc(uc))
 426                 return 0;
 427
 428         /*
 429          * We can silently continue without GuC only if it was never enabled
 430          * before on this system after reboot, otherwise we risk GPU hangs.
 431          * To check if GuC was loaded before we look at WOPCM registers.
 432          */
 433         if (uc_is_wopcm_locked(uc))
 434                 return -EIO;
 435
 436         return 0;
 437 }
 438
 439 static int __uc_init_hw(struct intel_uc *uc)
 440 {
 441         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
 442         struct intel_guc *guc = &uc->guc;
 443         struct intel_huc *huc = &uc->huc;
 444         int ret, attempts;
 445
 446         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 447         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 448
 449         if (!intel_uc_fw_is_loadable(&guc->fw)) {
 450                 ret = __uc_check_hw(uc) ||
 451                       intel_uc_fw_is_overridden(&guc->fw) ||
 452                       intel_uc_wants_guc_submission(uc) ?
 453                       intel_uc_fw_status_to_error(guc->fw.status) : 0;
 454                 goto err_out;
 455         }
 456
 457         ret = uc_init_wopcm(uc);
 458         if (ret)
 459                 goto err_out;
 460
 461         intel_guc_reset_interrupts(guc);
 462
 463         /* WaEnableuKernelHeaderValidFix:skl */
 464         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 465         if (GRAPHICS_VER(i915) == 9)
 466                 attempts = 3;
 467         else
 468                 attempts = 1;
 469
 470         while (attempts--) {
 471                 /*
 472                  * Always reset the GuC just before (re)loading, so
 473                  * that the state and timing are fairly predictable
 474                  */
 475                 ret = __uc_sanitize(uc);
 476                 if (ret)
 477                         goto err_out;
 478
 479                 intel_huc_fw_upload(huc);
 480                 intel_guc_ads_reset(guc);
 481                 intel_guc_write_params(guc);
 482                 ret = intel_guc_fw_upload(guc);
 483                 if (ret == 0)
 484                         break;
 485
 486                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 487                                  "retry %d more time(s)\n", ret, attempts);
 488         }
 489
 490         /* Did we succeded or run out of retries? */
 491         if (ret)
 492                 goto err_log_capture;
 493
 494         ret = guc_enable_communication(guc);
 495         if (ret)
 496                 goto err_log_capture;
 497
 498         intel_huc_auth(huc);
 499
 500         if (intel_uc_uses_guc_submission(uc))
 501                 intel_guc_submission_enable(guc);
 502
 503         if (intel_uc_uses_guc_slpc(uc)) {
 504                 ret = intel_guc_slpc_enable(&guc->slpc);
 505                 if (ret)
 506                         goto err_submission;
 507         }
 508
 509         drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
 510                  intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
 511                  guc->fw.major_ver_found, guc->fw.minor_ver_found,
 512                  "submission",
 513                  enableddisabled(intel_uc_uses_guc_submission(uc)));
 514
 515         drm_info(&i915->drm, "GuC SLPC: %s\n",
 516                  enableddisabled(intel_uc_uses_guc_slpc(uc)));
 517
 518         if (intel_uc_uses_huc(uc)) {
 519                 drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
 520                          intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
 521                          huc->fw.path,
 522                          huc->fw.major_ver_found, huc->fw.minor_ver_found,
 523                          "authenticated",
 524                          yesno(intel_huc_is_authenticated(huc)));
 525         }
 526
 527         return 0;
 528
 529         /*
 530          * We've failed to load the firmware :(
 531          */
 532 err_submission:
 533         intel_guc_submission_disable(guc);
 534 err_log_capture:
 535         __uc_capture_load_err_log(uc);
 536 err_out:
 537         __uc_sanitize(uc);
 538
 539         if (!ret) {
 540                 drm_notice(&i915->drm, "GuC is uninitialized\n");
 541                 /* We want to run without GuC submission */
 542                 return 0;
 543         }
 544
 545         i915_probe_error(i915, "GuC initialization failed %d\n", ret);
 546
 547         /* We want to keep KMS alive */
 548         return -EIO;
 549 }
 550
 551 static void __uc_fini_hw(struct intel_uc *uc)
 552 {
 553         struct intel_guc *guc = &uc->guc;
 554
 555         if (!intel_guc_is_fw_running(guc))
 556                 return;
 557
 558         if (intel_uc_uses_guc_submission(uc))
 559                 intel_guc_submission_disable(guc);
 560
 561         __uc_sanitize(uc);
 562 }
 563
 564 /**
 565  * intel_uc_reset_prepare - Prepare for reset
 566  * @uc: the intel_uc structure
 567  *
 568  * Preparing for full gpu reset.
 569  */
 570 void intel_uc_reset_prepare(struct intel_uc *uc)
 571 {
 572         struct intel_guc *guc = &uc->guc;
 573
 574         uc->reset_in_progress = true;
 575
 576         /* Nothing to do if GuC isn't supported */
 577         if (!intel_uc_supports_guc(uc))
 578                 return;
 579
 580         /* Firmware expected to be running when this function is called */
 581         if (!intel_guc_is_ready(guc))
 582                 goto sanitize;
 583
 584         if (intel_uc_uses_guc_submission(uc))
 585                 intel_guc_submission_reset_prepare(guc);
 586
 587 sanitize:
 588         __uc_sanitize(uc);
 589 }
 590
 591 void intel_uc_reset(struct intel_uc *uc, bool stalled)
 592 {
 593         struct intel_guc *guc = &uc->guc;
 594
 595         /* Firmware can not be running when this function is called  */
 596         if (intel_uc_uses_guc_submission(uc))
 597                 intel_guc_submission_reset(guc, stalled);
 598 }
 599
 600 void intel_uc_reset_finish(struct intel_uc *uc)
 601 {
 602         struct intel_guc *guc = &uc->guc;
 603
 604         uc->reset_in_progress = false;
 605
 606         /* Firmware expected to be running when this function is called */
 607         if (intel_guc_is_fw_running(guc) && intel_uc_uses_guc_submission(uc))
 608                 intel_guc_submission_reset_finish(guc);
 609 }
 610
 611 void intel_uc_cancel_requests(struct intel_uc *uc)
 612 {
 613         struct intel_guc *guc = &uc->guc;
 614
 615         /* Firmware can not be running when this function is called  */
 616         if (intel_uc_uses_guc_submission(uc))
 617                 intel_guc_submission_cancel_requests(guc);
 618 }
 619
 620 void intel_uc_runtime_suspend(struct intel_uc *uc)
 621 {
 622         struct intel_guc *guc = &uc->guc;
 623
 624         if (!intel_guc_is_ready(guc))
 625                 return;
 626
 627         /*
 628          * Wait for any outstanding CTB before tearing down communication /w the
 629          * GuC.
 630          */
 631 #define OUTSTANDING_CTB_TIMEOUT_PERIOD  (HZ / 5)
 632         intel_guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
 633                                        false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
 634         GEM_WARN_ON(atomic_read(&guc->outstanding_submission_g2h));
 635
 636         guc_disable_communication(guc);
 637 }
 638
 639 void intel_uc_suspend(struct intel_uc *uc)
 640 {
 641         struct intel_guc *guc = &uc->guc;
 642         intel_wakeref_t wakeref;
 643         int err;
 644
 645         if (!intel_guc_is_ready(guc))
 646                 return;
 647
 648         with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
 649                 err = intel_guc_suspend(guc);
 650                 if (err)
 651                         DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 652         }
 653 }
 654
 655 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
 656 {
 657         struct intel_guc *guc = &uc->guc;
 658         struct intel_gt *gt = guc_to_gt(guc);
 659         int err;
 660
 661         if (!intel_guc_is_fw_running(guc))
 662                 return 0;
 663
 664         /* Make sure we enable communication if and only if it's disabled */
 665         GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
 666
 667         if (enable_communication)
 668                 guc_enable_communication(guc);
 669
 670         /* If we are only resuming GuC communication but not reloading
 671          * GuC, we need to ensure the ARAT timer interrupt is enabled
 672          * again. In case of GuC reload, it is enabled during SLPC enable.
 673          */
 674         if (enable_communication && intel_uc_uses_guc_slpc(uc))
 675                 intel_guc_pm_intrmsk_enable(gt);
 676
 677         err = intel_guc_resume(guc);
 678         if (err) {
 679                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 680                 return err;
 681         }
 682
 683         return 0;
 684 }
 685
 686 int intel_uc_resume(struct intel_uc *uc)
 687 {
 688         /*
 689          * When coming out of S3/S4 we sanitize and re-init the HW, so
 690          * communication is already re-enabled at this point.
 691          */
 692         return __uc_resume(uc, false);
 693 }
 694
 695 int intel_uc_runtime_resume(struct intel_uc *uc)
 696 {
 697         /*
 698          * During runtime resume we don't sanitize, so we need to re-init
 699          * communication as well.
 700          */
 701         return __uc_resume(uc, true);
 702 }
 703
 704 static const struct intel_uc_ops uc_ops_off = {
 705         .init_hw = __uc_check_hw,
 706 };
 707
 708 static const struct intel_uc_ops uc_ops_on = {
 709         .sanitize = __uc_sanitize,
 710
 711         .init_fw = __uc_fetch_firmwares,
 712         .fini_fw = __uc_cleanup_firmwares,
 713
 714         .init = __uc_init,
 715         .fini = __uc_fini,
 716
 717         .init_hw = __uc_init_hw,
 718         .fini_hw = __uc_fini_hw,
 719 };