1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
6 #include "gt/intel_engine_pm.h"
7 #include "gt/intel_gpu_commands.h"
8 #include "i915_selftest.h"
10 #include "gem/selftests/igt_gem_utils.h"
11 #include "gem/selftests/mock_context.h"
12 #include "selftests/igt_reset.h"
13 #include "selftests/igt_spinner.h"
14 #include "selftests/intel_scheduler_helpers.h"
17 struct drm_i915_mocs_table table;
18 struct drm_i915_mocs_table *mocs;
19 struct drm_i915_mocs_table *l3cc;
20 struct i915_vma *scratch;
24 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)
26 struct intel_context *ce;
28 ce = intel_context_create(engine);
32 /* We build large requests to read the registers from the ring */
33 ce->ring_size = SZ_16K;
38 static int request_add_sync(struct i915_request *rq, int err)
42 if (i915_request_wait(rq, 0, HZ / 5) < 0)
49 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
55 if (spin && !igt_wait_for_spinner(spin, rq))
62 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
67 memset(arg, 0, sizeof(*arg));
69 flags = get_mocs_settings(gt->i915, &arg->table);
73 if (flags & HAS_RENDER_L3CC)
74 arg->l3cc = &arg->table;
76 if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
77 arg->mocs = &arg->table;
80 __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE);
81 if (IS_ERR(arg->scratch))
82 return PTR_ERR(arg->scratch);
84 arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);
85 if (IS_ERR(arg->vaddr)) {
86 err = PTR_ERR(arg->vaddr);
93 i915_vma_unpin_and_release(&arg->scratch, 0);
97 static void live_mocs_fini(struct live_mocs *arg)
99 i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
102 static int read_regs(struct i915_request *rq,
103 u32 addr, unsigned int count,
109 GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
111 cs = intel_ring_begin(rq, 4 * count);
115 for (i = 0; i < count; i++) {
116 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
122 *offset += sizeof(u32);
125 intel_ring_advance(rq, cs);
130 static int read_mocs_table(struct i915_request *rq,
131 const struct drm_i915_mocs_table *table,
134 struct intel_gt *gt = rq->engine->gt;
140 if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
141 addr = global_mocs_offset() + gt->uncore->gsi_offset;
143 addr = mocs_offset(rq->engine);
145 return read_regs(rq, addr, table->n_entries, offset);
148 static int read_l3cc_table(struct i915_request *rq,
149 const struct drm_i915_mocs_table *table,
152 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
157 return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
160 static int check_mocs_table(struct intel_engine_cs *engine,
161 const struct drm_i915_mocs_table *table,
170 for_each_mocs(expect, table, i) {
171 if (**vaddr != expect) {
172 pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
173 engine->name, i, **vaddr, expect);
182 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
185 * Registers in this range are affected by the MCR selector
186 * which only controls CPU initiated MMIO. Routing does not
187 * work for CS access so we cannot verify them on this path.
189 return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
192 static int check_l3cc_table(struct intel_engine_cs *engine,
193 const struct drm_i915_mocs_table *table,
196 /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
197 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
204 for_each_l3cc(expect, table, i) {
205 if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
206 pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
207 engine->name, i, **vaddr, expect);
217 static int check_mocs_engine(struct live_mocs *arg,
218 struct intel_context *ce)
220 struct i915_vma *vma = arg->scratch;
221 struct i915_request *rq;
226 memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
228 rq = intel_context_create_request(ce);
232 err = igt_vma_move_to_active_unlocked(vma, rq, EXEC_OBJECT_WRITE);
234 /* Read the mocs tables back using SRM */
235 offset = i915_ggtt_offset(vma);
237 err = read_mocs_table(rq, arg->mocs, &offset);
238 if (!err && ce->engine->class == RENDER_CLASS)
239 err = read_l3cc_table(rq, arg->l3cc, &offset);
240 offset -= i915_ggtt_offset(vma);
241 GEM_BUG_ON(offset > PAGE_SIZE);
243 err = request_add_sync(rq, err);
247 /* Compare the results against the expected tables */
250 err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
251 if (!err && ce->engine->class == RENDER_CLASS)
252 err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
256 GEM_BUG_ON(arg->vaddr + offset != vaddr);
260 static int live_mocs_kernel(void *arg)
262 struct intel_gt *gt = arg;
263 struct intel_engine_cs *engine;
264 enum intel_engine_id id;
265 struct live_mocs mocs;
268 /* Basic check the system is configured with the expected mocs table */
270 err = live_mocs_init(&mocs, gt);
274 for_each_engine(engine, gt, id) {
275 intel_engine_pm_get(engine);
276 err = check_mocs_engine(&mocs, engine->kernel_context);
277 intel_engine_pm_put(engine);
282 live_mocs_fini(&mocs);
286 static int live_mocs_clean(void *arg)
288 struct intel_gt *gt = arg;
289 struct intel_engine_cs *engine;
290 enum intel_engine_id id;
291 struct live_mocs mocs;
294 /* Every new context should see the same mocs table */
296 err = live_mocs_init(&mocs, gt);
300 for_each_engine(engine, gt, id) {
301 struct intel_context *ce;
303 ce = mocs_context_create(engine);
309 err = check_mocs_engine(&mocs, ce);
310 intel_context_put(ce);
315 live_mocs_fini(&mocs);
319 static int active_engine_reset(struct intel_context *ce,
323 struct igt_spinner spin;
324 struct i915_request *rq;
327 err = igt_spinner_init(&spin, ce->engine->gt);
331 rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
333 igt_spinner_fini(&spin);
337 err = request_add_spin(rq, &spin);
338 if (err == 0 && !using_guc)
339 err = intel_engine_reset(ce->engine, reason);
341 /* Ensure the reset happens and kills the engine */
343 err = intel_selftest_wait_for_rq(rq);
345 igt_spinner_end(&spin);
346 igt_spinner_fini(&spin);
351 static int __live_mocs_reset(struct live_mocs *mocs,
352 struct intel_context *ce, bool using_guc)
354 struct intel_gt *gt = ce->engine->gt;
357 if (intel_has_reset_engine(gt)) {
359 err = intel_engine_reset(ce->engine, "mocs");
363 err = check_mocs_engine(mocs, ce);
368 err = active_engine_reset(ce, "mocs", using_guc);
372 err = check_mocs_engine(mocs, ce);
377 if (intel_has_gpu_reset(gt)) {
378 intel_gt_reset(gt, ce->engine->mask, "mocs");
380 err = check_mocs_engine(mocs, ce);
388 static int live_mocs_reset(void *arg)
390 struct intel_gt *gt = arg;
391 struct intel_engine_cs *engine;
392 enum intel_engine_id id;
393 struct live_mocs mocs;
396 /* Check the mocs setup is retained over per-engine and global resets */
398 err = live_mocs_init(&mocs, gt);
402 igt_global_reset_lock(gt);
403 for_each_engine(engine, gt, id) {
404 bool using_guc = intel_engine_uses_guc(engine);
405 struct intel_selftest_saved_policy saved;
406 struct intel_context *ce;
409 err = intel_selftest_modify_policy(engine, &saved,
410 SELFTEST_SCHEDULER_MODIFY_FAST_RESET);
414 ce = mocs_context_create(engine);
420 intel_engine_pm_get(engine);
422 err = __live_mocs_reset(&mocs, ce, using_guc);
424 intel_engine_pm_put(engine);
425 intel_context_put(ce);
428 err2 = intel_selftest_restore_policy(engine, &saved);
434 igt_global_reset_unlock(gt);
436 live_mocs_fini(&mocs);
440 int intel_mocs_live_selftests(struct drm_i915_private *i915)
442 static const struct i915_subtest tests[] = {
443 SUBTEST(live_mocs_kernel),
444 SUBTEST(live_mocs_clean),
445 SUBTEST(live_mocs_reset),
447 struct drm_i915_mocs_table table;
449 if (!get_mocs_settings(i915, &table))
452 return intel_gt_live_subtests(tests, to_gt(i915));