drivers/gpu/drm/i915/gt/intel_workarounds.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "i915_drv.h"
   8 #include "intel_context.h"
   9 #include "intel_engine_pm.h"
  10 #include "intel_gt.h"
  11 #include "intel_ring.h"
  12 #include "intel_workarounds.h"
  13
  14 /**
  15  * DOC: Hardware workarounds
  16  *
  17  * This file is intended as a central place to implement most [1]_ of the
  18  * required workarounds for hardware to work as originally intended. They fall
  19  * in five basic categories depending on how/when they are applied:
  20  *
  21  * - Workarounds that touch registers that are saved/restored to/from the HW
  22  *   context image. The list is emitted (via Load Register Immediate commands)
  23  *   everytime a new context is created.
  24  * - GT workarounds. The list of these WAs is applied whenever these registers
  25  *   revert to default values (on GPU reset, suspend/resume [2]_, etc..).
  26  * - Display workarounds. The list is applied during display clock-gating
  27  *   initialization.
  28  * - Workarounds that whitelist a privileged register, so that UMDs can manage
  29  *   them directly. This is just a special case of a MMMIO workaround (as we
  30  *   write the list of these to/be-whitelisted registers to some special HW
  31  *   registers).
  32  * - Workaround batchbuffers, that get executed automatically by the hardware
  33  *   on every HW context restore.
  34  *
  35  * .. [1] Please notice that there are other WAs that, due to their nature,
  36  *    cannot be applied from a central place. Those are peppered around the rest
  37  *    of the code, as needed.
  38  *
  39  * .. [2] Technically, some registers are powercontext saved & restored, so they
  40  *    survive a suspend/resume. In practice, writing them again is not too
  41  *    costly and simplifies things. We can revisit this in the future.
  42  *
  43  * Layout
  44  * ~~~~~~
  45  *
  46  * Keep things in this file ordered by WA type, as per the above (context, GT,
  47  * display, register whitelist, batchbuffer). Then, inside each type, keep the
  48  * following order:
  49  *
  50  * - Infrastructure functions and macros
  51  * - WAs per platform in standard gen/chrono order
  52  * - Public functions to init or apply the given workaround type.
  53  */
  54
  55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
  56 {
  57         wal->name = name;
  58         wal->engine_name = engine_name;
  59 }
  60
  61 #define WA_LIST_CHUNK (1 << 4)
  62
  63 static void wa_init_finish(struct i915_wa_list *wal)
  64 {
  65         /* Trim unused entries. */
  66         if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
  67                 struct i915_wa *list = kmemdup(wal->list,
  68                                                wal->count * sizeof(*list),
  69                                                GFP_KERNEL);
  70
  71                 if (list) {
  72                         kfree(wal->list);
  73                         wal->list = list;
  74                 }
  75         }
  76
  77         if (!wal->count)
  78                 return;
  79
  80         DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
  81                          wal->wa_count, wal->name, wal->engine_name);
  82 }
  83
  84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
  85 {
  86         unsigned int addr = i915_mmio_reg_offset(wa->reg);
  87         unsigned int start = 0, end = wal->count;
  88         const unsigned int grow = WA_LIST_CHUNK;
  89         struct i915_wa *wa_;
  90
  91         GEM_BUG_ON(!is_power_of_2(grow));
  92
  93         if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
  94                 struct i915_wa *list;
  95
  96                 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
  97                                      GFP_KERNEL);
  98                 if (!list) {
  99                         DRM_ERROR("No space for workaround init!\n");
 100                         return;
 101                 }
 102
 103                 if (wal->list)
 104                         memcpy(list, wal->list, sizeof(*wa) * wal->count);
 105
 106                 wal->list = list;
 107         }
 108
 109         while (start < end) {
 110                 unsigned int mid = start + (end - start) / 2;
 111
 112                 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
 113                         start = mid + 1;
 114                 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
 115                         end = mid;
 116                 } else {
 117                         wa_ = &wal->list[mid];
 118
 119                         if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
 120                                 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
 121                                           i915_mmio_reg_offset(wa_->reg),
 122                                           wa_->clr, wa_->set);
 123
 124                                 wa_->set &= ~wa->clr;
 125                         }
 126
 127                         wal->wa_count++;
 128                         wa_->set |= wa->set;
 129                         wa_->clr |= wa->clr;
 130                         wa_->read |= wa->read;
 131                         return;
 132                 }
 133         }
 134
 135         wal->wa_count++;
 136         wa_ = &wal->list[wal->count++];
 137         *wa_ = *wa;
 138
 139         while (wa_-- > wal->list) {
 140                 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
 141                            i915_mmio_reg_offset(wa_[1].reg));
 142                 if (i915_mmio_reg_offset(wa_[1].reg) >
 143                     i915_mmio_reg_offset(wa_[0].reg))
 144                         break;
 145
 146                 swap(wa_[1], wa_[0]);
 147         }
 148 }
 149
 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
 151                    u32 clear, u32 set, u32 read_mask)
 152 {
 153         struct i915_wa wa = {
 154                 .reg  = reg,
 155                 .clr  = clear,
 156                 .set  = set,
 157                 .read = read_mask,
 158         };
 159
 160         _wa_add(wal, &wa);
 161 }
 162
 163 static void
 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 165 {
 166         wa_add(wal, reg, clear, set, clear);
 167 }
 168
 169 static void
 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 171 {
 172         wa_write_masked_or(wal, reg, ~0, set);
 173 }
 174
 175 static void
 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 177 {
 178         wa_write_masked_or(wal, reg, set, set);
 179 }
 180
 181 static void
 182 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
 183 {
 184         wa_write_masked_or(wal, reg, clr, 0);
 185 }
 186
 187 static void
 188 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 189 {
 190         wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
 191 }
 192
 193 static void
 194 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 195 {
 196         wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
 197 }
 198
 199 #define WA_SET_BIT_MASKED(addr, mask) \
 200         wa_masked_en(wal, (addr), (mask))
 201
 202 #define WA_CLR_BIT_MASKED(addr, mask) \
 203         wa_masked_dis(wal, (addr), (mask))
 204
 205 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 206         wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value)))
 207
 208 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 209                                       struct i915_wa_list *wal)
 210 {
 211         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 212
 213         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 214         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 215
 216         /* WaDisablePartialInstShootdown:bdw,chv */
 217         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 218                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 219
 220         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 221          * workaround for for a possible hang in the unlikely event a TLB
 222          * invalidation occurs during a PSD flush.
 223          */
 224         /* WaForceEnableNonCoherent:bdw,chv */
 225         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 226         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 227                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 228                           HDC_FORCE_NON_COHERENT);
 229
 230         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 231          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 232          *  polygons in the same 8x4 pixel/sample area to be processed without
 233          *  stalling waiting for the earlier ones to write to Hierarchical Z
 234          *  buffer."
 235          *
 236          * This optimization is off by default for BDW and CHV; turn it on.
 237          */
 238         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 239
 240         /* Wa4x4STCOptimizationDisable:bdw,chv */
 241         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 242
 243         /*
 244          * BSpec recommends 8x4 when MSAA is used,
 245          * however in practice 16x4 seems fastest.
 246          *
 247          * Note that PS/WM thread counts depend on the WIZ hashing
 248          * disable bit, which we don't touch here, but it's good
 249          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 250          */
 251         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 252                             GEN6_WIZ_HASHING_MASK,
 253                             GEN6_WIZ_HASHING_16x4);
 254 }
 255
 256 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
 257                                      struct i915_wa_list *wal)
 258 {
 259         struct drm_i915_private *i915 = engine->i915;
 260
 261         gen8_ctx_workarounds_init(engine, wal);
 262
 263         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 264         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 265
 266         /* WaDisableDopClockGating:bdw
 267          *
 268          * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 269          * to disable EUTC clock gating.
 270          */
 271         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 272                           DOP_CLOCK_GATING_DISABLE);
 273
 274         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 275                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 276
 277         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 278                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 279                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 280                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 281                           (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 282 }
 283
 284 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
 285                                      struct i915_wa_list *wal)
 286 {
 287         gen8_ctx_workarounds_init(engine, wal);
 288
 289         /* WaDisableThreadStallDopClockGating:chv */
 290         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 291
 292         /* Improve HiZ throughput on CHV. */
 293         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 294 }
 295
 296 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
 297                                       struct i915_wa_list *wal)
 298 {
 299         struct drm_i915_private *i915 = engine->i915;
 300
 301         if (HAS_LLC(i915)) {
 302                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 303                  *
 304                  * Must match Display Engine. See
 305                  * WaCompressedResourceDisplayNewHashMode.
 306                  */
 307                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 308                                   GEN9_PBE_COMPRESSED_HASH_SELECTION);
 309                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 310                                   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
 311         }
 312
 313         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
 314         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 315         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 316                           FLOW_CONTROL_ENABLE |
 317                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 318
 319         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 320         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 321         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 322                           GEN9_ENABLE_YV12_BUGFIX |
 323                           GEN9_ENABLE_GPGPU_PREEMPTION);
 324
 325         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
 326         /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 327         WA_SET_BIT_MASKED(CACHE_MODE_1,
 328                           GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 329                           GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 330
 331         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 332         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 333                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 334
 335         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 336         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 337                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 338                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 339
 340         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 341          * both tied to WaForceContextSaveRestoreNonCoherent
 342          * in some hsds for skl. We keep the tie for all gen9. The
 343          * documentation is a bit hazy and so we want to get common behaviour,
 344          * even though there is no clear evidence we would need both on kbl/bxt.
 345          * This area has been source of system hangs so we play it safe
 346          * and mimic the skl regardless of what bspec says.
 347          *
 348          * Use Force Non-Coherent whenever executing a 3D context. This
 349          * is a workaround for a possible hang in the unlikely event
 350          * a TLB invalidation occurs during a PSD flush.
 351          */
 352
 353         /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 354         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 355                           HDC_FORCE_NON_COHERENT);
 356
 357         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 358         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
 359                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 360                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 361
 362         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 363         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 364
 365         /*
 366          * Supporting preemption with fine-granularity requires changes in the
 367          * batch buffer programming. Since we can't break old userspace, we
 368          * need to set our default preemption level to safe value. Userspace is
 369          * still able to use more fine-grained preemption levels, since in
 370          * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
 371          * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
 372          * not real HW workarounds, but merely a way to start using preemption
 373          * while maintaining old contract with userspace.
 374          */
 375
 376         /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
 377         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 378
 379         /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
 380         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 381                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 382                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 383
 384         /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
 385         if (IS_GEN9_LP(i915))
 386                 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
 387 }
 388
 389 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
 390                                 struct i915_wa_list *wal)
 391 {
 392         struct drm_i915_private *i915 = engine->i915;
 393         u8 vals[3] = { 0, 0, 0 };
 394         unsigned int i;
 395
 396         for (i = 0; i < 3; i++) {
 397                 u8 ss;
 398
 399                 /*
 400                  * Only consider slices where one, and only one, subslice has 7
 401                  * EUs
 402                  */
 403                 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
 404                         continue;
 405
 406                 /*
 407                  * subslice_7eu[i] != 0 (because of the check above) and
 408                  * ss_max == 4 (maximum number of subslices possible per slice)
 409                  *
 410                  * ->    0 <= ss <= 3;
 411                  */
 412                 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
 413                 vals[i] = 3 - ss;
 414         }
 415
 416         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 417                 return;
 418
 419         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 420         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 421                             GEN9_IZ_HASHING_MASK(2) |
 422                             GEN9_IZ_HASHING_MASK(1) |
 423                             GEN9_IZ_HASHING_MASK(0),
 424                             GEN9_IZ_HASHING(2, vals[2]) |
 425                             GEN9_IZ_HASHING(1, vals[1]) |
 426                             GEN9_IZ_HASHING(0, vals[0]));
 427 }
 428
 429 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
 430                                      struct i915_wa_list *wal)
 431 {
 432         gen9_ctx_workarounds_init(engine, wal);
 433         skl_tune_iz_hashing(engine, wal);
 434 }
 435
 436 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
 437                                      struct i915_wa_list *wal)
 438 {
 439         gen9_ctx_workarounds_init(engine, wal);
 440
 441         /* WaDisableThreadStallDopClockGating:bxt */
 442         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 443                           STALL_DOP_GATING_DISABLE);
 444
 445         /* WaToEnableHwFixForPushConstHWBug:bxt */
 446         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 447                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 448 }
 449
 450 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 451                                      struct i915_wa_list *wal)
 452 {
 453         struct drm_i915_private *i915 = engine->i915;
 454
 455         gen9_ctx_workarounds_init(engine, wal);
 456
 457         /* WaToEnableHwFixForPushConstHWBug:kbl */
 458         if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
 459                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 460                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 461
 462         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 463         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 464                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 465 }
 466
 467 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
 468                                      struct i915_wa_list *wal)
 469 {
 470         gen9_ctx_workarounds_init(engine, wal);
 471
 472         /* WaToEnableHwFixForPushConstHWBug:glk */
 473         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 474                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 475 }
 476
 477 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 478                                      struct i915_wa_list *wal)
 479 {
 480         gen9_ctx_workarounds_init(engine, wal);
 481
 482         /* WaToEnableHwFixForPushConstHWBug:cfl */
 483         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 484                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 485
 486         /* WaDisableSbeCacheDispatchPortSharing:cfl */
 487         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 488                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 489 }
 490
 491 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
 492                                      struct i915_wa_list *wal)
 493 {
 494         /* WaForceContextSaveRestoreNonCoherent:cnl */
 495         WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
 496                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
 497
 498         /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 499         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 500                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 501
 502         /* WaPushConstantDereferenceHoldDisable:cnl */
 503         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 504
 505         /* FtrEnableFastAnisoL1BankingFix:cnl */
 506         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
 507
 508         /* WaDisable3DMidCmdPreemption:cnl */
 509         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 510
 511         /* WaDisableGPGPUMidCmdPreemption:cnl */
 512         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 513                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 514                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 515
 516         /* WaDisableEarlyEOT:cnl */
 517         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
 518 }
 519
 520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 521                                      struct i915_wa_list *wal)
 522 {
 523         struct drm_i915_private *i915 = engine->i915;
 524
 525         /* WaDisableBankHangMode:icl */
 526         wa_write(wal,
 527                  GEN8_L3CNTLREG,
 528                  intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
 529                  GEN8_ERRDETBCTRL);
 530
 531         /* Wa_1604370585:icl (pre-prod)
 532          * Formerly known as WaPushConstantDereferenceHoldDisable
 533          */
 534         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 535                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 536                                   PUSH_CONSTANT_DEREF_DISABLE);
 537
 538         /* WaForceEnableNonCoherent:icl
 539          * This is not the same workaround as in early Gen9 platforms, where
 540          * lacking this could cause system hangs, but coherency performance
 541          * overhead is high and only a few compute workloads really need it
 542          * (the register is whitelisted in hardware now, so UMDs can opt in
 543          * for coherency if they have a good reason).
 544          */
 545         WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 546
 547         /* Wa_2006611047:icl (pre-prod)
 548          * Formerly known as WaDisableImprovedTdlClkGating
 549          */
 550         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 551                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 552                                   GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 553
 554         /* Wa_2006665173:icl (pre-prod) */
 555         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 556                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 557                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 558
 559         /* WaEnableFloatBlendOptimization:icl */
 560         wa_write_masked_or(wal,
 561                            GEN10_CACHE_MODE_SS,
 562                            0, /* write-only, so skip validation */
 563                            _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
 564
 565         /* WaDisableGPGPUMidThreadPreemption:icl */
 566         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 567                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 568                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 569
 570         /* allow headerless messages for preemptible GPGPU context */
 571         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
 572                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 573
 574         /* Wa_1604278689:icl,ehl */
 575         wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 576         wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
 577                            0, /* write-only register; skip validation */
 578                            0xFFFFFFFF);
 579
 580         /* Wa_1406306137:icl,ehl */
 581         wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 582 }
 583
 584 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 585                                      struct i915_wa_list *wal)
 586 {
 587         /*
 588          * Wa_1409142259:tgl
 589          * Wa_1409347922:tgl
 590          * Wa_1409252684:tgl
 591          * Wa_1409217633:tgl
 592          * Wa_1409207793:tgl
 593          * Wa_1409178076:tgl
 594          * Wa_1408979724:tgl
 595          */
 596         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 597                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 598
 599         /*
 600          * Wa_1604555607:gen12 and Wa_1608008084:gen12
 601          * FF_MODE2 register will return the wrong value when read. The default
 602          * value for this register is zero for all fields and there are no bit
 603          * masks. So instead of doing a RMW we should just write the TDS timer
 604          * value for Wa_1604555607.
 605          */
 606         wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 607                FF_MODE2_TDS_TIMER_128, 0);
 608
 609         /* WaDisableGPGPUMidThreadPreemption:tgl */
 610         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 611                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 612                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 613 }
 614
 615 static void
 616 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 617                            struct i915_wa_list *wal,
 618                            const char *name)
 619 {
 620         struct drm_i915_private *i915 = engine->i915;
 621
 622         if (engine->class != RENDER_CLASS)
 623                 return;
 624
 625         wa_init_start(wal, name, engine->name);
 626
 627         if (IS_GEN(i915, 12))
 628                 tgl_ctx_workarounds_init(engine, wal);
 629         else if (IS_GEN(i915, 11))
 630                 icl_ctx_workarounds_init(engine, wal);
 631         else if (IS_CANNONLAKE(i915))
 632                 cnl_ctx_workarounds_init(engine, wal);
 633         else if (IS_COFFEELAKE(i915))
 634                 cfl_ctx_workarounds_init(engine, wal);
 635         else if (IS_GEMINILAKE(i915))
 636                 glk_ctx_workarounds_init(engine, wal);
 637         else if (IS_KABYLAKE(i915))
 638                 kbl_ctx_workarounds_init(engine, wal);
 639         else if (IS_BROXTON(i915))
 640                 bxt_ctx_workarounds_init(engine, wal);
 641         else if (IS_SKYLAKE(i915))
 642                 skl_ctx_workarounds_init(engine, wal);
 643         else if (IS_CHERRYVIEW(i915))
 644                 chv_ctx_workarounds_init(engine, wal);
 645         else if (IS_BROADWELL(i915))
 646                 bdw_ctx_workarounds_init(engine, wal);
 647         else if (INTEL_GEN(i915) < 8)
 648                 return;
 649         else
 650                 MISSING_CASE(INTEL_GEN(i915));
 651
 652         wa_init_finish(wal);
 653 }
 654
 655 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 656 {
 657         __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
 658 }
 659
 660 int intel_engine_emit_ctx_wa(struct i915_request *rq)
 661 {
 662         struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
 663         struct i915_wa *wa;
 664         unsigned int i;
 665         u32 *cs;
 666         int ret;
 667
 668         if (wal->count == 0)
 669                 return 0;
 670
 671         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 672         if (ret)
 673                 return ret;
 674
 675         cs = intel_ring_begin(rq, (wal->count * 2 + 2));
 676         if (IS_ERR(cs))
 677                 return PTR_ERR(cs);
 678
 679         *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
 680         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 681                 *cs++ = i915_mmio_reg_offset(wa->reg);
 682                 *cs++ = wa->set;
 683         }
 684         *cs++ = MI_NOOP;
 685
 686         intel_ring_advance(rq, cs);
 687
 688         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 689         if (ret)
 690                 return ret;
 691
 692         return 0;
 693 }
 694
 695 static void
 696 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 697 {
 698         /* WaDisableEarlyCull:ivb */
 699         wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
 700
 701         /* WaDisablePSDDualDispatchEnable:ivb */
 702         if (IS_IVB_GT1(i915))
 703                 wa_masked_en(wal,
 704                              GEN7_HALF_SLICE_CHICKEN1,
 705                              GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
 706
 707         /* WaDisable_RenderCache_OperationalFlush:ivb */
 708         wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
 709
 710         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
 711         wa_masked_dis(wal,
 712                       GEN7_COMMON_SLICE_CHICKEN1,
 713                       GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
 714
 715         /* WaApplyL3ControlAndL3ChickenMode:ivb */
 716         wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
 717         wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 718
 719         /* WaForceL3Serialization:ivb */
 720         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
 721
 722         /*
 723          * WaVSThreadDispatchOverride:ivb,vlv
 724          *
 725          * This actually overrides the dispatch
 726          * mode for all thread types.
 727          */
 728         wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
 729                            GEN7_FF_SCHED_MASK,
 730                            GEN7_FF_TS_SCHED_HW |
 731                            GEN7_FF_VS_SCHED_HW |
 732                            GEN7_FF_DS_SCHED_HW);
 733
 734         if (0) { /* causes HiZ corruption on ivb:gt1 */
 735                 /* enable HiZ Raw Stall Optimization */
 736                 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 737         }
 738
 739         /* WaDisable4x2SubspanOptimization:ivb */
 740         wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 741
 742         /*
 743          * BSpec recommends 8x4 when MSAA is used,
 744          * however in practice 16x4 seems fastest.
 745          *
 746          * Note that PS/WM thread counts depend on the WIZ hashing
 747          * disable bit, which we don't touch here, but it's good
 748          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 749          */
 750         wa_add(wal, GEN7_GT_MODE, 0,
 751                _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
 752                GEN6_WIZ_HASHING_16x4);
 753 }
 754
 755 static void
 756 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 757 {
 758         /* WaDisableEarlyCull:vlv */
 759         wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
 760
 761         /* WaPsdDispatchEnable:vlv */
 762         /* WaDisablePSDDualDispatchEnable:vlv */
 763         wa_masked_en(wal,
 764                      GEN7_HALF_SLICE_CHICKEN1,
 765                      GEN7_MAX_PS_THREAD_DEP |
 766                      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
 767
 768         /* WaDisable_RenderCache_OperationalFlush:vlv */
 769         wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
 770
 771         /* WaForceL3Serialization:vlv */
 772         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
 773
 774         /*
 775          * WaVSThreadDispatchOverride:ivb,vlv
 776          *
 777          * This actually overrides the dispatch
 778          * mode for all thread types.
 779          */
 780         wa_write_masked_or(wal,
 781                            GEN7_FF_THREAD_MODE,
 782                            GEN7_FF_SCHED_MASK,
 783                            GEN7_FF_TS_SCHED_HW |
 784                            GEN7_FF_VS_SCHED_HW |
 785                            GEN7_FF_DS_SCHED_HW);
 786
 787         /*
 788          * BSpec says this must be set, even though
 789          * WaDisable4x2SubspanOptimization isn't listed for VLV.
 790          */
 791         wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 792
 793         /*
 794          * BSpec recommends 8x4 when MSAA is used,
 795          * however in practice 16x4 seems fastest.
 796          *
 797          * Note that PS/WM thread counts depend on the WIZ hashing
 798          * disable bit, which we don't touch here, but it's good
 799          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 800          */
 801         wa_add(wal, GEN7_GT_MODE, 0,
 802                _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
 803                GEN6_WIZ_HASHING_16x4);
 804
 805         /*
 806          * WaIncreaseL3CreditsForVLVB0:vlv
 807          * This is the hardware default actually.
 808          */
 809         wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
 810 }
 811
 812 static void
 813 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 814 {
 815         /* L3 caching of data atomics doesn't work -- disable it. */
 816         wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
 817
 818         wa_add(wal,
 819                HSW_ROW_CHICKEN3, 0,
 820                _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 821                 0 /* XXX does this reg exist? */);
 822
 823         /* WaVSRefCountFullforceMissDisable:hsw */
 824         wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
 825
 826         wa_masked_dis(wal,
 827                       CACHE_MODE_0_GEN7,
 828                       /* WaDisable_RenderCache_OperationalFlush:hsw */
 829                       RC_OP_FLUSH_ENABLE |
 830                       /* enable HiZ Raw Stall Optimization */
 831                       HIZ_RAW_STALL_OPT_DISABLE);
 832
 833         /* WaDisable4x2SubspanOptimization:hsw */
 834         wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 835
 836         /*
 837          * BSpec recommends 8x4 when MSAA is used,
 838          * however in practice 16x4 seems fastest.
 839          *
 840          * Note that PS/WM thread counts depend on the WIZ hashing
 841          * disable bit, which we don't touch here, but it's good
 842          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 843          */
 844         wa_add(wal, GEN7_GT_MODE, 0,
 845                _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
 846                GEN6_WIZ_HASHING_16x4);
 847
 848         /* WaSampleCChickenBitEnable:hsw */
 849         wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
 850 }
 851
 852 static void
 853 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 854 {
 855         /* WaDisableKillLogic:bxt,skl,kbl */
 856         if (!IS_COFFEELAKE(i915))
 857                 wa_write_or(wal,
 858                             GAM_ECOCHK,
 859                             ECOCHK_DIS_TLB);
 860
 861         if (HAS_LLC(i915)) {
 862                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 863                  *
 864                  * Must match Display Engine. See
 865                  * WaCompressedResourceDisplayNewHashMode.
 866                  */
 867                 wa_write_or(wal,
 868                             MMCD_MISC_CTRL,
 869                             MMCD_PCLA | MMCD_HOTSPOT_EN);
 870         }
 871
 872         /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
 873         wa_write_or(wal,
 874                     GAM_ECOCHK,
 875                     BDW_DISABLE_HDC_INVALIDATION);
 876 }
 877
 878 static void
 879 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 880 {
 881         gen9_gt_workarounds_init(i915, wal);
 882
 883         /* WaDisableGafsUnitClkGating:skl */
 884         wa_write_or(wal,
 885                     GEN7_UCGCTL4,
 886                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 887
 888         /* WaInPlaceDecompressionHang:skl */
 889         if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
 890                 wa_write_or(wal,
 891                             GEN9_GAMT_ECO_REG_RW_IA,
 892                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 893 }
 894
 895 static void
 896 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 897 {
 898         gen9_gt_workarounds_init(i915, wal);
 899
 900         /* WaInPlaceDecompressionHang:bxt */
 901         wa_write_or(wal,
 902                     GEN9_GAMT_ECO_REG_RW_IA,
 903                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 904 }
 905
 906 static void
 907 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 908 {
 909         gen9_gt_workarounds_init(i915, wal);
 910
 911         /* WaDisableDynamicCreditSharing:kbl */
 912         if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
 913                 wa_write_or(wal,
 914                             GAMT_CHKN_BIT_REG,
 915                             GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
 916
 917         /* WaDisableGafsUnitClkGating:kbl */
 918         wa_write_or(wal,
 919                     GEN7_UCGCTL4,
 920                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 921
 922         /* WaInPlaceDecompressionHang:kbl */
 923         wa_write_or(wal,
 924                     GEN9_GAMT_ECO_REG_RW_IA,
 925                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 926 }
 927
 928 static void
 929 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 930 {
 931         gen9_gt_workarounds_init(i915, wal);
 932 }
 933
 934 static void
 935 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 936 {
 937         gen9_gt_workarounds_init(i915, wal);
 938
 939         /* WaDisableGafsUnitClkGating:cfl */
 940         wa_write_or(wal,
 941                     GEN7_UCGCTL4,
 942                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 943
 944         /* WaInPlaceDecompressionHang:cfl */
 945         wa_write_or(wal,
 946                     GEN9_GAMT_ECO_REG_RW_IA,
 947                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 948 }
 949
 950 static void
 951 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 952 {
 953         const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
 954         unsigned int slice, subslice;
 955         u32 l3_en, mcr, mcr_mask;
 956
 957         GEM_BUG_ON(INTEL_GEN(i915) < 10);
 958
 959         /*
 960          * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
 961          * L3Banks could be fused off in single slice scenario. If that is
 962          * the case, we might need to program MCR select to a valid L3Bank
 963          * by default, to make sure we correctly read certain registers
 964          * later on (in the range 0xB100 - 0xB3FF).
 965          *
 966          * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 967          * Before any MMIO read into slice/subslice specific registers, MCR
 968          * packet control register needs to be programmed to point to any
 969          * enabled s/ss pair. Otherwise, incorrect values will be returned.
 970          * This means each subsequent MMIO read will be forwarded to an
 971          * specific s/ss combination, but this is OK since these registers
 972          * are consistent across s/ss in almost all cases. In the rare
 973          * occasions, such as INSTDONE, where this value is dependent
 974          * on s/ss combo, the read should be done with read_subslice_reg.
 975          *
 976          * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
 977          * to which subslice, or to which L3 bank, the respective mmio reads
 978          * will go, we have to find a common index which works for both
 979          * accesses.
 980          *
 981          * Case where we cannot find a common index fortunately should not
 982          * happen in production hardware, so we only emit a warning instead of
 983          * implementing something more complex that requires checking the range
 984          * of every MMIO read.
 985          */
 986
 987         if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
 988                 u32 l3_fuse =
 989                         intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
 990                         GEN10_L3BANK_MASK;
 991
 992                 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse);
 993                 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
 994         } else {
 995                 l3_en = ~0;
 996         }
 997
 998         slice = fls(sseu->slice_mask) - 1;
 999         subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
1000         if (!subslice) {
1001                 drm_warn(&i915->drm,
1002                          "No common index found between subslice mask %x and L3 bank mask %x!\n",
1003                          intel_sseu_get_subslices(sseu, slice), l3_en);
1004                 subslice = fls(l3_en);
1005                 drm_WARN_ON(&i915->drm, !subslice);
1006         }
1007         subslice--;
1008
1009         if (INTEL_GEN(i915) >= 11) {
1010                 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1011                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1012         } else {
1013                 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1014                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1015         }
1016
1017         drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);
1018
1019         wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
1020 }
1021
1022 static void
1023 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
1024 {
1025         wa_init_mcr(i915, wal);
1026
1027         /* WaInPlaceDecompressionHang:cnl */
1028         wa_write_or(wal,
1029                     GEN9_GAMT_ECO_REG_RW_IA,
1030                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1031 }
1032
1033 static void
1034 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
1035 {
1036         wa_init_mcr(i915, wal);
1037
1038         /* WaInPlaceDecompressionHang:icl */
1039         wa_write_or(wal,
1040                     GEN9_GAMT_ECO_REG_RW_IA,
1041                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1042
1043         /* WaModifyGamTlbPartitioning:icl */
1044         wa_write_masked_or(wal,
1045                            GEN11_GACB_PERF_CTRL,
1046                            GEN11_HASH_CTRL_MASK,
1047                            GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
1048
1049         /* Wa_1405766107:icl
1050          * Formerly known as WaCL2SFHalfMaxAlloc
1051          */
1052         wa_write_or(wal,
1053                     GEN11_LSN_UNSLCVC,
1054                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
1055                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
1056
1057         /* Wa_220166154:icl
1058          * Formerly known as WaDisCtxReload
1059          */
1060         wa_write_or(wal,
1061                     GEN8_GAMW_ECO_DEV_RW_IA,
1062                     GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
1063
1064         /* Wa_1405779004:icl (pre-prod) */
1065         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
1066                 wa_write_or(wal,
1067                             SLICE_UNIT_LEVEL_CLKGATE,
1068                             MSCUNIT_CLKGATE_DIS);
1069
1070         /* Wa_1406838659:icl (pre-prod) */
1071         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1072                 wa_write_or(wal,
1073                             INF_UNIT_LEVEL_CLKGATE,
1074                             CGPSF_CLKGATE_DIS);
1075
1076         /* Wa_1406463099:icl
1077          * Formerly known as WaGamTlbPendError
1078          */
1079         wa_write_or(wal,
1080                     GAMT_CHKN_BIT_REG,
1081                     GAMT_CHKN_DISABLE_L3_COH_PIPE);
1082
1083         /* Wa_1607087056:icl,ehl,jsl */
1084         if (IS_ICELAKE(i915) ||
1085             IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
1086                 wa_write_or(wal,
1087                             SLICE_UNIT_LEVEL_CLKGATE,
1088                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
1089         }
1090 }
1091
1092 static void
1093 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
1094 {
1095         wa_init_mcr(i915, wal);
1096
1097         /* Wa_1409420604:tgl */
1098         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
1099                 wa_write_or(wal,
1100                             SUBSLICE_UNIT_LEVEL_CLKGATE2,
1101                             CPSSUNIT_CLKGATE_DIS);
1102
1103         /* Wa_1607087056:tgl also know as BUG:1409180338 */
1104         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
1105                 wa_write_or(wal,
1106                             SLICE_UNIT_LEVEL_CLKGATE,
1107                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
1108 }
1109
1110 static void
1111 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
1112 {
1113         if (IS_GEN(i915, 12))
1114                 tgl_gt_workarounds_init(i915, wal);
1115         else if (IS_GEN(i915, 11))
1116                 icl_gt_workarounds_init(i915, wal);
1117         else if (IS_CANNONLAKE(i915))
1118                 cnl_gt_workarounds_init(i915, wal);
1119         else if (IS_COFFEELAKE(i915))
1120                 cfl_gt_workarounds_init(i915, wal);
1121         else if (IS_GEMINILAKE(i915))
1122                 glk_gt_workarounds_init(i915, wal);
1123         else if (IS_KABYLAKE(i915))
1124                 kbl_gt_workarounds_init(i915, wal);
1125         else if (IS_BROXTON(i915))
1126                 bxt_gt_workarounds_init(i915, wal);
1127         else if (IS_SKYLAKE(i915))
1128                 skl_gt_workarounds_init(i915, wal);
1129         else if (IS_HASWELL(i915))
1130                 hsw_gt_workarounds_init(i915, wal);
1131         else if (IS_VALLEYVIEW(i915))
1132                 vlv_gt_workarounds_init(i915, wal);
1133         else if (IS_IVYBRIDGE(i915))
1134                 ivb_gt_workarounds_init(i915, wal);
1135         else if (INTEL_GEN(i915) <= 8)
1136                 return;
1137         else
1138                 MISSING_CASE(INTEL_GEN(i915));
1139 }
1140
1141 void intel_gt_init_workarounds(struct drm_i915_private *i915)
1142 {
1143         struct i915_wa_list *wal = &i915->gt_wa_list;
1144
1145         wa_init_start(wal, "GT", "global");
1146         gt_init_workarounds(i915, wal);
1147         wa_init_finish(wal);
1148 }
1149
1150 static enum forcewake_domains
1151 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1152 {
1153         enum forcewake_domains fw = 0;
1154         struct i915_wa *wa;
1155         unsigned int i;
1156
1157         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1158                 fw |= intel_uncore_forcewake_for_reg(uncore,
1159                                                      wa->reg,
1160                                                      FW_REG_READ |
1161                                                      FW_REG_WRITE);
1162
1163         return fw;
1164 }
1165
1166 static bool
1167 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
1168 {
1169         if ((cur ^ wa->set) & wa->read) {
1170                 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n",
1171                           name, from, i915_mmio_reg_offset(wa->reg),
1172                           cur, cur & wa->read, wa->set);
1173
1174                 return false;
1175         }
1176
1177         return true;
1178 }
1179
1180 static void
1181 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1182 {
1183         enum forcewake_domains fw;
1184         unsigned long flags;
1185         struct i915_wa *wa;
1186         unsigned int i;
1187
1188         if (!wal->count)
1189                 return;
1190
1191         fw = wal_get_fw_for_rmw(uncore, wal);
1192
1193         spin_lock_irqsave(&uncore->lock, flags);
1194         intel_uncore_forcewake_get__locked(uncore, fw);
1195
1196         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1197                 if (wa->clr)
1198                         intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set);
1199                 else
1200                         intel_uncore_write_fw(uncore, wa->reg, wa->set);
1201                 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1202                         wa_verify(wa,
1203                                   intel_uncore_read_fw(uncore, wa->reg),
1204                                   wal->name, "application");
1205         }
1206
1207         intel_uncore_forcewake_put__locked(uncore, fw);
1208         spin_unlock_irqrestore(&uncore->lock, flags);
1209 }
1210
1211 void intel_gt_apply_workarounds(struct intel_gt *gt)
1212 {
1213         wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
1214 }
1215
1216 static bool wa_list_verify(struct intel_uncore *uncore,
1217                            const struct i915_wa_list *wal,
1218                            const char *from)
1219 {
1220         struct i915_wa *wa;
1221         unsigned int i;
1222         bool ok = true;
1223
1224         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1225                 ok &= wa_verify(wa,
1226                                 intel_uncore_read(uncore, wa->reg),
1227                                 wal->name, from);
1228
1229         return ok;
1230 }
1231
1232 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1233 {
1234         return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
1235 }
1236
1237 static inline bool is_nonpriv_flags_valid(u32 flags)
1238 {
1239         /* Check only valid flag bits are set */
1240         if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1241                 return false;
1242
1243         /* NB: Only 3 out of 4 enum values are valid for access field */
1244         if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1245             RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1246                 return false;
1247
1248         return true;
1249 }
1250
1251 static void
1252 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1253 {
1254         struct i915_wa wa = {
1255                 .reg = reg
1256         };
1257
1258         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1259                 return;
1260
1261         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1262                 return;
1263
1264         wa.reg.reg |= flags;
1265         _wa_add(wal, &wa);
1266 }
1267
1268 static void
1269 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1270 {
1271         whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1272 }
1273
1274 static void gen9_whitelist_build(struct i915_wa_list *w)
1275 {
1276         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1277         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1278
1279         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1280         whitelist_reg(w, GEN8_CS_CHICKEN1);
1281
1282         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1283         whitelist_reg(w, GEN8_HDC_CHICKEN1);
1284
1285         /* WaSendPushConstantsFromMMIO:skl,bxt */
1286         whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1287 }
1288
1289 static void skl_whitelist_build(struct intel_engine_cs *engine)
1290 {
1291         struct i915_wa_list *w = &engine->whitelist;
1292
1293         if (engine->class != RENDER_CLASS)
1294                 return;
1295
1296         gen9_whitelist_build(w);
1297
1298         /* WaDisableLSQCROPERFforOCL:skl */
1299         whitelist_reg(w, GEN8_L3SQCREG4);
1300 }
1301
1302 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1303 {
1304         if (engine->class != RENDER_CLASS)
1305                 return;
1306
1307         gen9_whitelist_build(&engine->whitelist);
1308 }
1309
1310 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1311 {
1312         struct i915_wa_list *w = &engine->whitelist;
1313
1314         if (engine->class != RENDER_CLASS)
1315                 return;
1316
1317         gen9_whitelist_build(w);
1318
1319         /* WaDisableLSQCROPERFforOCL:kbl */
1320         whitelist_reg(w, GEN8_L3SQCREG4);
1321 }
1322
1323 static void glk_whitelist_build(struct intel_engine_cs *engine)
1324 {
1325         struct i915_wa_list *w = &engine->whitelist;
1326
1327         if (engine->class != RENDER_CLASS)
1328                 return;
1329
1330         gen9_whitelist_build(w);
1331
1332         /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1333         whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1334 }
1335
1336 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1337 {
1338         struct i915_wa_list *w = &engine->whitelist;
1339
1340         if (engine->class != RENDER_CLASS)
1341                 return;
1342
1343         gen9_whitelist_build(w);
1344
1345         /*
1346          * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1347          *
1348          * This covers 4 register which are next to one another :
1349          *   - PS_INVOCATION_COUNT
1350          *   - PS_INVOCATION_COUNT_UDW
1351          *   - PS_DEPTH_COUNT
1352          *   - PS_DEPTH_COUNT_UDW
1353          */
1354         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1355                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
1356                           RING_FORCE_TO_NONPRIV_RANGE_4);
1357 }
1358
1359 static void cnl_whitelist_build(struct intel_engine_cs *engine)
1360 {
1361         struct i915_wa_list *w = &engine->whitelist;
1362
1363         if (engine->class != RENDER_CLASS)
1364                 return;
1365
1366         /* WaEnablePreemptionGranularityControlByUMD:cnl */
1367         whitelist_reg(w, GEN8_CS_CHICKEN1);
1368 }
1369
1370 static void icl_whitelist_build(struct intel_engine_cs *engine)
1371 {
1372         struct i915_wa_list *w = &engine->whitelist;
1373
1374         switch (engine->class) {
1375         case RENDER_CLASS:
1376                 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1377                 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1378
1379                 /* WaAllowUMDToModifySamplerMode:icl */
1380                 whitelist_reg(w, GEN10_SAMPLER_MODE);
1381
1382                 /* WaEnableStateCacheRedirectToCS:icl */
1383                 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1384
1385                 /*
1386                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1387                  *
1388                  * This covers 4 register which are next to one another :
1389                  *   - PS_INVOCATION_COUNT
1390                  *   - PS_INVOCATION_COUNT_UDW
1391                  *   - PS_DEPTH_COUNT
1392                  *   - PS_DEPTH_COUNT_UDW
1393                  */
1394                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1395                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1396                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1397                 break;
1398
1399         case VIDEO_DECODE_CLASS:
1400                 /* hucStatusRegOffset */
1401                 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1402                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1403                 /* hucUKernelHdrInfoRegOffset */
1404                 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1405                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1406                 /* hucStatus2RegOffset */
1407                 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1408                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1409                 break;
1410
1411         default:
1412                 break;
1413         }
1414 }
1415
1416 static void tgl_whitelist_build(struct intel_engine_cs *engine)
1417 {
1418         struct i915_wa_list *w = &engine->whitelist;
1419
1420         switch (engine->class) {
1421         case RENDER_CLASS:
1422                 /*
1423                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
1424                  * Wa_1408556865:tgl
1425                  *
1426                  * This covers 4 registers which are next to one another :
1427                  *   - PS_INVOCATION_COUNT
1428                  *   - PS_INVOCATION_COUNT_UDW
1429                  *   - PS_DEPTH_COUNT
1430                  *   - PS_DEPTH_COUNT_UDW
1431                  */
1432                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1433                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1434                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1435
1436                 /* Wa_1808121037:tgl */
1437                 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
1438
1439                 /* Wa_1806527549:tgl */
1440                 whitelist_reg(w, HIZ_CHICKEN);
1441                 break;
1442         default:
1443                 break;
1444         }
1445 }
1446
1447 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1448 {
1449         struct drm_i915_private *i915 = engine->i915;
1450         struct i915_wa_list *w = &engine->whitelist;
1451
1452         wa_init_start(w, "whitelist", engine->name);
1453
1454         if (IS_GEN(i915, 12))
1455                 tgl_whitelist_build(engine);
1456         else if (IS_GEN(i915, 11))
1457                 icl_whitelist_build(engine);
1458         else if (IS_CANNONLAKE(i915))
1459                 cnl_whitelist_build(engine);
1460         else if (IS_COFFEELAKE(i915))
1461                 cfl_whitelist_build(engine);
1462         else if (IS_GEMINILAKE(i915))
1463                 glk_whitelist_build(engine);
1464         else if (IS_KABYLAKE(i915))
1465                 kbl_whitelist_build(engine);
1466         else if (IS_BROXTON(i915))
1467                 bxt_whitelist_build(engine);
1468         else if (IS_SKYLAKE(i915))
1469                 skl_whitelist_build(engine);
1470         else if (INTEL_GEN(i915) <= 8)
1471                 return;
1472         else
1473                 MISSING_CASE(INTEL_GEN(i915));
1474
1475         wa_init_finish(w);
1476 }
1477
1478 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1479 {
1480         const struct i915_wa_list *wal = &engine->whitelist;
1481         struct intel_uncore *uncore = engine->uncore;
1482         const u32 base = engine->mmio_base;
1483         struct i915_wa *wa;
1484         unsigned int i;
1485
1486         if (!wal->count)
1487                 return;
1488
1489         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1490                 intel_uncore_write(uncore,
1491                                    RING_FORCE_TO_NONPRIV(base, i),
1492                                    i915_mmio_reg_offset(wa->reg));
1493
1494         /* And clear the rest just in case of garbage */
1495         for (; i < RING_MAX_NONPRIV_SLOTS; i++)
1496                 intel_uncore_write(uncore,
1497                                    RING_FORCE_TO_NONPRIV(base, i),
1498                                    i915_mmio_reg_offset(RING_NOPID(base)));
1499 }
1500
1501 static void
1502 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1503 {
1504         struct drm_i915_private *i915 = engine->i915;
1505
1506         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
1507                 /*
1508                  * Wa_1607138336:tgl
1509                  * Wa_1607063988:tgl
1510                  */
1511                 wa_write_or(wal,
1512                             GEN9_CTX_PREEMPT_REG,
1513                             GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
1514
1515                 /*
1516                  * Wa_1607030317:tgl
1517                  * Wa_1607186500:tgl
1518                  * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
1519                  * of then says it is fixed on B0 the other one says it is
1520                  * permanent
1521                  */
1522                 wa_masked_en(wal,
1523                              GEN6_RC_SLEEP_PSMI_CONTROL,
1524                              GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
1525                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
1526
1527                 /*
1528                  * Wa_1606679103:tgl
1529                  * (see also Wa_1606682166:icl)
1530                  */
1531                 wa_write_or(wal,
1532                             GEN7_SARCHKMD,
1533                             GEN7_DISABLE_SAMPLER_PREFETCH);
1534
1535                 /* Wa_1407928979:tgl */
1536                 wa_write_or(wal,
1537                             GEN7_FF_THREAD_MODE,
1538                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
1539
1540                 /* Wa_1408615072:tgl */
1541                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1542                             VSUNIT_CLKGATE_DIS_TGL);
1543         }
1544
1545         if (IS_TIGERLAKE(i915)) {
1546                 /* Wa_1606931601:tgl */
1547                 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
1548
1549                 /* Wa_1409804808:tgl */
1550                 wa_masked_en(wal, GEN7_ROW_CHICKEN2,
1551                              GEN12_PUSH_CONST_DEREF_HOLD_DIS);
1552
1553                 /* Wa_1606700617:tgl */
1554                 wa_masked_en(wal,
1555                              GEN9_CS_DEBUG_MODE1,
1556                              FF_DOP_CLOCK_GATE_DISABLE);
1557
1558                 /*
1559                  * Wa_1409085225:tgl
1560                  * Wa_14010229206:tgl
1561                  */
1562                 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
1563         }
1564
1565         if (IS_GEN(i915, 11)) {
1566                 /* This is not an Wa. Enable for better image quality */
1567                 wa_masked_en(wal,
1568                              _3D_CHICKEN3,
1569                              _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1570
1571                 /* WaPipelineFlushCoherentLines:icl */
1572                 wa_write_or(wal,
1573                             GEN8_L3SQCREG4,
1574                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1575
1576                 /*
1577                  * Wa_1405543622:icl
1578                  * Formerly known as WaGAPZPriorityScheme
1579                  */
1580                 wa_write_or(wal,
1581                             GEN8_GARBCNTL,
1582                             GEN11_ARBITRATION_PRIO_ORDER_MASK);
1583
1584                 /*
1585                  * Wa_1604223664:icl
1586                  * Formerly known as WaL3BankAddressHashing
1587                  */
1588                 wa_write_masked_or(wal,
1589                                    GEN8_GARBCNTL,
1590                                    GEN11_HASH_CTRL_EXCL_MASK,
1591                                    GEN11_HASH_CTRL_EXCL_BIT0);
1592                 wa_write_masked_or(wal,
1593                                    GEN11_GLBLINVL,
1594                                    GEN11_BANK_HASH_ADDR_EXCL_MASK,
1595                                    GEN11_BANK_HASH_ADDR_EXCL_BIT0);
1596
1597                 /*
1598                  * Wa_1405733216:icl
1599                  * Formerly known as WaDisableCleanEvicts
1600                  */
1601                 wa_write_or(wal,
1602                             GEN8_L3SQCREG4,
1603                             GEN11_LQSC_CLEAN_EVICT_DISABLE);
1604
1605                 /* WaForwardProgressSoftReset:icl */
1606                 wa_write_or(wal,
1607                             GEN10_SCRATCH_LNCF2,
1608                             PMFLUSHDONE_LNICRSDROP |
1609                             PMFLUSH_GAPL3UNBLOCK |
1610                             PMFLUSHDONE_LNEBLK);
1611
1612                 /* Wa_1406609255:icl (pre-prod) */
1613                 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1614                         wa_write_or(wal,
1615                                     GEN7_SARCHKMD,
1616                                     GEN7_DISABLE_DEMAND_PREFETCH);
1617
1618                 /* Wa_1606682166:icl */
1619                 wa_write_or(wal,
1620                             GEN7_SARCHKMD,
1621                             GEN7_DISABLE_SAMPLER_PREFETCH);
1622
1623                 /* Wa_1409178092:icl */
1624                 wa_write_masked_or(wal,
1625                                    GEN11_SCRATCH2,
1626                                    GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
1627                                    0);
1628
1629                 /* WaEnable32PlaneMode:icl */
1630                 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
1631                              GEN11_ENABLE_32_PLANE_MODE);
1632
1633                 /*
1634                  * Wa_1408615072:icl,ehl  (vsunit)
1635                  * Wa_1407596294:icl,ehl  (hsunit)
1636                  */
1637                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1638                             VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
1639
1640                 /* Wa_1407352427:icl,ehl */
1641                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1642                             PSDUNIT_CLKGATE_DIS);
1643
1644                 /* Wa_1406680159:icl,ehl */
1645                 wa_write_or(wal,
1646                             SUBSLICE_UNIT_LEVEL_CLKGATE,
1647                             GWUNIT_CLKGATE_DIS);
1648
1649                 /*
1650                  * Wa_1408767742:icl[a2..forever],ehl[all]
1651                  * Wa_1605460711:icl[a0..c0]
1652                  */
1653                 wa_write_or(wal,
1654                             GEN7_FF_THREAD_MODE,
1655                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
1656         }
1657
1658         if (IS_GEN_RANGE(i915, 9, 12)) {
1659                 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
1660                 wa_masked_en(wal,
1661                              GEN7_FF_SLICE_CS_CHICKEN1,
1662                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
1663         }
1664
1665         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
1666                 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1667                 wa_write_or(wal,
1668                             GEN8_GARBCNTL,
1669                             GEN9_GAPS_TSV_CREDIT_DISABLE);
1670         }
1671
1672         if (IS_BROXTON(i915)) {
1673                 /* WaDisablePooledEuLoadBalancingFix:bxt */
1674                 wa_masked_en(wal,
1675                              FF_SLICE_CS_CHICKEN2,
1676                              GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1677         }
1678
1679         if (IS_GEN(i915, 9)) {
1680                 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1681                 wa_masked_en(wal,
1682                              GEN9_CSFE_CHICKEN1_RCS,
1683                              GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
1684
1685                 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1686                 wa_write_or(wal,
1687                             BDW_SCRATCH1,
1688                             GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1689
1690                 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1691                 if (IS_GEN9_LP(i915))
1692                         wa_write_masked_or(wal,
1693                                            GEN8_L3SQCREG1,
1694                                            L3_PRIO_CREDITS_MASK,
1695                                            L3_GENERAL_PRIO_CREDITS(62) |
1696                                            L3_HIGH_PRIO_CREDITS(2));
1697
1698                 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1699                 wa_write_or(wal,
1700                             GEN8_L3SQCREG4,
1701                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1702         }
1703
1704         if (IS_GEN(i915, 7))
1705                 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1706                 wa_masked_en(wal,
1707                              GFX_MODE_GEN7,
1708                              GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
1709
1710         if (IS_GEN_RANGE(i915, 6, 7))
1711                 /*
1712                  * We need to disable the AsyncFlip performance optimisations in
1713                  * order to use MI_WAIT_FOR_EVENT within the CS. It should
1714                  * already be programmed to '1' on all products.
1715                  *
1716                  * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1717                  */
1718                 wa_masked_en(wal,
1719                              MI_MODE,
1720                              ASYNC_FLIP_PERF_DISABLE);
1721
1722         if (IS_GEN(i915, 6)) {
1723                 /*
1724                  * Required for the hardware to program scanline values for
1725                  * waiting
1726                  * WaEnableFlushTlbInvalidationMode:snb
1727                  */
1728                 wa_masked_en(wal,
1729                              GFX_MODE,
1730                              GFX_TLB_INVALIDATE_EXPLICIT);
1731
1732                 /*
1733                  * From the Sandybridge PRM, volume 1 part 3, page 24:
1734                  * "If this bit is set, STCunit will have LRA as replacement
1735                  *  policy. [...] This bit must be reset. LRA replacement
1736                  *  policy is not supported."
1737                  */
1738                 wa_masked_dis(wal,
1739                               CACHE_MODE_0,
1740                               CM0_STC_EVICT_DISABLE_LRA_SNB);
1741         }
1742
1743         if (IS_GEN_RANGE(i915, 4, 6))
1744                 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1745                 wa_add(wal, MI_MODE,
1746                        0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
1747                        /* XXX bit doesn't stick on Broadwater */
1748                        IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
1749 }
1750
1751 static void
1752 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1753 {
1754         struct drm_i915_private *i915 = engine->i915;
1755
1756         /* WaKBLVECSSemaphoreWaitPoll:kbl */
1757         if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
1758                 wa_write(wal,
1759                          RING_SEMA_WAIT_POLL(engine->mmio_base),
1760                          1);
1761         }
1762 }
1763
1764 static void
1765 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1766 {
1767         if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
1768                 return;
1769
1770         if (engine->class == RENDER_CLASS)
1771                 rcs_engine_wa_init(engine, wal);
1772         else
1773                 xcs_engine_wa_init(engine, wal);
1774 }
1775
1776 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1777 {
1778         struct i915_wa_list *wal = &engine->wa_list;
1779
1780         if (INTEL_GEN(engine->i915) < 4)
1781                 return;
1782
1783         wa_init_start(wal, "engine", engine->name);
1784         engine_init_workarounds(engine, wal);
1785         wa_init_finish(wal);
1786 }
1787
1788 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1789 {
1790         wa_list_apply(engine->uncore, &engine->wa_list);
1791 }
1792
1793 static struct i915_vma *
1794 create_scratch(struct i915_address_space *vm, int count)
1795 {
1796         struct drm_i915_gem_object *obj;
1797         struct i915_vma *vma;
1798         unsigned int size;
1799         int err;
1800
1801         size = round_up(count * sizeof(u32), PAGE_SIZE);
1802         obj = i915_gem_object_create_internal(vm->i915, size);
1803         if (IS_ERR(obj))
1804                 return ERR_CAST(obj);
1805
1806         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1807
1808         vma = i915_vma_instance(obj, vm, NULL);
1809         if (IS_ERR(vma)) {
1810                 err = PTR_ERR(vma);
1811                 goto err_obj;
1812         }
1813
1814         err = i915_vma_pin(vma, 0, 0,
1815                            i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
1816         if (err)
1817                 goto err_obj;
1818
1819         return vma;
1820
1821 err_obj:
1822         i915_gem_object_put(obj);
1823         return ERR_PTR(err);
1824 }
1825
1826 static const struct {
1827         u32 start;
1828         u32 end;
1829 } mcr_ranges_gen8[] = {
1830         { .start = 0x5500, .end = 0x55ff },
1831         { .start = 0x7000, .end = 0x7fff },
1832         { .start = 0x9400, .end = 0x97ff },
1833         { .start = 0xb000, .end = 0xb3ff },
1834         { .start = 0xe000, .end = 0xe7ff },
1835         {},
1836 };
1837
1838 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
1839 {
1840         int i;
1841
1842         if (INTEL_GEN(i915) < 8)
1843                 return false;
1844
1845         /*
1846          * Registers in these ranges are affected by the MCR selector
1847          * which only controls CPU initiated MMIO. Routing does not
1848          * work for CS access so we cannot verify them on this path.
1849          */
1850         for (i = 0; mcr_ranges_gen8[i].start; i++)
1851                 if (offset >= mcr_ranges_gen8[i].start &&
1852                     offset <= mcr_ranges_gen8[i].end)
1853                         return true;
1854
1855         return false;
1856 }
1857
1858 static int
1859 wa_list_srm(struct i915_request *rq,
1860             const struct i915_wa_list *wal,
1861             struct i915_vma *vma)
1862 {
1863         struct drm_i915_private *i915 = rq->i915;
1864         unsigned int i, count = 0;
1865         const struct i915_wa *wa;
1866         u32 srm, *cs;
1867
1868         srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1869         if (INTEL_GEN(i915) >= 8)
1870                 srm++;
1871
1872         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1873                 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
1874                         count++;
1875         }
1876
1877         cs = intel_ring_begin(rq, 4 * count);
1878         if (IS_ERR(cs))
1879                 return PTR_ERR(cs);
1880
1881         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1882                 u32 offset = i915_mmio_reg_offset(wa->reg);
1883
1884                 if (mcr_range(i915, offset))
1885                         continue;
1886
1887                 *cs++ = srm;
1888                 *cs++ = offset;
1889                 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
1890                 *cs++ = 0;
1891         }
1892         intel_ring_advance(rq, cs);
1893
1894         return 0;
1895 }
1896
1897 static int engine_wa_list_verify(struct intel_context *ce,
1898                                  const struct i915_wa_list * const wal,
1899                                  const char *from)
1900 {
1901         const struct i915_wa *wa;
1902         struct i915_request *rq;
1903         struct i915_vma *vma;
1904         unsigned int i;
1905         u32 *results;
1906         int err;
1907
1908         if (!wal->count)
1909                 return 0;
1910
1911         vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1912         if (IS_ERR(vma))
1913                 return PTR_ERR(vma);
1914
1915         intel_engine_pm_get(ce->engine);
1916         rq = intel_context_create_request(ce);
1917         intel_engine_pm_put(ce->engine);
1918         if (IS_ERR(rq)) {
1919                 err = PTR_ERR(rq);
1920                 goto err_vma;
1921         }
1922
1923         i915_vma_lock(vma);
1924         err = i915_request_await_object(rq, vma->obj, true);
1925         if (err == 0)
1926                 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1927         i915_vma_unlock(vma);
1928         if (err) {
1929                 i915_request_add(rq);
1930                 goto err_vma;
1931         }
1932
1933         err = wa_list_srm(rq, wal, vma);
1934         if (err)
1935                 goto err_vma;
1936
1937         i915_request_get(rq);
1938         i915_request_add(rq);
1939         if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1940                 err = -ETIME;
1941                 goto err_rq;
1942         }
1943
1944         results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1945         if (IS_ERR(results)) {
1946                 err = PTR_ERR(results);
1947                 goto err_rq;
1948         }
1949
1950         err = 0;
1951         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1952                 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
1953                         continue;
1954
1955                 if (!wa_verify(wa, results[i], wal->name, from))
1956                         err = -ENXIO;
1957         }
1958
1959         i915_gem_object_unpin_map(vma->obj);
1960
1961 err_rq:
1962         i915_request_put(rq);
1963 err_vma:
1964         i915_vma_unpin(vma);
1965         i915_vma_put(vma);
1966         return err;
1967 }
1968
1969 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
1970                                     const char *from)
1971 {
1972         return engine_wa_list_verify(engine->kernel_context,
1973                                      &engine->wa_list,
1974                                      from);
1975 }
1976
1977 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1978 #include "selftest_workarounds.c"
1979 #endif