drivers/gpu/drm/i915/gt/intel_reset.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2008-2018 Intel Corporation
   5  */
   6
   7 #include <linux/sched/mm.h>
   8 #include <linux/stop_machine.h>
   9
  10 #include "display/intel_display_types.h"
  11 #include "display/intel_overlay.h"
  12
  13 #include "gem/i915_gem_context.h"
  14
  15 #include "i915_drv.h"
  16 #include "i915_gpu_error.h"
  17 #include "i915_irq.h"
  18 #include "intel_breadcrumbs.h"
  19 #include "intel_engine_pm.h"
  20 #include "intel_gt.h"
  21 #include "intel_gt_pm.h"
  22 #include "intel_gt_requests.h"
  23 #include "intel_reset.h"
  24
  25 #include "uc/intel_guc.h"
  26 #include "uc/intel_guc_submission.h"
  27
  28 #define RESET_MAX_RETRIES 3
  29
  30 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  31 #define RESET_UNDER_STOP_MACHINE 0
  32
  33 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
  34 {
  35         intel_uncore_rmw_fw(uncore, reg, 0, set);
  36 }
  37
  38 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
  39 {
  40         intel_uncore_rmw_fw(uncore, reg, clr, 0);
  41 }
  42
  43 static void skip_context(struct i915_request *rq)
  44 {
  45         struct intel_context *hung_ctx = rq->context;
  46
  47         list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
  48                 if (!i915_request_is_active(rq))
  49                         return;
  50
  51                 if (rq->context == hung_ctx) {
  52                         i915_request_set_error_once(rq, -EIO);
  53                         __i915_request_skip(rq);
  54                 }
  55         }
  56 }
  57
  58 static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
  59 {
  60         struct drm_i915_file_private *file_priv = ctx->file_priv;
  61         unsigned long prev_hang;
  62         unsigned int score;
  63
  64         if (IS_ERR_OR_NULL(file_priv))
  65                 return;
  66
  67         score = 0;
  68         if (banned)
  69                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  70
  71         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  72         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  73                 score += I915_CLIENT_SCORE_HANG_FAST;
  74
  75         if (score) {
  76                 atomic_add(score, &file_priv->ban_score);
  77
  78                 drm_dbg(&ctx->i915->drm,
  79                         "client %s: gained %u ban score, now %u\n",
  80                         ctx->name, score,
  81                         atomic_read(&file_priv->ban_score));
  82         }
  83 }
  84
  85 static bool mark_guilty(struct i915_request *rq)
  86 {
  87         struct i915_gem_context *ctx;
  88         unsigned long prev_hang;
  89         bool banned;
  90         int i;
  91
  92         if (intel_context_is_closed(rq->context)) {
  93                 intel_context_set_banned(rq->context);
  94                 return true;
  95         }
  96
  97         rcu_read_lock();
  98         ctx = rcu_dereference(rq->context->gem_context);
  99         if (ctx && !kref_get_unless_zero(&ctx->ref))
 100                 ctx = NULL;
 101         rcu_read_unlock();
 102         if (!ctx)
 103                 return intel_context_is_banned(rq->context);
 104
 105         atomic_inc(&ctx->guilty_count);
 106
 107         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
 108         if (!i915_gem_context_is_bannable(ctx)) {
 109                 banned = false;
 110                 goto out;
 111         }
 112
 113         drm_notice(&ctx->i915->drm,
 114                    "%s context reset due to GPU hang\n",
 115                    ctx->name);
 116
 117         /* Record the timestamp for the last N hangs */
 118         prev_hang = ctx->hang_timestamp[0];
 119         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
 120                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
 121         ctx->hang_timestamp[i] = jiffies;
 122
 123         /* If we have hung N+1 times in rapid succession, we ban the context! */
 124         banned = !i915_gem_context_is_recoverable(ctx);
 125         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
 126                 banned = true;
 127         if (banned) {
 128                 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
 129                         ctx->name, atomic_read(&ctx->guilty_count));
 130                 intel_context_set_banned(rq->context);
 131         }
 132
 133         client_mark_guilty(ctx, banned);
 134
 135 out:
 136         i915_gem_context_put(ctx);
 137         return banned;
 138 }
 139
 140 static void mark_innocent(struct i915_request *rq)
 141 {
 142         struct i915_gem_context *ctx;
 143
 144         rcu_read_lock();
 145         ctx = rcu_dereference(rq->context->gem_context);
 146         if (ctx)
 147                 atomic_inc(&ctx->active_count);
 148         rcu_read_unlock();
 149 }
 150
 151 void __i915_request_reset(struct i915_request *rq, bool guilty)
 152 {
 153         RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
 154         GEM_BUG_ON(__i915_request_is_complete(rq));
 155
 156         rcu_read_lock(); /* protect the GEM context */
 157         if (guilty) {
 158                 i915_request_set_error_once(rq, -EIO);
 159                 __i915_request_skip(rq);
 160                 if (mark_guilty(rq))
 161                         skip_context(rq);
 162         } else {
 163                 i915_request_set_error_once(rq, -EAGAIN);
 164                 mark_innocent(rq);
 165         }
 166         rcu_read_unlock();
 167 }
 168
 169 static bool i915_in_reset(struct pci_dev *pdev)
 170 {
 171         u8 gdrst;
 172
 173         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 174         return gdrst & GRDOM_RESET_STATUS;
 175 }
 176
 177 static int i915_do_reset(struct intel_gt *gt,
 178                          intel_engine_mask_t engine_mask,
 179                          unsigned int retry)
 180 {
 181         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 182         int err;
 183
 184         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 185         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 186         udelay(50);
 187         err = wait_for_atomic(i915_in_reset(pdev), 50);
 188
 189         /* Clear the reset request. */
 190         pci_write_config_byte(pdev, I915_GDRST, 0);
 191         udelay(50);
 192         if (!err)
 193                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 194
 195         return err;
 196 }
 197
 198 static bool g4x_reset_complete(struct pci_dev *pdev)
 199 {
 200         u8 gdrst;
 201
 202         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 203         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 204 }
 205
 206 static int g33_do_reset(struct intel_gt *gt,
 207                         intel_engine_mask_t engine_mask,
 208                         unsigned int retry)
 209 {
 210         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 211
 212         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 213         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 214 }
 215
 216 static int g4x_do_reset(struct intel_gt *gt,
 217                         intel_engine_mask_t engine_mask,
 218                         unsigned int retry)
 219 {
 220         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 221         struct intel_uncore *uncore = gt->uncore;
 222         int ret;
 223
 224         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 225         rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 226         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 227
 228         pci_write_config_byte(pdev, I915_GDRST,
 229                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 230         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 231         if (ret) {
 232                 GT_TRACE(gt, "Wait for media reset failed\n");
 233                 goto out;
 234         }
 235
 236         pci_write_config_byte(pdev, I915_GDRST,
 237                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 238         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 239         if (ret) {
 240                 GT_TRACE(gt, "Wait for render reset failed\n");
 241                 goto out;
 242         }
 243
 244 out:
 245         pci_write_config_byte(pdev, I915_GDRST, 0);
 246
 247         rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 248         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 249
 250         return ret;
 251 }
 252
 253 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
 254                         unsigned int retry)
 255 {
 256         struct intel_uncore *uncore = gt->uncore;
 257         int ret;
 258
 259         intel_uncore_write_fw(uncore, ILK_GDSR,
 260                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 261         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 262                                            ILK_GRDOM_RESET_ENABLE, 0,
 263                                            5000, 0,
 264                                            NULL);
 265         if (ret) {
 266                 GT_TRACE(gt, "Wait for render reset failed\n");
 267                 goto out;
 268         }
 269
 270         intel_uncore_write_fw(uncore, ILK_GDSR,
 271                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 272         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 273                                            ILK_GRDOM_RESET_ENABLE, 0,
 274                                            5000, 0,
 275                                            NULL);
 276         if (ret) {
 277                 GT_TRACE(gt, "Wait for media reset failed\n");
 278                 goto out;
 279         }
 280
 281 out:
 282         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 283         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 284         return ret;
 285 }
 286
 287 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 288 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 289 {
 290         struct intel_uncore *uncore = gt->uncore;
 291         int err;
 292
 293         /*
 294          * GEN6_GDRST is not in the gt power well, no need to check
 295          * for fifo space for the write or forcewake the chip for
 296          * the read
 297          */
 298         intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 299
 300         /* Wait for the device to ack the reset requests */
 301         err = __intel_wait_for_register_fw(uncore,
 302                                            GEN6_GDRST, hw_domain_mask, 0,
 303                                            500, 0,
 304                                            NULL);
 305         if (err)
 306                 GT_TRACE(gt,
 307                          "Wait for 0x%08x engines reset failed\n",
 308                          hw_domain_mask);
 309
 310         return err;
 311 }
 312
 313 static int gen6_reset_engines(struct intel_gt *gt,
 314                               intel_engine_mask_t engine_mask,
 315                               unsigned int retry)
 316 {
 317         static const u32 hw_engine_mask[] = {
 318                 [RCS0]  = GEN6_GRDOM_RENDER,
 319                 [BCS0]  = GEN6_GRDOM_BLT,
 320                 [VCS0]  = GEN6_GRDOM_MEDIA,
 321                 [VCS1]  = GEN8_GRDOM_MEDIA2,
 322                 [VECS0] = GEN6_GRDOM_VECS,
 323         };
 324         struct intel_engine_cs *engine;
 325         u32 hw_mask;
 326
 327         if (engine_mask == ALL_ENGINES) {
 328                 hw_mask = GEN6_GRDOM_FULL;
 329         } else {
 330                 intel_engine_mask_t tmp;
 331
 332                 hw_mask = 0;
 333                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 334                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 335                         hw_mask |= hw_engine_mask[engine->id];
 336                 }
 337         }
 338
 339         return gen6_hw_domain_reset(gt, hw_mask);
 340 }
 341
 342 static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
 343 {
 344         struct intel_uncore *uncore = engine->uncore;
 345         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 346         i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
 347         u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
 348         i915_reg_t sfc_usage;
 349         u32 sfc_usage_bit;
 350         u32 sfc_reset_bit;
 351         int ret;
 352
 353         switch (engine->class) {
 354         case VIDEO_DECODE_CLASS:
 355                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 356                         return 0;
 357
 358                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 359                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 360
 361                 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
 362                 sfc_forced_lock_ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 363
 364                 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
 365                 sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 366                 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 367                 break;
 368
 369         case VIDEO_ENHANCEMENT_CLASS:
 370                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 371                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 372
 373                 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
 374                 sfc_forced_lock_ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 375
 376                 sfc_usage = GEN11_VECS_SFC_USAGE(engine);
 377                 sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 378                 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 379                 break;
 380
 381         default:
 382                 return 0;
 383         }
 384
 385         /*
 386          * If the engine is using a SFC, tell the engine that a software reset
 387          * is going to happen. The engine will then try to force lock the SFC.
 388          * If SFC ends up being locked to the engine we want to reset, we have
 389          * to reset it as well (we will unlock it once the reset sequence is
 390          * completed).
 391          */
 392         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 393                 return 0;
 394
 395         rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 396
 397         ret = __intel_wait_for_register_fw(uncore,
 398                                            sfc_forced_lock_ack,
 399                                            sfc_forced_lock_ack_bit,
 400                                            sfc_forced_lock_ack_bit,
 401                                            1000, 0, NULL);
 402
 403         /* Was the SFC released while we were trying to lock it? */
 404         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 405                 return 0;
 406
 407         if (ret) {
 408                 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
 409                 return ret;
 410         }
 411
 412         *hw_mask |= sfc_reset_bit;
 413         return 0;
 414 }
 415
 416 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
 417 {
 418         struct intel_uncore *uncore = engine->uncore;
 419         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 420         i915_reg_t sfc_forced_lock;
 421         u32 sfc_forced_lock_bit;
 422
 423         switch (engine->class) {
 424         case VIDEO_DECODE_CLASS:
 425                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 426                         return;
 427
 428                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 429                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 430                 break;
 431
 432         case VIDEO_ENHANCEMENT_CLASS:
 433                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 434                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 435                 break;
 436
 437         default:
 438                 return;
 439         }
 440
 441         rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 442 }
 443
 444 static int gen11_reset_engines(struct intel_gt *gt,
 445                                intel_engine_mask_t engine_mask,
 446                                unsigned int retry)
 447 {
 448         static const u32 hw_engine_mask[] = {
 449                 [RCS0]  = GEN11_GRDOM_RENDER,
 450                 [BCS0]  = GEN11_GRDOM_BLT,
 451                 [VCS0]  = GEN11_GRDOM_MEDIA,
 452                 [VCS1]  = GEN11_GRDOM_MEDIA2,
 453                 [VCS2]  = GEN11_GRDOM_MEDIA3,
 454                 [VCS3]  = GEN11_GRDOM_MEDIA4,
 455                 [VECS0] = GEN11_GRDOM_VECS,
 456                 [VECS1] = GEN11_GRDOM_VECS2,
 457         };
 458         struct intel_engine_cs *engine;
 459         intel_engine_mask_t tmp;
 460         u32 hw_mask;
 461         int ret;
 462
 463         if (engine_mask == ALL_ENGINES) {
 464                 hw_mask = GEN11_GRDOM_FULL;
 465         } else {
 466                 hw_mask = 0;
 467                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 468                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 469                         hw_mask |= hw_engine_mask[engine->id];
 470                         ret = gen11_lock_sfc(engine, &hw_mask);
 471                         if (ret)
 472                                 goto sfc_unlock;
 473                 }
 474         }
 475
 476         ret = gen6_hw_domain_reset(gt, hw_mask);
 477
 478 sfc_unlock:
 479         /*
 480          * We unlock the SFC based on the lock status and not the result of
 481          * gen11_lock_sfc to make sure that we clean properly if something
 482          * wrong happened during the lock (e.g. lock acquired after timeout
 483          * expiration).
 484          */
 485         if (engine_mask != ALL_ENGINES)
 486                 for_each_engine_masked(engine, gt, engine_mask, tmp)
 487                         gen11_unlock_sfc(engine);
 488
 489         return ret;
 490 }
 491
 492 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 493 {
 494         struct intel_uncore *uncore = engine->uncore;
 495         const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
 496         u32 request, mask, ack;
 497         int ret;
 498
 499         if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
 500                 return -ETIMEDOUT;
 501
 502         ack = intel_uncore_read_fw(uncore, reg);
 503         if (ack & RESET_CTL_CAT_ERROR) {
 504                 /*
 505                  * For catastrophic errors, ready-for-reset sequence
 506                  * needs to be bypassed: HAS#396813
 507                  */
 508                 request = RESET_CTL_CAT_ERROR;
 509                 mask = RESET_CTL_CAT_ERROR;
 510
 511                 /* Catastrophic errors need to be cleared by HW */
 512                 ack = 0;
 513         } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
 514                 request = RESET_CTL_REQUEST_RESET;
 515                 mask = RESET_CTL_READY_TO_RESET;
 516                 ack = RESET_CTL_READY_TO_RESET;
 517         } else {
 518                 return 0;
 519         }
 520
 521         intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
 522         ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 523                                            700, 0, NULL);
 524         if (ret)
 525                 drm_err(&engine->i915->drm,
 526                         "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
 527                         engine->name, request,
 528                         intel_uncore_read_fw(uncore, reg));
 529
 530         return ret;
 531 }
 532
 533 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 534 {
 535         intel_uncore_write_fw(engine->uncore,
 536                               RING_RESET_CTL(engine->mmio_base),
 537                               _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 538 }
 539
 540 static int gen8_reset_engines(struct intel_gt *gt,
 541                               intel_engine_mask_t engine_mask,
 542                               unsigned int retry)
 543 {
 544         struct intel_engine_cs *engine;
 545         const bool reset_non_ready = retry >= 1;
 546         intel_engine_mask_t tmp;
 547         int ret;
 548
 549         for_each_engine_masked(engine, gt, engine_mask, tmp) {
 550                 ret = gen8_engine_reset_prepare(engine);
 551                 if (ret && !reset_non_ready)
 552                         goto skip_reset;
 553
 554                 /*
 555                  * If this is not the first failed attempt to prepare,
 556                  * we decide to proceed anyway.
 557                  *
 558                  * By doing so we risk context corruption and with
 559                  * some gens (kbl), possible system hang if reset
 560                  * happens during active bb execution.
 561                  *
 562                  * We rather take context corruption instead of
 563                  * failed reset with a wedged driver/gpu. And
 564                  * active bb execution case should be covered by
 565                  * stop_engines() we have before the reset.
 566                  */
 567         }
 568
 569         if (INTEL_GEN(gt->i915) >= 11)
 570                 ret = gen11_reset_engines(gt, engine_mask, retry);
 571         else
 572                 ret = gen6_reset_engines(gt, engine_mask, retry);
 573
 574 skip_reset:
 575         for_each_engine_masked(engine, gt, engine_mask, tmp)
 576                 gen8_engine_reset_cancel(engine);
 577
 578         return ret;
 579 }
 580
 581 static int mock_reset(struct intel_gt *gt,
 582                       intel_engine_mask_t mask,
 583                       unsigned int retry)
 584 {
 585         return 0;
 586 }
 587
 588 typedef int (*reset_func)(struct intel_gt *,
 589                           intel_engine_mask_t engine_mask,
 590                           unsigned int retry);
 591
 592 static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
 593 {
 594         struct drm_i915_private *i915 = gt->i915;
 595
 596         if (is_mock_gt(gt))
 597                 return mock_reset;
 598         else if (INTEL_GEN(i915) >= 8)
 599                 return gen8_reset_engines;
 600         else if (INTEL_GEN(i915) >= 6)
 601                 return gen6_reset_engines;
 602         else if (INTEL_GEN(i915) >= 5)
 603                 return ilk_do_reset;
 604         else if (IS_G4X(i915))
 605                 return g4x_do_reset;
 606         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 607                 return g33_do_reset;
 608         else if (INTEL_GEN(i915) >= 3)
 609                 return i915_do_reset;
 610         else
 611                 return NULL;
 612 }
 613
 614 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 615 {
 616         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 617         reset_func reset;
 618         int ret = -ETIMEDOUT;
 619         int retry;
 620
 621         reset = intel_get_gpu_reset(gt);
 622         if (!reset)
 623                 return -ENODEV;
 624
 625         /*
 626          * If the power well sleeps during the reset, the reset
 627          * request may be dropped and never completes (causing -EIO).
 628          */
 629         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 630         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 631                 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
 632                 preempt_disable();
 633                 ret = reset(gt, engine_mask, retry);
 634                 preempt_enable();
 635         }
 636         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 637
 638         return ret;
 639 }
 640
 641 bool intel_has_gpu_reset(const struct intel_gt *gt)
 642 {
 643         if (!gt->i915->params.reset)
 644                 return NULL;
 645
 646         return intel_get_gpu_reset(gt);
 647 }
 648
 649 bool intel_has_reset_engine(const struct intel_gt *gt)
 650 {
 651         if (gt->i915->params.reset < 2)
 652                 return false;
 653
 654         return INTEL_INFO(gt->i915)->has_reset_engine;
 655 }
 656
 657 int intel_reset_guc(struct intel_gt *gt)
 658 {
 659         u32 guc_domain =
 660                 INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 661         int ret;
 662
 663         GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 664
 665         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 666         ret = gen6_hw_domain_reset(gt, guc_domain);
 667         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 668
 669         return ret;
 670 }
 671
 672 /*
 673  * Ensure irq handler finishes, and not run again.
 674  * Also return the active request so that we only search for it once.
 675  */
 676 static void reset_prepare_engine(struct intel_engine_cs *engine)
 677 {
 678         /*
 679          * During the reset sequence, we must prevent the engine from
 680          * entering RC6. As the context state is undefined until we restart
 681          * the engine, if it does enter RC6 during the reset, the state
 682          * written to the powercontext is undefined and so we may lose
 683          * GPU state upon resume, i.e. fail to restart after a reset.
 684          */
 685         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 686         if (engine->reset.prepare)
 687                 engine->reset.prepare(engine);
 688 }
 689
 690 static void revoke_mmaps(struct intel_gt *gt)
 691 {
 692         int i;
 693
 694         for (i = 0; i < gt->ggtt->num_fences; i++) {
 695                 struct drm_vma_offset_node *node;
 696                 struct i915_vma *vma;
 697                 u64 vma_offset;
 698
 699                 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
 700                 if (!vma)
 701                         continue;
 702
 703                 if (!i915_vma_has_userfault(vma))
 704                         continue;
 705
 706                 GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
 707
 708                 if (!vma->mmo)
 709                         continue;
 710
 711                 node = &vma->mmo->vma_node;
 712                 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
 713
 714                 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
 715                                     drm_vma_node_offset_addr(node) + vma_offset,
 716                                     vma->size,
 717                                     1);
 718         }
 719 }
 720
 721 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
 722 {
 723         struct intel_engine_cs *engine;
 724         intel_engine_mask_t awake = 0;
 725         enum intel_engine_id id;
 726
 727         for_each_engine(engine, gt, id) {
 728                 if (intel_engine_pm_get_if_awake(engine))
 729                         awake |= engine->mask;
 730                 reset_prepare_engine(engine);
 731         }
 732
 733         intel_uc_reset_prepare(&gt->uc);
 734
 735         return awake;
 736 }
 737
 738 static void gt_revoke(struct intel_gt *gt)
 739 {
 740         revoke_mmaps(gt);
 741 }
 742
 743 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 744 {
 745         struct intel_engine_cs *engine;
 746         enum intel_engine_id id;
 747         int err;
 748
 749         /*
 750          * Everything depends on having the GTT running, so we need to start
 751          * there.
 752          */
 753         err = i915_ggtt_enable_hw(gt->i915);
 754         if (err)
 755                 return err;
 756
 757         local_bh_disable();
 758         for_each_engine(engine, gt, id)
 759                 __intel_engine_reset(engine, stalled_mask & engine->mask);
 760         local_bh_enable();
 761
 762         intel_ggtt_restore_fences(gt->ggtt);
 763
 764         return err;
 765 }
 766
 767 static void reset_finish_engine(struct intel_engine_cs *engine)
 768 {
 769         if (engine->reset.finish)
 770                 engine->reset.finish(engine);
 771         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
 772
 773         intel_engine_signal_breadcrumbs(engine);
 774 }
 775
 776 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
 777 {
 778         struct intel_engine_cs *engine;
 779         enum intel_engine_id id;
 780
 781         for_each_engine(engine, gt, id) {
 782                 reset_finish_engine(engine);
 783                 if (awake & engine->mask)
 784                         intel_engine_pm_put(engine);
 785         }
 786 }
 787
 788 static void nop_submit_request(struct i915_request *request)
 789 {
 790         struct intel_engine_cs *engine = request->engine;
 791         unsigned long flags;
 792
 793         RQ_TRACE(request, "-EIO\n");
 794         i915_request_set_error_once(request, -EIO);
 795
 796         spin_lock_irqsave(&engine->active.lock, flags);
 797         __i915_request_submit(request);
 798         i915_request_mark_complete(request);
 799         spin_unlock_irqrestore(&engine->active.lock, flags);
 800
 801         intel_engine_signal_breadcrumbs(engine);
 802 }
 803
 804 static void __intel_gt_set_wedged(struct intel_gt *gt)
 805 {
 806         struct intel_engine_cs *engine;
 807         intel_engine_mask_t awake;
 808         enum intel_engine_id id;
 809
 810         if (test_bit(I915_WEDGED, &gt->reset.flags))
 811                 return;
 812
 813         GT_TRACE(gt, "start\n");
 814
 815         /*
 816          * First, stop submission to hw, but do not yet complete requests by
 817          * rolling the global seqno forward (since this would complete requests
 818          * for which we haven't set the fence error to EIO yet).
 819          */
 820         awake = reset_prepare(gt);
 821
 822         /* Even if the GPU reset fails, it should still stop the engines */
 823         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 824                 __intel_gt_reset(gt, ALL_ENGINES);
 825
 826         for_each_engine(engine, gt, id)
 827                 engine->submit_request = nop_submit_request;
 828
 829         /*
 830          * Make sure no request can slip through without getting completed by
 831          * either this call here to intel_engine_write_global_seqno, or the one
 832          * in nop_submit_request.
 833          */
 834         synchronize_rcu_expedited();
 835         set_bit(I915_WEDGED, &gt->reset.flags);
 836
 837         /* Mark all executing requests as skipped */
 838         local_bh_disable();
 839         for_each_engine(engine, gt, id)
 840                 if (engine->reset.cancel)
 841                         engine->reset.cancel(engine);
 842         local_bh_enable();
 843
 844         reset_finish(gt, awake);
 845
 846         GT_TRACE(gt, "end\n");
 847 }
 848
 849 void intel_gt_set_wedged(struct intel_gt *gt)
 850 {
 851         intel_wakeref_t wakeref;
 852
 853         if (test_bit(I915_WEDGED, &gt->reset.flags))
 854                 return;
 855
 856         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 857         mutex_lock(&gt->reset.mutex);
 858
 859         if (GEM_SHOW_DEBUG()) {
 860                 struct drm_printer p = drm_debug_printer(__func__);
 861                 struct intel_engine_cs *engine;
 862                 enum intel_engine_id id;
 863
 864                 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
 865                 for_each_engine(engine, gt, id) {
 866                         if (intel_engine_is_idle(engine))
 867                                 continue;
 868
 869                         intel_engine_dump(engine, &p, "%s\n", engine->name);
 870                 }
 871         }
 872
 873         __intel_gt_set_wedged(gt);
 874
 875         mutex_unlock(&gt->reset.mutex);
 876         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 877 }
 878
 879 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
 880 {
 881         struct intel_gt_timelines *timelines = &gt->timelines;
 882         struct intel_timeline *tl;
 883         bool ok;
 884
 885         if (!test_bit(I915_WEDGED, &gt->reset.flags))
 886                 return true;
 887
 888         /* Never fully initialised, recovery impossible */
 889         if (intel_gt_has_unrecoverable_error(gt))
 890                 return false;
 891
 892         GT_TRACE(gt, "start\n");
 893
 894         /*
 895          * Before unwedging, make sure that all pending operations
 896          * are flushed and errored out - we may have requests waiting upon
 897          * third party fences. We marked all inflight requests as EIO, and
 898          * every execbuf since returned EIO, for consistency we want all
 899          * the currently pending requests to also be marked as EIO, which
 900          * is done inside our nop_submit_request - and so we must wait.
 901          *
 902          * No more can be submitted until we reset the wedged bit.
 903          */
 904         spin_lock(&timelines->lock);
 905         list_for_each_entry(tl, &timelines->active_list, link) {
 906                 struct dma_fence *fence;
 907
 908                 fence = i915_active_fence_get(&tl->last_request);
 909                 if (!fence)
 910                         continue;
 911
 912                 spin_unlock(&timelines->lock);
 913
 914                 /*
 915                  * All internal dependencies (i915_requests) will have
 916                  * been flushed by the set-wedge, but we may be stuck waiting
 917                  * for external fences. These should all be capped to 10s
 918                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
 919                  * in the worst case.
 920                  */
 921                 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
 922                 dma_fence_put(fence);
 923
 924                 /* Restart iteration after droping lock */
 925                 spin_lock(&timelines->lock);
 926                 tl = list_entry(&timelines->active_list, typeof(*tl), link);
 927         }
 928         spin_unlock(&timelines->lock);
 929
 930         /* We must reset pending GPU events before restoring our submission */
 931         ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
 932         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 933                 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
 934         if (!ok) {
 935                 /*
 936                  * Warn CI about the unrecoverable wedged condition.
 937                  * Time for a reboot.
 938                  */
 939                 add_taint_for_CI(gt->i915, TAINT_WARN);
 940                 return false;
 941         }
 942
 943         /*
 944          * Undo nop_submit_request. We prevent all new i915 requests from
 945          * being queued (by disallowing execbuf whilst wedged) so having
 946          * waited for all active requests above, we know the system is idle
 947          * and do not have to worry about a thread being inside
 948          * engine->submit_request() as we swap over. So unlike installing
 949          * the nop_submit_request on reset, we can do this from normal
 950          * context and do not require stop_machine().
 951          */
 952         intel_engines_reset_default_submission(gt);
 953
 954         GT_TRACE(gt, "end\n");
 955
 956         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
 957         clear_bit(I915_WEDGED, &gt->reset.flags);
 958
 959         return true;
 960 }
 961
 962 bool intel_gt_unset_wedged(struct intel_gt *gt)
 963 {
 964         bool result;
 965
 966         mutex_lock(&gt->reset.mutex);
 967         result = __intel_gt_unset_wedged(gt);
 968         mutex_unlock(&gt->reset.mutex);
 969
 970         return result;
 971 }
 972
 973 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 974 {
 975         int err, i;
 976
 977         gt_revoke(gt);
 978
 979         err = __intel_gt_reset(gt, ALL_ENGINES);
 980         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
 981                 msleep(10 * (i + 1));
 982                 err = __intel_gt_reset(gt, ALL_ENGINES);
 983         }
 984         if (err)
 985                 return err;
 986
 987         return gt_reset(gt, stalled_mask);
 988 }
 989
 990 static int resume(struct intel_gt *gt)
 991 {
 992         struct intel_engine_cs *engine;
 993         enum intel_engine_id id;
 994         int ret;
 995
 996         for_each_engine(engine, gt, id) {
 997                 ret = intel_engine_resume(engine);
 998                 if (ret)
 999                         return ret;
1000         }
1001
1002         return 0;
1003 }
1004
1005 /**
1006  * intel_gt_reset - reset chip after a hang
1007  * @gt: #intel_gt to reset
1008  * @stalled_mask: mask of the stalled engines with the guilty requests
1009  * @reason: user error message for why we are resetting
1010  *
1011  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1012  * on failure.
1013  *
1014  * Procedure is fairly simple:
1015  *   - reset the chip using the reset reg
1016  *   - re-init context state
1017  *   - re-init hardware status page
1018  *   - re-init ring buffer
1019  *   - re-init interrupt state
1020  *   - re-init display
1021  */
1022 void intel_gt_reset(struct intel_gt *gt,
1023                     intel_engine_mask_t stalled_mask,
1024                     const char *reason)
1025 {
1026         intel_engine_mask_t awake;
1027         int ret;
1028
1029         GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1030
1031         might_sleep();
1032         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1033         mutex_lock(&gt->reset.mutex);
1034
1035         /* Clear any previous failed attempts at recovery. Time to try again. */
1036         if (!__intel_gt_unset_wedged(gt))
1037                 goto unlock;
1038
1039         if (reason)
1040                 drm_notice(&gt->i915->drm,
1041                            "Resetting chip for %s\n", reason);
1042         atomic_inc(&gt->i915->gpu_error.reset_count);
1043
1044         awake = reset_prepare(gt);
1045
1046         if (!intel_has_gpu_reset(gt)) {
1047                 if (gt->i915->params.reset)
1048                         drm_err(&gt->i915->drm, "GPU reset not supported\n");
1049                 else
1050                         drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1051                 goto error;
1052         }
1053
1054         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1055                 intel_runtime_pm_disable_interrupts(gt->i915);
1056
1057         if (do_reset(gt, stalled_mask)) {
1058                 drm_err(&gt->i915->drm, "Failed to reset chip\n");
1059                 goto taint;
1060         }
1061
1062         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1063                 intel_runtime_pm_enable_interrupts(gt->i915);
1064
1065         intel_overlay_reset(gt->i915);
1066
1067         /*
1068          * Next we need to restore the context, but we don't use those
1069          * yet either...
1070          *
1071          * Ring buffer needs to be re-initialized in the KMS case, or if X
1072          * was running at the time of the reset (i.e. we weren't VT
1073          * switched away).
1074          */
1075         ret = intel_gt_init_hw(gt);
1076         if (ret) {
1077                 drm_err(&gt->i915->drm,
1078                         "Failed to initialise HW following reset (%d)\n",
1079                         ret);
1080                 goto taint;
1081         }
1082
1083         ret = resume(gt);
1084         if (ret)
1085                 goto taint;
1086
1087 finish:
1088         reset_finish(gt, awake);
1089 unlock:
1090         mutex_unlock(&gt->reset.mutex);
1091         return;
1092
1093 taint:
1094         /*
1095          * History tells us that if we cannot reset the GPU now, we
1096          * never will. This then impacts everything that is run
1097          * subsequently. On failing the reset, we mark the driver
1098          * as wedged, preventing further execution on the GPU.
1099          * We also want to go one step further and add a taint to the
1100          * kernel so that any subsequent faults can be traced back to
1101          * this failure. This is important for CI, where if the
1102          * GPU/driver fails we would like to reboot and restart testing
1103          * rather than continue on into oblivion. For everyone else,
1104          * the system should still plod along, but they have been warned!
1105          */
1106         add_taint_for_CI(gt->i915, TAINT_WARN);
1107 error:
1108         __intel_gt_set_wedged(gt);
1109         goto finish;
1110 }
1111
1112 static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1113 {
1114         return __intel_gt_reset(engine->gt, engine->mask);
1115 }
1116
1117 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1118 {
1119         struct intel_gt *gt = engine->gt;
1120         bool uses_guc = intel_engine_in_guc_submission_mode(engine);
1121         int ret;
1122
1123         ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1124         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1125
1126         if (!intel_engine_pm_get_if_awake(engine))
1127                 return 0;
1128
1129         reset_prepare_engine(engine);
1130
1131         if (msg)
1132                 drm_notice(&engine->i915->drm,
1133                            "Resetting %s for %s\n", engine->name, msg);
1134         atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1135
1136         if (!uses_guc)
1137                 ret = intel_gt_reset_engine(engine);
1138         else
1139                 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1140         if (ret) {
1141                 /* If we fail here, we expect to fallback to a global reset */
1142                 ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret);
1143                 goto out;
1144         }
1145
1146         /*
1147          * The request that caused the hang is stuck on elsp, we know the
1148          * active request and can drop it, adjust head to skip the offending
1149          * request to resume executing remaining requests in the queue.
1150          */
1151         __intel_engine_reset(engine, true);
1152
1153         /*
1154          * The engine and its registers (and workarounds in case of render)
1155          * have been reset to their default values. Follow the init_ring
1156          * process to program RING_MODE, HWSP and re-enable submission.
1157          */
1158         ret = intel_engine_resume(engine);
1159
1160 out:
1161         intel_engine_cancel_stop_cs(engine);
1162         reset_finish_engine(engine);
1163         intel_engine_pm_put_async(engine);
1164         return ret;
1165 }
1166
1167 /**
1168  * intel_engine_reset - reset GPU engine to recover from a hang
1169  * @engine: engine to reset
1170  * @msg: reason for GPU reset; or NULL for no drm_notice()
1171  *
1172  * Reset a specific GPU engine. Useful if a hang is detected.
1173  * Returns zero on successful reset or otherwise an error code.
1174  *
1175  * Procedure is:
1176  *  - identifies the request that caused the hang and it is dropped
1177  *  - reset engine (which will force the engine to idle)
1178  *  - re-init/configure engine
1179  */
1180 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1181 {
1182         int err;
1183
1184         local_bh_disable();
1185         err = __intel_engine_reset_bh(engine, msg);
1186         local_bh_enable();
1187
1188         return err;
1189 }
1190
1191 static void intel_gt_reset_global(struct intel_gt *gt,
1192                                   u32 engine_mask,
1193                                   const char *reason)
1194 {
1195         struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1196         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1197         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1198         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1199         struct intel_wedge_me w;
1200
1201         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1202
1203         GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1204         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1205
1206         /* Use a watchdog to ensure that our reset completes */
1207         intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1208                 intel_display_prepare_reset(gt->i915);
1209
1210                 /* Flush everyone using a resource about to be clobbered */
1211                 synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1212
1213                 intel_gt_reset(gt, engine_mask, reason);
1214
1215                 intel_display_finish_reset(gt->i915);
1216         }
1217
1218         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1219                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1220 }
1221
1222 /**
1223  * intel_gt_handle_error - handle a gpu error
1224  * @gt: the intel_gt
1225  * @engine_mask: mask representing engines that are hung
1226  * @flags: control flags
1227  * @fmt: Error message format string
1228  *
1229  * Do some basic checking of register state at error time and
1230  * dump it to the syslog.  Also call i915_capture_error_state() to make
1231  * sure we get a record and make it available in debugfs.  Fire a uevent
1232  * so userspace knows something bad happened (should trigger collection
1233  * of a ring dump etc.).
1234  */
1235 void intel_gt_handle_error(struct intel_gt *gt,
1236                            intel_engine_mask_t engine_mask,
1237                            unsigned long flags,
1238                            const char *fmt, ...)
1239 {
1240         struct intel_engine_cs *engine;
1241         intel_wakeref_t wakeref;
1242         intel_engine_mask_t tmp;
1243         char error_msg[80];
1244         char *msg = NULL;
1245
1246         if (fmt) {
1247                 va_list args;
1248
1249                 va_start(args, fmt);
1250                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1251                 va_end(args);
1252
1253                 msg = error_msg;
1254         }
1255
1256         /*
1257          * In most cases it's guaranteed that we get here with an RPM
1258          * reference held, for example because there is a pending GPU
1259          * request that won't finish until the reset is done. This
1260          * isn't the case at least when we get here by doing a
1261          * simulated reset via debugfs, so get an RPM reference.
1262          */
1263         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1264
1265         engine_mask &= gt->info.engine_mask;
1266
1267         if (flags & I915_ERROR_CAPTURE) {
1268                 i915_capture_error_state(gt, engine_mask);
1269                 intel_gt_clear_error_registers(gt, engine_mask);
1270         }
1271
1272         /*
1273          * Try engine reset when available. We fall back to full reset if
1274          * single reset fails.
1275          */
1276         if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1277                 local_bh_disable();
1278                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1279                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1280                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1281                                              &gt->reset.flags))
1282                                 continue;
1283
1284                         if (__intel_engine_reset_bh(engine, msg) == 0)
1285                                 engine_mask &= ~engine->mask;
1286
1287                         clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1288                                               &gt->reset.flags);
1289                 }
1290                 local_bh_enable();
1291         }
1292
1293         if (!engine_mask)
1294                 goto out;
1295
1296         /* Full reset needs the mutex, stop any other user trying to do so. */
1297         if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1298                 wait_event(gt->reset.queue,
1299                            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1300                 goto out; /* piggy-back on the other reset */
1301         }
1302
1303         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1304         synchronize_rcu_expedited();
1305
1306         /* Prevent any other reset-engine attempt. */
1307         for_each_engine(engine, gt, tmp) {
1308                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1309                                         &gt->reset.flags))
1310                         wait_on_bit(&gt->reset.flags,
1311                                     I915_RESET_ENGINE + engine->id,
1312                                     TASK_UNINTERRUPTIBLE);
1313         }
1314
1315         intel_gt_reset_global(gt, engine_mask, msg);
1316
1317         for_each_engine(engine, gt, tmp)
1318                 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1319                                  &gt->reset.flags);
1320         clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1321         smp_mb__after_atomic();
1322         wake_up_all(&gt->reset.queue);
1323
1324 out:
1325         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1326 }
1327
1328 int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1329 {
1330         might_lock(&gt->reset.backoff_srcu);
1331         might_sleep();
1332
1333         rcu_read_lock();
1334         while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1335                 rcu_read_unlock();
1336
1337                 if (wait_event_interruptible(gt->reset.queue,
1338                                              !test_bit(I915_RESET_BACKOFF,
1339                                                        &gt->reset.flags)))
1340                         return -EINTR;
1341
1342                 rcu_read_lock();
1343         }
1344         *srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1345         rcu_read_unlock();
1346
1347         return 0;
1348 }
1349
1350 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1351 __releases(&gt->reset.backoff_srcu)
1352 {
1353         srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1354 }
1355
1356 int intel_gt_terminally_wedged(struct intel_gt *gt)
1357 {
1358         might_sleep();
1359
1360         if (!intel_gt_is_wedged(gt))
1361                 return 0;
1362
1363         if (intel_gt_has_unrecoverable_error(gt))
1364                 return -EIO;
1365
1366         /* Reset still in progress? Maybe we will recover? */
1367         if (wait_event_interruptible(gt->reset.queue,
1368                                      !test_bit(I915_RESET_BACKOFF,
1369                                                &gt->reset.flags)))
1370                 return -EINTR;
1371
1372         return intel_gt_is_wedged(gt) ? -EIO : 0;
1373 }
1374
1375 void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1376 {
1377         BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1378                      I915_WEDGED_ON_INIT);
1379         intel_gt_set_wedged(gt);
1380         set_bit(I915_WEDGED_ON_INIT, &gt->reset.flags);
1381
1382         /* Wedged on init is non-recoverable */
1383         add_taint_for_CI(gt->i915, TAINT_WARN);
1384 }
1385
1386 void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1387 {
1388         intel_gt_set_wedged(gt);
1389         set_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
1390         intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1391 }
1392
1393 void intel_gt_init_reset(struct intel_gt *gt)
1394 {
1395         init_waitqueue_head(&gt->reset.queue);
1396         mutex_init(&gt->reset.mutex);
1397         init_srcu_struct(&gt->reset.backoff_srcu);
1398
1399         /*
1400          * While undesirable to wait inside the shrinker, complain anyway.
1401          *
1402          * If we have to wait during shrinking, we guarantee forward progress
1403          * by forcing the reset. Therefore during the reset we must not
1404          * re-enter the shrinker. By declaring that we take the reset mutex
1405          * within the shrinker, we forbid ourselves from performing any
1406          * fs-reclaim or taking related locks during reset.
1407          */
1408         i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex);
1409
1410         /* no GPU until we are ready! */
1411         __set_bit(I915_WEDGED, &gt->reset.flags);
1412 }
1413
1414 void intel_gt_fini_reset(struct intel_gt *gt)
1415 {
1416         cleanup_srcu_struct(&gt->reset.backoff_srcu);
1417 }
1418
1419 static void intel_wedge_me(struct work_struct *work)
1420 {
1421         struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1422
1423         drm_err(&w->gt->i915->drm,
1424                 "%s timed out, cancelling all in-flight rendering.\n",
1425                 w->name);
1426         intel_gt_set_wedged(w->gt);
1427 }
1428
1429 void __intel_init_wedge(struct intel_wedge_me *w,
1430                         struct intel_gt *gt,
1431                         long timeout,
1432                         const char *name)
1433 {
1434         w->gt = gt;
1435         w->name = name;
1436
1437         INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1438         schedule_delayed_work(&w->work, timeout);
1439 }
1440
1441 void __intel_fini_wedge(struct intel_wedge_me *w)
1442 {
1443         cancel_delayed_work_sync(&w->work);
1444         destroy_delayed_work_on_stack(&w->work);
1445         w->gt = NULL;
1446 }
1447
1448 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1449 #include "selftest_reset.c"
1450 #include "selftest_hangcheck.c"
1451 #endif