drivers/gpu/drm/i915/gt/intel_region_lmem.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8 #include "intel_memory_region.h"
   9 #include "intel_region_lmem.h"
  10 #include "intel_region_ttm.h"
  11 #include "gem/i915_gem_lmem.h"
  12 #include "gem/i915_gem_region.h"
  13 #include "gem/i915_gem_ttm.h"
  14 #include "gt/intel_gt.h"
  15 #include "gt/intel_gt_mcr.h"
  16 #include "gt/intel_gt_regs.h"
  17
  18 static void _release_bars(struct pci_dev *pdev)
  19 {
  20         int resno;
  21
  22         for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
  23                 if (pci_resource_len(pdev, resno))
  24                         pci_release_resource(pdev, resno);
  25         }
  26 }
  27
  28 static void
  29 _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
  30 {
  31         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
  32         int bar_size = pci_rebar_bytes_to_size(size);
  33         int ret;
  34
  35         _release_bars(pdev);
  36
  37         ret = pci_resize_resource(pdev, resno, bar_size);
  38         if (ret) {
  39                 drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
  40                          resno, 1 << bar_size, ERR_PTR(ret));
  41                 return;
  42         }
  43
  44         drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
  45 }
  46
  47 #define LMEM_BAR_NUM 2
  48 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
  49 {
  50         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
  51         struct pci_bus *root = pdev->bus;
  52         struct resource *root_res;
  53         resource_size_t rebar_size;
  54         resource_size_t current_size;
  55         u32 pci_cmd;
  56         int i;
  57
  58         current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
  59
  60         if (i915->params.lmem_bar_size) {
  61                 u32 bar_sizes;
  62
  63                 rebar_size = i915->params.lmem_bar_size *
  64                         (resource_size_t)SZ_1M;
  65                 bar_sizes = pci_rebar_get_possible_sizes(pdev,
  66                                                          LMEM_BAR_NUM);
  67
  68                 if (rebar_size == current_size)
  69                         return;
  70
  71                 if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
  72                     rebar_size >= roundup_pow_of_two(lmem_size)) {
  73                         rebar_size = lmem_size;
  74
  75                         drm_info(&i915->drm,
  76                                  "Given bar size is not within supported size, setting it to default: %llu\n",
  77                                  (u64)lmem_size >> 20);
  78                 }
  79         } else {
  80                 rebar_size = current_size;
  81
  82                 if (rebar_size != roundup_pow_of_two(lmem_size))
  83                         rebar_size = lmem_size;
  84                 else
  85                         return;
  86         }
  87
  88         /* Find out if root bus contains 64bit memory addressing */
  89         while (root->parent)
  90                 root = root->parent;
  91
  92         pci_bus_for_each_resource(root, root_res, i) {
  93                 if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
  94                     root_res->start > 0x100000000ull)
  95                         break;
  96         }
  97
  98         /* pci_resize_resource will fail anyways */
  99         if (!root_res) {
 100                 drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
 101                 return;
 102         }
 103
 104         /* First disable PCI memory decoding references */
 105         pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
 106         pci_write_config_dword(pdev, PCI_COMMAND,
 107                                pci_cmd & ~PCI_COMMAND_MEMORY);
 108
 109         _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
 110
 111         pci_assign_unassigned_bus_resources(pdev->bus);
 112         pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
 113 }
 114
 115 static int
 116 region_lmem_release(struct intel_memory_region *mem)
 117 {
 118         int ret;
 119
 120         ret = intel_region_ttm_fini(mem);
 121         io_mapping_fini(&mem->iomap);
 122
 123         return ret;
 124 }
 125
 126 static int
 127 region_lmem_init(struct intel_memory_region *mem)
 128 {
 129         int ret;
 130
 131         if (!io_mapping_init_wc(&mem->iomap,
 132                                 mem->io_start,
 133                                 mem->io_size))
 134                 return -EIO;
 135
 136         ret = intel_region_ttm_init(mem);
 137         if (ret)
 138                 goto out_no_buddy;
 139
 140         return 0;
 141
 142 out_no_buddy:
 143         io_mapping_fini(&mem->iomap);
 144
 145         return ret;
 146 }
 147
 148 static const struct intel_memory_region_ops intel_region_lmem_ops = {
 149         .init = region_lmem_init,
 150         .release = region_lmem_release,
 151         .init_object = __i915_gem_ttm_object_init,
 152 };
 153
 154 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
 155                                      u64 *start, u32 *size)
 156 {
 157         if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
 158                 return false;
 159
 160         *start = 0;
 161         *size = SZ_1M;
 162
 163         drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
 164                 *start, *start + *size);
 165
 166         return true;
 167 }
 168
 169 static int reserve_lowmem_region(struct intel_uncore *uncore,
 170                                  struct intel_memory_region *mem)
 171 {
 172         u64 reserve_start;
 173         u32 reserve_size;
 174         int ret;
 175
 176         if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size))
 177                 return 0;
 178
 179         ret = intel_memory_region_reserve(mem, reserve_start, reserve_size);
 180         if (ret)
 181                 drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n");
 182
 183         return ret;
 184 }
 185
 186 static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 187 {
 188         struct drm_i915_private *i915 = gt->i915;
 189         struct intel_uncore *uncore = gt->uncore;
 190         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 191         struct intel_memory_region *mem;
 192         resource_size_t min_page_size;
 193         resource_size_t io_start;
 194         resource_size_t io_size;
 195         resource_size_t lmem_size;
 196         int err;
 197
 198         if (!IS_DGFX(i915))
 199                 return ERR_PTR(-ENODEV);
 200
 201         if (HAS_FLAT_CCS(i915)) {
 202                 resource_size_t lmem_range;
 203                 u64 tile_stolen, flat_ccs_base;
 204
 205                 lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
 206                 lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
 207                 lmem_size *= SZ_1G;
 208
 209                 flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
 210                 flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
 211
 212                 if (GEM_WARN_ON(lmem_size < flat_ccs_base))
 213                         return ERR_PTR(-EIO);
 214
 215                 tile_stolen = lmem_size - flat_ccs_base;
 216
 217                 /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
 218                 if (tile_stolen == lmem_size)
 219                         drm_err(&i915->drm,
 220                                 "CCS_BASE_ADDR register did not have expected value\n");
 221
 222                 lmem_size -= tile_stolen;
 223         } else {
 224                 /* Stolen starts from GSMBASE without CCS */
 225                 lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
 226         }
 227
 228         i915_resize_lmem_bar(i915, lmem_size);
 229
 230         if (i915->params.lmem_size > 0) {
 231                 lmem_size = min_t(resource_size_t, lmem_size,
 232                                   mul_u32_u32(i915->params.lmem_size, SZ_1M));
 233         }
 234
 235         io_start = pci_resource_start(pdev, 2);
 236         io_size = min(pci_resource_len(pdev, 2), lmem_size);
 237         if (!io_size)
 238                 return ERR_PTR(-EIO);
 239
 240         min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
 241                                                 I915_GTT_PAGE_SIZE_4K;
 242         mem = intel_memory_region_create(i915,
 243                                          0,
 244                                          lmem_size,
 245                                          min_page_size,
 246                                          io_start,
 247                                          io_size,
 248                                          INTEL_MEMORY_LOCAL,
 249                                          0,
 250                                          &intel_region_lmem_ops);
 251         if (IS_ERR(mem))
 252                 return mem;
 253
 254         err = reserve_lowmem_region(uncore, mem);
 255         if (err)
 256                 goto err_region_put;
 257
 258         drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
 259         drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
 260                 &mem->io_start);
 261         drm_info(&i915->drm, "Local memory IO size: %pa\n",
 262                  &mem->io_size);
 263         drm_info(&i915->drm, "Local memory available: %pa\n",
 264                  &lmem_size);
 265
 266         if (io_size < lmem_size)
 267                 drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
 268                          (u64)io_size >> 20);
 269
 270         return mem;
 271
 272 err_region_put:
 273         intel_memory_region_destroy(mem);
 274         return ERR_PTR(err);
 275 }
 276
 277 struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt)
 278 {
 279         return setup_lmem(gt);
 280 }