1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <linux/slab.h>
8 #include "gem/i915_gem_lmem.h"
10 #include "i915_trace.h"
11 #include "intel_gtt.h"
12 #include "gen6_ppgtt.h"
13 #include "gen8_ppgtt.h"
15 struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz)
17 struct i915_page_table *pt;
19 pt = kmalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL);
21 return ERR_PTR(-ENOMEM);
23 pt->base = vm->alloc_pt_dma(vm, sz);
24 if (IS_ERR(pt->base)) {
26 return ERR_PTR(-ENOMEM);
29 pt->is_compact = false;
30 atomic_set(&pt->used, 0);
34 struct i915_page_directory *__alloc_pd(int count)
36 struct i915_page_directory *pd;
38 pd = kzalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
42 pd->entry = kcalloc(count, sizeof(*pd->entry), I915_GFP_ALLOW_FAIL);
43 if (unlikely(!pd->entry)) {
48 spin_lock_init(&pd->lock);
52 struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
54 struct i915_page_directory *pd;
56 pd = __alloc_pd(I915_PDES);
58 return ERR_PTR(-ENOMEM);
60 pd->pt.base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
61 if (IS_ERR(pd->pt.base)) {
64 return ERR_PTR(-ENOMEM);
70 void free_px(struct i915_address_space *vm, struct i915_page_table *pt, int lvl)
72 BUILD_BUG_ON(offsetof(struct i915_page_directory, pt));
75 struct i915_page_directory *pd =
76 container_of(pt, typeof(*pd), pt);
81 i915_gem_object_put(pt->base);
87 write_dma_entry(struct drm_i915_gem_object * const pdma,
88 const unsigned short idx,
89 const u64 encoded_entry)
91 u64 * const vaddr = __px_vaddr(pdma);
93 vaddr[idx] = encoded_entry;
94 drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
98 __set_pd_entry(struct i915_page_directory * const pd,
99 const unsigned short idx,
100 struct i915_page_table * const to,
101 u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
103 /* Each thread pre-pins the pd, and we may have a thread per pde. */
104 GEM_BUG_ON(atomic_read(px_used(pd)) > NALLOC * I915_PDES);
106 atomic_inc(px_used(pd));
108 write_dma_entry(px_base(pd), idx, encode(px_dma(to), I915_CACHE_LLC));
112 clear_pd_entry(struct i915_page_directory * const pd,
113 const unsigned short idx,
114 const struct drm_i915_gem_object * const scratch)
116 GEM_BUG_ON(atomic_read(px_used(pd)) == 0);
118 write_dma_entry(px_base(pd), idx, scratch->encode);
119 pd->entry[idx] = NULL;
120 atomic_dec(px_used(pd));
124 release_pd_entry(struct i915_page_directory * const pd,
125 const unsigned short idx,
126 struct i915_page_table * const pt,
127 const struct drm_i915_gem_object * const scratch)
131 if (atomic_add_unless(&pt->used, -1, 1))
134 spin_lock(&pd->lock);
135 if (atomic_dec_and_test(&pt->used)) {
136 clear_pd_entry(pd, idx, scratch);
139 spin_unlock(&pd->lock);
144 int i915_ppgtt_init_hw(struct intel_gt *gt)
146 struct drm_i915_private *i915 = gt->i915;
148 gtt_write_workarounds(gt);
150 if (GRAPHICS_VER(i915) == 6)
151 gen6_ppgtt_enable(gt);
152 else if (GRAPHICS_VER(i915) == 7)
153 gen7_ppgtt_enable(gt);
158 static struct i915_ppgtt *
159 __ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
161 if (GRAPHICS_VER(gt->i915) < 8)
162 return gen6_ppgtt_create(gt);
164 return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
167 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
168 unsigned long lmem_pt_obj_flags)
170 struct i915_ppgtt *ppgtt;
172 ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
176 trace_i915_ppgtt_create(&ppgtt->vm);
181 void ppgtt_bind_vma(struct i915_address_space *vm,
182 struct i915_vm_pt_stash *stash,
183 struct i915_vma_resource *vma_res,
184 enum i915_cache_level cache_level,
189 if (!vma_res->allocated) {
190 vm->allocate_va_range(vm, stash, vma_res->start,
192 vma_res->allocated = true;
195 /* Applicable to VLV, and gen8+ */
197 if (vma_res->bi.readonly)
198 pte_flags |= PTE_READ_ONLY;
199 if (vma_res->bi.lmem)
202 vm->insert_entries(vm, vma_res, cache_level, pte_flags);
206 void ppgtt_unbind_vma(struct i915_address_space *vm,
207 struct i915_vma_resource *vma_res)
209 if (vma_res->allocated)
210 vm->clear_range(vm, vma_res->start, vma_res->vma_size);
213 static unsigned long pd_count(u64 size, int shift)
215 /* Beware later misalignment */
216 return (size + 2 * (BIT_ULL(shift) - 1)) >> shift;
219 int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
220 struct i915_vm_pt_stash *stash,
226 shift = vm->pd_shift;
230 pt_sz = stash->pt_sz;
232 pt_sz = I915_GTT_PAGE_SIZE_4K;
234 GEM_BUG_ON(!IS_DGFX(vm->i915));
236 GEM_BUG_ON(!is_power_of_2(pt_sz));
238 count = pd_count(size, shift);
240 struct i915_page_table *pt;
242 pt = alloc_pt(vm, pt_sz);
244 i915_vm_free_pt_stash(vm, stash);
248 pt->stash = stash->pt[0];
252 for (n = 1; n < vm->top; n++) {
253 shift += ilog2(I915_PDES); /* Each PD holds 512 entries */
254 count = pd_count(size, shift);
256 struct i915_page_directory *pd;
260 i915_vm_free_pt_stash(vm, stash);
264 pd->pt.stash = stash->pt[1];
265 stash->pt[1] = &pd->pt;
272 int i915_vm_map_pt_stash(struct i915_address_space *vm,
273 struct i915_vm_pt_stash *stash)
275 struct i915_page_table *pt;
278 for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
279 for (pt = stash->pt[n]; pt; pt = pt->stash) {
280 err = map_pt_dma_locked(vm, pt->base);
289 void i915_vm_free_pt_stash(struct i915_address_space *vm,
290 struct i915_vm_pt_stash *stash)
292 struct i915_page_table *pt;
295 for (n = 0; n < ARRAY_SIZE(stash->pt); n++) {
296 while ((pt = stash->pt[n])) {
297 stash->pt[n] = pt->stash;
303 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
304 unsigned long lmem_pt_obj_flags)
306 struct drm_i915_private *i915 = gt->i915;
309 ppgtt->vm.i915 = i915;
310 ppgtt->vm.dma = i915->drm.dev;
311 ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
312 ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
314 dma_resv_init(&ppgtt->vm._resv);
315 i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
317 ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
318 ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;