1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2020 Intel Corporation
5 * Please try to maintain the following order within this file unless it makes
6 * sense to do otherwise. From top to bottom:
8 * 2. #defines, and macros
9 * 3. structure definitions
10 * 4. function prototypes
12 * Within each section, please try to order by generation in ascending order,
13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
16 #ifndef __INTEL_GTT_H__
17 #define __INTEL_GTT_H__
19 #include <linux/io-mapping.h>
20 #include <linux/kref.h>
22 #include <linux/pagevec.h>
23 #include <linux/scatterlist.h>
24 #include <linux/workqueue.h>
26 #include <drm/drm_mm.h>
28 #include "gt/intel_reset.h"
29 #include "i915_selftest.h"
30 #include "i915_vma_resource.h"
31 #include "i915_vma_types.h"
32 #include "i915_params.h"
33 #include "intel_memory_region.h"
35 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
37 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
38 #define DBG(...) trace_printk(__VA_ARGS__)
43 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
56 #define I915_FENCE_REG_NONE -1
57 #define I915_MAX_NUM_FENCES 32
58 /* 32 fences + sign bit for FENCE_REG_NONE */
59 #define I915_MAX_NUM_FENCE_BITS 6
61 typedef u32 gen6_pte_t;
62 typedef u64 gen8_pte_t;
64 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
66 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
67 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
69 #define I915_PDE_MASK (I915_PDES - 1)
71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
75 #define GEN6_PTE_CACHE_LLC (2 << 1)
76 #define GEN6_PTE_UNCACHED (1 << 1)
77 #define GEN6_PTE_VALID REG_BIT(0)
79 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
80 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
81 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
82 #define GEN6_PDE_SHIFT 22
83 #define GEN6_PDE_VALID REG_BIT(0)
84 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
86 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
89 #define BYT_PTE_WRITEABLE REG_BIT(1)
91 #define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
92 #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
93 #define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)
94 #define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)
95 #define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)
97 #define GEN12_GGTT_PTE_LM BIT_ULL(1)
98 #define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
99 #define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
100 #define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12)
101 #define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52)
103 #define GEN12_PDE_64K BIT(6)
104 #define GEN12_PTE_PS64 BIT(8)
107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
108 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
110 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
111 (((bits) & 0x8) << (11 - 3)))
112 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
113 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
114 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
115 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
116 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
117 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
118 #define HSW_PTE_UNCACHED (0)
119 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
120 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
123 * GEN8 32b style address is defined as a 3 level page table:
124 * 31:30 | 29:21 | 20:12 | 11:0
125 * PDPE | PDE | PTE | offset
126 * The difference as compared to normal x86 3 level page table is the PDPEs are
127 * programmed via register.
129 * GEN8 48b style address is defined as a 4 level page table:
130 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
131 * PML4E | PDPE | PDE | PTE | offset
133 #define GEN8_3LVL_PDPES 4
135 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
136 #define PPAT_CACHED_PDE 0 /* WB LLC */
137 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
138 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
140 #define CHV_PPAT_SNOOP REG_BIT(6)
141 #define GEN8_PPAT_AGE(x) ((x)<<4)
142 #define GEN8_PPAT_LLCeLLC (3<<2)
143 #define GEN8_PPAT_LLCELLC (2<<2)
144 #define GEN8_PPAT_LLC (1<<2)
145 #define GEN8_PPAT_WB (3<<0)
146 #define GEN8_PPAT_WT (2<<0)
147 #define GEN8_PPAT_WC (1<<0)
148 #define GEN8_PPAT_UC (0<<0)
149 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
150 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
152 #define GEN8_PAGE_PRESENT BIT_ULL(0)
153 #define GEN8_PAGE_RW BIT_ULL(1)
155 #define GEN8_PDE_IPS_64K BIT(11)
156 #define GEN8_PDE_PS_2M BIT(7)
158 #define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
159 #define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
160 #define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
161 #define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
162 #define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
163 #define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
164 #define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
166 enum i915_cache_level;
168 struct drm_i915_gem_object;
169 struct i915_fence_reg;
173 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
174 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
176 struct i915_page_table {
177 struct drm_i915_gem_object *base;
180 struct i915_page_table *stash;
185 struct i915_page_directory {
186 struct i915_page_table pt;
191 #define __px_choose_expr(x, type, expr, other) \
192 __builtin_choose_expr( \
193 __builtin_types_compatible_p(typeof(x), type) || \
194 __builtin_types_compatible_p(typeof(x), const type), \
195 ({ type __x = (type)(x); expr; }), \
198 #define px_base(px) \
199 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \
200 __px_choose_expr(px, struct i915_page_table *, __x->base, \
201 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \
204 struct page *__px_page(struct drm_i915_gem_object *p);
205 dma_addr_t __px_dma(struct drm_i915_gem_object *p);
206 #define px_dma(px) (__px_dma(px_base(px)))
208 void *__px_vaddr(struct drm_i915_gem_object *p);
209 #define px_vaddr(px) (__px_vaddr(px_base(px)))
212 __px_choose_expr(px, struct i915_page_table *, __x, \
213 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
215 #define px_used(px) (&px_pt(px)->used)
217 struct i915_vm_pt_stash {
218 /* preallocated chains of page tables/directories */
219 struct i915_page_table *pt[2];
221 * Optionally override the alignment/size of the physical page that
222 * contains each PT. If not set defaults back to the usual
223 * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging
224 * structures. MUST be a power-of-two. ONLY applicable on discrete
230 struct i915_vma_ops {
231 /* Map an object into an address space with the given cache flags. */
232 void (*bind_vma)(struct i915_address_space *vm,
233 struct i915_vm_pt_stash *stash,
234 struct i915_vma_resource *vma_res,
235 enum i915_cache_level cache_level,
238 * Unmap an object from an address space. This usually consists of
239 * setting the valid PTE entries to a reserved scratch page.
241 void (*unbind_vma)(struct i915_address_space *vm,
242 struct i915_vma_resource *vma_res);
246 struct i915_address_space {
248 struct work_struct release_work;
252 struct drm_i915_private *i915;
254 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
255 u64 reserved; /* size addr space reserved */
256 u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1];
258 unsigned int bind_async_flags;
260 struct mutex mutex; /* protects vma and our lists */
262 struct kref resv_ref; /* kref to keep the reservation lock alive. */
263 struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */
264 #define VM_CLASS_GGTT 0
265 #define VM_CLASS_PPGTT 1
266 #define VM_CLASS_DPT 2
268 struct drm_i915_gem_object *scratch[4];
270 * List of vma currently bound.
272 struct list_head bound_list;
275 * List of vmas not yet bound or evicted.
277 struct list_head unbound_list;
282 /* Display page table */
285 /* Some systems support read-only mappings for GGTT and/or PPGTT */
286 bool has_read_only:1;
288 /* Skip pte rewrite on unbind for suspend. Protected by @mutex */
289 bool skip_pte_rewrite:1;
295 /* Flags used when creating page-table objects for this vm */
296 unsigned long lmem_pt_obj_flags;
298 /* Interval tree for pending unbind vma resources */
299 struct rb_root_cached pending_unbind;
301 struct drm_i915_gem_object *
302 (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
303 struct drm_i915_gem_object *
304 (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
306 u64 (*pte_encode)(dma_addr_t addr,
307 enum i915_cache_level level,
308 u32 flags); /* Create a valid PTE */
309 #define PTE_READ_ONLY BIT(0)
310 #define PTE_LM BIT(1)
312 void (*allocate_va_range)(struct i915_address_space *vm,
313 struct i915_vm_pt_stash *stash,
314 u64 start, u64 length);
315 void (*clear_range)(struct i915_address_space *vm,
316 u64 start, u64 length);
317 void (*scratch_range)(struct i915_address_space *vm,
318 u64 start, u64 length);
319 void (*insert_page)(struct i915_address_space *vm,
322 enum i915_cache_level cache_level,
324 void (*insert_entries)(struct i915_address_space *vm,
325 struct i915_vma_resource *vma_res,
326 enum i915_cache_level cache_level,
328 void (*raw_insert_page)(struct i915_address_space *vm,
331 enum i915_cache_level cache_level,
333 void (*raw_insert_entries)(struct i915_address_space *vm,
334 struct i915_vma_resource *vma_res,
335 enum i915_cache_level cache_level,
337 void (*cleanup)(struct i915_address_space *vm);
339 void (*foreach)(struct i915_address_space *vm,
340 u64 start, u64 length,
341 void (*fn)(struct i915_address_space *vm,
342 struct i915_page_table *pt,
346 struct i915_vma_ops vma_ops;
348 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
349 I915_SELFTEST_DECLARE(bool scrub_64K);
353 * The Graphics Translation Table is the way in which GEN hardware translates a
354 * Graphics Virtual Address into a Physical Address. In addition to the normal
355 * collateral associated with any va->pa translations GEN hardware also has a
356 * portion of the GTT which can be mapped by the CPU and remain both coherent
357 * and correct (in cases like swizzling). That region is referred to as GMADR in
361 struct i915_address_space vm;
363 struct io_mapping iomap; /* Mapping to our CPU mappable region */
364 struct resource gmadr; /* GMADR resource */
365 resource_size_t mappable_end; /* End offset that we can CPU map */
367 /** "Graphics Stolen Memory" holds the global PTEs */
369 void (*invalidate)(struct i915_ggtt *ggtt);
371 /** PPGTT used for aliasing the PPGTT with the GTT */
372 struct i915_ppgtt *alias;
378 /** Bit 6 swizzling required for X tiling */
380 /** Bit 6 swizzling required for Y tiling */
385 unsigned int num_fences;
386 struct i915_fence_reg *fence_regs;
387 struct list_head fence_list;
390 * List of all objects in gtt_space, currently mmaped by userspace.
391 * All objects within this list must also be on bound_list.
393 struct list_head userfault_list;
395 struct mutex error_mutex;
396 struct drm_mm_node error_capture;
397 struct drm_mm_node uc_fw;
399 /** List of GTs mapping this GGTT */
400 struct list_head gt_list;
404 struct i915_address_space vm;
406 struct i915_page_directory *pd;
409 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
410 #define i915_is_dpt(vm) ((vm)->is_dpt)
411 #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm))
413 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915);
416 i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
419 i915_vm_is_4lvl(const struct i915_address_space *vm)
421 return (vm->total - 1) >> 32;
425 i915_vm_has_scratch_64K(struct i915_address_space *vm)
427 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
430 static inline u64 i915_vm_min_alignment(struct i915_address_space *vm,
431 enum intel_memory_type type)
433 /* avoid INTEL_MEMORY_MOCK overflow */
434 if ((int)type >= ARRAY_SIZE(vm->min_alignment))
435 type = INTEL_MEMORY_SYSTEM;
437 return vm->min_alignment[type];
440 static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm,
441 struct drm_i915_gem_object *obj)
443 struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
444 enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM;
446 return i915_vm_min_alignment(vm, type);
450 i915_vm_has_cache_coloring(struct i915_address_space *vm)
452 return i915_is_ggtt(vm) && vm->mm.color_adjust;
455 static inline struct i915_ggtt *
456 i915_vm_to_ggtt(struct i915_address_space *vm)
458 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
459 GEM_BUG_ON(!i915_is_ggtt(vm));
460 return container_of(vm, struct i915_ggtt, vm);
463 static inline struct i915_ppgtt *
464 i915_vm_to_ppgtt(struct i915_address_space *vm)
466 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
467 GEM_BUG_ON(i915_is_ggtt_or_dpt(vm));
468 return container_of(vm, struct i915_ppgtt, vm);
471 static inline struct i915_address_space *
472 i915_vm_get(struct i915_address_space *vm)
478 static inline struct i915_address_space *
479 i915_vm_tryget(struct i915_address_space *vm)
481 return kref_get_unless_zero(&vm->ref) ? vm : NULL;
484 static inline void assert_vm_alive(struct i915_address_space *vm)
486 GEM_BUG_ON(!kref_read(&vm->ref));
490 * i915_vm_resv_get - Obtain a reference on the vm's reservation lock
491 * @vm: The vm whose reservation lock we want to share.
493 * Return: A pointer to the vm's reservation lock.
495 static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm)
497 kref_get(&vm->resv_ref);
501 void i915_vm_release(struct kref *kref);
503 void i915_vm_resv_release(struct kref *kref);
505 static inline void i915_vm_put(struct i915_address_space *vm)
507 kref_put(&vm->ref, i915_vm_release);
511 * i915_vm_resv_put - Release a reference on the vm's reservation lock
512 * @vm: The vm whose reservation lock reference we want to release
514 static inline void i915_vm_resv_put(struct i915_address_space *vm)
516 kref_put(&vm->resv_ref, i915_vm_resv_release);
519 void i915_address_space_init(struct i915_address_space *vm, int subclass);
520 void i915_address_space_fini(struct i915_address_space *vm);
522 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
524 const u32 mask = NUM_PTE(pde_shift) - 1;
526 return (address >> PAGE_SHIFT) & mask;
530 * Helper to counts the number of PTEs within the given length. This count
531 * does not cross a page table boundary, so the max value would be
532 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
534 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
536 const u64 mask = ~((1ULL << pde_shift) - 1);
539 GEM_BUG_ON(length == 0);
540 GEM_BUG_ON(offset_in_page(addr | length));
544 if ((addr & mask) != (end & mask))
545 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
547 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
550 static inline u32 i915_pde_index(u64 addr, u32 shift)
552 return (addr >> shift) & I915_PDE_MASK;
555 static inline struct i915_page_table *
556 i915_pt_entry(const struct i915_page_directory * const pd,
557 const unsigned short n)
562 static inline struct i915_page_directory *
563 i915_pd_entry(const struct i915_page_directory * const pdp,
564 const unsigned short n)
566 return pdp->entry[n];
569 static inline dma_addr_t
570 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
572 struct i915_page_table *pt = ppgtt->pd->entry[n];
574 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
577 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
578 unsigned long lmem_pt_obj_flags);
579 void intel_ggtt_bind_vma(struct i915_address_space *vm,
580 struct i915_vm_pt_stash *stash,
581 struct i915_vma_resource *vma_res,
582 enum i915_cache_level cache_level,
584 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
585 struct i915_vma_resource *vma_res);
587 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
588 int i915_ggtt_init_hw(struct drm_i915_private *i915);
589 int i915_ggtt_enable_hw(struct drm_i915_private *i915);
590 int i915_init_ggtt(struct drm_i915_private *i915);
591 void i915_ggtt_driver_release(struct drm_i915_private *i915);
592 void i915_ggtt_driver_late_release(struct drm_i915_private *i915);
593 struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915);
595 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
597 return ggtt->mappable_end > 0;
600 int i915_ppgtt_init_hw(struct intel_gt *gt);
602 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
603 unsigned long lmem_pt_obj_flags);
605 void i915_ggtt_suspend_vm(struct i915_address_space *vm);
606 bool i915_ggtt_resume_vm(struct i915_address_space *vm);
607 void i915_ggtt_suspend(struct i915_ggtt *gtt);
608 void i915_ggtt_resume(struct i915_ggtt *ggtt);
611 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
613 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
614 #define fill32_px(px, v) do { \
615 u64 v__ = lower_32_bits(v); \
616 fill_px((px), v__ << 32 | v__); \
619 int setup_scratch_page(struct i915_address_space *vm);
620 void free_scratch(struct i915_address_space *vm);
622 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
623 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
624 struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz);
625 struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
626 struct i915_page_directory *__alloc_pd(int npde);
628 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
629 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
631 void free_px(struct i915_address_space *vm,
632 struct i915_page_table *pt, int lvl);
633 #define free_pt(vm, px) free_px(vm, px, 0)
634 #define free_pd(vm, px) free_px(vm, px_pt(px), 1)
637 __set_pd_entry(struct i915_page_directory * const pd,
638 const unsigned short idx,
639 struct i915_page_table *pt,
640 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
642 #define set_pd_entry(pd, idx, to) \
643 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode)
646 clear_pd_entry(struct i915_page_directory * const pd,
647 const unsigned short idx,
648 const struct drm_i915_gem_object * const scratch);
651 release_pd_entry(struct i915_page_directory * const pd,
652 const unsigned short idx,
653 struct i915_page_table * const pt,
654 const struct drm_i915_gem_object * const scratch);
655 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
657 void ppgtt_bind_vma(struct i915_address_space *vm,
658 struct i915_vm_pt_stash *stash,
659 struct i915_vma_resource *vma_res,
660 enum i915_cache_level cache_level,
662 void ppgtt_unbind_vma(struct i915_address_space *vm,
663 struct i915_vma_resource *vma_res);
665 void gtt_write_workarounds(struct intel_gt *gt);
667 void setup_private_pat(struct intel_gt *gt);
669 int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
670 struct i915_vm_pt_stash *stash,
672 int i915_vm_map_pt_stash(struct i915_address_space *vm,
673 struct i915_vm_pt_stash *stash);
674 void i915_vm_free_pt_stash(struct i915_address_space *vm,
675 struct i915_vm_pt_stash *stash);
678 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size);
681 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size);
683 static inline struct sgt_dma {
684 struct scatterlist *sg;
686 } sgt_dma(struct i915_vma_resource *vma_res) {
687 struct scatterlist *sg = vma_res->bi.pages->sgl;
688 dma_addr_t addr = sg_dma_address(sg);
690 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };