drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "debugfs_gt.h"
   7
   8 #include "gem/i915_gem_lmem.h"
   9 #include "i915_drv.h"
  10 #include "intel_context.h"
  11 #include "intel_gt.h"
  12 #include "intel_gt_buffer_pool.h"
  13 #include "intel_gt_clock_utils.h"
  14 #include "intel_gt_pm.h"
  15 #include "intel_gt_requests.h"
  16 #include "intel_migrate.h"
  17 #include "intel_mocs.h"
  18 #include "intel_rc6.h"
  19 #include "intel_renderstate.h"
  20 #include "intel_rps.h"
  21 #include "intel_uncore.h"
  22 #include "intel_pm.h"
  23 #include "shmem_utils.h"
  24
  25 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  26 {
  27         gt->i915 = i915;
  28         gt->uncore = &i915->uncore;
  29
  30         spin_lock_init(&gt->irq_lock);
  31
  32         INIT_LIST_HEAD(&gt->closed_vma);
  33         spin_lock_init(&gt->closed_lock);
  34
  35         init_llist_head(&gt->watchdog.list);
  36         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  37
  38         intel_gt_init_buffer_pool(gt);
  39         intel_gt_init_reset(gt);
  40         intel_gt_init_requests(gt);
  41         intel_gt_init_timelines(gt);
  42         intel_gt_pm_init_early(gt);
  43
  44         intel_uc_init_early(&gt->uc);
  45         intel_rps_init_early(&gt->rps);
  46 }
  47
  48 int intel_gt_probe_lmem(struct intel_gt *gt)
  49 {
  50         struct drm_i915_private *i915 = gt->i915;
  51         struct intel_memory_region *mem;
  52         int id;
  53         int err;
  54
  55         mem = intel_gt_setup_lmem(gt);
  56         if (mem == ERR_PTR(-ENODEV))
  57                 mem = intel_gt_setup_fake_lmem(gt);
  58         if (IS_ERR(mem)) {
  59                 err = PTR_ERR(mem);
  60                 if (err == -ENODEV)
  61                         return 0;
  62
  63                 drm_err(&i915->drm,
  64                         "Failed to setup region(%d) type=%d\n",
  65                         err, INTEL_MEMORY_LOCAL);
  66                 return err;
  67         }
  68
  69         id = INTEL_REGION_LMEM;
  70
  71         mem->id = id;
  72
  73         intel_memory_region_set_name(mem, "local%u", mem->instance);
  74
  75         GEM_BUG_ON(!HAS_REGION(i915, id));
  76         GEM_BUG_ON(i915->mm.regions[id]);
  77         i915->mm.regions[id] = mem;
  78
  79         return 0;
  80 }
  81
  82 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  83 {
  84         gt->ggtt = ggtt;
  85 }
  86
  87 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
  88         { 0x00B100, 0x00B3FF },
  89         {},
  90 };
  91
  92 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
  93         { 0x004000, 0x004AFF },
  94         { 0x00C800, 0x00CFFF },
  95         { 0x00DD00, 0x00DDFF },
  96         { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
  97         {},
  98 };
  99
 100 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
 101         { 0x00B000, 0x00B0FF },
 102         { 0x00D800, 0x00D8FF },
 103         {},
 104 };
 105
 106 static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 107         { 0x00B000, 0x00B0FF },
 108         { 0x00D880, 0x00D8FF },
 109         {},
 110 };
 111
 112 static u16 slicemask(struct intel_gt *gt, int count)
 113 {
 114         u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
 115
 116         return intel_slicemask_from_dssmask(dss_mask, count);
 117 }
 118
 119 int intel_gt_init_mmio(struct intel_gt *gt)
 120 {
 121         struct drm_i915_private *i915 = gt->i915;
 122
 123         intel_gt_init_clock_frequency(gt);
 124
 125         intel_uc_init_mmio(&gt->uc);
 126         intel_sseu_info_init(gt);
 127
 128         /*
 129          * An mslice is unavailable only if both the meml3 for the slice is
 130          * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 131          */
 132         if (HAS_MSLICES(i915))
 133                 gt->info.mslice_mask =
 134                         slicemask(gt, GEN_DSS_PER_MSLICE) |
 135                         (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 136                          GEN12_MEML3_EN_MASK);
 137
 138         if (IS_DG2(i915)) {
 139                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 140                 gt->steering_table[LNCF] = dg2_lncf_steering_table;
 141         } else if (IS_XEHPSDV(i915)) {
 142                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 143                 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
 144         } else if (GRAPHICS_VER(i915) >= 11 &&
 145                    GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
 146                 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
 147                 gt->info.l3bank_mask =
 148                         ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 149                         GEN10_L3BANK_MASK;
 150         } else if (HAS_MSLICES(i915)) {
 151                 MISSING_CASE(INTEL_INFO(i915)->platform);
 152         }
 153
 154         return intel_engines_init_mmio(gt);
 155 }
 156
 157 static void init_unused_ring(struct intel_gt *gt, u32 base)
 158 {
 159         struct intel_uncore *uncore = gt->uncore;
 160
 161         intel_uncore_write(uncore, RING_CTL(base), 0);
 162         intel_uncore_write(uncore, RING_HEAD(base), 0);
 163         intel_uncore_write(uncore, RING_TAIL(base), 0);
 164         intel_uncore_write(uncore, RING_START(base), 0);
 165 }
 166
 167 static void init_unused_rings(struct intel_gt *gt)
 168 {
 169         struct drm_i915_private *i915 = gt->i915;
 170
 171         if (IS_I830(i915)) {
 172                 init_unused_ring(gt, PRB1_BASE);
 173                 init_unused_ring(gt, SRB0_BASE);
 174                 init_unused_ring(gt, SRB1_BASE);
 175                 init_unused_ring(gt, SRB2_BASE);
 176                 init_unused_ring(gt, SRB3_BASE);
 177         } else if (GRAPHICS_VER(i915) == 2) {
 178                 init_unused_ring(gt, SRB0_BASE);
 179                 init_unused_ring(gt, SRB1_BASE);
 180         } else if (GRAPHICS_VER(i915) == 3) {
 181                 init_unused_ring(gt, PRB1_BASE);
 182                 init_unused_ring(gt, PRB2_BASE);
 183         }
 184 }
 185
 186 int intel_gt_init_hw(struct intel_gt *gt)
 187 {
 188         struct drm_i915_private *i915 = gt->i915;
 189         struct intel_uncore *uncore = gt->uncore;
 190         int ret;
 191
 192         gt->last_init_time = ktime_get();
 193
 194         /* Double layer security blanket, see i915_gem_init() */
 195         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 196
 197         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 198                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 199
 200         if (IS_HASWELL(i915))
 201                 intel_uncore_write(uncore,
 202                                    MI_PREDICATE_RESULT_2,
 203                                    IS_HSW_GT3(i915) ?
 204                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 205
 206         /* Apply the GT workarounds... */
 207         intel_gt_apply_workarounds(gt);
 208         /* ...and determine whether they are sticking. */
 209         intel_gt_verify_workarounds(gt, "init");
 210
 211         intel_gt_init_swizzling(gt);
 212
 213         /*
 214          * At least 830 can leave some of the unused rings
 215          * "active" (ie. head != tail) after resume which
 216          * will prevent c3 entry. Makes sure all unused rings
 217          * are totally idle.
 218          */
 219         init_unused_rings(gt);
 220
 221         ret = i915_ppgtt_init_hw(gt);
 222         if (ret) {
 223                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 224                 goto out;
 225         }
 226
 227         /* We can't enable contexts until all firmware is loaded */
 228         ret = intel_uc_init_hw(&gt->uc);
 229         if (ret) {
 230                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 231                 goto out;
 232         }
 233
 234         intel_mocs_init(gt);
 235
 236 out:
 237         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 238         return ret;
 239 }
 240
 241 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 242 {
 243         intel_uncore_rmw(uncore, reg, 0, set);
 244 }
 245
 246 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 247 {
 248         intel_uncore_rmw(uncore, reg, clr, 0);
 249 }
 250
 251 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 252 {
 253         intel_uncore_rmw(uncore, reg, 0, 0);
 254 }
 255
 256 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 257 {
 258         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 259         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 260 }
 261
 262 void
 263 intel_gt_clear_error_registers(struct intel_gt *gt,
 264                                intel_engine_mask_t engine_mask)
 265 {
 266         struct drm_i915_private *i915 = gt->i915;
 267         struct intel_uncore *uncore = gt->uncore;
 268         u32 eir;
 269
 270         if (GRAPHICS_VER(i915) != 2)
 271                 clear_register(uncore, PGTBL_ER);
 272
 273         if (GRAPHICS_VER(i915) < 4)
 274                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 275         else
 276                 clear_register(uncore, IPEIR_I965);
 277
 278         clear_register(uncore, EIR);
 279         eir = intel_uncore_read(uncore, EIR);
 280         if (eir) {
 281                 /*
 282                  * some errors might have become stuck,
 283                  * mask them.
 284                  */
 285                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 286                 rmw_set(uncore, EMR, eir);
 287                 intel_uncore_write(uncore, GEN2_IIR,
 288                                    I915_MASTER_ERROR_INTERRUPT);
 289         }
 290
 291         if (GRAPHICS_VER(i915) >= 12) {
 292                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 293                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 294         } else if (GRAPHICS_VER(i915) >= 8) {
 295                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 296                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 297         } else if (GRAPHICS_VER(i915) >= 6) {
 298                 struct intel_engine_cs *engine;
 299                 enum intel_engine_id id;
 300
 301                 for_each_engine_masked(engine, gt, engine_mask, id)
 302                         gen6_clear_engine_error_register(engine);
 303         }
 304 }
 305
 306 static void gen6_check_faults(struct intel_gt *gt)
 307 {
 308         struct intel_engine_cs *engine;
 309         enum intel_engine_id id;
 310         u32 fault;
 311
 312         for_each_engine(engine, gt, id) {
 313                 fault = GEN6_RING_FAULT_REG_READ(engine);
 314                 if (fault & RING_FAULT_VALID) {
 315                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 316                                 "\tAddr: 0x%08lx\n"
 317                                 "\tAddress space: %s\n"
 318                                 "\tSource ID: %d\n"
 319                                 "\tType: %d\n",
 320                                 fault & PAGE_MASK,
 321                                 fault & RING_FAULT_GTTSEL_MASK ?
 322                                 "GGTT" : "PPGTT",
 323                                 RING_FAULT_SRCID(fault),
 324                                 RING_FAULT_FAULT_TYPE(fault));
 325                 }
 326         }
 327 }
 328
 329 static void gen8_check_faults(struct intel_gt *gt)
 330 {
 331         struct intel_uncore *uncore = gt->uncore;
 332         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 333         u32 fault;
 334
 335         if (GRAPHICS_VER(gt->i915) >= 12) {
 336                 fault_reg = GEN12_RING_FAULT_REG;
 337                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 338                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 339         } else {
 340                 fault_reg = GEN8_RING_FAULT_REG;
 341                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 342                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 343         }
 344
 345         fault = intel_uncore_read(uncore, fault_reg);
 346         if (fault & RING_FAULT_VALID) {
 347                 u32 fault_data0, fault_data1;
 348                 u64 fault_addr;
 349
 350                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 351                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 352
 353                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 354                              ((u64)fault_data0 << 12);
 355
 356                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 357                         "\tAddr: 0x%08x_%08x\n"
 358                         "\tAddress space: %s\n"
 359                         "\tEngine ID: %d\n"
 360                         "\tSource ID: %d\n"
 361                         "\tType: %d\n",
 362                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 363                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 364                         GEN8_RING_FAULT_ENGINE_ID(fault),
 365                         RING_FAULT_SRCID(fault),
 366                         RING_FAULT_FAULT_TYPE(fault));
 367         }
 368 }
 369
 370 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 371 {
 372         struct drm_i915_private *i915 = gt->i915;
 373
 374         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 375         if (GRAPHICS_VER(i915) >= 8)
 376                 gen8_check_faults(gt);
 377         else if (GRAPHICS_VER(i915) >= 6)
 378                 gen6_check_faults(gt);
 379         else
 380                 return;
 381
 382         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 383 }
 384
 385 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 386 {
 387         struct intel_uncore *uncore = gt->uncore;
 388         intel_wakeref_t wakeref;
 389
 390         /*
 391          * No actual flushing is required for the GTT write domain for reads
 392          * from the GTT domain. Writes to it "immediately" go to main memory
 393          * as far as we know, so there's no chipset flush. It also doesn't
 394          * land in the GPU render cache.
 395          *
 396          * However, we do have to enforce the order so that all writes through
 397          * the GTT land before any writes to the device, such as updates to
 398          * the GATT itself.
 399          *
 400          * We also have to wait a bit for the writes to land from the GTT.
 401          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 402          * timing. This issue has only been observed when switching quickly
 403          * between GTT writes and CPU reads from inside the kernel on recent hw,
 404          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 405          * system agents we cannot reproduce this behaviour, until Cannonlake
 406          * that was!).
 407          */
 408
 409         wmb();
 410
 411         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 412                 return;
 413
 414         intel_gt_chipset_flush(gt);
 415
 416         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 417                 unsigned long flags;
 418
 419                 spin_lock_irqsave(&uncore->lock, flags);
 420                 intel_uncore_posting_read_fw(uncore,
 421                                              RING_HEAD(RENDER_RING_BASE));
 422                 spin_unlock_irqrestore(&uncore->lock, flags);
 423         }
 424 }
 425
 426 void intel_gt_chipset_flush(struct intel_gt *gt)
 427 {
 428         wmb();
 429         if (GRAPHICS_VER(gt->i915) < 6)
 430                 intel_gtt_chipset_flush();
 431 }
 432
 433 void intel_gt_driver_register(struct intel_gt *gt)
 434 {
 435         intel_rps_driver_register(&gt->rps);
 436
 437         debugfs_gt_register(gt);
 438 }
 439
 440 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 441 {
 442         struct drm_i915_private *i915 = gt->i915;
 443         struct drm_i915_gem_object *obj;
 444         struct i915_vma *vma;
 445         int ret;
 446
 447         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 448         if (IS_ERR(obj))
 449                 obj = i915_gem_object_create_stolen(i915, size);
 450         if (IS_ERR(obj))
 451                 obj = i915_gem_object_create_internal(i915, size);
 452         if (IS_ERR(obj)) {
 453                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 454                 return PTR_ERR(obj);
 455         }
 456
 457         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 458         if (IS_ERR(vma)) {
 459                 ret = PTR_ERR(vma);
 460                 goto err_unref;
 461         }
 462
 463         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 464         if (ret)
 465                 goto err_unref;
 466
 467         gt->scratch = i915_vma_make_unshrinkable(vma);
 468
 469         return 0;
 470
 471 err_unref:
 472         i915_gem_object_put(obj);
 473         return ret;
 474 }
 475
 476 static void intel_gt_fini_scratch(struct intel_gt *gt)
 477 {
 478         i915_vma_unpin_and_release(&gt->scratch, 0);
 479 }
 480
 481 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 482 {
 483         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 484                 return &i915_ppgtt_create(gt)->vm;
 485         else
 486                 return i915_vm_get(&gt->ggtt->vm);
 487 }
 488
 489 static int __engines_record_defaults(struct intel_gt *gt)
 490 {
 491         struct i915_request *requests[I915_NUM_ENGINES] = {};
 492         struct intel_engine_cs *engine;
 493         enum intel_engine_id id;
 494         int err = 0;
 495
 496         /*
 497          * As we reset the gpu during very early sanitisation, the current
 498          * register state on the GPU should reflect its defaults values.
 499          * We load a context onto the hw (with restore-inhibit), then switch
 500          * over to a second context to save that default register state. We
 501          * can then prime every new context with that state so they all start
 502          * from the same default HW values.
 503          */
 504
 505         for_each_engine(engine, gt, id) {
 506                 struct intel_renderstate so;
 507                 struct intel_context *ce;
 508                 struct i915_request *rq;
 509
 510                 /* We must be able to switch to something! */
 511                 GEM_BUG_ON(!engine->kernel_context);
 512
 513                 ce = intel_context_create(engine);
 514                 if (IS_ERR(ce)) {
 515                         err = PTR_ERR(ce);
 516                         goto out;
 517                 }
 518
 519                 err = intel_renderstate_init(&so, ce);
 520                 if (err)
 521                         goto err;
 522
 523                 rq = i915_request_create(ce);
 524                 if (IS_ERR(rq)) {
 525                         err = PTR_ERR(rq);
 526                         goto err_fini;
 527                 }
 528
 529                 err = intel_engine_emit_ctx_wa(rq);
 530                 if (err)
 531                         goto err_rq;
 532
 533                 err = intel_renderstate_emit(&so, rq);
 534                 if (err)
 535                         goto err_rq;
 536
 537 err_rq:
 538                 requests[id] = i915_request_get(rq);
 539                 i915_request_add(rq);
 540 err_fini:
 541                 intel_renderstate_fini(&so, ce);
 542 err:
 543                 if (err) {
 544                         intel_context_put(ce);
 545                         goto out;
 546                 }
 547         }
 548
 549         /* Flush the default context image to memory, and enable powersaving. */
 550         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 551                 err = -EIO;
 552                 goto out;
 553         }
 554
 555         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 556                 struct i915_request *rq;
 557                 struct file *state;
 558
 559                 rq = requests[id];
 560                 if (!rq)
 561                         continue;
 562
 563                 if (rq->fence.error) {
 564                         err = -EIO;
 565                         goto out;
 566                 }
 567
 568                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 569                 if (!rq->context->state)
 570                         continue;
 571
 572                 /* Keep a copy of the state's backing pages; free the obj */
 573                 state = shmem_create_from_object(rq->context->state->obj);
 574                 if (IS_ERR(state)) {
 575                         err = PTR_ERR(state);
 576                         goto out;
 577                 }
 578                 rq->engine->default_state = state;
 579         }
 580
 581 out:
 582         /*
 583          * If we have to abandon now, we expect the engines to be idle
 584          * and ready to be torn-down. The quickest way we can accomplish
 585          * this is by declaring ourselves wedged.
 586          */
 587         if (err)
 588                 intel_gt_set_wedged(gt);
 589
 590         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 591                 struct intel_context *ce;
 592                 struct i915_request *rq;
 593
 594                 rq = requests[id];
 595                 if (!rq)
 596                         continue;
 597
 598                 ce = rq->context;
 599                 i915_request_put(rq);
 600                 intel_context_put(ce);
 601         }
 602         return err;
 603 }
 604
 605 static int __engines_verify_workarounds(struct intel_gt *gt)
 606 {
 607         struct intel_engine_cs *engine;
 608         enum intel_engine_id id;
 609         int err = 0;
 610
 611         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 612                 return 0;
 613
 614         for_each_engine(engine, gt, id) {
 615                 if (intel_engine_verify_workarounds(engine, "load"))
 616                         err = -EIO;
 617         }
 618
 619         /* Flush and restore the kernel context for safety */
 620         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 621                 err = -EIO;
 622
 623         return err;
 624 }
 625
 626 static void __intel_gt_disable(struct intel_gt *gt)
 627 {
 628         intel_gt_set_wedged_on_fini(gt);
 629
 630         intel_gt_suspend_prepare(gt);
 631         intel_gt_suspend_late(gt);
 632
 633         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 634 }
 635
 636 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 637 {
 638         long remaining_timeout;
 639
 640         /* If the device is asleep, we have no requests outstanding */
 641         if (!intel_gt_pm_is_awake(gt))
 642                 return 0;
 643
 644         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 645                                                            &remaining_timeout)) > 0) {
 646                 cond_resched();
 647                 if (signal_pending(current))
 648                         return -EINTR;
 649         }
 650
 651         return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
 652                                                           remaining_timeout);
 653 }
 654
 655 int intel_gt_init(struct intel_gt *gt)
 656 {
 657         int err;
 658
 659         err = i915_inject_probe_error(gt->i915, -ENODEV);
 660         if (err)
 661                 return err;
 662
 663         /*
 664          * This is just a security blanket to placate dragons.
 665          * On some systems, we very sporadically observe that the first TLBs
 666          * used by the CS may be stale, despite us poking the TLB reset. If
 667          * we hold the forcewake during initialisation these problems
 668          * just magically go away.
 669          */
 670         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 671
 672         err = intel_gt_init_scratch(gt,
 673                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 674         if (err)
 675                 goto out_fw;
 676
 677         intel_gt_pm_init(gt);
 678
 679         gt->vm = kernel_vm(gt);
 680         if (!gt->vm) {
 681                 err = -ENOMEM;
 682                 goto err_pm;
 683         }
 684
 685         err = intel_engines_init(gt);
 686         if (err)
 687                 goto err_engines;
 688
 689         err = intel_uc_init(&gt->uc);
 690         if (err)
 691                 goto err_engines;
 692
 693         err = intel_gt_resume(gt);
 694         if (err)
 695                 goto err_uc_init;
 696
 697         err = __engines_record_defaults(gt);
 698         if (err)
 699                 goto err_gt;
 700
 701         err = __engines_verify_workarounds(gt);
 702         if (err)
 703                 goto err_gt;
 704
 705         intel_uc_init_late(&gt->uc);
 706
 707         err = i915_inject_probe_error(gt->i915, -EIO);
 708         if (err)
 709                 goto err_gt;
 710
 711         intel_migrate_init(&gt->migrate, gt);
 712
 713         goto out_fw;
 714 err_gt:
 715         __intel_gt_disable(gt);
 716         intel_uc_fini_hw(&gt->uc);
 717 err_uc_init:
 718         intel_uc_fini(&gt->uc);
 719 err_engines:
 720         intel_engines_release(gt);
 721         i915_vm_put(fetch_and_zero(&gt->vm));
 722 err_pm:
 723         intel_gt_pm_fini(gt);
 724         intel_gt_fini_scratch(gt);
 725 out_fw:
 726         if (err)
 727                 intel_gt_set_wedged_on_init(gt);
 728         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 729         return err;
 730 }
 731
 732 void intel_gt_driver_remove(struct intel_gt *gt)
 733 {
 734         __intel_gt_disable(gt);
 735
 736         intel_migrate_fini(&gt->migrate);
 737         intel_uc_driver_remove(&gt->uc);
 738
 739         intel_engines_release(gt);
 740 }
 741
 742 void intel_gt_driver_unregister(struct intel_gt *gt)
 743 {
 744         intel_wakeref_t wakeref;
 745
 746         intel_rps_driver_unregister(&gt->rps);
 747
 748         /*
 749          * Upon unregistering the device to prevent any new users, cancel
 750          * all in-flight requests so that we can quickly unbind the active
 751          * resources.
 752          */
 753         intel_gt_set_wedged(gt);
 754
 755         /* Scrub all HW state upon release */
 756         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 757                 __intel_gt_reset(gt, ALL_ENGINES);
 758 }
 759
 760 void intel_gt_driver_release(struct intel_gt *gt)
 761 {
 762         struct i915_address_space *vm;
 763
 764         vm = fetch_and_zero(&gt->vm);
 765         if (vm) /* FIXME being called twice on error paths :( */
 766                 i915_vm_put(vm);
 767
 768         intel_gt_pm_fini(gt);
 769         intel_gt_fini_scratch(gt);
 770         intel_gt_fini_buffer_pool(gt);
 771 }
 772
 773 void intel_gt_driver_late_release(struct intel_gt *gt)
 774 {
 775         /* We need to wait for inflight RCU frees to release their grip */
 776         rcu_barrier();
 777
 778         intel_uc_driver_late_release(&gt->uc);
 779         intel_gt_fini_requests(gt);
 780         intel_gt_fini_reset(gt);
 781         intel_gt_fini_timelines(gt);
 782         intel_engines_free(gt);
 783 }
 784
 785 /**
 786  * intel_gt_reg_needs_read_steering - determine whether a register read
 787  *     requires explicit steering
 788  * @gt: GT structure
 789  * @reg: the register to check steering requirements for
 790  * @type: type of multicast steering to check
 791  *
 792  * Determines whether @reg needs explicit steering of a specific type for
 793  * reads.
 794  *
 795  * Returns false if @reg does not belong to a register range of the given
 796  * steering type, or if the default (subslice-based) steering IDs are suitable
 797  * for @type steering too.
 798  */
 799 static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
 800                                              i915_reg_t reg,
 801                                              enum intel_steering_type type)
 802 {
 803         const u32 offset = i915_mmio_reg_offset(reg);
 804         const struct intel_mmio_range *entry;
 805
 806         if (likely(!intel_gt_needs_read_steering(gt, type)))
 807                 return false;
 808
 809         for (entry = gt->steering_table[type]; entry->end; entry++) {
 810                 if (offset >= entry->start && offset <= entry->end)
 811                         return true;
 812         }
 813
 814         return false;
 815 }
 816
 817 /**
 818  * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
 819  * @gt: GT structure
 820  * @type: multicast register type
 821  * @sliceid: Slice ID returned
 822  * @subsliceid: Subslice ID returned
 823  *
 824  * Determines sliceid and subsliceid values that will steer reads
 825  * of a specific multicast register class to a valid value.
 826  */
 827 static void intel_gt_get_valid_steering(struct intel_gt *gt,
 828                                         enum intel_steering_type type,
 829                                         u8 *sliceid, u8 *subsliceid)
 830 {
 831         switch (type) {
 832         case L3BANK:
 833                 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
 834
 835                 *sliceid = 0;           /* unused */
 836                 *subsliceid = __ffs(gt->info.l3bank_mask);
 837                 break;
 838         case MSLICE:
 839                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 840
 841                 *sliceid = __ffs(gt->info.mslice_mask);
 842                 *subsliceid = 0;        /* unused */
 843                 break;
 844         case LNCF:
 845                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 846
 847                 /*
 848                  * An LNCF is always present if its mslice is present, so we
 849                  * can safely just steer to LNCF 0 in all cases.
 850                  */
 851                 *sliceid = __ffs(gt->info.mslice_mask) << 1;
 852                 *subsliceid = 0;        /* unused */
 853                 break;
 854         default:
 855                 MISSING_CASE(type);
 856                 *sliceid = 0;
 857                 *subsliceid = 0;
 858         }
 859 }
 860
 861 /**
 862  * intel_gt_read_register_fw - reads a GT register with support for multicast
 863  * @gt: GT structure
 864  * @reg: register to read
 865  *
 866  * This function will read a GT register.  If the register is a multicast
 867  * register, the read will be steered to a valid instance (i.e., one that
 868  * isn't fused off or powered down by power gating).
 869  *
 870  * Returns the value from a valid instance of @reg.
 871  */
 872 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
 873 {
 874         int type;
 875         u8 sliceid, subsliceid;
 876
 877         for (type = 0; type < NUM_STEERING_TYPES; type++) {
 878                 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
 879                         intel_gt_get_valid_steering(gt, type, &sliceid,
 880                                                     &subsliceid);
 881                         return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
 882                                                                       reg,
 883                                                                       sliceid,
 884                                                                       subsliceid);
 885                 }
 886         }
 887
 888         return intel_uncore_read_fw(gt->uncore, reg);
 889 }
 890
 891 void intel_gt_info_print(const struct intel_gt_info *info,
 892                          struct drm_printer *p)
 893 {
 894         drm_printf(p, "available engines: %x\n", info->engine_mask);
 895
 896         intel_sseu_dump(&info->sseu, p);
 897 }