drivers/gpu/drm/i915/gt/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26
  27 #include "gem/i915_gem_context.h"
  28
  29 #include "i915_drv.h"
  30
  31 #include "intel_breadcrumbs.h"
  32 #include "intel_context.h"
  33 #include "intel_engine.h"
  34 #include "intel_engine_pm.h"
  35 #include "intel_engine_user.h"
  36 #include "intel_execlists_submission.h"
  37 #include "intel_gt.h"
  38 #include "intel_gt_requests.h"
  39 #include "intel_gt_pm.h"
  40 #include "intel_lrc_reg.h"
  41 #include "intel_reset.h"
  42 #include "intel_ring.h"
  43 #include "uc/intel_guc_submission.h"
  44
  45 /* Haswell does have the CXT_SIZE register however it does not appear to be
  46  * valid. Now, docs explain in dwords what is in the context object. The full
  47  * size is 70720 bytes, however, the power context and execlist context will
  48  * never be saved (power context is stored elsewhere, and execlists don't work
  49  * on HSW) - so the final size, including the extra state required for the
  50  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
  51  */
  52 #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
  53
  54 #define DEFAULT_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
  55 #define GEN8_LR_CONTEXT_RENDER_SIZE     (20 * PAGE_SIZE)
  56 #define GEN9_LR_CONTEXT_RENDER_SIZE     (22 * PAGE_SIZE)
  57 #define GEN10_LR_CONTEXT_RENDER_SIZE    (18 * PAGE_SIZE)
  58 #define GEN11_LR_CONTEXT_RENDER_SIZE    (14 * PAGE_SIZE)
  59
  60 #define GEN8_LR_CONTEXT_OTHER_SIZE      ( 2 * PAGE_SIZE)
  61
  62 #define MAX_MMIO_BASES 3
  63 struct engine_info {
  64         unsigned int hw_id;
  65         u8 class;
  66         u8 instance;
  67         /* mmio bases table *must* be sorted in reverse gen order */
  68         struct engine_mmio_base {
  69                 u32 gen : 8;
  70                 u32 base : 24;
  71         } mmio_bases[MAX_MMIO_BASES];
  72 };
  73
  74 static const struct engine_info intel_engines[] = {
  75         [RCS0] = {
  76                 .hw_id = RCS0_HW,
  77                 .class = RENDER_CLASS,
  78                 .instance = 0,
  79                 .mmio_bases = {
  80                         { .gen = 1, .base = RENDER_RING_BASE }
  81                 },
  82         },
  83         [BCS0] = {
  84                 .hw_id = BCS0_HW,
  85                 .class = COPY_ENGINE_CLASS,
  86                 .instance = 0,
  87                 .mmio_bases = {
  88                         { .gen = 6, .base = BLT_RING_BASE }
  89                 },
  90         },
  91         [VCS0] = {
  92                 .hw_id = VCS0_HW,
  93                 .class = VIDEO_DECODE_CLASS,
  94                 .instance = 0,
  95                 .mmio_bases = {
  96                         { .gen = 11, .base = GEN11_BSD_RING_BASE },
  97                         { .gen = 6, .base = GEN6_BSD_RING_BASE },
  98                         { .gen = 4, .base = BSD_RING_BASE }
  99                 },
 100         },
 101         [VCS1] = {
 102                 .hw_id = VCS1_HW,
 103                 .class = VIDEO_DECODE_CLASS,
 104                 .instance = 1,
 105                 .mmio_bases = {
 106                         { .gen = 11, .base = GEN11_BSD2_RING_BASE },
 107                         { .gen = 8, .base = GEN8_BSD2_RING_BASE }
 108                 },
 109         },
 110         [VCS2] = {
 111                 .hw_id = VCS2_HW,
 112                 .class = VIDEO_DECODE_CLASS,
 113                 .instance = 2,
 114                 .mmio_bases = {
 115                         { .gen = 11, .base = GEN11_BSD3_RING_BASE }
 116                 },
 117         },
 118         [VCS3] = {
 119                 .hw_id = VCS3_HW,
 120                 .class = VIDEO_DECODE_CLASS,
 121                 .instance = 3,
 122                 .mmio_bases = {
 123                         { .gen = 11, .base = GEN11_BSD4_RING_BASE }
 124                 },
 125         },
 126         [VECS0] = {
 127                 .hw_id = VECS0_HW,
 128                 .class = VIDEO_ENHANCEMENT_CLASS,
 129                 .instance = 0,
 130                 .mmio_bases = {
 131                         { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
 132                         { .gen = 7, .base = VEBOX_RING_BASE }
 133                 },
 134         },
 135         [VECS1] = {
 136                 .hw_id = VECS1_HW,
 137                 .class = VIDEO_ENHANCEMENT_CLASS,
 138                 .instance = 1,
 139                 .mmio_bases = {
 140                         { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
 141                 },
 142         },
 143 };
 144
 145 /**
 146  * intel_engine_context_size() - return the size of the context for an engine
 147  * @gt: the gt
 148  * @class: engine class
 149  *
 150  * Each engine class may require a different amount of space for a context
 151  * image.
 152  *
 153  * Return: size (in bytes) of an engine class specific context image
 154  *
 155  * Note: this size includes the HWSP, which is part of the context image
 156  * in LRC mode, but does not include the "shared data page" used with
 157  * GuC submission. The caller should account for this if using the GuC.
 158  */
 159 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 160 {
 161         struct intel_uncore *uncore = gt->uncore;
 162         u32 cxt_size;
 163
 164         BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 165
 166         switch (class) {
 167         case RENDER_CLASS:
 168                 switch (INTEL_GEN(gt->i915)) {
 169                 default:
 170                         MISSING_CASE(INTEL_GEN(gt->i915));
 171                         return DEFAULT_LR_CONTEXT_RENDER_SIZE;
 172                 case 12:
 173                 case 11:
 174                         return GEN11_LR_CONTEXT_RENDER_SIZE;
 175                 case 10:
 176                         return GEN10_LR_CONTEXT_RENDER_SIZE;
 177                 case 9:
 178                         return GEN9_LR_CONTEXT_RENDER_SIZE;
 179                 case 8:
 180                         return GEN8_LR_CONTEXT_RENDER_SIZE;
 181                 case 7:
 182                         if (IS_HASWELL(gt->i915))
 183                                 return HSW_CXT_TOTAL_SIZE;
 184
 185                         cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
 186                         return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
 187                                         PAGE_SIZE);
 188                 case 6:
 189                         cxt_size = intel_uncore_read(uncore, CXT_SIZE);
 190                         return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
 191                                         PAGE_SIZE);
 192                 case 5:
 193                 case 4:
 194                         /*
 195                          * There is a discrepancy here between the size reported
 196                          * by the register and the size of the context layout
 197                          * in the docs. Both are described as authorative!
 198                          *
 199                          * The discrepancy is on the order of a few cachelines,
 200                          * but the total is under one page (4k), which is our
 201                          * minimum allocation anyway so it should all come
 202                          * out in the wash.
 203                          */
 204                         cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
 205                         drm_dbg(&gt->i915->drm,
 206                                 "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
 207                                 INTEL_GEN(gt->i915), cxt_size * 64,
 208                                 cxt_size - 1);
 209                         return round_up(cxt_size * 64, PAGE_SIZE);
 210                 case 3:
 211                 case 2:
 212                 /* For the special day when i810 gets merged. */
 213                 case 1:
 214                         return 0;
 215                 }
 216                 break;
 217         default:
 218                 MISSING_CASE(class);
 219                 fallthrough;
 220         case VIDEO_DECODE_CLASS:
 221         case VIDEO_ENHANCEMENT_CLASS:
 222         case COPY_ENGINE_CLASS:
 223                 if (INTEL_GEN(gt->i915) < 8)
 224                         return 0;
 225                 return GEN8_LR_CONTEXT_OTHER_SIZE;
 226         }
 227 }
 228
 229 static u32 __engine_mmio_base(struct drm_i915_private *i915,
 230                               const struct engine_mmio_base *bases)
 231 {
 232         int i;
 233
 234         for (i = 0; i < MAX_MMIO_BASES; i++)
 235                 if (INTEL_GEN(i915) >= bases[i].gen)
 236                         break;
 237
 238         GEM_BUG_ON(i == MAX_MMIO_BASES);
 239         GEM_BUG_ON(!bases[i].base);
 240
 241         return bases[i].base;
 242 }
 243
 244 static void __sprint_engine_name(struct intel_engine_cs *engine)
 245 {
 246         /*
 247          * Before we know what the uABI name for this engine will be,
 248          * we still would like to keep track of this engine in the debug logs.
 249          * We throw in a ' here as a reminder that this isn't its final name.
 250          */
 251         GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
 252                              intel_engine_class_repr(engine->class),
 253                              engine->instance) >= sizeof(engine->name));
 254 }
 255
 256 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
 257 {
 258         /*
 259          * Though they added more rings on g4x/ilk, they did not add
 260          * per-engine HWSTAM until gen6.
 261          */
 262         if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
 263                 return;
 264
 265         if (INTEL_GEN(engine->i915) >= 3)
 266                 ENGINE_WRITE(engine, RING_HWSTAM, mask);
 267         else
 268                 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
 269 }
 270
 271 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
 272 {
 273         /* Mask off all writes into the unknown HWSP */
 274         intel_engine_set_hwsp_writemask(engine, ~0u);
 275 }
 276
 277 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 278 {
 279         const struct engine_info *info = &intel_engines[id];
 280         struct drm_i915_private *i915 = gt->i915;
 281         struct intel_engine_cs *engine;
 282
 283         BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
 284         BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
 285
 286         if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
 287                 return -EINVAL;
 288
 289         if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
 290                 return -EINVAL;
 291
 292         if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
 293                 return -EINVAL;
 294
 295         if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
 296                 return -EINVAL;
 297
 298         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
 299         if (!engine)
 300                 return -ENOMEM;
 301
 302         BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
 303
 304         engine->id = id;
 305         engine->legacy_idx = INVALID_ENGINE;
 306         engine->mask = BIT(id);
 307         engine->i915 = i915;
 308         engine->gt = gt;
 309         engine->uncore = gt->uncore;
 310         engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
 311         engine->hw_id = info->hw_id;
 312         engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
 313
 314         engine->class = info->class;
 315         engine->instance = info->instance;
 316         __sprint_engine_name(engine);
 317
 318         engine->props.heartbeat_interval_ms =
 319                 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
 320         engine->props.max_busywait_duration_ns =
 321                 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
 322         engine->props.preempt_timeout_ms =
 323                 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
 324         engine->props.stop_timeout_ms =
 325                 CONFIG_DRM_I915_STOP_TIMEOUT;
 326         engine->props.timeslice_duration_ms =
 327                 CONFIG_DRM_I915_TIMESLICE_DURATION;
 328
 329         /* Override to uninterruptible for OpenCL workloads. */
 330         if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
 331                 engine->props.preempt_timeout_ms = 0;
 332
 333         engine->defaults = engine->props; /* never to change again */
 334
 335         engine->context_size = intel_engine_context_size(gt, engine->class);
 336         if (WARN_ON(engine->context_size > BIT(20)))
 337                 engine->context_size = 0;
 338         if (engine->context_size)
 339                 DRIVER_CAPS(i915)->has_logical_contexts = true;
 340
 341         /* Nothing to do here, execute in order of dependencies */
 342         engine->schedule = NULL;
 343
 344         ewma__engine_latency_init(&engine->latency);
 345         seqcount_init(&engine->stats.lock);
 346
 347         ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 348
 349         /* Scrub mmio state on takeover */
 350         intel_engine_sanitize_mmio(engine);
 351
 352         gt->engine_class[info->class][info->instance] = engine;
 353         gt->engine[id] = engine;
 354
 355         return 0;
 356 }
 357
 358 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 359 {
 360         struct drm_i915_private *i915 = engine->i915;
 361
 362         if (engine->class == VIDEO_DECODE_CLASS) {
 363                 /*
 364                  * HEVC support is present on first engine instance
 365                  * before Gen11 and on all instances afterwards.
 366                  */
 367                 if (INTEL_GEN(i915) >= 11 ||
 368                     (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 369                         engine->uabi_capabilities |=
 370                                 I915_VIDEO_CLASS_CAPABILITY_HEVC;
 371
 372                 /*
 373                  * SFC block is present only on even logical engine
 374                  * instances.
 375                  */
 376                 if ((INTEL_GEN(i915) >= 11 &&
 377                      (engine->gt->info.vdbox_sfc_access &
 378                       BIT(engine->instance))) ||
 379                     (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 380                         engine->uabi_capabilities |=
 381                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 382         } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
 383                 if (INTEL_GEN(i915) >= 9)
 384                         engine->uabi_capabilities |=
 385                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 386         }
 387 }
 388
 389 static void intel_setup_engine_capabilities(struct intel_gt *gt)
 390 {
 391         struct intel_engine_cs *engine;
 392         enum intel_engine_id id;
 393
 394         for_each_engine(engine, gt, id)
 395                 __setup_engine_capabilities(engine);
 396 }
 397
 398 /**
 399  * intel_engines_release() - free the resources allocated for Command Streamers
 400  * @gt: pointer to struct intel_gt
 401  */
 402 void intel_engines_release(struct intel_gt *gt)
 403 {
 404         struct intel_engine_cs *engine;
 405         enum intel_engine_id id;
 406
 407         /*
 408          * Before we release the resources held by engine, we must be certain
 409          * that the HW is no longer accessing them -- having the GPU scribble
 410          * to or read from a page being used for something else causes no end
 411          * of fun.
 412          *
 413          * The GPU should be reset by this point, but assume the worst just
 414          * in case we aborted before completely initialising the engines.
 415          */
 416         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 417         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 418                 __intel_gt_reset(gt, ALL_ENGINES);
 419
 420         /* Decouple the backend; but keep the layout for late GPU resets */
 421         for_each_engine(engine, gt, id) {
 422                 if (!engine->release)
 423                         continue;
 424
 425                 intel_wakeref_wait_for_idle(&engine->wakeref);
 426                 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
 427
 428                 engine->release(engine);
 429                 engine->release = NULL;
 430
 431                 memset(&engine->reset, 0, sizeof(engine->reset));
 432         }
 433 }
 434
 435 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
 436 {
 437         if (!engine->request_pool)
 438                 return;
 439
 440         kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
 441 }
 442
 443 void intel_engines_free(struct intel_gt *gt)
 444 {
 445         struct intel_engine_cs *engine;
 446         enum intel_engine_id id;
 447
 448         /* Free the requests! dma-resv keeps fences around for an eternity */
 449         rcu_barrier();
 450
 451         for_each_engine(engine, gt, id) {
 452                 intel_engine_free_request_pool(engine);
 453                 kfree(engine);
 454                 gt->engine[id] = NULL;
 455         }
 456 }
 457
 458 /*
 459  * Determine which engines are fused off in our particular hardware.
 460  * Note that we have a catch-22 situation where we need to be able to access
 461  * the blitter forcewake domain to read the engine fuses, but at the same time
 462  * we need to know which engines are available on the system to know which
 463  * forcewake domains are present. We solve this by intializing the forcewake
 464  * domains based on the full engine mask in the platform capabilities before
 465  * calling this function and pruning the domains for fused-off engines
 466  * afterwards.
 467  */
 468 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 469 {
 470         struct drm_i915_private *i915 = gt->i915;
 471         struct intel_gt_info *info = &gt->info;
 472         struct intel_uncore *uncore = gt->uncore;
 473         unsigned int logical_vdbox = 0;
 474         unsigned int i;
 475         u32 media_fuse;
 476         u16 vdbox_mask;
 477         u16 vebox_mask;
 478
 479         info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
 480
 481         if (INTEL_GEN(i915) < 11)
 482                 return info->engine_mask;
 483
 484         media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
 485
 486         vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
 487         vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
 488                       GEN11_GT_VEBOX_DISABLE_SHIFT;
 489
 490         for (i = 0; i < I915_MAX_VCS; i++) {
 491                 if (!HAS_ENGINE(gt, _VCS(i))) {
 492                         vdbox_mask &= ~BIT(i);
 493                         continue;
 494                 }
 495
 496                 if (!(BIT(i) & vdbox_mask)) {
 497                         info->engine_mask &= ~BIT(_VCS(i));
 498                         drm_dbg(&i915->drm, "vcs%u fused off\n", i);
 499                         continue;
 500                 }
 501
 502                 /*
 503                  * In Gen11, only even numbered logical VDBOXes are
 504                  * hooked up to an SFC (Scaler & Format Converter) unit.
 505                  * In TGL each VDBOX has access to an SFC.
 506                  */
 507                 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
 508                         gt->info.vdbox_sfc_access |= BIT(i);
 509         }
 510         drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
 511                 vdbox_mask, VDBOX_MASK(gt));
 512         GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
 513
 514         for (i = 0; i < I915_MAX_VECS; i++) {
 515                 if (!HAS_ENGINE(gt, _VECS(i))) {
 516                         vebox_mask &= ~BIT(i);
 517                         continue;
 518                 }
 519
 520                 if (!(BIT(i) & vebox_mask)) {
 521                         info->engine_mask &= ~BIT(_VECS(i));
 522                         drm_dbg(&i915->drm, "vecs%u fused off\n", i);
 523                 }
 524         }
 525         drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
 526                 vebox_mask, VEBOX_MASK(gt));
 527         GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
 528
 529         return info->engine_mask;
 530 }
 531
 532 /**
 533  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
 534  * @gt: pointer to struct intel_gt
 535  *
 536  * Return: non-zero if the initialization failed.
 537  */
 538 int intel_engines_init_mmio(struct intel_gt *gt)
 539 {
 540         struct drm_i915_private *i915 = gt->i915;
 541         const unsigned int engine_mask = init_engine_mask(gt);
 542         unsigned int mask = 0;
 543         unsigned int i;
 544         int err;
 545
 546         drm_WARN_ON(&i915->drm, engine_mask == 0);
 547         drm_WARN_ON(&i915->drm, engine_mask &
 548                     GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
 549
 550         if (i915_inject_probe_failure(i915))
 551                 return -ENODEV;
 552
 553         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 554                 if (!HAS_ENGINE(gt, i))
 555                         continue;
 556
 557                 err = intel_engine_setup(gt, i);
 558                 if (err)
 559                         goto cleanup;
 560
 561                 mask |= BIT(i);
 562         }
 563
 564         /*
 565          * Catch failures to update intel_engines table when the new engines
 566          * are added to the driver by a warning and disabling the forgotten
 567          * engines.
 568          */
 569         if (drm_WARN_ON(&i915->drm, mask != engine_mask))
 570                 gt->info.engine_mask = mask;
 571
 572         gt->info.num_engines = hweight32(mask);
 573
 574         intel_gt_check_and_clear_faults(gt);
 575
 576         intel_setup_engine_capabilities(gt);
 577
 578         intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
 579
 580         return 0;
 581
 582 cleanup:
 583         intel_engines_free(gt);
 584         return err;
 585 }
 586
 587 void intel_engine_init_execlists(struct intel_engine_cs *engine)
 588 {
 589         struct intel_engine_execlists * const execlists = &engine->execlists;
 590
 591         execlists->port_mask = 1;
 592         GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
 593         GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
 594
 595         memset(execlists->pending, 0, sizeof(execlists->pending));
 596         execlists->active =
 597                 memset(execlists->inflight, 0, sizeof(execlists->inflight));
 598
 599         execlists->queue_priority_hint = INT_MIN;
 600         execlists->queue = RB_ROOT_CACHED;
 601 }
 602
 603 static void cleanup_status_page(struct intel_engine_cs *engine)
 604 {
 605         struct i915_vma *vma;
 606
 607         /* Prevent writes into HWSP after returning the page to the system */
 608         intel_engine_set_hwsp_writemask(engine, ~0u);
 609
 610         vma = fetch_and_zero(&engine->status_page.vma);
 611         if (!vma)
 612                 return;
 613
 614         if (!HWS_NEEDS_PHYSICAL(engine->i915))
 615                 i915_vma_unpin(vma);
 616
 617         i915_gem_object_unpin_map(vma->obj);
 618         i915_gem_object_put(vma->obj);
 619 }
 620
 621 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
 622                                 struct i915_vma *vma)
 623 {
 624         unsigned int flags;
 625
 626         if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
 627                 /*
 628                  * On g33, we cannot place HWS above 256MiB, so
 629                  * restrict its pinning to the low mappable arena.
 630                  * Though this restriction is not documented for
 631                  * gen4, gen5, or byt, they also behave similarly
 632                  * and hang if the HWS is placed at the top of the
 633                  * GTT. To generalise, it appears that all !llc
 634                  * platforms have issues with us placing the HWS
 635                  * above the mappable region (even though we never
 636                  * actually map it).
 637                  */
 638                 flags = PIN_MAPPABLE;
 639         else
 640                 flags = PIN_HIGH;
 641
 642         return i915_ggtt_pin(vma, NULL, 0, flags);
 643 }
 644
 645 static int init_status_page(struct intel_engine_cs *engine)
 646 {
 647         struct drm_i915_gem_object *obj;
 648         struct i915_vma *vma;
 649         void *vaddr;
 650         int ret;
 651
 652         INIT_LIST_HEAD(&engine->status_page.timelines);
 653
 654         /*
 655          * Though the HWS register does support 36bit addresses, historically
 656          * we have had hangs and corruption reported due to wild writes if
 657          * the HWS is placed above 4G. We only allow objects to be allocated
 658          * in GFP_DMA32 for i965, and no earlier physical address users had
 659          * access to more than 4G.
 660          */
 661         obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
 662         if (IS_ERR(obj)) {
 663                 drm_err(&engine->i915->drm,
 664                         "Failed to allocate status page\n");
 665                 return PTR_ERR(obj);
 666         }
 667
 668         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 669
 670         vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 671         if (IS_ERR(vma)) {
 672                 ret = PTR_ERR(vma);
 673                 goto err;
 674         }
 675
 676         vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
 677         if (IS_ERR(vaddr)) {
 678                 ret = PTR_ERR(vaddr);
 679                 goto err;
 680         }
 681
 682         engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
 683         engine->status_page.vma = vma;
 684
 685         if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
 686                 ret = pin_ggtt_status_page(engine, vma);
 687                 if (ret)
 688                         goto err_unpin;
 689         }
 690
 691         return 0;
 692
 693 err_unpin:
 694         i915_gem_object_unpin_map(obj);
 695 err:
 696         i915_gem_object_put(obj);
 697         return ret;
 698 }
 699
 700 static int engine_setup_common(struct intel_engine_cs *engine)
 701 {
 702         int err;
 703
 704         init_llist_head(&engine->barrier_tasks);
 705
 706         err = init_status_page(engine);
 707         if (err)
 708                 return err;
 709
 710         engine->breadcrumbs = intel_breadcrumbs_create(engine);
 711         if (!engine->breadcrumbs) {
 712                 err = -ENOMEM;
 713                 goto err_status;
 714         }
 715
 716         intel_engine_init_active(engine, ENGINE_PHYSICAL);
 717         intel_engine_init_execlists(engine);
 718         intel_engine_init_cmd_parser(engine);
 719         intel_engine_init__pm(engine);
 720         intel_engine_init_retire(engine);
 721
 722         /* Use the whole device by default */
 723         engine->sseu =
 724                 intel_sseu_from_device_info(&engine->gt->info.sseu);
 725
 726         intel_engine_init_workarounds(engine);
 727         intel_engine_init_whitelist(engine);
 728         intel_engine_init_ctx_wa(engine);
 729
 730         if (INTEL_GEN(engine->i915) >= 12)
 731                 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
 732
 733         return 0;
 734
 735 err_status:
 736         cleanup_status_page(engine);
 737         return err;
 738 }
 739
 740 struct measure_breadcrumb {
 741         struct i915_request rq;
 742         struct intel_ring ring;
 743         u32 cs[2048];
 744 };
 745
 746 static int measure_breadcrumb_dw(struct intel_context *ce)
 747 {
 748         struct intel_engine_cs *engine = ce->engine;
 749         struct measure_breadcrumb *frame;
 750         int dw;
 751
 752         GEM_BUG_ON(!engine->gt->scratch);
 753
 754         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 755         if (!frame)
 756                 return -ENOMEM;
 757
 758         frame->rq.engine = engine;
 759         frame->rq.context = ce;
 760         rcu_assign_pointer(frame->rq.timeline, ce->timeline);
 761
 762         frame->ring.vaddr = frame->cs;
 763         frame->ring.size = sizeof(frame->cs);
 764         frame->ring.wrap =
 765                 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
 766         frame->ring.effective_size = frame->ring.size;
 767         intel_ring_update_space(&frame->ring);
 768         frame->rq.ring = &frame->ring;
 769
 770         mutex_lock(&ce->timeline->mutex);
 771         spin_lock_irq(&engine->active.lock);
 772
 773         dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
 774
 775         spin_unlock_irq(&engine->active.lock);
 776         mutex_unlock(&ce->timeline->mutex);
 777
 778         GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
 779
 780         kfree(frame);
 781         return dw;
 782 }
 783
 784 void
 785 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
 786 {
 787         INIT_LIST_HEAD(&engine->active.requests);
 788         INIT_LIST_HEAD(&engine->active.hold);
 789
 790         spin_lock_init(&engine->active.lock);
 791         lockdep_set_subclass(&engine->active.lock, subclass);
 792
 793         /*
 794          * Due to an interesting quirk in lockdep's internal debug tracking,
 795          * after setting a subclass we must ensure the lock is used. Otherwise,
 796          * nr_unused_locks is incremented once too often.
 797          */
 798 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 799         local_irq_disable();
 800         lock_map_acquire(&engine->active.lock.dep_map);
 801         lock_map_release(&engine->active.lock.dep_map);
 802         local_irq_enable();
 803 #endif
 804 }
 805
 806 static struct intel_context *
 807 create_pinned_context(struct intel_engine_cs *engine,
 808                       unsigned int hwsp,
 809                       struct lock_class_key *key,
 810                       const char *name)
 811 {
 812         struct intel_context *ce;
 813         int err;
 814
 815         ce = intel_context_create(engine);
 816         if (IS_ERR(ce))
 817                 return ce;
 818
 819         __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
 820         ce->timeline = page_pack_bits(NULL, hwsp);
 821
 822         err = intel_context_pin(ce); /* perma-pin so it is always available */
 823         if (err) {
 824                 intel_context_put(ce);
 825                 return ERR_PTR(err);
 826         }
 827
 828         /*
 829          * Give our perma-pinned kernel timelines a separate lockdep class,
 830          * so that we can use them from within the normal user timelines
 831          * should we need to inject GPU operations during their request
 832          * construction.
 833          */
 834         lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
 835
 836         return ce;
 837 }
 838
 839 static void destroy_pinned_context(struct intel_context *ce)
 840 {
 841         struct intel_engine_cs *engine = ce->engine;
 842         struct i915_vma *hwsp = engine->status_page.vma;
 843
 844         GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
 845
 846         mutex_lock(&hwsp->vm->mutex);
 847         list_del(&ce->timeline->engine_link);
 848         mutex_unlock(&hwsp->vm->mutex);
 849
 850         intel_context_unpin(ce);
 851         intel_context_put(ce);
 852 }
 853
 854 static struct intel_context *
 855 create_kernel_context(struct intel_engine_cs *engine)
 856 {
 857         static struct lock_class_key kernel;
 858
 859         return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
 860                                      &kernel, "kernel_context");
 861 }
 862
 863 /**
 864  * intel_engines_init_common - initialize cengine state which might require hw access
 865  * @engine: Engine to initialize.
 866  *
 867  * Initializes @engine@ structure members shared between legacy and execlists
 868  * submission modes which do require hardware access.
 869  *
 870  * Typcally done at later stages of submission mode specific engine setup.
 871  *
 872  * Returns zero on success or an error code on failure.
 873  */
 874 static int engine_init_common(struct intel_engine_cs *engine)
 875 {
 876         struct intel_context *ce;
 877         int ret;
 878
 879         engine->set_default_submission(engine);
 880
 881         /*
 882          * We may need to do things with the shrinker which
 883          * require us to immediately switch back to the default
 884          * context. This can cause a problem as pinning the
 885          * default context also requires GTT space which may not
 886          * be available. To avoid this we always pin the default
 887          * context.
 888          */
 889         ce = create_kernel_context(engine);
 890         if (IS_ERR(ce))
 891                 return PTR_ERR(ce);
 892
 893         ret = measure_breadcrumb_dw(ce);
 894         if (ret < 0)
 895                 goto err_context;
 896
 897         engine->emit_fini_breadcrumb_dw = ret;
 898         engine->kernel_context = ce;
 899
 900         return 0;
 901
 902 err_context:
 903         intel_context_put(ce);
 904         return ret;
 905 }
 906
 907 int intel_engines_init(struct intel_gt *gt)
 908 {
 909         int (*setup)(struct intel_engine_cs *engine);
 910         struct intel_engine_cs *engine;
 911         enum intel_engine_id id;
 912         int err;
 913
 914         if (intel_uc_uses_guc_submission(&gt->uc))
 915                 setup = intel_guc_submission_setup;
 916         else if (HAS_EXECLISTS(gt->i915))
 917                 setup = intel_execlists_submission_setup;
 918         else
 919                 setup = intel_ring_submission_setup;
 920
 921         for_each_engine(engine, gt, id) {
 922                 err = engine_setup_common(engine);
 923                 if (err)
 924                         return err;
 925
 926                 err = setup(engine);
 927                 if (err)
 928                         return err;
 929
 930                 err = engine_init_common(engine);
 931                 if (err)
 932                         return err;
 933
 934                 intel_engine_add_user(engine);
 935         }
 936
 937         return 0;
 938 }
 939
 940 /**
 941  * intel_engines_cleanup_common - cleans up the engine state created by
 942  *                                the common initiailizers.
 943  * @engine: Engine to cleanup.
 944  *
 945  * This cleans up everything created by the common helpers.
 946  */
 947 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 948 {
 949         GEM_BUG_ON(!list_empty(&engine->active.requests));
 950         tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
 951
 952         intel_breadcrumbs_free(engine->breadcrumbs);
 953
 954         intel_engine_fini_retire(engine);
 955         intel_engine_cleanup_cmd_parser(engine);
 956
 957         if (engine->default_state)
 958                 fput(engine->default_state);
 959
 960         if (engine->kernel_context)
 961                 destroy_pinned_context(engine->kernel_context);
 962
 963         GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
 964         cleanup_status_page(engine);
 965
 966         intel_wa_list_free(&engine->ctx_wa_list);
 967         intel_wa_list_free(&engine->wa_list);
 968         intel_wa_list_free(&engine->whitelist);
 969 }
 970
 971 /**
 972  * intel_engine_resume - re-initializes the HW state of the engine
 973  * @engine: Engine to resume.
 974  *
 975  * Returns zero on success or an error code on failure.
 976  */
 977 int intel_engine_resume(struct intel_engine_cs *engine)
 978 {
 979         intel_engine_apply_workarounds(engine);
 980         intel_engine_apply_whitelist(engine);
 981
 982         return engine->resume(engine);
 983 }
 984
 985 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
 986 {
 987         struct drm_i915_private *i915 = engine->i915;
 988
 989         u64 acthd;
 990
 991         if (INTEL_GEN(i915) >= 8)
 992                 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
 993         else if (INTEL_GEN(i915) >= 4)
 994                 acthd = ENGINE_READ(engine, RING_ACTHD);
 995         else
 996                 acthd = ENGINE_READ(engine, ACTHD);
 997
 998         return acthd;
 999 }
1000
1001 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1002 {
1003         u64 bbaddr;
1004
1005         if (INTEL_GEN(engine->i915) >= 8)
1006                 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1007         else
1008                 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1009
1010         return bbaddr;
1011 }
1012
1013 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1014 {
1015         if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1016                 return 0;
1017
1018         /*
1019          * If we are doing a normal GPU reset, we can take our time and allow
1020          * the engine to quiesce. We've stopped submission to the engine, and
1021          * if we wait long enough an innocent context should complete and
1022          * leave the engine idle. So they should not be caught unaware by
1023          * the forthcoming GPU reset (which usually follows the stop_cs)!
1024          */
1025         return READ_ONCE(engine->props.stop_timeout_ms);
1026 }
1027
1028 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1029                                   int fast_timeout_us,
1030                                   int slow_timeout_ms)
1031 {
1032         struct intel_uncore *uncore = engine->uncore;
1033         const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1034         int err;
1035
1036         intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1037         err = __intel_wait_for_register_fw(engine->uncore, mode,
1038                                            MODE_IDLE, MODE_IDLE,
1039                                            fast_timeout_us,
1040                                            slow_timeout_ms,
1041                                            NULL);
1042
1043         /* A final mmio read to let GPU writes be hopefully flushed to memory */
1044         intel_uncore_posting_read_fw(uncore, mode);
1045         return err;
1046 }
1047
1048 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1049 {
1050         int err = 0;
1051
1052         if (INTEL_GEN(engine->i915) < 3)
1053                 return -ENODEV;
1054
1055         ENGINE_TRACE(engine, "\n");
1056         if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1057                 ENGINE_TRACE(engine,
1058                              "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1059                              ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1060                              ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1061
1062                 /*
1063                  * Sometimes we observe that the idle flag is not
1064                  * set even though the ring is empty. So double
1065                  * check before giving up.
1066                  */
1067                 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1068                     (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1069                         err = -ETIMEDOUT;
1070         }
1071
1072         return err;
1073 }
1074
1075 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1076 {
1077         ENGINE_TRACE(engine, "\n");
1078
1079         ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1080 }
1081
1082 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1083 {
1084         switch (type) {
1085         case I915_CACHE_NONE: return " uncached";
1086         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1087         case I915_CACHE_L3_LLC: return " L3+LLC";
1088         case I915_CACHE_WT: return " WT";
1089         default: return "";
1090         }
1091 }
1092
1093 static u32
1094 read_subslice_reg(const struct intel_engine_cs *engine,
1095                   int slice, int subslice, i915_reg_t reg)
1096 {
1097         struct drm_i915_private *i915 = engine->i915;
1098         struct intel_uncore *uncore = engine->uncore;
1099         u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1100         enum forcewake_domains fw_domains;
1101
1102         if (INTEL_GEN(i915) >= 11) {
1103                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1104                 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1105         } else {
1106                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1107                 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1108         }
1109
1110         fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1111                                                     FW_REG_READ);
1112         fw_domains |= intel_uncore_forcewake_for_reg(uncore,
1113                                                      GEN8_MCR_SELECTOR,
1114                                                      FW_REG_READ | FW_REG_WRITE);
1115
1116         spin_lock_irq(&uncore->lock);
1117         intel_uncore_forcewake_get__locked(uncore, fw_domains);
1118
1119         old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1120
1121         mcr &= ~mcr_mask;
1122         mcr |= mcr_ss;
1123         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1124
1125         val = intel_uncore_read_fw(uncore, reg);
1126
1127         mcr &= ~mcr_mask;
1128         mcr |= old_mcr & mcr_mask;
1129
1130         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1131
1132         intel_uncore_forcewake_put__locked(uncore, fw_domains);
1133         spin_unlock_irq(&uncore->lock);
1134
1135         return val;
1136 }
1137
1138 /* NB: please notice the memset */
1139 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1140                                struct intel_instdone *instdone)
1141 {
1142         struct drm_i915_private *i915 = engine->i915;
1143         const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
1144         struct intel_uncore *uncore = engine->uncore;
1145         u32 mmio_base = engine->mmio_base;
1146         int slice;
1147         int subslice;
1148
1149         memset(instdone, 0, sizeof(*instdone));
1150
1151         switch (INTEL_GEN(i915)) {
1152         default:
1153                 instdone->instdone =
1154                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1155
1156                 if (engine->id != RCS0)
1157                         break;
1158
1159                 instdone->slice_common =
1160                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1161                 if (INTEL_GEN(i915) >= 12) {
1162                         instdone->slice_common_extra[0] =
1163                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1164                         instdone->slice_common_extra[1] =
1165                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1166                 }
1167                 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
1168                         instdone->sampler[slice][subslice] =
1169                                 read_subslice_reg(engine, slice, subslice,
1170                                                   GEN7_SAMPLER_INSTDONE);
1171                         instdone->row[slice][subslice] =
1172                                 read_subslice_reg(engine, slice, subslice,
1173                                                   GEN7_ROW_INSTDONE);
1174                 }
1175                 break;
1176         case 7:
1177                 instdone->instdone =
1178                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1179
1180                 if (engine->id != RCS0)
1181                         break;
1182
1183                 instdone->slice_common =
1184                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1185                 instdone->sampler[0][0] =
1186                         intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1187                 instdone->row[0][0] =
1188                         intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1189
1190                 break;
1191         case 6:
1192         case 5:
1193         case 4:
1194                 instdone->instdone =
1195                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1196                 if (engine->id == RCS0)
1197                         /* HACK: Using the wrong struct member */
1198                         instdone->slice_common =
1199                                 intel_uncore_read(uncore, GEN4_INSTDONE1);
1200                 break;
1201         case 3:
1202         case 2:
1203                 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1204                 break;
1205         }
1206 }
1207
1208 static bool ring_is_idle(struct intel_engine_cs *engine)
1209 {
1210         bool idle = true;
1211
1212         if (I915_SELFTEST_ONLY(!engine->mmio_base))
1213                 return true;
1214
1215         if (!intel_engine_pm_get_if_awake(engine))
1216                 return true;
1217
1218         /* First check that no commands are left in the ring */
1219         if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1220             (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1221                 idle = false;
1222
1223         /* No bit for gen2, so assume the CS parser is idle */
1224         if (INTEL_GEN(engine->i915) > 2 &&
1225             !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1226                 idle = false;
1227
1228         intel_engine_pm_put(engine);
1229
1230         return idle;
1231 }
1232
1233 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1234 {
1235         struct tasklet_struct *t = &engine->execlists.tasklet;
1236
1237         if (!t->func)
1238                 return;
1239
1240         local_bh_disable();
1241         if (tasklet_trylock(t)) {
1242                 /* Must wait for any GPU reset in progress. */
1243                 if (__tasklet_is_enabled(t))
1244                         t->func(t->data);
1245                 tasklet_unlock(t);
1246         }
1247         local_bh_enable();
1248
1249         /* Synchronise and wait for the tasklet on another CPU */
1250         if (sync)
1251                 tasklet_unlock_wait(t);
1252 }
1253
1254 /**
1255  * intel_engine_is_idle() - Report if the engine has finished process all work
1256  * @engine: the intel_engine_cs
1257  *
1258  * Return true if there are no requests pending, nothing left to be submitted
1259  * to hardware, and that the engine is idle.
1260  */
1261 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1262 {
1263         /* More white lies, if wedged, hw state is inconsistent */
1264         if (intel_gt_is_wedged(engine->gt))
1265                 return true;
1266
1267         if (!intel_engine_pm_is_awake(engine))
1268                 return true;
1269
1270         /* Waiting to drain ELSP? */
1271         if (execlists_active(&engine->execlists)) {
1272                 synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq);
1273
1274                 intel_engine_flush_submission(engine);
1275
1276                 if (execlists_active(&engine->execlists))
1277                         return false;
1278         }
1279
1280         /* ELSP is empty, but there are ready requests? E.g. after reset */
1281         if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1282                 return false;
1283
1284         /* Ring stopped? */
1285         return ring_is_idle(engine);
1286 }
1287
1288 bool intel_engines_are_idle(struct intel_gt *gt)
1289 {
1290         struct intel_engine_cs *engine;
1291         enum intel_engine_id id;
1292
1293         /*
1294          * If the driver is wedged, HW state may be very inconsistent and
1295          * report that it is still busy, even though we have stopped using it.
1296          */
1297         if (intel_gt_is_wedged(gt))
1298                 return true;
1299
1300         /* Already parked (and passed an idleness test); must still be idle */
1301         if (!READ_ONCE(gt->awake))
1302                 return true;
1303
1304         for_each_engine(engine, gt, id) {
1305                 if (!intel_engine_is_idle(engine))
1306                         return false;
1307         }
1308
1309         return true;
1310 }
1311
1312 void intel_engines_reset_default_submission(struct intel_gt *gt)
1313 {
1314         struct intel_engine_cs *engine;
1315         enum intel_engine_id id;
1316
1317         for_each_engine(engine, gt, id) {
1318                 if (engine->sanitize)
1319                         engine->sanitize(engine);
1320
1321                 engine->set_default_submission(engine);
1322         }
1323 }
1324
1325 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1326 {
1327         switch (INTEL_GEN(engine->i915)) {
1328         case 2:
1329                 return false; /* uses physical not virtual addresses */
1330         case 3:
1331                 /* maybe only uses physical not virtual addresses */
1332                 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1333         case 4:
1334                 return !IS_I965G(engine->i915); /* who knows! */
1335         case 6:
1336                 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1337         default:
1338                 return true;
1339         }
1340 }
1341
1342 static struct intel_timeline *get_timeline(struct i915_request *rq)
1343 {
1344         struct intel_timeline *tl;
1345
1346         /*
1347          * Even though we are holding the engine->active.lock here, there
1348          * is no control over the submission queue per-se and we are
1349          * inspecting the active state at a random point in time, with an
1350          * unknown queue. Play safe and make sure the timeline remains valid.
1351          * (Only being used for pretty printing, one extra kref shouldn't
1352          * cause a camel stampede!)
1353          */
1354         rcu_read_lock();
1355         tl = rcu_dereference(rq->timeline);
1356         if (!kref_get_unless_zero(&tl->kref))
1357                 tl = NULL;
1358         rcu_read_unlock();
1359
1360         return tl;
1361 }
1362
1363 static int print_ring(char *buf, int sz, struct i915_request *rq)
1364 {
1365         int len = 0;
1366
1367         if (!i915_request_signaled(rq)) {
1368                 struct intel_timeline *tl = get_timeline(rq);
1369
1370                 len = scnprintf(buf, sz,
1371                                 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1372                                 i915_ggtt_offset(rq->ring->vma),
1373                                 tl ? tl->hwsp_offset : 0,
1374                                 hwsp_seqno(rq),
1375                                 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1376                                                       1000 * 1000));
1377
1378                 if (tl)
1379                         intel_timeline_put(tl);
1380         }
1381
1382         return len;
1383 }
1384
1385 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1386 {
1387         const size_t rowsize = 8 * sizeof(u32);
1388         const void *prev = NULL;
1389         bool skip = false;
1390         size_t pos;
1391
1392         for (pos = 0; pos < len; pos += rowsize) {
1393                 char line[128];
1394
1395                 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1396                         if (!skip) {
1397                                 drm_printf(m, "*\n");
1398                                 skip = true;
1399                         }
1400                         continue;
1401                 }
1402
1403                 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1404                                                 rowsize, sizeof(u32),
1405                                                 line, sizeof(line),
1406                                                 false) >= sizeof(line));
1407                 drm_printf(m, "[%04zx] %s\n", pos, line);
1408
1409                 prev = buf + pos;
1410                 skip = false;
1411         }
1412 }
1413
1414 static const char *repr_timer(const struct timer_list *t)
1415 {
1416         if (!READ_ONCE(t->expires))
1417                 return "inactive";
1418
1419         if (timer_pending(t))
1420                 return "active";
1421
1422         return "expired";
1423 }
1424
1425 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1426                                          struct drm_printer *m)
1427 {
1428         struct drm_i915_private *dev_priv = engine->i915;
1429         struct intel_engine_execlists * const execlists = &engine->execlists;
1430         u64 addr;
1431
1432         if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
1433                 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1434         if (HAS_EXECLISTS(dev_priv)) {
1435                 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1436                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1437                 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1438                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1439         }
1440         drm_printf(m, "\tRING_START: 0x%08x\n",
1441                    ENGINE_READ(engine, RING_START));
1442         drm_printf(m, "\tRING_HEAD:  0x%08x\n",
1443                    ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1444         drm_printf(m, "\tRING_TAIL:  0x%08x\n",
1445                    ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1446         drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
1447                    ENGINE_READ(engine, RING_CTL),
1448                    ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1449         if (INTEL_GEN(engine->i915) > 2) {
1450                 drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
1451                            ENGINE_READ(engine, RING_MI_MODE),
1452                            ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1453         }
1454
1455         if (INTEL_GEN(dev_priv) >= 6) {
1456                 drm_printf(m, "\tRING_IMR:   0x%08x\n",
1457                            ENGINE_READ(engine, RING_IMR));
1458                 drm_printf(m, "\tRING_ESR:   0x%08x\n",
1459                            ENGINE_READ(engine, RING_ESR));
1460                 drm_printf(m, "\tRING_EMR:   0x%08x\n",
1461                            ENGINE_READ(engine, RING_EMR));
1462                 drm_printf(m, "\tRING_EIR:   0x%08x\n",
1463                            ENGINE_READ(engine, RING_EIR));
1464         }
1465
1466         addr = intel_engine_get_active_head(engine);
1467         drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
1468                    upper_32_bits(addr), lower_32_bits(addr));
1469         addr = intel_engine_get_last_batch_head(engine);
1470         drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1471                    upper_32_bits(addr), lower_32_bits(addr));
1472         if (INTEL_GEN(dev_priv) >= 8)
1473                 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1474         else if (INTEL_GEN(dev_priv) >= 4)
1475                 addr = ENGINE_READ(engine, RING_DMA_FADD);
1476         else
1477                 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1478         drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1479                    upper_32_bits(addr), lower_32_bits(addr));
1480         if (INTEL_GEN(dev_priv) >= 4) {
1481                 drm_printf(m, "\tIPEIR: 0x%08x\n",
1482                            ENGINE_READ(engine, RING_IPEIR));
1483                 drm_printf(m, "\tIPEHR: 0x%08x\n",
1484                            ENGINE_READ(engine, RING_IPEHR));
1485         } else {
1486                 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1487                 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1488         }
1489
1490         if (intel_engine_in_guc_submission_mode(engine)) {
1491                 /* nothing to print yet */
1492         } else if (HAS_EXECLISTS(dev_priv)) {
1493                 struct i915_request * const *port, *rq;
1494                 const u32 *hws =
1495                         &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1496                 const u8 num_entries = execlists->csb_size;
1497                 unsigned int idx;
1498                 u8 read, write;
1499
1500                 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1501                            yesno(test_bit(TASKLET_STATE_SCHED,
1502                                           &engine->execlists.tasklet.state)),
1503                            enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
1504                            repr_timer(&engine->execlists.preempt),
1505                            repr_timer(&engine->execlists.timer));
1506
1507                 read = execlists->csb_head;
1508                 write = READ_ONCE(*execlists->csb_write);
1509
1510                 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1511                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1512                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1513                            read, write, num_entries);
1514
1515                 if (read >= num_entries)
1516                         read = 0;
1517                 if (write >= num_entries)
1518                         write = 0;
1519                 if (read > write)
1520                         write += num_entries;
1521                 while (read < write) {
1522                         idx = ++read % num_entries;
1523                         drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1524                                    idx, hws[idx * 2], hws[idx * 2 + 1]);
1525                 }
1526
1527                 execlists_active_lock_bh(execlists);
1528                 rcu_read_lock();
1529                 for (port = execlists->active; (rq = *port); port++) {
1530                         char hdr[160];
1531                         int len;
1532
1533                         len = scnprintf(hdr, sizeof(hdr),
1534                                         "\t\tActive[%d]:  ccid:%08x%s%s, ",
1535                                         (int)(port - execlists->active),
1536                                         rq->context->lrc.ccid,
1537                                         intel_context_is_closed(rq->context) ? "!" : "",
1538                                         intel_context_is_banned(rq->context) ? "*" : "");
1539                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1540                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1541                         i915_request_show(m, rq, hdr, 0);
1542                 }
1543                 for (port = execlists->pending; (rq = *port); port++) {
1544                         char hdr[160];
1545                         int len;
1546
1547                         len = scnprintf(hdr, sizeof(hdr),
1548                                         "\t\tPending[%d]: ccid:%08x%s%s, ",
1549                                         (int)(port - execlists->pending),
1550                                         rq->context->lrc.ccid,
1551                                         intel_context_is_closed(rq->context) ? "!" : "",
1552                                         intel_context_is_banned(rq->context) ? "*" : "");
1553                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1554                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1555                         i915_request_show(m, rq, hdr, 0);
1556                 }
1557                 rcu_read_unlock();
1558                 execlists_active_unlock_bh(execlists);
1559         } else if (INTEL_GEN(dev_priv) > 6) {
1560                 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1561                            ENGINE_READ(engine, RING_PP_DIR_BASE));
1562                 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1563                            ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1564                 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1565                            ENGINE_READ(engine, RING_PP_DIR_DCLV));
1566         }
1567 }
1568
1569 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1570 {
1571         void *ring;
1572         int size;
1573
1574         drm_printf(m,
1575                    "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1576                    rq->head, rq->postfix, rq->tail,
1577                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1578                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1579
1580         size = rq->tail - rq->head;
1581         if (rq->tail < rq->head)
1582                 size += rq->ring->size;
1583
1584         ring = kmalloc(size, GFP_ATOMIC);
1585         if (ring) {
1586                 const void *vaddr = rq->ring->vaddr;
1587                 unsigned int head = rq->head;
1588                 unsigned int len = 0;
1589
1590                 if (rq->tail < head) {
1591                         len = rq->ring->size - head;
1592                         memcpy(ring, vaddr + head, len);
1593                         head = 0;
1594                 }
1595                 memcpy(ring + len, vaddr + head, size - len);
1596
1597                 hexdump(m, ring, size);
1598                 kfree(ring);
1599         }
1600 }
1601
1602 static unsigned long list_count(struct list_head *list)
1603 {
1604         struct list_head *pos;
1605         unsigned long count = 0;
1606
1607         list_for_each(pos, list)
1608                 count++;
1609
1610         return count;
1611 }
1612
1613 static unsigned long read_ul(void *p, size_t x)
1614 {
1615         return *(unsigned long *)(p + x);
1616 }
1617
1618 static void print_properties(struct intel_engine_cs *engine,
1619                              struct drm_printer *m)
1620 {
1621         static const struct pmap {
1622                 size_t offset;
1623                 const char *name;
1624         } props[] = {
1625 #define P(x) { \
1626         .offset = offsetof(typeof(engine->props), x), \
1627         .name = #x \
1628 }
1629                 P(heartbeat_interval_ms),
1630                 P(max_busywait_duration_ns),
1631                 P(preempt_timeout_ms),
1632                 P(stop_timeout_ms),
1633                 P(timeslice_duration_ms),
1634
1635                 {},
1636 #undef P
1637         };
1638         const struct pmap *p;
1639
1640         drm_printf(m, "\tProperties:\n");
1641         for (p = props; p->name; p++)
1642                 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
1643                            p->name,
1644                            read_ul(&engine->props, p->offset),
1645                            read_ul(&engine->defaults, p->offset));
1646 }
1647
1648 void intel_engine_dump(struct intel_engine_cs *engine,
1649                        struct drm_printer *m,
1650                        const char *header, ...)
1651 {
1652         struct i915_gpu_error * const error = &engine->i915->gpu_error;
1653         struct i915_request *rq;
1654         intel_wakeref_t wakeref;
1655         unsigned long flags;
1656         ktime_t dummy;
1657
1658         if (header) {
1659                 va_list ap;
1660
1661                 va_start(ap, header);
1662                 drm_vprintf(m, header, &ap);
1663                 va_end(ap);
1664         }
1665
1666         if (intel_gt_is_wedged(engine->gt))
1667                 drm_printf(m, "*** WEDGED ***\n");
1668
1669         drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1670         drm_printf(m, "\tBarriers?: %s\n",
1671                    yesno(!llist_empty(&engine->barrier_tasks)));
1672         drm_printf(m, "\tLatency: %luus\n",
1673                    ewma__engine_latency_read(&engine->latency));
1674         if (intel_engine_supports_stats(engine))
1675                 drm_printf(m, "\tRuntime: %llums\n",
1676                            ktime_to_ms(intel_engine_get_busy_time(engine,
1677                                                                   &dummy)));
1678         drm_printf(m, "\tForcewake: %x domains, %d active\n",
1679                    engine->fw_domain, READ_ONCE(engine->fw_active));
1680
1681         rcu_read_lock();
1682         rq = READ_ONCE(engine->heartbeat.systole);
1683         if (rq)
1684                 drm_printf(m, "\tHeartbeat: %d ms ago\n",
1685                            jiffies_to_msecs(jiffies - rq->emitted_jiffies));
1686         rcu_read_unlock();
1687         drm_printf(m, "\tReset count: %d (global %d)\n",
1688                    i915_reset_engine_count(error, engine),
1689                    i915_reset_count(error));
1690         print_properties(engine, m);
1691
1692         drm_printf(m, "\tRequests:\n");
1693
1694         spin_lock_irqsave(&engine->active.lock, flags);
1695         rq = intel_engine_find_active_request(engine);
1696         if (rq) {
1697                 struct intel_timeline *tl = get_timeline(rq);
1698
1699                 i915_request_show(m, rq, "\t\tactive ", 0);
1700
1701                 drm_printf(m, "\t\tring->start:  0x%08x\n",
1702                            i915_ggtt_offset(rq->ring->vma));
1703                 drm_printf(m, "\t\tring->head:   0x%08x\n",
1704                            rq->ring->head);
1705                 drm_printf(m, "\t\tring->tail:   0x%08x\n",
1706                            rq->ring->tail);
1707                 drm_printf(m, "\t\tring->emit:   0x%08x\n",
1708                            rq->ring->emit);
1709                 drm_printf(m, "\t\tring->space:  0x%08x\n",
1710                            rq->ring->space);
1711
1712                 if (tl) {
1713                         drm_printf(m, "\t\tring->hwsp:   0x%08x\n",
1714                                    tl->hwsp_offset);
1715                         intel_timeline_put(tl);
1716                 }
1717
1718                 print_request_ring(m, rq);
1719
1720                 if (rq->context->lrc_reg_state) {
1721                         drm_printf(m, "Logical Ring Context:\n");
1722                         hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
1723                 }
1724         }
1725         drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold));
1726         spin_unlock_irqrestore(&engine->active.lock, flags);
1727
1728         drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
1729         wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
1730         if (wakeref) {
1731                 intel_engine_print_registers(engine, m);
1732                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1733         } else {
1734                 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1735         }
1736
1737         intel_execlists_show_requests(engine, m, i915_request_show, 8);
1738
1739         drm_printf(m, "HWSP:\n");
1740         hexdump(m, engine->status_page.addr, PAGE_SIZE);
1741
1742         drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1743
1744         intel_engine_print_breadcrumbs(engine, m);
1745 }
1746
1747 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
1748                                             ktime_t *now)
1749 {
1750         ktime_t total = engine->stats.total;
1751
1752         /*
1753          * If the engine is executing something at the moment
1754          * add it to the total.
1755          */
1756         *now = ktime_get();
1757         if (READ_ONCE(engine->stats.active))
1758                 total = ktime_add(total, ktime_sub(*now, engine->stats.start));
1759
1760         return total;
1761 }
1762
1763 /**
1764  * intel_engine_get_busy_time() - Return current accumulated engine busyness
1765  * @engine: engine to report on
1766  * @now: monotonic timestamp of sampling
1767  *
1768  * Returns accumulated time @engine was busy since engine stats were enabled.
1769  */
1770 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
1771 {
1772         unsigned int seq;
1773         ktime_t total;
1774
1775         do {
1776                 seq = read_seqcount_begin(&engine->stats.lock);
1777                 total = __intel_engine_get_busy_time(engine, now);
1778         } while (read_seqcount_retry(&engine->stats.lock, seq));
1779
1780         return total;
1781 }
1782
1783 static bool match_ring(struct i915_request *rq)
1784 {
1785         u32 ring = ENGINE_READ(rq->engine, RING_START);
1786
1787         return ring == i915_ggtt_offset(rq->ring->vma);
1788 }
1789
1790 struct i915_request *
1791 intel_engine_find_active_request(struct intel_engine_cs *engine)
1792 {
1793         struct i915_request *request, *active = NULL;
1794
1795         /*
1796          * We are called by the error capture, reset and to dump engine
1797          * state at random points in time. In particular, note that neither is
1798          * crucially ordered with an interrupt. After a hang, the GPU is dead
1799          * and we assume that no more writes can happen (we waited long enough
1800          * for all writes that were in transaction to be flushed) - adding an
1801          * extra delay for a recent interrupt is pointless. Hence, we do
1802          * not need an engine->irq_seqno_barrier() before the seqno reads.
1803          * At all other times, we must assume the GPU is still running, but
1804          * we only care about the snapshot of this moment.
1805          */
1806         lockdep_assert_held(&engine->active.lock);
1807
1808         rcu_read_lock();
1809         request = execlists_active(&engine->execlists);
1810         if (request) {
1811                 struct intel_timeline *tl = request->context->timeline;
1812
1813                 list_for_each_entry_from_reverse(request, &tl->requests, link) {
1814                         if (__i915_request_is_complete(request))
1815                                 break;
1816
1817                         active = request;
1818                 }
1819         }
1820         rcu_read_unlock();
1821         if (active)
1822                 return active;
1823
1824         list_for_each_entry(request, &engine->active.requests, sched.link) {
1825                 if (__i915_request_is_complete(request))
1826                         continue;
1827
1828                 if (!__i915_request_has_started(request))
1829                         continue;
1830
1831                 /* More than one preemptible request may match! */
1832                 if (!match_ring(request))
1833                         continue;
1834
1835                 active = request;
1836                 break;
1837         }
1838
1839         return active;
1840 }
1841
1842 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1843 #include "mock_engine.c"
1844 #include "selftest_engine.c"
1845 #include "selftest_engine_cs.c"
1846 #endif