drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_atomic.h"
  35 #include "intel_connector.h"
  36 #include "intel_display_types.h"
  37 #include "intel_dsi.h"
  38 #include "intel_fifo_underrun.h"
  39 #include "intel_panel.h"
  40 #include "intel_sideband.h"
  41
  42 /* return pixels in terms of txbyteclkhs */
  43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  44                        u16 burst_mode_ratio)
  45 {
  46         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  47                                          8 * 100), lane_count);
  48 }
  49
  50 /* return pixels equvalent to txbyteclkhs */
  51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  52                         u16 burst_mode_ratio)
  53 {
  54         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  55                                                 (bpp * burst_mode_ratio));
  56 }
  57
  58 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  59 {
  60         /* It just so happens the VBT matches register contents. */
  61         switch (fmt) {
  62         case VID_MODE_FORMAT_RGB888:
  63                 return MIPI_DSI_FMT_RGB888;
  64         case VID_MODE_FORMAT_RGB666:
  65                 return MIPI_DSI_FMT_RGB666;
  66         case VID_MODE_FORMAT_RGB666_PACKED:
  67                 return MIPI_DSI_FMT_RGB666_PACKED;
  68         case VID_MODE_FORMAT_RGB565:
  69                 return MIPI_DSI_FMT_RGB565;
  70         default:
  71                 MISSING_CASE(fmt);
  72                 return MIPI_DSI_FMT_RGB666;
  73         }
  74 }
  75
  76 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  77 {
  78         struct drm_encoder *encoder = &intel_dsi->base.base;
  79         struct drm_device *dev = encoder->dev;
  80         struct drm_i915_private *dev_priv = to_i915(dev);
  81         u32 mask;
  82
  83         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  84                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  85
  86         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  87                                   mask, 100))
  88                 DRM_ERROR("DPI FIFOs are not empty\n");
  89 }
  90
  91 static void write_data(struct drm_i915_private *dev_priv,
  92                        i915_reg_t reg,
  93                        const u8 *data, u32 len)
  94 {
  95         u32 i, j;
  96
  97         for (i = 0; i < len; i += 4) {
  98                 u32 val = 0;
  99
 100                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 101                         val |= *data++ << 8 * j;
 102
 103                 I915_WRITE(reg, val);
 104         }
 105 }
 106
 107 static void read_data(struct drm_i915_private *dev_priv,
 108                       i915_reg_t reg,
 109                       u8 *data, u32 len)
 110 {
 111         u32 i, j;
 112
 113         for (i = 0; i < len; i += 4) {
 114                 u32 val = I915_READ(reg);
 115
 116                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 117                         *data++ = val >> 8 * j;
 118         }
 119 }
 120
 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 122                                        const struct mipi_dsi_msg *msg)
 123 {
 124         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 125         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 126         struct drm_i915_private *dev_priv = to_i915(dev);
 127         enum port port = intel_dsi_host->port;
 128         struct mipi_dsi_packet packet;
 129         ssize_t ret;
 130         const u8 *header, *data;
 131         i915_reg_t data_reg, ctrl_reg;
 132         u32 data_mask, ctrl_mask;
 133
 134         ret = mipi_dsi_create_packet(&packet, msg);
 135         if (ret < 0)
 136                 return ret;
 137
 138         header = packet.header;
 139         data = packet.payload;
 140
 141         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 142                 data_reg = MIPI_LP_GEN_DATA(port);
 143                 data_mask = LP_DATA_FIFO_FULL;
 144                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 145                 ctrl_mask = LP_CTRL_FIFO_FULL;
 146         } else {
 147                 data_reg = MIPI_HS_GEN_DATA(port);
 148                 data_mask = HS_DATA_FIFO_FULL;
 149                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 150                 ctrl_mask = HS_CTRL_FIFO_FULL;
 151         }
 152
 153         /* note: this is never true for reads */
 154         if (packet.payload_length) {
 155                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 156                                             data_mask, 50))
 157                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 158
 159                 write_data(dev_priv, data_reg, packet.payload,
 160                            packet.payload_length);
 161         }
 162
 163         if (msg->rx_len) {
 164                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 165         }
 166
 167         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 168                                     ctrl_mask, 50)) {
 169                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 170         }
 171
 172         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 173
 174         /* ->rx_len is set only for reads */
 175         if (msg->rx_len) {
 176                 data_mask = GEN_READ_DATA_AVAIL;
 177                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 178                                           data_mask, 50))
 179                         DRM_ERROR("Timeout waiting for read data.\n");
 180
 181                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 182         }
 183
 184         /* XXX: fix for reads and writes */
 185         return 4 + packet.payload_length;
 186 }
 187
 188 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 189                                  struct mipi_dsi_device *dsi)
 190 {
 191         return 0;
 192 }
 193
 194 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 195                                  struct mipi_dsi_device *dsi)
 196 {
 197         return 0;
 198 }
 199
 200 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 201         .attach = intel_dsi_host_attach,
 202         .detach = intel_dsi_host_detach,
 203         .transfer = intel_dsi_host_transfer,
 204 };
 205
 206 /*
 207  * send a video mode command
 208  *
 209  * XXX: commands with data in MIPI_DPI_DATA?
 210  */
 211 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 212                         enum port port)
 213 {
 214         struct drm_encoder *encoder = &intel_dsi->base.base;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = to_i915(dev);
 217         u32 mask;
 218
 219         /* XXX: pipe, hs */
 220         if (hs)
 221                 cmd &= ~DPI_LP_MODE;
 222         else
 223                 cmd |= DPI_LP_MODE;
 224
 225         /* clear bit */
 226         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 227
 228         /* XXX: old code skips write if control unchanged */
 229         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 230                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 231
 232         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 233
 234         mask = SPL_PKT_SENT_INTERRUPT;
 235         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 236                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 237
 238         return 0;
 239 }
 240
 241 static void band_gap_reset(struct drm_i915_private *dev_priv)
 242 {
 243         vlv_flisdsi_get(dev_priv);
 244
 245         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 246         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 247         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 248         udelay(150);
 249         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 250         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 251
 252         vlv_flisdsi_put(dev_priv);
 253 }
 254
 255 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 256                                     struct intel_crtc_state *pipe_config,
 257                                     struct drm_connector_state *conn_state)
 258 {
 259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 260         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 261                                                    base);
 262         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 263         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 264         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 265         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 266         int ret;
 267
 268         DRM_DEBUG_KMS("\n");
 269         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 270
 271         if (fixed_mode) {
 272                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 273
 274                 if (HAS_GMCH(dev_priv))
 275                         intel_gmch_panel_fitting(crtc, pipe_config,
 276                                                  conn_state->scaling_mode);
 277                 else
 278                         intel_pch_panel_fitting(crtc, pipe_config,
 279                                                 conn_state->scaling_mode);
 280         }
 281
 282         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 283                 return -EINVAL;
 284
 285         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 286         adjusted_mode->flags = 0;
 287
 288         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 289                 pipe_config->pipe_bpp = 24;
 290         else
 291                 pipe_config->pipe_bpp = 18;
 292
 293         if (IS_GEN9_LP(dev_priv)) {
 294                 /* Enable Frame time stamp based scanline reporting */
 295                 adjusted_mode->private_flags |=
 296                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 297
 298                 /* Dual link goes to DSI transcoder A. */
 299                 if (intel_dsi->ports == BIT(PORT_C))
 300                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 301                 else
 302                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 303
 304                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 305                 if (ret)
 306                         return -EINVAL;
 307         } else {
 308                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 309                 if (ret)
 310                         return -EINVAL;
 311         }
 312
 313         pipe_config->clock_set = true;
 314
 315         return 0;
 316 }
 317
 318 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 319 {
 320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 321         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 322         enum port port;
 323         u32 tmp;
 324         bool cold_boot = false;
 325
 326         /* Set the MIPI mode
 327          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 328          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 329          */
 330         for_each_dsi_port(port, intel_dsi->ports) {
 331                 tmp = I915_READ(MIPI_CTRL(port));
 332                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 333         }
 334
 335         /* Put the IO into reset */
 336         tmp = I915_READ(MIPI_CTRL(PORT_A));
 337         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 338         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 339
 340         /* Program LP Wake */
 341         for_each_dsi_port(port, intel_dsi->ports) {
 342                 tmp = I915_READ(MIPI_CTRL(port));
 343                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 344                         tmp &= ~GLK_LP_WAKE;
 345                 else
 346                         tmp |= GLK_LP_WAKE;
 347                 I915_WRITE(MIPI_CTRL(port), tmp);
 348         }
 349
 350         /* Wait for Pwr ACK */
 351         for_each_dsi_port(port, intel_dsi->ports) {
 352                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 353                                           GLK_MIPIIO_PORT_POWERED, 20))
 354                         DRM_ERROR("MIPIO port is powergated\n");
 355         }
 356
 357         /* Check for cold boot scenario */
 358         for_each_dsi_port(port, intel_dsi->ports) {
 359                 cold_boot |=
 360                         !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
 361         }
 362
 363         return cold_boot;
 364 }
 365
 366 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 367 {
 368         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 369         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 370         enum port port;
 371         u32 val;
 372
 373         /* Wait for MIPI PHY status bit to set */
 374         for_each_dsi_port(port, intel_dsi->ports) {
 375                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 376                                           GLK_PHY_STATUS_PORT_READY, 20))
 377                         DRM_ERROR("PHY is not ON\n");
 378         }
 379
 380         /* Get IO out of reset */
 381         val = I915_READ(MIPI_CTRL(PORT_A));
 382         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 383
 384         /* Get IO out of Low power state*/
 385         for_each_dsi_port(port, intel_dsi->ports) {
 386                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 387                         val = I915_READ(MIPI_DEVICE_READY(port));
 388                         val &= ~ULPS_STATE_MASK;
 389                         val |= DEVICE_READY;
 390                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 391                         usleep_range(10, 15);
 392                 } else {
 393                         /* Enter ULPS */
 394                         val = I915_READ(MIPI_DEVICE_READY(port));
 395                         val &= ~ULPS_STATE_MASK;
 396                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 397                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 398
 399                         /* Wait for ULPS active */
 400                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 401                                                     GLK_ULPS_NOT_ACTIVE, 20))
 402                                 DRM_ERROR("ULPS not active\n");
 403
 404                         /* Exit ULPS */
 405                         val = I915_READ(MIPI_DEVICE_READY(port));
 406                         val &= ~ULPS_STATE_MASK;
 407                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 408                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 409
 410                         /* Enter Normal Mode */
 411                         val = I915_READ(MIPI_DEVICE_READY(port));
 412                         val &= ~ULPS_STATE_MASK;
 413                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 414                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 415
 416                         val = I915_READ(MIPI_CTRL(port));
 417                         val &= ~GLK_LP_WAKE;
 418                         I915_WRITE(MIPI_CTRL(port), val);
 419                 }
 420         }
 421
 422         /* Wait for Stop state */
 423         for_each_dsi_port(port, intel_dsi->ports) {
 424                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 425                                           GLK_DATA_LANE_STOP_STATE, 20))
 426                         DRM_ERROR("Date lane not in STOP state\n");
 427         }
 428
 429         /* Wait for AFE LATCH */
 430         for_each_dsi_port(port, intel_dsi->ports) {
 431                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 432                                           AFE_LATCHOUT, 20))
 433                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 434         }
 435 }
 436
 437 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 438 {
 439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 440         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 441         enum port port;
 442         u32 val;
 443
 444         DRM_DEBUG_KMS("\n");
 445
 446         /* Enable MIPI PHY transparent latch */
 447         for_each_dsi_port(port, intel_dsi->ports) {
 448                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 449                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 450                 usleep_range(2000, 2500);
 451         }
 452
 453         /* Clear ULPS and set device ready */
 454         for_each_dsi_port(port, intel_dsi->ports) {
 455                 val = I915_READ(MIPI_DEVICE_READY(port));
 456                 val &= ~ULPS_STATE_MASK;
 457                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 458                 usleep_range(2000, 2500);
 459                 val |= DEVICE_READY;
 460                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 461         }
 462 }
 463
 464 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 465 {
 466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 467         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 468         enum port port;
 469         u32 val;
 470
 471         DRM_DEBUG_KMS("\n");
 472
 473         vlv_flisdsi_get(dev_priv);
 474         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 475          * needed everytime after power gate */
 476         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 477         vlv_flisdsi_put(dev_priv);
 478
 479         /* bandgap reset is needed after everytime we do power gate */
 480         band_gap_reset(dev_priv);
 481
 482         for_each_dsi_port(port, intel_dsi->ports) {
 483
 484                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 485                 usleep_range(2500, 3000);
 486
 487                 /* Enable MIPI PHY transparent latch
 488                  * Common bit for both MIPI Port A & MIPI Port C
 489                  * No similar bit in MIPI Port C reg
 490                  */
 491                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 492                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 493                 usleep_range(1000, 1500);
 494
 495                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 496                 usleep_range(2500, 3000);
 497
 498                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 499                 usleep_range(2500, 3000);
 500         }
 501 }
 502
 503 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 504 {
 505         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 506
 507         if (IS_GEMINILAKE(dev_priv))
 508                 glk_dsi_device_ready(encoder);
 509         else if (IS_GEN9_LP(dev_priv))
 510                 bxt_dsi_device_ready(encoder);
 511         else
 512                 vlv_dsi_device_ready(encoder);
 513 }
 514
 515 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 516 {
 517         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 518         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 519         enum port port;
 520         u32 val;
 521
 522         /* Enter ULPS */
 523         for_each_dsi_port(port, intel_dsi->ports) {
 524                 val = I915_READ(MIPI_DEVICE_READY(port));
 525                 val &= ~ULPS_STATE_MASK;
 526                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 527                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 528         }
 529
 530         /* Wait for MIPI PHY status bit to unset */
 531         for_each_dsi_port(port, intel_dsi->ports) {
 532                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 533                                             GLK_PHY_STATUS_PORT_READY, 20))
 534                         DRM_ERROR("PHY is not turning OFF\n");
 535         }
 536
 537         /* Wait for Pwr ACK bit to unset */
 538         for_each_dsi_port(port, intel_dsi->ports) {
 539                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 540                                             GLK_MIPIIO_PORT_POWERED, 20))
 541                         DRM_ERROR("MIPI IO Port is not powergated\n");
 542         }
 543 }
 544
 545 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 546 {
 547         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 548         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 549         enum port port;
 550         u32 tmp;
 551
 552         /* Put the IO into reset */
 553         tmp = I915_READ(MIPI_CTRL(PORT_A));
 554         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 555         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 556
 557         /* Wait for MIPI PHY status bit to unset */
 558         for_each_dsi_port(port, intel_dsi->ports) {
 559                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 560                                             GLK_PHY_STATUS_PORT_READY, 20))
 561                         DRM_ERROR("PHY is not turning OFF\n");
 562         }
 563
 564         /* Clear MIPI mode */
 565         for_each_dsi_port(port, intel_dsi->ports) {
 566                 tmp = I915_READ(MIPI_CTRL(port));
 567                 tmp &= ~GLK_MIPIIO_ENABLE;
 568                 I915_WRITE(MIPI_CTRL(port), tmp);
 569         }
 570 }
 571
 572 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 573 {
 574         glk_dsi_enter_low_power_mode(encoder);
 575         glk_dsi_disable_mipi_io(encoder);
 576 }
 577
 578 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 579 {
 580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 581         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 582         enum port port;
 583
 584         DRM_DEBUG_KMS("\n");
 585         for_each_dsi_port(port, intel_dsi->ports) {
 586                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 587                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 588                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 589                 u32 val;
 590
 591                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 592                                                         ULPS_STATE_ENTER);
 593                 usleep_range(2000, 2500);
 594
 595                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 596                                                         ULPS_STATE_EXIT);
 597                 usleep_range(2000, 2500);
 598
 599                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 600                                                         ULPS_STATE_ENTER);
 601                 usleep_range(2000, 2500);
 602
 603                 /*
 604                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 605                  * Port A only. MIPI Port C has no similar bit for checking.
 606                  */
 607                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 608                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 609                                             AFE_LATCHOUT, 30))
 610                         DRM_ERROR("DSI LP not going Low\n");
 611
 612                 /* Disable MIPI PHY transparent latch */
 613                 val = I915_READ(port_ctrl);
 614                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 615                 usleep_range(1000, 1500);
 616
 617                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 618                 usleep_range(2000, 2500);
 619         }
 620 }
 621
 622 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 623                                   const struct intel_crtc_state *crtc_state)
 624 {
 625         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 626         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 627         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 628         enum port port;
 629
 630         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 631                 u32 temp;
 632                 if (IS_GEN9_LP(dev_priv)) {
 633                         for_each_dsi_port(port, intel_dsi->ports) {
 634                                 temp = I915_READ(MIPI_CTRL(port));
 635                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 636                                         intel_dsi->pixel_overlap <<
 637                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 638                                 I915_WRITE(MIPI_CTRL(port), temp);
 639                         }
 640                 } else {
 641                         temp = I915_READ(VLV_CHICKEN_3);
 642                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 643                                         intel_dsi->pixel_overlap <<
 644                                         PIXEL_OVERLAP_CNT_SHIFT;
 645                         I915_WRITE(VLV_CHICKEN_3, temp);
 646                 }
 647         }
 648
 649         for_each_dsi_port(port, intel_dsi->ports) {
 650                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 651                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 652                 u32 temp;
 653
 654                 temp = I915_READ(port_ctrl);
 655
 656                 temp &= ~LANE_CONFIGURATION_MASK;
 657                 temp &= ~DUAL_LINK_MODE_MASK;
 658
 659                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 660                         temp |= (intel_dsi->dual_link - 1)
 661                                                 << DUAL_LINK_MODE_SHIFT;
 662                         if (IS_BROXTON(dev_priv))
 663                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 664                         else
 665                                 temp |= crtc->pipe ?
 666                                         LANE_CONFIGURATION_DUAL_LINK_B :
 667                                         LANE_CONFIGURATION_DUAL_LINK_A;
 668                 }
 669
 670                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 671                         temp |= DITHERING_ENABLE;
 672
 673                 /* assert ip_tg_enable signal */
 674                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 675                 POSTING_READ(port_ctrl);
 676         }
 677 }
 678
 679 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 680 {
 681         struct drm_device *dev = encoder->base.dev;
 682         struct drm_i915_private *dev_priv = to_i915(dev);
 683         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 684         enum port port;
 685
 686         for_each_dsi_port(port, intel_dsi->ports) {
 687                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 688                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 689                 u32 temp;
 690
 691                 /* de-assert ip_tg_enable signal */
 692                 temp = I915_READ(port_ctrl);
 693                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 694                 POSTING_READ(port_ctrl);
 695         }
 696 }
 697
 698 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 699                               const struct intel_crtc_state *pipe_config);
 700 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 701
 702 /*
 703  * Panel enable/disable sequences from the VBT spec.
 704  *
 705  * Note the spec has AssertReset / DeassertReset swapped from their
 706  * usual naming. We use the normal names to avoid confusion (so below
 707  * they are swapped compared to the spec).
 708  *
 709  * Steps starting with MIPI refer to VBT sequences, note that for v2
 710  * VBTs several steps which have a VBT in v2 are expected to be handled
 711  * directly by the driver, by directly driving gpios for example.
 712  *
 713  * v2 video mode seq         v3 video mode seq         command mode seq
 714  * - power on                - MIPIPanelPowerOn        - power on
 715  * - wait t1+t2                                        - wait t1+t2
 716  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 717  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 718  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 719  *                                                     - MIPITearOn
 720  *                                                     - MIPIDisplayOn
 721  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 722  * - MIPIDisplayOn           - MIPIDisplayOn
 723  * - wait t5                                           - wait t5
 724  * - backlight on            - MIPIBacklightOn         - backlight on
 725  * ...                       ...                       ... issue mem cmds ...
 726  * - backlight off           - MIPIBacklightOff        - backlight off
 727  * - wait t6                                           - wait t6
 728  * - MIPIDisplayOff
 729  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 730  *                                                     - MIPITearOff
 731  *                           - MIPIDisplayOff          - MIPIDisplayOff
 732  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 733  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 734  * - wait t3                                           - wait t3
 735  * - power off               - MIPIPanelPowerOff       - power off
 736  * - wait t4                                           - wait t4
 737  */
 738
 739 /*
 740  * DSI port enable has to be done before pipe and plane enable, so we do it in
 741  * the pre_enable hook instead of the enable hook.
 742  */
 743 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 744                                  const struct intel_crtc_state *pipe_config,
 745                                  const struct drm_connector_state *conn_state)
 746 {
 747         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 748         struct drm_crtc *crtc = pipe_config->uapi.crtc;
 749         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 751         enum pipe pipe = intel_crtc->pipe;
 752         enum port port;
 753         u32 val;
 754         bool glk_cold_boot = false;
 755
 756         DRM_DEBUG_KMS("\n");
 757
 758         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 759
 760         /*
 761          * The BIOS may leave the PLL in a wonky state where it doesn't
 762          * lock. It needs to be fully powered down to fix it.
 763          */
 764         if (IS_GEN9_LP(dev_priv)) {
 765                 bxt_dsi_pll_disable(encoder);
 766                 bxt_dsi_pll_enable(encoder, pipe_config);
 767         } else {
 768                 vlv_dsi_pll_disable(encoder);
 769                 vlv_dsi_pll_enable(encoder, pipe_config);
 770         }
 771
 772         if (IS_BROXTON(dev_priv)) {
 773                 /* Add MIPI IO reset programming for modeset */
 774                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 775                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 776                                         val | MIPIO_RST_CTRL);
 777
 778                 /* Power up DSI regulator */
 779                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 780                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 781         }
 782
 783         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 784                 u32 val;
 785
 786                 /* Disable DPOunit clock gating, can stall pipe */
 787                 val = I915_READ(DSPCLK_GATE_D);
 788                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 789                 I915_WRITE(DSPCLK_GATE_D, val);
 790         }
 791
 792         if (!IS_GEMINILAKE(dev_priv))
 793                 intel_dsi_prepare(encoder, pipe_config);
 794
 795         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 796         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 797
 798         /* Deassert reset */
 799         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 800
 801         if (IS_GEMINILAKE(dev_priv)) {
 802                 glk_cold_boot = glk_dsi_enable_io(encoder);
 803
 804                 /* Prepare port in cold boot(s3/s4) scenario */
 805                 if (glk_cold_boot)
 806                         intel_dsi_prepare(encoder, pipe_config);
 807         }
 808
 809         /* Put device in ready state (LP-11) */
 810         intel_dsi_device_ready(encoder);
 811
 812         /* Prepare port in normal boot scenario */
 813         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 814                 intel_dsi_prepare(encoder, pipe_config);
 815
 816         /* Send initialization commands in LP mode */
 817         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 818
 819         /* Enable port in pre-enable phase itself because as per hw team
 820          * recommendation, port should be enabled befor plane & pipe */
 821         if (is_cmd_mode(intel_dsi)) {
 822                 for_each_dsi_port(port, intel_dsi->ports)
 823                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 824                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 825                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 826         } else {
 827                 msleep(20); /* XXX */
 828                 for_each_dsi_port(port, intel_dsi->ports)
 829                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 830                 intel_dsi_msleep(intel_dsi, 100);
 831
 832                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 833
 834                 intel_dsi_port_enable(encoder, pipe_config);
 835         }
 836
 837         intel_panel_enable_backlight(pipe_config, conn_state);
 838         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 839 }
 840
 841 /*
 842  * DSI port disable has to be done after pipe and plane disable, so we do it in
 843  * the post_disable hook.
 844  */
 845 static void intel_dsi_disable(struct intel_encoder *encoder,
 846                               const struct intel_crtc_state *old_crtc_state,
 847                               const struct drm_connector_state *old_conn_state)
 848 {
 849         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 850         enum port port;
 851
 852         DRM_DEBUG_KMS("\n");
 853
 854         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 855         intel_panel_disable_backlight(old_conn_state);
 856
 857         /*
 858          * According to the spec we should send SHUTDOWN before
 859          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 860          * has shown that the v3 sequence works for v2 VBTs too
 861          */
 862         if (is_vid_mode(intel_dsi)) {
 863                 /* Send Shutdown command to the panel in LP mode */
 864                 for_each_dsi_port(port, intel_dsi->ports)
 865                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 866                 msleep(10);
 867         }
 868 }
 869
 870 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 871 {
 872         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 873
 874         if (IS_GEMINILAKE(dev_priv))
 875                 glk_dsi_clear_device_ready(encoder);
 876         else
 877                 vlv_dsi_clear_device_ready(encoder);
 878 }
 879
 880 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 881                                    const struct intel_crtc_state *old_crtc_state,
 882                                    const struct drm_connector_state *old_conn_state)
 883 {
 884         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 885         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 886         enum port port;
 887         u32 val;
 888
 889         DRM_DEBUG_KMS("\n");
 890
 891         if (IS_GEN9_LP(dev_priv)) {
 892                 intel_crtc_vblank_off(old_crtc_state);
 893
 894                 skl_scaler_disable(old_crtc_state);
 895         }
 896
 897         if (is_vid_mode(intel_dsi)) {
 898                 for_each_dsi_port(port, intel_dsi->ports)
 899                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 900
 901                 intel_dsi_port_disable(encoder);
 902                 usleep_range(2000, 5000);
 903         }
 904
 905         intel_dsi_unprepare(encoder);
 906
 907         /*
 908          * if disable packets are sent before sending shutdown packet then in
 909          * some next enable sequence send turn on packet error is observed
 910          */
 911         if (is_cmd_mode(intel_dsi))
 912                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 913         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 914
 915         /* Transition to LP-00 */
 916         intel_dsi_clear_device_ready(encoder);
 917
 918         if (IS_BROXTON(dev_priv)) {
 919                 /* Power down DSI regulator to save power */
 920                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 921                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 922
 923                 /* Add MIPI IO reset programming for modeset */
 924                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 925                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 926                                 val & ~MIPIO_RST_CTRL);
 927         }
 928
 929         if (IS_GEN9_LP(dev_priv)) {
 930                 bxt_dsi_pll_disable(encoder);
 931         } else {
 932                 u32 val;
 933
 934                 vlv_dsi_pll_disable(encoder);
 935
 936                 val = I915_READ(DSPCLK_GATE_D);
 937                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 938                 I915_WRITE(DSPCLK_GATE_D, val);
 939         }
 940
 941         /* Assert reset */
 942         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 943
 944         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 945         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 946
 947         /*
 948          * FIXME As we do with eDP, just make a note of the time here
 949          * and perform the wait before the next panel power on.
 950          */
 951         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 952 }
 953
 954 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 955                                    enum pipe *pipe)
 956 {
 957         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 958         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 959         intel_wakeref_t wakeref;
 960         enum port port;
 961         bool active = false;
 962
 963         DRM_DEBUG_KMS("\n");
 964
 965         wakeref = intel_display_power_get_if_enabled(dev_priv,
 966                                                      encoder->power_domain);
 967         if (!wakeref)
 968                 return false;
 969
 970         /*
 971          * On Broxton the PLL needs to be enabled with a valid divider
 972          * configuration, otherwise accessing DSI registers will hang the
 973          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 974          */
 975         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
 976                 goto out_put_power;
 977
 978         /* XXX: this only works for one DSI output */
 979         for_each_dsi_port(port, intel_dsi->ports) {
 980                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 981                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 982                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 983
 984                 /*
 985                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 986                  * bit in port C control register does not get set. As a
 987                  * workaround, check pipe B conf instead.
 988                  */
 989                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 990                     port == PORT_C)
 991                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 992
 993                 /* Try command mode if video mode not enabled */
 994                 if (!enabled) {
 995                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 996                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 997                 }
 998
 999                 if (!enabled)
1000                         continue;
1001
1002                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1003                         continue;
1004
1005                 if (IS_GEN9_LP(dev_priv)) {
1006                         u32 tmp = I915_READ(MIPI_CTRL(port));
1007                         tmp &= BXT_PIPE_SELECT_MASK;
1008                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1009
1010                         if (WARN_ON(tmp > PIPE_C))
1011                                 continue;
1012
1013                         *pipe = tmp;
1014                 } else {
1015                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1016                 }
1017
1018                 active = true;
1019                 break;
1020         }
1021
1022 out_put_power:
1023         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1024
1025         return active;
1026 }
1027
1028 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1029                                     struct intel_crtc_state *pipe_config)
1030 {
1031         struct drm_device *dev = encoder->base.dev;
1032         struct drm_i915_private *dev_priv = to_i915(dev);
1033         struct drm_display_mode *adjusted_mode =
1034                                         &pipe_config->hw.adjusted_mode;
1035         struct drm_display_mode *adjusted_mode_sw;
1036         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1037         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1038         unsigned int lane_count = intel_dsi->lane_count;
1039         unsigned int bpp, fmt;
1040         enum port port;
1041         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1042         u16 hfp_sw, hsync_sw, hbp_sw;
1043         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1044                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1045
1046         /* FIXME: hw readout should not depend on SW state */
1047         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1048
1049         /*
1050          * Atleast one port is active as encoder->get_config called only if
1051          * encoder->get_hw_state() returns true.
1052          */
1053         for_each_dsi_port(port, intel_dsi->ports) {
1054                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1055                         break;
1056         }
1057
1058         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1059         bpp = mipi_dsi_pixel_format_to_bpp(
1060                         pixel_format_from_register_bits(fmt));
1061
1062         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1063
1064         /* Enable Frame time stamo based scanline reporting */
1065         adjusted_mode->private_flags |=
1066                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1067
1068         /* In terms of pixels */
1069         adjusted_mode->crtc_hdisplay =
1070                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1071         adjusted_mode->crtc_vdisplay =
1072                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1073         adjusted_mode->crtc_vtotal =
1074                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1075
1076         hactive = adjusted_mode->crtc_hdisplay;
1077         hfp = I915_READ(MIPI_HFP_COUNT(port));
1078
1079         /*
1080          * Meaningful for video mode non-burst sync pulse mode only,
1081          * can be zero for non-burst sync events and burst modes
1082          */
1083         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1084         hbp = I915_READ(MIPI_HBP_COUNT(port));
1085
1086         /* harizontal values are in terms of high speed byte clock */
1087         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1088                                                 intel_dsi->burst_mode_ratio);
1089         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1090                                                 intel_dsi->burst_mode_ratio);
1091         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1092                                                 intel_dsi->burst_mode_ratio);
1093
1094         if (intel_dsi->dual_link) {
1095                 hfp *= 2;
1096                 hsync *= 2;
1097                 hbp *= 2;
1098         }
1099
1100         /* vertical values are in terms of lines */
1101         vfp = I915_READ(MIPI_VFP_COUNT(port));
1102         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1103         vbp = I915_READ(MIPI_VBP_COUNT(port));
1104
1105         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1106         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1107         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1108         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1109         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1110
1111         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1112         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1113         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1114         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1115
1116         /*
1117          * In BXT DSI there is no regs programmed with few horizontal timings
1118          * in Pixels but txbyteclkhs.. So retrieval process adds some
1119          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1120          * Actually here for the given adjusted_mode, we are calculating the
1121          * value programmed to the port and then back to the horizontal timing
1122          * param in pixels. This is the expected value, including roundup errors
1123          * And if that is same as retrieved value from port, then
1124          * (HW state) adjusted_mode's horizontal timings are corrected to
1125          * match with SW state to nullify the errors.
1126          */
1127         /* Calculating the value programmed to the Port register */
1128         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1129                                         adjusted_mode_sw->crtc_hdisplay;
1130         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1131                                         adjusted_mode_sw->crtc_hsync_start;
1132         hbp_sw = adjusted_mode_sw->crtc_htotal -
1133                                         adjusted_mode_sw->crtc_hsync_end;
1134
1135         if (intel_dsi->dual_link) {
1136                 hfp_sw /= 2;
1137                 hsync_sw /= 2;
1138                 hbp_sw /= 2;
1139         }
1140
1141         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1142                                                 intel_dsi->burst_mode_ratio);
1143         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1144                             intel_dsi->burst_mode_ratio);
1145         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1146                                                 intel_dsi->burst_mode_ratio);
1147
1148         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1149         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1150                                                 intel_dsi->burst_mode_ratio);
1151         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1152                                                 intel_dsi->burst_mode_ratio);
1153         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1154                                                 intel_dsi->burst_mode_ratio);
1155
1156         if (intel_dsi->dual_link) {
1157                 hfp_sw *= 2;
1158                 hsync_sw *= 2;
1159                 hbp_sw *= 2;
1160         }
1161
1162         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1163                                                         hsync_sw + hbp_sw;
1164         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1165         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1166         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1167         crtc_hblank_end_sw = crtc_htotal_sw;
1168
1169         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1170                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1171
1172         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1173                 adjusted_mode->crtc_hsync_start =
1174                                         adjusted_mode_sw->crtc_hsync_start;
1175
1176         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1177                 adjusted_mode->crtc_hsync_end =
1178                                         adjusted_mode_sw->crtc_hsync_end;
1179
1180         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1181                 adjusted_mode->crtc_hblank_start =
1182                                         adjusted_mode_sw->crtc_hblank_start;
1183
1184         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1185                 adjusted_mode->crtc_hblank_end =
1186                                         adjusted_mode_sw->crtc_hblank_end;
1187 }
1188
1189 static void intel_dsi_get_config(struct intel_encoder *encoder,
1190                                  struct intel_crtc_state *pipe_config)
1191 {
1192         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1193         u32 pclk;
1194         DRM_DEBUG_KMS("\n");
1195
1196         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1197
1198         if (IS_GEN9_LP(dev_priv)) {
1199                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1200                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1201         } else {
1202                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1203         }
1204
1205         if (pclk) {
1206                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1207                 pipe_config->port_clock = pclk;
1208         }
1209 }
1210
1211 /* return txclkesc cycles in terms of divider and duration in us */
1212 static u16 txclkesc(u32 divider, unsigned int us)
1213 {
1214         switch (divider) {
1215         case ESCAPE_CLOCK_DIVIDER_1:
1216         default:
1217                 return 20 * us;
1218         case ESCAPE_CLOCK_DIVIDER_2:
1219                 return 10 * us;
1220         case ESCAPE_CLOCK_DIVIDER_4:
1221                 return 5 * us;
1222         }
1223 }
1224
1225 static void set_dsi_timings(struct drm_encoder *encoder,
1226                             const struct drm_display_mode *adjusted_mode)
1227 {
1228         struct drm_device *dev = encoder->dev;
1229         struct drm_i915_private *dev_priv = to_i915(dev);
1230         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1231         enum port port;
1232         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1233         unsigned int lane_count = intel_dsi->lane_count;
1234
1235         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1236
1237         hactive = adjusted_mode->crtc_hdisplay;
1238         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1239         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1240         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1241
1242         if (intel_dsi->dual_link) {
1243                 hactive /= 2;
1244                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1245                         hactive += intel_dsi->pixel_overlap;
1246                 hfp /= 2;
1247                 hsync /= 2;
1248                 hbp /= 2;
1249         }
1250
1251         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1252         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1253         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1254
1255         /* horizontal values are in terms of high speed byte clock */
1256         hactive = txbyteclkhs(hactive, bpp, lane_count,
1257                               intel_dsi->burst_mode_ratio);
1258         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1259         hsync = txbyteclkhs(hsync, bpp, lane_count,
1260                             intel_dsi->burst_mode_ratio);
1261         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1262
1263         for_each_dsi_port(port, intel_dsi->ports) {
1264                 if (IS_GEN9_LP(dev_priv)) {
1265                         /*
1266                          * Program hdisplay and vdisplay on MIPI transcoder.
1267                          * This is different from calculated hactive and
1268                          * vactive, as they are calculated per channel basis,
1269                          * whereas these values should be based on resolution.
1270                          */
1271                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1272                                    adjusted_mode->crtc_hdisplay);
1273                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1274                                    adjusted_mode->crtc_vdisplay);
1275                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1276                                    adjusted_mode->crtc_vtotal);
1277                 }
1278
1279                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1280                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1281
1282                 /* meaningful for video mode non-burst sync pulse mode only,
1283                  * can be zero for non-burst sync events and burst modes */
1284                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1285                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1286
1287                 /* vertical values are in terms of lines */
1288                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1289                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1290                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1291         }
1292 }
1293
1294 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1295 {
1296         switch (fmt) {
1297         case MIPI_DSI_FMT_RGB888:
1298                 return VID_MODE_FORMAT_RGB888;
1299         case MIPI_DSI_FMT_RGB666:
1300                 return VID_MODE_FORMAT_RGB666;
1301         case MIPI_DSI_FMT_RGB666_PACKED:
1302                 return VID_MODE_FORMAT_RGB666_PACKED;
1303         case MIPI_DSI_FMT_RGB565:
1304                 return VID_MODE_FORMAT_RGB565;
1305         default:
1306                 MISSING_CASE(fmt);
1307                 return VID_MODE_FORMAT_RGB666;
1308         }
1309 }
1310
1311 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1312                               const struct intel_crtc_state *pipe_config)
1313 {
1314         struct drm_encoder *encoder = &intel_encoder->base;
1315         struct drm_device *dev = encoder->dev;
1316         struct drm_i915_private *dev_priv = to_i915(dev);
1317         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1318         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1319         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1320         enum port port;
1321         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1322         u32 val, tmp;
1323         u16 mode_hdisplay;
1324
1325         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1326
1327         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1328
1329         if (intel_dsi->dual_link) {
1330                 mode_hdisplay /= 2;
1331                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1332                         mode_hdisplay += intel_dsi->pixel_overlap;
1333         }
1334
1335         for_each_dsi_port(port, intel_dsi->ports) {
1336                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1337                         /*
1338                          * escape clock divider, 20MHz, shared for A and C.
1339                          * device ready must be off when doing this! txclkesc?
1340                          */
1341                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1342                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1343                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1344                                         ESCAPE_CLOCK_DIVIDER_1);
1345
1346                         /* read request priority is per pipe */
1347                         tmp = I915_READ(MIPI_CTRL(port));
1348                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1349                         I915_WRITE(MIPI_CTRL(port), tmp |
1350                                         READ_REQUEST_PRIORITY_HIGH);
1351                 } else if (IS_GEN9_LP(dev_priv)) {
1352                         enum pipe pipe = intel_crtc->pipe;
1353
1354                         tmp = I915_READ(MIPI_CTRL(port));
1355                         tmp &= ~BXT_PIPE_SELECT_MASK;
1356
1357                         tmp |= BXT_PIPE_SELECT(pipe);
1358                         I915_WRITE(MIPI_CTRL(port), tmp);
1359                 }
1360
1361                 /* XXX: why here, why like this? handling in irq handler?! */
1362                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1363                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1364
1365                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1366
1367                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1368                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1369                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1370         }
1371
1372         set_dsi_timings(encoder, adjusted_mode);
1373
1374         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1375         if (is_cmd_mode(intel_dsi)) {
1376                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1377                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1378         } else {
1379                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1380                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1381         }
1382
1383         tmp = 0;
1384         if (intel_dsi->eotp_pkt == 0)
1385                 tmp |= EOT_DISABLE;
1386         if (intel_dsi->clock_stop)
1387                 tmp |= CLOCKSTOP;
1388
1389         if (IS_GEN9_LP(dev_priv)) {
1390                 tmp |= BXT_DPHY_DEFEATURE_EN;
1391                 if (!is_cmd_mode(intel_dsi))
1392                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1393         }
1394
1395         for_each_dsi_port(port, intel_dsi->ports) {
1396                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1397
1398                 /* timeouts for recovery. one frame IIUC. if counter expires,
1399                  * EOT and stop state. */
1400
1401                 /*
1402                  * In burst mode, value greater than one DPI line Time in byte
1403                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1404                  * said value is recommended.
1405                  *
1406                  * In non-burst mode, Value greater than one DPI frame time in
1407                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1408                  * said value is recommended.
1409                  *
1410                  * In DBI only mode, value greater than one DBI frame time in
1411                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1412                  * said value is recommended.
1413                  */
1414
1415                 if (is_vid_mode(intel_dsi) &&
1416                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1417                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1418                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1419                                             intel_dsi->lane_count,
1420                                             intel_dsi->burst_mode_ratio) + 1);
1421                 } else {
1422                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1423                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1424                                             adjusted_mode->crtc_htotal,
1425                                             bpp, intel_dsi->lane_count,
1426                                             intel_dsi->burst_mode_ratio) + 1);
1427                 }
1428                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1429                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1430                                                 intel_dsi->turn_arnd_val);
1431                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1432                                                 intel_dsi->rst_timer_val);
1433
1434                 /* dphy stuff */
1435
1436                 /* in terms of low power clock */
1437                 I915_WRITE(MIPI_INIT_COUNT(port),
1438                                 txclkesc(intel_dsi->escape_clk_div, 100));
1439
1440                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1441                         /*
1442                          * BXT spec says write MIPI_INIT_COUNT for
1443                          * both the ports, even if only one is
1444                          * getting used. So write the other port
1445                          * if not in dual link mode.
1446                          */
1447                         I915_WRITE(MIPI_INIT_COUNT(port ==
1448                                                 PORT_A ? PORT_C : PORT_A),
1449                                         intel_dsi->init_count);
1450                 }
1451
1452                 /* recovery disables */
1453                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1454
1455                 /* in terms of low power clock */
1456                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1457
1458                 /* in terms of txbyteclkhs. actual high to low switch +
1459                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1460                  *
1461                  * XXX: write MIPI_STOP_STATE_STALL?
1462                  */
1463                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1464                                                 intel_dsi->hs_to_lp_count);
1465
1466                 /* XXX: low power clock equivalence in terms of byte clock.
1467                  * the number of byte clocks occupied in one low power clock.
1468                  * based on txbyteclkhs and txclkesc.
1469                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1470                  * ) / 105.???
1471                  */
1472                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1473
1474                 if (IS_GEMINILAKE(dev_priv)) {
1475                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1476                                         intel_dsi->lp_byte_clk);
1477                         /* Shadow of DPHY reg */
1478                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1479                                         intel_dsi->dphy_reg);
1480                 }
1481
1482                 /* the bw essential for transmitting 16 long packets containing
1483                  * 252 bytes meant for dcs write memory command is programmed in
1484                  * this register in terms of byte clocks. based on dsi transfer
1485                  * rate and the number of lanes configured the time taken to
1486                  * transmit 16 long packets in a dsi stream varies. */
1487                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1488
1489                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1490                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1491                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1492
1493                 if (is_vid_mode(intel_dsi))
1494                         /* Some panels might have resolution which is not a
1495                          * multiple of 64 like 1366 x 768. Enable RANDOM
1496                          * resolution support for such panels by default */
1497                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1498                                 intel_dsi->video_frmt_cfg_bits |
1499                                 intel_dsi->video_mode_format |
1500                                 IP_TG_CONFIG |
1501                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1502         }
1503 }
1504
1505 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1506 {
1507         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1508         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1509         enum port port;
1510         u32 val;
1511
1512         if (IS_GEMINILAKE(dev_priv))
1513                 return;
1514
1515         for_each_dsi_port(port, intel_dsi->ports) {
1516                 /* Panel commands can be sent when clock is in LP11 */
1517                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1518
1519                 if (IS_GEN9_LP(dev_priv))
1520                         bxt_dsi_reset_clocks(encoder, port);
1521                 else
1522                         vlv_dsi_reset_clocks(encoder, port);
1523                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1524
1525                 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1526                 val &= ~VID_MODE_FORMAT_MASK;
1527                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1528
1529                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1530         }
1531 }
1532
1533 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1534 {
1535         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1536
1537         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1538         intel_encoder_destroy(encoder);
1539 }
1540
1541 static const struct drm_encoder_funcs intel_dsi_funcs = {
1542         .destroy = intel_dsi_encoder_destroy,
1543 };
1544
1545 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1546         .get_modes = intel_dsi_get_modes,
1547         .mode_valid = intel_dsi_mode_valid,
1548         .atomic_check = intel_digital_connector_atomic_check,
1549 };
1550
1551 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1552         .late_register = intel_connector_register,
1553         .early_unregister = intel_connector_unregister,
1554         .destroy = intel_connector_destroy,
1555         .fill_modes = drm_helper_probe_single_connector_modes,
1556         .atomic_get_property = intel_digital_connector_atomic_get_property,
1557         .atomic_set_property = intel_digital_connector_atomic_set_property,
1558         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1559         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1560 };
1561
1562 static enum drm_panel_orientation
1563 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1566         struct intel_encoder *encoder = connector->encoder;
1567         enum intel_display_power_domain power_domain;
1568         enum drm_panel_orientation orientation;
1569         struct intel_plane *plane;
1570         struct intel_crtc *crtc;
1571         intel_wakeref_t wakeref;
1572         enum pipe pipe;
1573         u32 val;
1574
1575         if (!encoder->get_hw_state(encoder, &pipe))
1576                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1577
1578         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1579         plane = to_intel_plane(crtc->base.primary);
1580
1581         power_domain = POWER_DOMAIN_PIPE(pipe);
1582         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1583         if (!wakeref)
1584                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1585
1586         val = I915_READ(DSPCNTR(plane->i9xx_plane));
1587
1588         if (!(val & DISPLAY_PLANE_ENABLE))
1589                 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1590         else if (val & DISPPLANE_ROTATE_180)
1591                 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1592         else
1593                 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1594
1595         intel_display_power_put(dev_priv, power_domain, wakeref);
1596
1597         return orientation;
1598 }
1599
1600 static enum drm_panel_orientation
1601 vlv_dsi_get_panel_orientation(struct intel_connector *connector)
1602 {
1603         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1604         enum drm_panel_orientation orientation;
1605
1606         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1607                 orientation = vlv_dsi_get_hw_panel_orientation(connector);
1608                 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
1609                         return orientation;
1610         }
1611
1612         return intel_dsi_get_panel_orientation(connector);
1613 }
1614
1615 static void vlv_dsi_add_properties(struct intel_connector *connector)
1616 {
1617         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1618
1619         if (connector->panel.fixed_mode) {
1620                 u32 allowed_scalers;
1621
1622                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1623                 if (!HAS_GMCH(dev_priv))
1624                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1625
1626                 drm_connector_attach_scaling_mode_property(&connector->base,
1627                                                                 allowed_scalers);
1628
1629                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1630
1631                 drm_connector_set_panel_orientation_with_quirk(
1632                                 &connector->base,
1633                                 vlv_dsi_get_panel_orientation(connector),
1634                                 connector->panel.fixed_mode->hdisplay,
1635                                 connector->panel.fixed_mode->vdisplay);
1636         }
1637 }
1638
1639 #define NS_KHZ_RATIO            1000000
1640
1641 #define PREPARE_CNT_MAX         0x3F
1642 #define EXIT_ZERO_CNT_MAX       0x3F
1643 #define CLK_ZERO_CNT_MAX        0xFF
1644 #define TRAIL_CNT_MAX           0x1F
1645
1646 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1647 {
1648         struct drm_device *dev = intel_dsi->base.base.dev;
1649         struct drm_i915_private *dev_priv = to_i915(dev);
1650         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1651         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1652         u32 ui_num, ui_den;
1653         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1654         u32 ths_prepare_ns, tclk_trail_ns;
1655         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1656         u32 lp_to_hs_switch, hs_to_lp_switch;
1657         u32 mul;
1658
1659         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1660
1661         switch (intel_dsi->lane_count) {
1662         case 1:
1663         case 2:
1664                 extra_byte_count = 2;
1665                 break;
1666         case 3:
1667                 extra_byte_count = 4;
1668                 break;
1669         case 4:
1670         default:
1671                 extra_byte_count = 3;
1672                 break;
1673         }
1674
1675         /* in Kbps */
1676         ui_num = NS_KHZ_RATIO;
1677         ui_den = intel_dsi_bitrate(intel_dsi);
1678
1679         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1680         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1681
1682         /*
1683          * B060
1684          * LP byte clock = TLPX/ (8UI)
1685          */
1686         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1687
1688         /* DDR clock period = 2 * UI
1689          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1690          * UI(nsec) = 10^6 / bitrate
1691          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1692          * DDR clock count  = ns_value / DDR clock period
1693          *
1694          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1695          * HS byte clock count for other platform in HS ddr clock count
1696          */
1697         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1698         ths_prepare_ns = max(mipi_config->ths_prepare,
1699                              mipi_config->tclk_prepare);
1700
1701         /* prepare count */
1702         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1703
1704         if (prepare_cnt > PREPARE_CNT_MAX) {
1705                 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
1706                 prepare_cnt = PREPARE_CNT_MAX;
1707         }
1708
1709         /* exit zero count */
1710         exit_zero_cnt = DIV_ROUND_UP(
1711                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1712                                 ui_num * mul
1713                                 );
1714
1715         /*
1716          * Exit zero is unified val ths_zero and ths_exit
1717          * minimum value for ths_exit = 110ns
1718          * min (exit_zero_cnt * 2) = 110/UI
1719          * exit_zero_cnt = 55/UI
1720          */
1721         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1722                 exit_zero_cnt += 1;
1723
1724         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1725                 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
1726                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1727         }
1728
1729         /* clk zero count */
1730         clk_zero_cnt = DIV_ROUND_UP(
1731                                 (tclk_prepare_clkzero - ths_prepare_ns)
1732                                 * ui_den, ui_num * mul);
1733
1734         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1735                 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
1736                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1737         }
1738
1739         /* trail count */
1740         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1741         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1742
1743         if (trail_cnt > TRAIL_CNT_MAX) {
1744                 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
1745                 trail_cnt = TRAIL_CNT_MAX;
1746         }
1747
1748         /* B080 */
1749         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1750                                                 clk_zero_cnt << 8 | prepare_cnt;
1751
1752         /*
1753          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1754          *                                      mul + 10UI + Extra Byte Count
1755          *
1756          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1757          * Extra Byte Count is calculated according to number of lanes.
1758          * High Low Switch Count is the Max of LP to HS and
1759          * HS to LP switch count
1760          *
1761          */
1762         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1763
1764         /* B044 */
1765         /* FIXME:
1766          * The comment above does not match with the code */
1767         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1768                                                 exit_zero_cnt * mul + 10, 8);
1769
1770         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1771
1772         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1773         intel_dsi->hs_to_lp_count += extra_byte_count;
1774
1775         /* B088 */
1776         /* LP -> HS for clock lanes
1777          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1778          *                                              extra byte count
1779          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1780          *                                      2(in UI) + extra byte count
1781          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1782          *                                      8 + extra byte count
1783          */
1784         intel_dsi->clk_lp_to_hs_count =
1785                 DIV_ROUND_UP(
1786                         4 * tlpx_ui + prepare_cnt * 2 +
1787                         clk_zero_cnt * 2,
1788                         8);
1789
1790         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1791
1792         /* HS->LP for Clock Lanes
1793          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1794          *                                              Extra byte count
1795          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1796          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1797          *                                              Extra byte count
1798          */
1799         intel_dsi->clk_hs_to_lp_count =
1800                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1801                         8);
1802         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1803
1804         intel_dsi_log_params(intel_dsi);
1805 }
1806
1807 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1808 {
1809         struct drm_device *dev = &dev_priv->drm;
1810         struct intel_dsi *intel_dsi;
1811         struct intel_encoder *intel_encoder;
1812         struct drm_encoder *encoder;
1813         struct intel_connector *intel_connector;
1814         struct drm_connector *connector;
1815         struct drm_display_mode *current_mode, *fixed_mode;
1816         enum port port;
1817         enum pipe pipe;
1818
1819         DRM_DEBUG_KMS("\n");
1820
1821         /* There is no detection method for MIPI so rely on VBT */
1822         if (!intel_bios_is_dsi_present(dev_priv, &port))
1823                 return;
1824
1825         if (IS_GEN9_LP(dev_priv))
1826                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1827         else
1828                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1829
1830         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1831         if (!intel_dsi)
1832                 return;
1833
1834         intel_connector = intel_connector_alloc();
1835         if (!intel_connector) {
1836                 kfree(intel_dsi);
1837                 return;
1838         }
1839
1840         intel_encoder = &intel_dsi->base;
1841         encoder = &intel_encoder->base;
1842         intel_dsi->attached_connector = intel_connector;
1843
1844         connector = &intel_connector->base;
1845
1846         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1847                          "DSI %c", port_name(port));
1848
1849         intel_encoder->compute_config = intel_dsi_compute_config;
1850         intel_encoder->pre_enable = intel_dsi_pre_enable;
1851         intel_encoder->disable = intel_dsi_disable;
1852         intel_encoder->post_disable = intel_dsi_post_disable;
1853         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1854         intel_encoder->get_config = intel_dsi_get_config;
1855         intel_encoder->update_pipe = intel_panel_update_backlight;
1856
1857         intel_connector->get_hw_state = intel_connector_get_hw_state;
1858
1859         intel_encoder->port = port;
1860         intel_encoder->type = INTEL_OUTPUT_DSI;
1861         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1862         intel_encoder->cloneable = 0;
1863
1864         /*
1865          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1866          * port C. BXT isn't limited like this.
1867          */
1868         if (IS_GEN9_LP(dev_priv))
1869                 intel_encoder->pipe_mask = ~0;
1870         else if (port == PORT_A)
1871                 intel_encoder->pipe_mask = BIT(PIPE_A);
1872         else
1873                 intel_encoder->pipe_mask = BIT(PIPE_B);
1874
1875         if (dev_priv->vbt.dsi.config->dual_link)
1876                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1877         else
1878                 intel_dsi->ports = BIT(port);
1879
1880         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1881         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1882
1883         /* Create a DSI host (and a device) for each port. */
1884         for_each_dsi_port(port, intel_dsi->ports) {
1885                 struct intel_dsi_host *host;
1886
1887                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1888                                            port);
1889                 if (!host)
1890                         goto err;
1891
1892                 intel_dsi->dsi_hosts[port] = host;
1893         }
1894
1895         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1896                 DRM_DEBUG_KMS("no device found\n");
1897                 goto err;
1898         }
1899
1900         /* Use clock read-back from current hw-state for fastboot */
1901         current_mode = intel_encoder_current_mode(intel_encoder);
1902         if (current_mode) {
1903                 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
1904                               intel_dsi->pclk, current_mode->clock);
1905                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1906                                             current_mode->clock)) {
1907                         DRM_DEBUG_KMS("Using GOP pclk\n");
1908                         intel_dsi->pclk = current_mode->clock;
1909                 }
1910
1911                 kfree(current_mode);
1912         }
1913
1914         vlv_dphy_param_init(intel_dsi);
1915
1916         intel_dsi_vbt_gpio_init(intel_dsi,
1917                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1918
1919         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1920                            DRM_MODE_CONNECTOR_DSI);
1921
1922         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1923
1924         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1925         connector->interlace_allowed = false;
1926         connector->doublescan_allowed = false;
1927
1928         intel_connector_attach_encoder(intel_connector, intel_encoder);
1929
1930         mutex_lock(&dev->mode_config.mutex);
1931         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1932         mutex_unlock(&dev->mode_config.mutex);
1933
1934         if (!fixed_mode) {
1935                 DRM_DEBUG_KMS("no fixed mode\n");
1936                 goto err_cleanup_connector;
1937         }
1938
1939         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1940         intel_panel_setup_backlight(connector, INVALID_PIPE);
1941
1942         vlv_dsi_add_properties(intel_connector);
1943
1944         return;
1945
1946 err_cleanup_connector:
1947         drm_connector_cleanup(&intel_connector->base);
1948 err:
1949         drm_encoder_cleanup(&intel_encoder->base);
1950         kfree(intel_dsi);
1951         kfree(intel_connector);
1952 }