drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/intel_lpe_audio.h>
  40
  41 #include "i915_debugfs.h"
  42 #include "i915_drv.h"
  43 #include "intel_atomic.h"
  44 #include "intel_connector.h"
  45 #include "intel_ddi.h"
  46 #include "intel_de.h"
  47 #include "intel_display_types.h"
  48 #include "intel_dp.h"
  49 #include "intel_gmbus.h"
  50 #include "intel_hdcp.h"
  51 #include "intel_hdmi.h"
  52 #include "intel_lspcon.h"
  53 #include "intel_panel.h"
  54 #include "intel_snps_phy.h"
  55
  56 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  57 {
  58         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  59 }
  60
  61 static void
  62 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  63 {
  64         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  65         struct drm_i915_private *dev_priv = to_i915(dev);
  66         u32 enabled_bits;
  67
  68         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  69
  70         drm_WARN(dev,
  71                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  72                  "HDMI port enabled, expecting disabled\n");
  73 }
  74
  75 static void
  76 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  77                                      enum transcoder cpu_transcoder)
  78 {
  79         drm_WARN(&dev_priv->drm,
  80                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  81                  TRANS_DDI_FUNC_ENABLE,
  82                  "HDMI transcoder function enabled, expecting disabled\n");
  83 }
  84
  85 static u32 g4x_infoframe_index(unsigned int type)
  86 {
  87         switch (type) {
  88         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  89                 return VIDEO_DIP_SELECT_GAMUT;
  90         case HDMI_INFOFRAME_TYPE_AVI:
  91                 return VIDEO_DIP_SELECT_AVI;
  92         case HDMI_INFOFRAME_TYPE_SPD:
  93                 return VIDEO_DIP_SELECT_SPD;
  94         case HDMI_INFOFRAME_TYPE_VENDOR:
  95                 return VIDEO_DIP_SELECT_VENDOR;
  96         default:
  97                 MISSING_CASE(type);
  98                 return 0;
  99         }
 100 }
 101
 102 static u32 g4x_infoframe_enable(unsigned int type)
 103 {
 104         switch (type) {
 105         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 106                 return VIDEO_DIP_ENABLE_GCP;
 107         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 108                 return VIDEO_DIP_ENABLE_GAMUT;
 109         case DP_SDP_VSC:
 110                 return 0;
 111         case HDMI_INFOFRAME_TYPE_AVI:
 112                 return VIDEO_DIP_ENABLE_AVI;
 113         case HDMI_INFOFRAME_TYPE_SPD:
 114                 return VIDEO_DIP_ENABLE_SPD;
 115         case HDMI_INFOFRAME_TYPE_VENDOR:
 116                 return VIDEO_DIP_ENABLE_VENDOR;
 117         case HDMI_INFOFRAME_TYPE_DRM:
 118                 return 0;
 119         default:
 120                 MISSING_CASE(type);
 121                 return 0;
 122         }
 123 }
 124
 125 static u32 hsw_infoframe_enable(unsigned int type)
 126 {
 127         switch (type) {
 128         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 129                 return VIDEO_DIP_ENABLE_GCP_HSW;
 130         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 131                 return VIDEO_DIP_ENABLE_GMP_HSW;
 132         case DP_SDP_VSC:
 133                 return VIDEO_DIP_ENABLE_VSC_HSW;
 134         case DP_SDP_PPS:
 135                 return VDIP_ENABLE_PPS;
 136         case HDMI_INFOFRAME_TYPE_AVI:
 137                 return VIDEO_DIP_ENABLE_AVI_HSW;
 138         case HDMI_INFOFRAME_TYPE_SPD:
 139                 return VIDEO_DIP_ENABLE_SPD_HSW;
 140         case HDMI_INFOFRAME_TYPE_VENDOR:
 141                 return VIDEO_DIP_ENABLE_VS_HSW;
 142         case HDMI_INFOFRAME_TYPE_DRM:
 143                 return VIDEO_DIP_ENABLE_DRM_GLK;
 144         default:
 145                 MISSING_CASE(type);
 146                 return 0;
 147         }
 148 }
 149
 150 static i915_reg_t
 151 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 152                  enum transcoder cpu_transcoder,
 153                  unsigned int type,
 154                  int i)
 155 {
 156         switch (type) {
 157         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 158                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 159         case DP_SDP_VSC:
 160                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 161         case DP_SDP_PPS:
 162                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 163         case HDMI_INFOFRAME_TYPE_AVI:
 164                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 165         case HDMI_INFOFRAME_TYPE_SPD:
 166                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 167         case HDMI_INFOFRAME_TYPE_VENDOR:
 168                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 169         case HDMI_INFOFRAME_TYPE_DRM:
 170                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 171         default:
 172                 MISSING_CASE(type);
 173                 return INVALID_MMIO_REG;
 174         }
 175 }
 176
 177 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 178                              unsigned int type)
 179 {
 180         switch (type) {
 181         case DP_SDP_VSC:
 182                 return VIDEO_DIP_VSC_DATA_SIZE;
 183         case DP_SDP_PPS:
 184                 return VIDEO_DIP_PPS_DATA_SIZE;
 185         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 186                 if (DISPLAY_VER(dev_priv) >= 11)
 187                         return VIDEO_DIP_GMP_DATA_SIZE;
 188                 else
 189                         return VIDEO_DIP_DATA_SIZE;
 190         default:
 191                 return VIDEO_DIP_DATA_SIZE;
 192         }
 193 }
 194
 195 static void g4x_write_infoframe(struct intel_encoder *encoder,
 196                                 const struct intel_crtc_state *crtc_state,
 197                                 unsigned int type,
 198                                 const void *frame, ssize_t len)
 199 {
 200         const u32 *data = frame;
 201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 202         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 203         int i;
 204
 205         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 206                  "Writing DIP with CTL reg disabled\n");
 207
 208         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 209         val |= g4x_infoframe_index(type);
 210
 211         val &= ~g4x_infoframe_enable(type);
 212
 213         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 214
 215         for (i = 0; i < len; i += 4) {
 216                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 217                 data++;
 218         }
 219         /* Write every possible data byte to force correct ECC calculation. */
 220         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 221                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 222
 223         val |= g4x_infoframe_enable(type);
 224         val &= ~VIDEO_DIP_FREQ_MASK;
 225         val |= VIDEO_DIP_FREQ_VSYNC;
 226
 227         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 228         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 229 }
 230
 231 static void g4x_read_infoframe(struct intel_encoder *encoder,
 232                                const struct intel_crtc_state *crtc_state,
 233                                unsigned int type,
 234                                void *frame, ssize_t len)
 235 {
 236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 237         u32 val, *data = frame;
 238         int i;
 239
 240         val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 241
 242         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 243         val |= g4x_infoframe_index(type);
 244
 245         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 246
 247         for (i = 0; i < len; i += 4)
 248                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 249 }
 250
 251 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 252                                   const struct intel_crtc_state *pipe_config)
 253 {
 254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 255         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 256
 257         if ((val & VIDEO_DIP_ENABLE) == 0)
 258                 return 0;
 259
 260         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 261                 return 0;
 262
 263         return val & (VIDEO_DIP_ENABLE_AVI |
 264                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 265 }
 266
 267 static void ibx_write_infoframe(struct intel_encoder *encoder,
 268                                 const struct intel_crtc_state *crtc_state,
 269                                 unsigned int type,
 270                                 const void *frame, ssize_t len)
 271 {
 272         const u32 *data = frame;
 273         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 275         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 276         u32 val = intel_de_read(dev_priv, reg);
 277         int i;
 278
 279         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 280                  "Writing DIP with CTL reg disabled\n");
 281
 282         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 283         val |= g4x_infoframe_index(type);
 284
 285         val &= ~g4x_infoframe_enable(type);
 286
 287         intel_de_write(dev_priv, reg, val);
 288
 289         for (i = 0; i < len; i += 4) {
 290                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 291                                *data);
 292                 data++;
 293         }
 294         /* Write every possible data byte to force correct ECC calculation. */
 295         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 296                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 297
 298         val |= g4x_infoframe_enable(type);
 299         val &= ~VIDEO_DIP_FREQ_MASK;
 300         val |= VIDEO_DIP_FREQ_VSYNC;
 301
 302         intel_de_write(dev_priv, reg, val);
 303         intel_de_posting_read(dev_priv, reg);
 304 }
 305
 306 static void ibx_read_infoframe(struct intel_encoder *encoder,
 307                                const struct intel_crtc_state *crtc_state,
 308                                unsigned int type,
 309                                void *frame, ssize_t len)
 310 {
 311         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 312         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 313         u32 val, *data = frame;
 314         int i;
 315
 316         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 317
 318         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 319         val |= g4x_infoframe_index(type);
 320
 321         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 322
 323         for (i = 0; i < len; i += 4)
 324                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 325 }
 326
 327 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 328                                   const struct intel_crtc_state *pipe_config)
 329 {
 330         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 331         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 332         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 333         u32 val = intel_de_read(dev_priv, reg);
 334
 335         if ((val & VIDEO_DIP_ENABLE) == 0)
 336                 return 0;
 337
 338         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 339                 return 0;
 340
 341         return val & (VIDEO_DIP_ENABLE_AVI |
 342                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 343                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 344 }
 345
 346 static void cpt_write_infoframe(struct intel_encoder *encoder,
 347                                 const struct intel_crtc_state *crtc_state,
 348                                 unsigned int type,
 349                                 const void *frame, ssize_t len)
 350 {
 351         const u32 *data = frame;
 352         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 353         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 354         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 355         u32 val = intel_de_read(dev_priv, reg);
 356         int i;
 357
 358         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 359                  "Writing DIP with CTL reg disabled\n");
 360
 361         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 362         val |= g4x_infoframe_index(type);
 363
 364         /* The DIP control register spec says that we need to update the AVI
 365          * infoframe without clearing its enable bit */
 366         if (type != HDMI_INFOFRAME_TYPE_AVI)
 367                 val &= ~g4x_infoframe_enable(type);
 368
 369         intel_de_write(dev_priv, reg, val);
 370
 371         for (i = 0; i < len; i += 4) {
 372                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 373                                *data);
 374                 data++;
 375         }
 376         /* Write every possible data byte to force correct ECC calculation. */
 377         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 378                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 379
 380         val |= g4x_infoframe_enable(type);
 381         val &= ~VIDEO_DIP_FREQ_MASK;
 382         val |= VIDEO_DIP_FREQ_VSYNC;
 383
 384         intel_de_write(dev_priv, reg, val);
 385         intel_de_posting_read(dev_priv, reg);
 386 }
 387
 388 static void cpt_read_infoframe(struct intel_encoder *encoder,
 389                                const struct intel_crtc_state *crtc_state,
 390                                unsigned int type,
 391                                void *frame, ssize_t len)
 392 {
 393         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 394         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 395         u32 val, *data = frame;
 396         int i;
 397
 398         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 399
 400         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 401         val |= g4x_infoframe_index(type);
 402
 403         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 404
 405         for (i = 0; i < len; i += 4)
 406                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 407 }
 408
 409 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 410                                   const struct intel_crtc_state *pipe_config)
 411 {
 412         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 413         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 414         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 415
 416         if ((val & VIDEO_DIP_ENABLE) == 0)
 417                 return 0;
 418
 419         return val & (VIDEO_DIP_ENABLE_AVI |
 420                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 421                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 422 }
 423
 424 static void vlv_write_infoframe(struct intel_encoder *encoder,
 425                                 const struct intel_crtc_state *crtc_state,
 426                                 unsigned int type,
 427                                 const void *frame, ssize_t len)
 428 {
 429         const u32 *data = frame;
 430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 431         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 432         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 433         u32 val = intel_de_read(dev_priv, reg);
 434         int i;
 435
 436         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 437                  "Writing DIP with CTL reg disabled\n");
 438
 439         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 440         val |= g4x_infoframe_index(type);
 441
 442         val &= ~g4x_infoframe_enable(type);
 443
 444         intel_de_write(dev_priv, reg, val);
 445
 446         for (i = 0; i < len; i += 4) {
 447                 intel_de_write(dev_priv,
 448                                VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
 449                 data++;
 450         }
 451         /* Write every possible data byte to force correct ECC calculation. */
 452         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 453                 intel_de_write(dev_priv,
 454                                VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
 455
 456         val |= g4x_infoframe_enable(type);
 457         val &= ~VIDEO_DIP_FREQ_MASK;
 458         val |= VIDEO_DIP_FREQ_VSYNC;
 459
 460         intel_de_write(dev_priv, reg, val);
 461         intel_de_posting_read(dev_priv, reg);
 462 }
 463
 464 static void vlv_read_infoframe(struct intel_encoder *encoder,
 465                                const struct intel_crtc_state *crtc_state,
 466                                unsigned int type,
 467                                void *frame, ssize_t len)
 468 {
 469         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 470         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 471         u32 val, *data = frame;
 472         int i;
 473
 474         val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
 475
 476         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 477         val |= g4x_infoframe_index(type);
 478
 479         intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 480
 481         for (i = 0; i < len; i += 4)
 482                 *data++ = intel_de_read(dev_priv,
 483                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 484 }
 485
 486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 487                                   const struct intel_crtc_state *pipe_config)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 491         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 492
 493         if ((val & VIDEO_DIP_ENABLE) == 0)
 494                 return 0;
 495
 496         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 497                 return 0;
 498
 499         return val & (VIDEO_DIP_ENABLE_AVI |
 500                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 501                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 502 }
 503
 504 void hsw_write_infoframe(struct intel_encoder *encoder,
 505                          const struct intel_crtc_state *crtc_state,
 506                          unsigned int type,
 507                          const void *frame, ssize_t len)
 508 {
 509         const u32 *data = frame;
 510         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 511         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 512         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 513         int data_size;
 514         int i;
 515         u32 val = intel_de_read(dev_priv, ctl_reg);
 516
 517         data_size = hsw_dip_data_size(dev_priv, type);
 518
 519         drm_WARN_ON(&dev_priv->drm, len > data_size);
 520
 521         val &= ~hsw_infoframe_enable(type);
 522         intel_de_write(dev_priv, ctl_reg, val);
 523
 524         for (i = 0; i < len; i += 4) {
 525                 intel_de_write(dev_priv,
 526                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 527                                *data);
 528                 data++;
 529         }
 530         /* Write every possible data byte to force correct ECC calculation. */
 531         for (; i < data_size; i += 4)
 532                 intel_de_write(dev_priv,
 533                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 534                                0);
 535
 536         /* Wa_14013475917 */
 537         if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
 538             type == DP_SDP_VSC)
 539                 return;
 540
 541         val |= hsw_infoframe_enable(type);
 542         intel_de_write(dev_priv, ctl_reg, val);
 543         intel_de_posting_read(dev_priv, ctl_reg);
 544 }
 545
 546 void hsw_read_infoframe(struct intel_encoder *encoder,
 547                         const struct intel_crtc_state *crtc_state,
 548                         unsigned int type, void *frame, ssize_t len)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 551         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 552         u32 *data = frame;
 553         int i;
 554
 555         for (i = 0; i < len; i += 4)
 556                 *data++ = intel_de_read(dev_priv,
 557                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 558 }
 559
 560 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 561                                   const struct intel_crtc_state *pipe_config)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 564         u32 val = intel_de_read(dev_priv,
 565                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 566         u32 mask;
 567
 568         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 569                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 570                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 571
 572         if (DISPLAY_VER(dev_priv) >= 10)
 573                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 574
 575         return val & mask;
 576 }
 577
 578 static const u8 infoframe_type_to_idx[] = {
 579         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 580         HDMI_PACKET_TYPE_GAMUT_METADATA,
 581         DP_SDP_VSC,
 582         HDMI_INFOFRAME_TYPE_AVI,
 583         HDMI_INFOFRAME_TYPE_SPD,
 584         HDMI_INFOFRAME_TYPE_VENDOR,
 585         HDMI_INFOFRAME_TYPE_DRM,
 586 };
 587
 588 u32 intel_hdmi_infoframe_enable(unsigned int type)
 589 {
 590         int i;
 591
 592         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 593                 if (infoframe_type_to_idx[i] == type)
 594                         return BIT(i);
 595         }
 596
 597         return 0;
 598 }
 599
 600 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 601                                   const struct intel_crtc_state *crtc_state)
 602 {
 603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 604         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 605         u32 val, ret = 0;
 606         int i;
 607
 608         val = dig_port->infoframes_enabled(encoder, crtc_state);
 609
 610         /* map from hardware bits to dip idx */
 611         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 612                 unsigned int type = infoframe_type_to_idx[i];
 613
 614                 if (HAS_DDI(dev_priv)) {
 615                         if (val & hsw_infoframe_enable(type))
 616                                 ret |= BIT(i);
 617                 } else {
 618                         if (val & g4x_infoframe_enable(type))
 619                                 ret |= BIT(i);
 620                 }
 621         }
 622
 623         return ret;
 624 }
 625
 626 /*
 627  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 628  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 629  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 630  * used for both technologies.
 631  *
 632  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 633  * DW1:       DB3       | DB2 | DB1 | DB0
 634  * DW2:       DB7       | DB6 | DB5 | DB4
 635  * DW3: ...
 636  *
 637  * (HB is Header Byte, DB is Data Byte)
 638  *
 639  * The hdmi pack() functions don't know about that hardware specific hole so we
 640  * trick them by giving an offset into the buffer and moving back the header
 641  * bytes by one.
 642  */
 643 static void intel_write_infoframe(struct intel_encoder *encoder,
 644                                   const struct intel_crtc_state *crtc_state,
 645                                   enum hdmi_infoframe_type type,
 646                                   const union hdmi_infoframe *frame)
 647 {
 648         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 649         u8 buffer[VIDEO_DIP_DATA_SIZE];
 650         ssize_t len;
 651
 652         if ((crtc_state->infoframes.enable &
 653              intel_hdmi_infoframe_enable(type)) == 0)
 654                 return;
 655
 656         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 657                 return;
 658
 659         /* see comment above for the reason for this offset */
 660         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 661         if (drm_WARN_ON(encoder->base.dev, len < 0))
 662                 return;
 663
 664         /* Insert the 'hole' (see big comment above) at position 3 */
 665         memmove(&buffer[0], &buffer[1], 3);
 666         buffer[3] = 0;
 667         len++;
 668
 669         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 670 }
 671
 672 void intel_read_infoframe(struct intel_encoder *encoder,
 673                           const struct intel_crtc_state *crtc_state,
 674                           enum hdmi_infoframe_type type,
 675                           union hdmi_infoframe *frame)
 676 {
 677         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 678         u8 buffer[VIDEO_DIP_DATA_SIZE];
 679         int ret;
 680
 681         if ((crtc_state->infoframes.enable &
 682              intel_hdmi_infoframe_enable(type)) == 0)
 683                 return;
 684
 685         dig_port->read_infoframe(encoder, crtc_state,
 686                                        type, buffer, sizeof(buffer));
 687
 688         /* Fill the 'hole' (see big comment above) at position 3 */
 689         memmove(&buffer[1], &buffer[0], 3);
 690
 691         /* see comment above for the reason for this offset */
 692         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 693         if (ret) {
 694                 drm_dbg_kms(encoder->base.dev,
 695                             "Failed to unpack infoframe type 0x%02x\n", type);
 696                 return;
 697         }
 698
 699         if (frame->any.type != type)
 700                 drm_dbg_kms(encoder->base.dev,
 701                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 702                             frame->any.type, type);
 703 }
 704
 705 static bool
 706 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 707                                  struct intel_crtc_state *crtc_state,
 708                                  struct drm_connector_state *conn_state)
 709 {
 710         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 711         const struct drm_display_mode *adjusted_mode =
 712                 &crtc_state->hw.adjusted_mode;
 713         struct drm_connector *connector = conn_state->connector;
 714         int ret;
 715
 716         if (!crtc_state->has_infoframe)
 717                 return true;
 718
 719         crtc_state->infoframes.enable |=
 720                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 721
 722         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 723                                                        adjusted_mode);
 724         if (ret)
 725                 return false;
 726
 727         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 728                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 729         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 730                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 731         else
 732                 frame->colorspace = HDMI_COLORSPACE_RGB;
 733
 734         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 735
 736         /* nonsense combination */
 737         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 738                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 739
 740         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 741                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 742                                                    adjusted_mode,
 743                                                    crtc_state->limited_color_range ?
 744                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 745                                                    HDMI_QUANTIZATION_RANGE_FULL);
 746         } else {
 747                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 748                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 749         }
 750
 751         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 752
 753         /* TODO: handle pixel repetition for YCBCR420 outputs */
 754
 755         ret = hdmi_avi_infoframe_check(frame);
 756         if (drm_WARN_ON(encoder->base.dev, ret))
 757                 return false;
 758
 759         return true;
 760 }
 761
 762 static bool
 763 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 764                                  struct intel_crtc_state *crtc_state,
 765                                  struct drm_connector_state *conn_state)
 766 {
 767         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 768         int ret;
 769
 770         if (!crtc_state->has_infoframe)
 771                 return true;
 772
 773         crtc_state->infoframes.enable |=
 774                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 775
 776         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 777         if (drm_WARN_ON(encoder->base.dev, ret))
 778                 return false;
 779
 780         frame->sdi = HDMI_SPD_SDI_PC;
 781
 782         ret = hdmi_spd_infoframe_check(frame);
 783         if (drm_WARN_ON(encoder->base.dev, ret))
 784                 return false;
 785
 786         return true;
 787 }
 788
 789 static bool
 790 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 791                                   struct intel_crtc_state *crtc_state,
 792                                   struct drm_connector_state *conn_state)
 793 {
 794         struct hdmi_vendor_infoframe *frame =
 795                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 796         const struct drm_display_info *info =
 797                 &conn_state->connector->display_info;
 798         int ret;
 799
 800         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 801                 return true;
 802
 803         crtc_state->infoframes.enable |=
 804                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 805
 806         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 807                                                           conn_state->connector,
 808                                                           &crtc_state->hw.adjusted_mode);
 809         if (drm_WARN_ON(encoder->base.dev, ret))
 810                 return false;
 811
 812         ret = hdmi_vendor_infoframe_check(frame);
 813         if (drm_WARN_ON(encoder->base.dev, ret))
 814                 return false;
 815
 816         return true;
 817 }
 818
 819 static bool
 820 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 821                                  struct intel_crtc_state *crtc_state,
 822                                  struct drm_connector_state *conn_state)
 823 {
 824         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 825         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 826         int ret;
 827
 828         if (DISPLAY_VER(dev_priv) < 10)
 829                 return true;
 830
 831         if (!crtc_state->has_infoframe)
 832                 return true;
 833
 834         if (!conn_state->hdr_output_metadata)
 835                 return true;
 836
 837         crtc_state->infoframes.enable |=
 838                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 839
 840         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 841         if (ret < 0) {
 842                 drm_dbg_kms(&dev_priv->drm,
 843                             "couldn't set HDR metadata in infoframe\n");
 844                 return false;
 845         }
 846
 847         ret = hdmi_drm_infoframe_check(frame);
 848         if (drm_WARN_ON(&dev_priv->drm, ret))
 849                 return false;
 850
 851         return true;
 852 }
 853
 854 static void g4x_set_infoframes(struct intel_encoder *encoder,
 855                                bool enable,
 856                                const struct intel_crtc_state *crtc_state,
 857                                const struct drm_connector_state *conn_state)
 858 {
 859         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 860         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 861         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 862         i915_reg_t reg = VIDEO_DIP_CTL;
 863         u32 val = intel_de_read(dev_priv, reg);
 864         u32 port = VIDEO_DIP_PORT(encoder->port);
 865
 866         assert_hdmi_port_disabled(intel_hdmi);
 867
 868         /* If the registers were not initialized yet, they might be zeroes,
 869          * which means we're selecting the AVI DIP and we're setting its
 870          * frequency to once. This seems to really confuse the HW and make
 871          * things stop working (the register spec says the AVI always needs to
 872          * be sent every VSync). So here we avoid writing to the register more
 873          * than we need and also explicitly select the AVI DIP and explicitly
 874          * set its frequency to every VSync. Avoiding to write it twice seems to
 875          * be enough to solve the problem, but being defensive shouldn't hurt us
 876          * either. */
 877         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 878
 879         if (!enable) {
 880                 if (!(val & VIDEO_DIP_ENABLE))
 881                         return;
 882                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 883                         drm_dbg_kms(&dev_priv->drm,
 884                                     "video DIP still enabled on port %c\n",
 885                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 886                         return;
 887                 }
 888                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 889                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 890                 intel_de_write(dev_priv, reg, val);
 891                 intel_de_posting_read(dev_priv, reg);
 892                 return;
 893         }
 894
 895         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 896                 if (val & VIDEO_DIP_ENABLE) {
 897                         drm_dbg_kms(&dev_priv->drm,
 898                                     "video DIP already enabled on port %c\n",
 899                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 900                         return;
 901                 }
 902                 val &= ~VIDEO_DIP_PORT_MASK;
 903                 val |= port;
 904         }
 905
 906         val |= VIDEO_DIP_ENABLE;
 907         val &= ~(VIDEO_DIP_ENABLE_AVI |
 908                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 909
 910         intel_de_write(dev_priv, reg, val);
 911         intel_de_posting_read(dev_priv, reg);
 912
 913         intel_write_infoframe(encoder, crtc_state,
 914                               HDMI_INFOFRAME_TYPE_AVI,
 915                               &crtc_state->infoframes.avi);
 916         intel_write_infoframe(encoder, crtc_state,
 917                               HDMI_INFOFRAME_TYPE_SPD,
 918                               &crtc_state->infoframes.spd);
 919         intel_write_infoframe(encoder, crtc_state,
 920                               HDMI_INFOFRAME_TYPE_VENDOR,
 921                               &crtc_state->infoframes.hdmi);
 922 }
 923
 924 /*
 925  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 926  *
 927  * From HDMI specification 1.4a:
 928  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 929  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 930  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 931  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 932  *   phase of 0
 933  */
 934 static bool gcp_default_phase_possible(int pipe_bpp,
 935                                        const struct drm_display_mode *mode)
 936 {
 937         unsigned int pixels_per_group;
 938
 939         switch (pipe_bpp) {
 940         case 30:
 941                 /* 4 pixels in 5 clocks */
 942                 pixels_per_group = 4;
 943                 break;
 944         case 36:
 945                 /* 2 pixels in 3 clocks */
 946                 pixels_per_group = 2;
 947                 break;
 948         case 48:
 949                 /* 1 pixel in 2 clocks */
 950                 pixels_per_group = 1;
 951                 break;
 952         default:
 953                 /* phase information not relevant for 8bpc */
 954                 return false;
 955         }
 956
 957         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 958                 mode->crtc_htotal % pixels_per_group == 0 &&
 959                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 960                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 961                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 962                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 963                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 964                  mode->crtc_htotal/2 % pixels_per_group == 0);
 965 }
 966
 967 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 968                                          const struct intel_crtc_state *crtc_state,
 969                                          const struct drm_connector_state *conn_state)
 970 {
 971         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 972         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 973         i915_reg_t reg;
 974
 975         if ((crtc_state->infoframes.enable &
 976              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 977                 return false;
 978
 979         if (HAS_DDI(dev_priv))
 980                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 981         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 982                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 983         else if (HAS_PCH_SPLIT(dev_priv))
 984                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 985         else
 986                 return false;
 987
 988         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 989
 990         return true;
 991 }
 992
 993 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 994                                    struct intel_crtc_state *crtc_state)
 995 {
 996         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 997         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 998         i915_reg_t reg;
 999
1000         if ((crtc_state->infoframes.enable &
1001              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1002                 return;
1003
1004         if (HAS_DDI(dev_priv))
1005                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1006         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1007                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1008         else if (HAS_PCH_SPLIT(dev_priv))
1009                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1010         else
1011                 return;
1012
1013         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1014 }
1015
1016 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1017                                              struct intel_crtc_state *crtc_state,
1018                                              struct drm_connector_state *conn_state)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1021
1022         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1023                 return;
1024
1025         crtc_state->infoframes.enable |=
1026                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1027
1028         /* Indicate color indication for deep color mode */
1029         if (crtc_state->pipe_bpp > 24)
1030                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1031
1032         /* Enable default_phase whenever the display mode is suitably aligned */
1033         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1034                                        &crtc_state->hw.adjusted_mode))
1035                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1036 }
1037
1038 static void ibx_set_infoframes(struct intel_encoder *encoder,
1039                                bool enable,
1040                                const struct intel_crtc_state *crtc_state,
1041                                const struct drm_connector_state *conn_state)
1042 {
1043         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1044         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1045         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1046         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1047         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1048         u32 val = intel_de_read(dev_priv, reg);
1049         u32 port = VIDEO_DIP_PORT(encoder->port);
1050
1051         assert_hdmi_port_disabled(intel_hdmi);
1052
1053         /* See the big comment in g4x_set_infoframes() */
1054         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1055
1056         if (!enable) {
1057                 if (!(val & VIDEO_DIP_ENABLE))
1058                         return;
1059                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1060                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1061                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1062                 intel_de_write(dev_priv, reg, val);
1063                 intel_de_posting_read(dev_priv, reg);
1064                 return;
1065         }
1066
1067         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1068                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1069                          "DIP already enabled on port %c\n",
1070                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1071                 val &= ~VIDEO_DIP_PORT_MASK;
1072                 val |= port;
1073         }
1074
1075         val |= VIDEO_DIP_ENABLE;
1076         val &= ~(VIDEO_DIP_ENABLE_AVI |
1077                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1078                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1079
1080         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1081                 val |= VIDEO_DIP_ENABLE_GCP;
1082
1083         intel_de_write(dev_priv, reg, val);
1084         intel_de_posting_read(dev_priv, reg);
1085
1086         intel_write_infoframe(encoder, crtc_state,
1087                               HDMI_INFOFRAME_TYPE_AVI,
1088                               &crtc_state->infoframes.avi);
1089         intel_write_infoframe(encoder, crtc_state,
1090                               HDMI_INFOFRAME_TYPE_SPD,
1091                               &crtc_state->infoframes.spd);
1092         intel_write_infoframe(encoder, crtc_state,
1093                               HDMI_INFOFRAME_TYPE_VENDOR,
1094                               &crtc_state->infoframes.hdmi);
1095 }
1096
1097 static void cpt_set_infoframes(struct intel_encoder *encoder,
1098                                bool enable,
1099                                const struct intel_crtc_state *crtc_state,
1100                                const struct drm_connector_state *conn_state)
1101 {
1102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1103         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1104         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1105         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1106         u32 val = intel_de_read(dev_priv, reg);
1107
1108         assert_hdmi_port_disabled(intel_hdmi);
1109
1110         /* See the big comment in g4x_set_infoframes() */
1111         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1112
1113         if (!enable) {
1114                 if (!(val & VIDEO_DIP_ENABLE))
1115                         return;
1116                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1117                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1118                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1119                 intel_de_write(dev_priv, reg, val);
1120                 intel_de_posting_read(dev_priv, reg);
1121                 return;
1122         }
1123
1124         /* Set both together, unset both together: see the spec. */
1125         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1126         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1127                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1128
1129         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1130                 val |= VIDEO_DIP_ENABLE_GCP;
1131
1132         intel_de_write(dev_priv, reg, val);
1133         intel_de_posting_read(dev_priv, reg);
1134
1135         intel_write_infoframe(encoder, crtc_state,
1136                               HDMI_INFOFRAME_TYPE_AVI,
1137                               &crtc_state->infoframes.avi);
1138         intel_write_infoframe(encoder, crtc_state,
1139                               HDMI_INFOFRAME_TYPE_SPD,
1140                               &crtc_state->infoframes.spd);
1141         intel_write_infoframe(encoder, crtc_state,
1142                               HDMI_INFOFRAME_TYPE_VENDOR,
1143                               &crtc_state->infoframes.hdmi);
1144 }
1145
1146 static void vlv_set_infoframes(struct intel_encoder *encoder,
1147                                bool enable,
1148                                const struct intel_crtc_state *crtc_state,
1149                                const struct drm_connector_state *conn_state)
1150 {
1151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1152         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1153         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1154         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1155         u32 val = intel_de_read(dev_priv, reg);
1156         u32 port = VIDEO_DIP_PORT(encoder->port);
1157
1158         assert_hdmi_port_disabled(intel_hdmi);
1159
1160         /* See the big comment in g4x_set_infoframes() */
1161         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1162
1163         if (!enable) {
1164                 if (!(val & VIDEO_DIP_ENABLE))
1165                         return;
1166                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1167                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1168                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1169                 intel_de_write(dev_priv, reg, val);
1170                 intel_de_posting_read(dev_priv, reg);
1171                 return;
1172         }
1173
1174         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1175                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1176                          "DIP already enabled on port %c\n",
1177                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1178                 val &= ~VIDEO_DIP_PORT_MASK;
1179                 val |= port;
1180         }
1181
1182         val |= VIDEO_DIP_ENABLE;
1183         val &= ~(VIDEO_DIP_ENABLE_AVI |
1184                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1185                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1186
1187         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1188                 val |= VIDEO_DIP_ENABLE_GCP;
1189
1190         intel_de_write(dev_priv, reg, val);
1191         intel_de_posting_read(dev_priv, reg);
1192
1193         intel_write_infoframe(encoder, crtc_state,
1194                               HDMI_INFOFRAME_TYPE_AVI,
1195                               &crtc_state->infoframes.avi);
1196         intel_write_infoframe(encoder, crtc_state,
1197                               HDMI_INFOFRAME_TYPE_SPD,
1198                               &crtc_state->infoframes.spd);
1199         intel_write_infoframe(encoder, crtc_state,
1200                               HDMI_INFOFRAME_TYPE_VENDOR,
1201                               &crtc_state->infoframes.hdmi);
1202 }
1203
1204 static void hsw_set_infoframes(struct intel_encoder *encoder,
1205                                bool enable,
1206                                const struct intel_crtc_state *crtc_state,
1207                                const struct drm_connector_state *conn_state)
1208 {
1209         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1210         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1211         u32 val = intel_de_read(dev_priv, reg);
1212
1213         assert_hdmi_transcoder_func_disabled(dev_priv,
1214                                              crtc_state->cpu_transcoder);
1215
1216         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1217                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1218                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1219                  VIDEO_DIP_ENABLE_DRM_GLK);
1220
1221         if (!enable) {
1222                 intel_de_write(dev_priv, reg, val);
1223                 intel_de_posting_read(dev_priv, reg);
1224                 return;
1225         }
1226
1227         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1228                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1229
1230         intel_de_write(dev_priv, reg, val);
1231         intel_de_posting_read(dev_priv, reg);
1232
1233         intel_write_infoframe(encoder, crtc_state,
1234                               HDMI_INFOFRAME_TYPE_AVI,
1235                               &crtc_state->infoframes.avi);
1236         intel_write_infoframe(encoder, crtc_state,
1237                               HDMI_INFOFRAME_TYPE_SPD,
1238                               &crtc_state->infoframes.spd);
1239         intel_write_infoframe(encoder, crtc_state,
1240                               HDMI_INFOFRAME_TYPE_VENDOR,
1241                               &crtc_state->infoframes.hdmi);
1242         intel_write_infoframe(encoder, crtc_state,
1243                               HDMI_INFOFRAME_TYPE_DRM,
1244                               &crtc_state->infoframes.drm);
1245 }
1246
1247 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1248 {
1249         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1250         struct i2c_adapter *adapter =
1251                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1252
1253         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1254                 return;
1255
1256         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1257                     enable ? "Enabling" : "Disabling");
1258
1259         drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1260 }
1261
1262 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1263                                 unsigned int offset, void *buffer, size_t size)
1264 {
1265         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1266         struct intel_hdmi *hdmi = &dig_port->hdmi;
1267         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1268                                                               hdmi->ddc_bus);
1269         int ret;
1270         u8 start = offset & 0xff;
1271         struct i2c_msg msgs[] = {
1272                 {
1273                         .addr = DRM_HDCP_DDC_ADDR,
1274                         .flags = 0,
1275                         .len = 1,
1276                         .buf = &start,
1277                 },
1278                 {
1279                         .addr = DRM_HDCP_DDC_ADDR,
1280                         .flags = I2C_M_RD,
1281                         .len = size,
1282                         .buf = buffer
1283                 }
1284         };
1285         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1286         if (ret == ARRAY_SIZE(msgs))
1287                 return 0;
1288         return ret >= 0 ? -EIO : ret;
1289 }
1290
1291 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1292                                  unsigned int offset, void *buffer, size_t size)
1293 {
1294         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1295         struct intel_hdmi *hdmi = &dig_port->hdmi;
1296         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1297                                                               hdmi->ddc_bus);
1298         int ret;
1299         u8 *write_buf;
1300         struct i2c_msg msg;
1301
1302         write_buf = kzalloc(size + 1, GFP_KERNEL);
1303         if (!write_buf)
1304                 return -ENOMEM;
1305
1306         write_buf[0] = offset & 0xff;
1307         memcpy(&write_buf[1], buffer, size);
1308
1309         msg.addr = DRM_HDCP_DDC_ADDR;
1310         msg.flags = 0,
1311         msg.len = size + 1,
1312         msg.buf = write_buf;
1313
1314         ret = i2c_transfer(adapter, &msg, 1);
1315         if (ret == 1)
1316                 ret = 0;
1317         else if (ret >= 0)
1318                 ret = -EIO;
1319
1320         kfree(write_buf);
1321         return ret;
1322 }
1323
1324 static
1325 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1326                                   u8 *an)
1327 {
1328         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1329         struct intel_hdmi *hdmi = &dig_port->hdmi;
1330         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1331                                                               hdmi->ddc_bus);
1332         int ret;
1333
1334         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1335                                     DRM_HDCP_AN_LEN);
1336         if (ret) {
1337                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1338                             ret);
1339                 return ret;
1340         }
1341
1342         ret = intel_gmbus_output_aksv(adapter);
1343         if (ret < 0) {
1344                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1345                 return ret;
1346         }
1347         return 0;
1348 }
1349
1350 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1351                                      u8 *bksv)
1352 {
1353         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1354
1355         int ret;
1356         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1357                                    DRM_HDCP_KSV_LEN);
1358         if (ret)
1359                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1360                             ret);
1361         return ret;
1362 }
1363
1364 static
1365 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1366                                  u8 *bstatus)
1367 {
1368         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1369
1370         int ret;
1371         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1372                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1373         if (ret)
1374                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1375                             ret);
1376         return ret;
1377 }
1378
1379 static
1380 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1381                                      bool *repeater_present)
1382 {
1383         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1384         int ret;
1385         u8 val;
1386
1387         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1388         if (ret) {
1389                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1390                             ret);
1391                 return ret;
1392         }
1393         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1394         return 0;
1395 }
1396
1397 static
1398 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1399                                   u8 *ri_prime)
1400 {
1401         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1402
1403         int ret;
1404         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1405                                    ri_prime, DRM_HDCP_RI_LEN);
1406         if (ret)
1407                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1408                             ret);
1409         return ret;
1410 }
1411
1412 static
1413 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1414                                    bool *ksv_ready)
1415 {
1416         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1417         int ret;
1418         u8 val;
1419
1420         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1421         if (ret) {
1422                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1423                             ret);
1424                 return ret;
1425         }
1426         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1427         return 0;
1428 }
1429
1430 static
1431 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1432                                   int num_downstream, u8 *ksv_fifo)
1433 {
1434         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1435         int ret;
1436         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1437                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1438         if (ret) {
1439                 drm_dbg_kms(&i915->drm,
1440                             "Read ksv fifo over DDC failed (%d)\n", ret);
1441                 return ret;
1442         }
1443         return 0;
1444 }
1445
1446 static
1447 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1448                                       int i, u32 *part)
1449 {
1450         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1451         int ret;
1452
1453         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1454                 return -EINVAL;
1455
1456         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1457                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1458         if (ret)
1459                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1460                             i, ret);
1461         return ret;
1462 }
1463
1464 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1465                                            enum transcoder cpu_transcoder)
1466 {
1467         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1468         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1469         struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1470         u32 scanline;
1471         int ret;
1472
1473         for (;;) {
1474                 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1475                 if (scanline > 100 && scanline < 200)
1476                         break;
1477                 usleep_range(25, 50);
1478         }
1479
1480         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1481                                          false, TRANS_DDI_HDCP_SIGNALLING);
1482         if (ret) {
1483                 drm_err(&dev_priv->drm,
1484                         "Disable HDCP signalling failed (%d)\n", ret);
1485                 return ret;
1486         }
1487
1488         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1489                                          true, TRANS_DDI_HDCP_SIGNALLING);
1490         if (ret) {
1491                 drm_err(&dev_priv->drm,
1492                         "Enable HDCP signalling failed (%d)\n", ret);
1493                 return ret;
1494         }
1495
1496         return 0;
1497 }
1498
1499 static
1500 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1501                                       enum transcoder cpu_transcoder,
1502                                       bool enable)
1503 {
1504         struct intel_hdmi *hdmi = &dig_port->hdmi;
1505         struct intel_connector *connector = hdmi->attached_connector;
1506         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1507         int ret;
1508
1509         if (!enable)
1510                 usleep_range(6, 60); /* Bspec says >= 6us */
1511
1512         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1513                                          cpu_transcoder, enable,
1514                                          TRANS_DDI_HDCP_SIGNALLING);
1515         if (ret) {
1516                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1517                         enable ? "Enable" : "Disable", ret);
1518                 return ret;
1519         }
1520
1521         /*
1522          * WA: To fix incorrect positioning of the window of
1523          * opportunity and enc_en signalling in KABYLAKE.
1524          */
1525         if (IS_KABYLAKE(dev_priv) && enable)
1526                 return kbl_repositioning_enc_en_signal(connector,
1527                                                        cpu_transcoder);
1528
1529         return 0;
1530 }
1531
1532 static
1533 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1534                                      struct intel_connector *connector)
1535 {
1536         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1537         enum port port = dig_port->base.port;
1538         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1539         int ret;
1540         union {
1541                 u32 reg;
1542                 u8 shim[DRM_HDCP_RI_LEN];
1543         } ri;
1544
1545         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1546         if (ret)
1547                 return false;
1548
1549         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1550
1551         /* Wait for Ri prime match */
1552         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1553                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1554                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1555                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1556                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1557                                                         port)));
1558                 return false;
1559         }
1560         return true;
1561 }
1562
1563 static
1564 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1565                                 struct intel_connector *connector)
1566 {
1567         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1568         int retry;
1569
1570         for (retry = 0; retry < 3; retry++)
1571                 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1572                         return true;
1573
1574         drm_err(&i915->drm, "Link check failed\n");
1575         return false;
1576 }
1577
1578 struct hdcp2_hdmi_msg_timeout {
1579         u8 msg_id;
1580         u16 timeout;
1581 };
1582
1583 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1584         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1585         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1586         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1587         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1588         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1589 };
1590
1591 static
1592 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1593                                     u8 *rx_status)
1594 {
1595         return intel_hdmi_hdcp_read(dig_port,
1596                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1597                                     rx_status,
1598                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1599 }
1600
1601 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1602 {
1603         int i;
1604
1605         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1606                 if (is_paired)
1607                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1608                 else
1609                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1610         }
1611
1612         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1613                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1614                         return hdcp2_msg_timeout[i].timeout;
1615         }
1616
1617         return -EINVAL;
1618 }
1619
1620 static int
1621 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1622                               u8 msg_id, bool *msg_ready,
1623                               ssize_t *msg_sz)
1624 {
1625         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1626         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1627         int ret;
1628
1629         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1630         if (ret < 0) {
1631                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1632                             ret);
1633                 return ret;
1634         }
1635
1636         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1637                   rx_status[0]);
1638
1639         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1640                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1641                              *msg_sz);
1642         else
1643                 *msg_ready = *msg_sz;
1644
1645         return 0;
1646 }
1647
1648 static ssize_t
1649 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1650                               u8 msg_id, bool paired)
1651 {
1652         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1653         bool msg_ready = false;
1654         int timeout, ret;
1655         ssize_t msg_sz = 0;
1656
1657         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1658         if (timeout < 0)
1659                 return timeout;
1660
1661         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1662                                                              msg_id, &msg_ready,
1663                                                              &msg_sz),
1664                          !ret && msg_ready && msg_sz, timeout * 1000,
1665                          1000, 5 * 1000);
1666         if (ret)
1667                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1668                             msg_id, ret, timeout);
1669
1670         return ret ? ret : msg_sz;
1671 }
1672
1673 static
1674 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1675                                void *buf, size_t size)
1676 {
1677         unsigned int offset;
1678
1679         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1680         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1681 }
1682
1683 static
1684 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1685                               u8 msg_id, void *buf, size_t size)
1686 {
1687         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1688         struct intel_hdmi *hdmi = &dig_port->hdmi;
1689         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1690         unsigned int offset;
1691         ssize_t ret;
1692
1693         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1694                                             hdcp->is_paired);
1695         if (ret < 0)
1696                 return ret;
1697
1698         /*
1699          * Available msg size should be equal to or lesser than the
1700          * available buffer.
1701          */
1702         if (ret > size) {
1703                 drm_dbg_kms(&i915->drm,
1704                             "msg_sz(%zd) is more than exp size(%zu)\n",
1705                             ret, size);
1706                 return -1;
1707         }
1708
1709         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1710         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1711         if (ret)
1712                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1713                             msg_id, ret);
1714
1715         return ret;
1716 }
1717
1718 static
1719 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1720                                 struct intel_connector *connector)
1721 {
1722         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1723         int ret;
1724
1725         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1726         if (ret)
1727                 return ret;
1728
1729         /*
1730          * Re-auth request and Link Integrity Failures are represented by
1731          * same bit. i.e reauth_req.
1732          */
1733         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1734                 ret = HDCP_REAUTH_REQUEST;
1735         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1736                 ret = HDCP_TOPOLOGY_CHANGE;
1737
1738         return ret;
1739 }
1740
1741 static
1742 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1743                              bool *capable)
1744 {
1745         u8 hdcp2_version;
1746         int ret;
1747
1748         *capable = false;
1749         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1750                                    &hdcp2_version, sizeof(hdcp2_version));
1751         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1752                 *capable = true;
1753
1754         return ret;
1755 }
1756
1757 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1758         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1759         .read_bksv = intel_hdmi_hdcp_read_bksv,
1760         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1761         .repeater_present = intel_hdmi_hdcp_repeater_present,
1762         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1763         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1764         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1765         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1766         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1767         .check_link = intel_hdmi_hdcp_check_link,
1768         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1769         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1770         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1771         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1772         .protocol = HDCP_PROTOCOL_HDMI,
1773 };
1774
1775 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1776 {
1777         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1778         int max_tmds_clock, vbt_max_tmds_clock;
1779
1780         if (DISPLAY_VER(dev_priv) >= 10)
1781                 max_tmds_clock = 594000;
1782         else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1783                 max_tmds_clock = 300000;
1784         else if (DISPLAY_VER(dev_priv) >= 5)
1785                 max_tmds_clock = 225000;
1786         else
1787                 max_tmds_clock = 165000;
1788
1789         vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1790         if (vbt_max_tmds_clock)
1791                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1792
1793         return max_tmds_clock;
1794 }
1795
1796 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1797                                 const struct drm_connector_state *conn_state)
1798 {
1799         return hdmi->has_hdmi_sink &&
1800                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1801 }
1802
1803 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1804                                  bool respect_downstream_limits,
1805                                  bool has_hdmi_sink)
1806 {
1807         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1808         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1809
1810         if (respect_downstream_limits) {
1811                 struct intel_connector *connector = hdmi->attached_connector;
1812                 const struct drm_display_info *info = &connector->base.display_info;
1813
1814                 if (hdmi->dp_dual_mode.max_tmds_clock)
1815                         max_tmds_clock = min(max_tmds_clock,
1816                                              hdmi->dp_dual_mode.max_tmds_clock);
1817
1818                 if (info->max_tmds_clock)
1819                         max_tmds_clock = min(max_tmds_clock,
1820                                              info->max_tmds_clock);
1821                 else if (!has_hdmi_sink)
1822                         max_tmds_clock = min(max_tmds_clock, 165000);
1823         }
1824
1825         return max_tmds_clock;
1826 }
1827
1828 static enum drm_mode_status
1829 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1830                       int clock, bool respect_downstream_limits,
1831                       bool has_hdmi_sink)
1832 {
1833         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1834
1835         if (clock < 25000)
1836                 return MODE_CLOCK_LOW;
1837         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1838                                           has_hdmi_sink))
1839                 return MODE_CLOCK_HIGH;
1840
1841         /* GLK DPLL can't generate 446-480 MHz */
1842         if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1843                 return MODE_CLOCK_RANGE;
1844
1845         /* BXT/GLK DPLL can't generate 223-240 MHz */
1846         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1847             clock > 223333 && clock < 240000)
1848                 return MODE_CLOCK_RANGE;
1849
1850         /* CHV DPLL can't generate 216-240 MHz */
1851         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1852                 return MODE_CLOCK_RANGE;
1853
1854         /*
1855          * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1856          * set of link rates.
1857          *
1858          * FIXME: We will hopefully get an algorithmic way of programming
1859          * the MPLLB for HDMI in the future.
1860          */
1861         if (IS_DG2(dev_priv))
1862                 return intel_snps_phy_check_hdmi_link_rate(clock);
1863
1864         return MODE_OK;
1865 }
1866
1867 static int intel_hdmi_port_clock(int clock, int bpc)
1868 {
1869         /*
1870          * Need to adjust the port link by:
1871          *  1.5x for 12bpc
1872          *  1.25x for 10bpc
1873          */
1874         return clock * bpc / 8;
1875 }
1876
1877 static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
1878                                     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1879 {
1880         struct drm_i915_private *i915 = to_i915(connector->dev);
1881         const struct drm_display_info *info = &connector->display_info;
1882         const struct drm_hdmi_info *hdmi = &info->hdmi;
1883
1884         switch (bpc) {
1885         case 12:
1886                 if (HAS_GMCH(i915))
1887                         return false;
1888
1889                 if (!has_hdmi_sink)
1890                         return false;
1891
1892                 if (ycbcr420_output)
1893                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1894                 else
1895                         return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
1896         case 10:
1897                 if (DISPLAY_VER(i915) < 11)
1898                         return false;
1899
1900                 if (!has_hdmi_sink)
1901                         return false;
1902
1903                 if (ycbcr420_output)
1904                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1905                 else
1906                         return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30;
1907         case 8:
1908                 return true;
1909         default:
1910                 MISSING_CASE(bpc);
1911                 return false;
1912         }
1913 }
1914
1915 static enum drm_mode_status
1916 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1917                             bool has_hdmi_sink, bool ycbcr420_output)
1918 {
1919         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1920         enum drm_mode_status status;
1921
1922         if (ycbcr420_output)
1923                 clock /= 2;
1924
1925         /* check if we can do 8bpc */
1926         status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1927                                        true, has_hdmi_sink);
1928
1929         /* if we can't do 8bpc we may still be able to do 12bpc */
1930         if (status != MODE_OK &&
1931             intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
1932                 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1933                                                true, has_hdmi_sink);
1934
1935         /* if we can't do 8,12bpc we may still be able to do 10bpc */
1936         if (status != MODE_OK &&
1937             intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
1938                 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1939                                                true, has_hdmi_sink);
1940
1941         return status;
1942 }
1943
1944 static enum drm_mode_status
1945 intel_hdmi_mode_valid(struct drm_connector *connector,
1946                       struct drm_display_mode *mode)
1947 {
1948         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1949         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1950         struct drm_i915_private *dev_priv = to_i915(dev);
1951         enum drm_mode_status status;
1952         int clock = mode->clock;
1953         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1954         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1955         bool ycbcr_420_only;
1956
1957         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1958                 return MODE_NO_DBLESCAN;
1959
1960         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1961                 clock *= 2;
1962
1963         if (clock > max_dotclk)
1964                 return MODE_CLOCK_HIGH;
1965
1966         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1967                 if (!has_hdmi_sink)
1968                         return MODE_CLOCK_LOW;
1969                 clock *= 2;
1970         }
1971
1972         ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
1973
1974         status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
1975         if (status != MODE_OK) {
1976                 if (ycbcr_420_only ||
1977                     !connector->ycbcr_420_allowed ||
1978                     !drm_mode_is_420_also(&connector->display_info, mode))
1979                         return status;
1980
1981                 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
1982                 if (status != MODE_OK)
1983                         return status;
1984         }
1985
1986         return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1987 }
1988
1989 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1990                                     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1991 {
1992         struct drm_atomic_state *state = crtc_state->uapi.state;
1993         struct drm_connector_state *connector_state;
1994         struct drm_connector *connector;
1995         int i;
1996
1997         if (crtc_state->pipe_bpp < bpc * 3)
1998                 return false;
1999
2000         for_each_new_connector_in_state(state, connector, connector_state, i) {
2001                 if (connector_state->crtc != crtc_state->uapi.crtc)
2002                         continue;
2003
2004                 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2005                         return false;
2006         }
2007
2008         return true;
2009 }
2010
2011 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2012                                      int bpc)
2013 {
2014         struct drm_i915_private *dev_priv =
2015                 to_i915(crtc_state->uapi.crtc->dev);
2016         const struct drm_display_mode *adjusted_mode =
2017                 &crtc_state->hw.adjusted_mode;
2018
2019         /*
2020          * HDMI deep color affects the clocks, so it's only possible
2021          * when not cloning with other encoder types.
2022          */
2023         if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2024                 return false;
2025
2026         /* Display Wa_1405510057:icl,ehl */
2027         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2028             bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2029             (adjusted_mode->crtc_hblank_end -
2030              adjusted_mode->crtc_hblank_start) % 8 == 2)
2031                 return false;
2032
2033         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2034                                               crtc_state->has_hdmi_sink,
2035                                               crtc_state->output_format ==
2036                                               INTEL_OUTPUT_FORMAT_YCBCR420);
2037 }
2038
2039 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2040                                   struct intel_crtc_state *crtc_state,
2041                                   int clock)
2042 {
2043         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2044         int bpc;
2045
2046         for (bpc = 12; bpc >= 10; bpc -= 2) {
2047                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2048                     hdmi_port_clock_valid(intel_hdmi,
2049                                           intel_hdmi_port_clock(clock, bpc),
2050                                           true, crtc_state->has_hdmi_sink) == MODE_OK)
2051                         return bpc;
2052         }
2053
2054         return 8;
2055 }
2056
2057 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2058                                     struct intel_crtc_state *crtc_state)
2059 {
2060         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2061         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2062         const struct drm_display_mode *adjusted_mode =
2063                 &crtc_state->hw.adjusted_mode;
2064         int bpc, clock = adjusted_mode->crtc_clock;
2065
2066         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2067                 clock *= 2;
2068
2069         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2070         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2071                 clock /= 2;
2072
2073         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2074
2075         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2076
2077         /*
2078          * pipe_bpp could already be below 8bpc due to
2079          * FDI bandwidth constraints. We shouldn't bump it
2080          * back up to 8bpc in that case.
2081          */
2082         if (crtc_state->pipe_bpp > bpc * 3)
2083                 crtc_state->pipe_bpp = bpc * 3;
2084
2085         drm_dbg_kms(&i915->drm,
2086                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2087                     bpc, crtc_state->pipe_bpp);
2088
2089         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2090                                   false, crtc_state->has_hdmi_sink) != MODE_OK) {
2091                 drm_dbg_kms(&i915->drm,
2092                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2093                             crtc_state->port_clock);
2094                 return -EINVAL;
2095         }
2096
2097         return 0;
2098 }
2099
2100 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2101                                     const struct drm_connector_state *conn_state)
2102 {
2103         const struct intel_digital_connector_state *intel_conn_state =
2104                 to_intel_digital_connector_state(conn_state);
2105         const struct drm_display_mode *adjusted_mode =
2106                 &crtc_state->hw.adjusted_mode;
2107
2108         /*
2109          * Our YCbCr output is always limited range.
2110          * crtc_state->limited_color_range only applies to RGB,
2111          * and it must never be set for YCbCr or we risk setting
2112          * some conflicting bits in PIPECONF which will mess up
2113          * the colors on the monitor.
2114          */
2115         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2116                 return false;
2117
2118         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2119                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2120                 return crtc_state->has_hdmi_sink &&
2121                         drm_default_rgb_quant_range(adjusted_mode) ==
2122                         HDMI_QUANTIZATION_RANGE_LIMITED;
2123         } else {
2124                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2125         }
2126 }
2127
2128 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2129                                  const struct intel_crtc_state *crtc_state,
2130                                  const struct drm_connector_state *conn_state)
2131 {
2132         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2133         const struct intel_digital_connector_state *intel_conn_state =
2134                 to_intel_digital_connector_state(conn_state);
2135
2136         if (!crtc_state->has_hdmi_sink)
2137                 return false;
2138
2139         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2140                 return intel_hdmi->has_audio;
2141         else
2142                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2143 }
2144
2145 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2146                                             struct intel_crtc_state *crtc_state,
2147                                             const struct drm_connector_state *conn_state)
2148 {
2149         struct drm_connector *connector = conn_state->connector;
2150         struct drm_i915_private *i915 = to_i915(connector->dev);
2151         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2152         int ret;
2153         bool ycbcr_420_only;
2154
2155         ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
2156         if (connector->ycbcr_420_allowed && ycbcr_420_only) {
2157                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2158         } else {
2159                 if (!connector->ycbcr_420_allowed && ycbcr_420_only)
2160                         drm_dbg_kms(&i915->drm,
2161                                     "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2162                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2163         }
2164
2165         ret = intel_hdmi_compute_clock(encoder, crtc_state);
2166         if (ret) {
2167                 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
2168                     connector->ycbcr_420_allowed &&
2169                     drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
2170                         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2171                         ret = intel_hdmi_compute_clock(encoder, crtc_state);
2172                 }
2173         }
2174
2175         return ret;
2176 }
2177
2178 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2179                               struct intel_crtc_state *pipe_config,
2180                               struct drm_connector_state *conn_state)
2181 {
2182         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2183         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2184         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2185         struct drm_connector *connector = conn_state->connector;
2186         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2187         int ret;
2188
2189         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2190                 return -EINVAL;
2191
2192         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2193         pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2194                                                          conn_state);
2195
2196         if (pipe_config->has_hdmi_sink)
2197                 pipe_config->has_infoframe = true;
2198
2199         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2200                 pipe_config->pixel_multiplier = 2;
2201
2202         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2203                 pipe_config->has_pch_encoder = true;
2204
2205         pipe_config->has_audio =
2206                 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2207
2208         ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2209         if (ret)
2210                 return ret;
2211
2212         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2213                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2214                 if (ret)
2215                         return ret;
2216         }
2217
2218         pipe_config->limited_color_range =
2219                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2220
2221         if (conn_state->picture_aspect_ratio)
2222                 adjusted_mode->picture_aspect_ratio =
2223                         conn_state->picture_aspect_ratio;
2224
2225         pipe_config->lane_count = 4;
2226
2227         if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2228                 if (scdc->scrambling.low_rates)
2229                         pipe_config->hdmi_scrambling = true;
2230
2231                 if (pipe_config->port_clock > 340000) {
2232                         pipe_config->hdmi_scrambling = true;
2233                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2234                 }
2235         }
2236
2237         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2238                                          conn_state);
2239
2240         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2241                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2242                 return -EINVAL;
2243         }
2244
2245         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2246                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2247                 return -EINVAL;
2248         }
2249
2250         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2251                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2252                 return -EINVAL;
2253         }
2254
2255         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2256                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2257                 return -EINVAL;
2258         }
2259
2260         return 0;
2261 }
2262
2263 static void
2264 intel_hdmi_unset_edid(struct drm_connector *connector)
2265 {
2266         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2267
2268         intel_hdmi->has_hdmi_sink = false;
2269         intel_hdmi->has_audio = false;
2270
2271         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2272         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2273
2274         kfree(to_intel_connector(connector)->detect_edid);
2275         to_intel_connector(connector)->detect_edid = NULL;
2276 }
2277
2278 static void
2279 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2280 {
2281         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2282         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2283         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2284         struct i2c_adapter *adapter =
2285                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2286         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2287
2288         /*
2289          * Type 1 DVI adaptors are not required to implement any
2290          * registers, so we can't always detect their presence.
2291          * Ideally we should be able to check the state of the
2292          * CONFIG1 pin, but no such luck on our hardware.
2293          *
2294          * The only method left to us is to check the VBT to see
2295          * if the port is a dual mode capable DP port. But let's
2296          * only do that when we sucesfully read the EDID, to avoid
2297          * confusing log messages about DP dual mode adaptors when
2298          * there's nothing connected to the port.
2299          */
2300         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2301                 /* An overridden EDID imply that we want this port for testing.
2302                  * Make sure not to set limits for that port.
2303                  */
2304                 if (has_edid && !connector->override_edid &&
2305                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2306                         drm_dbg_kms(&dev_priv->drm,
2307                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2308                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2309                 } else {
2310                         type = DRM_DP_DUAL_MODE_NONE;
2311                 }
2312         }
2313
2314         if (type == DRM_DP_DUAL_MODE_NONE)
2315                 return;
2316
2317         hdmi->dp_dual_mode.type = type;
2318         hdmi->dp_dual_mode.max_tmds_clock =
2319                 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2320
2321         drm_dbg_kms(&dev_priv->drm,
2322                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2323                     drm_dp_get_dual_mode_type_name(type),
2324                     hdmi->dp_dual_mode.max_tmds_clock);
2325 }
2326
2327 static bool
2328 intel_hdmi_set_edid(struct drm_connector *connector)
2329 {
2330         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2331         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2332         intel_wakeref_t wakeref;
2333         struct edid *edid;
2334         bool connected = false;
2335         struct i2c_adapter *i2c;
2336
2337         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2338
2339         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2340
2341         edid = drm_get_edid(connector, i2c);
2342
2343         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2344                 drm_dbg_kms(&dev_priv->drm,
2345                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2346                 intel_gmbus_force_bit(i2c, true);
2347                 edid = drm_get_edid(connector, i2c);
2348                 intel_gmbus_force_bit(i2c, false);
2349         }
2350
2351         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2352
2353         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2354
2355         to_intel_connector(connector)->detect_edid = edid;
2356         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2357                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2358                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2359
2360                 connected = true;
2361         }
2362
2363         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2364
2365         return connected;
2366 }
2367
2368 static enum drm_connector_status
2369 intel_hdmi_detect(struct drm_connector *connector, bool force)
2370 {
2371         enum drm_connector_status status = connector_status_disconnected;
2372         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2373         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2374         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2375         intel_wakeref_t wakeref;
2376
2377         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2378                     connector->base.id, connector->name);
2379
2380         if (!INTEL_DISPLAY_ENABLED(dev_priv))
2381                 return connector_status_disconnected;
2382
2383         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2384
2385         if (DISPLAY_VER(dev_priv) >= 11 &&
2386             !intel_digital_port_connected(encoder))
2387                 goto out;
2388
2389         intel_hdmi_unset_edid(connector);
2390
2391         if (intel_hdmi_set_edid(connector))
2392                 status = connector_status_connected;
2393
2394 out:
2395         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2396
2397         if (status != connector_status_connected)
2398                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2399
2400         /*
2401          * Make sure the refs for power wells enabled during detect are
2402          * dropped to avoid a new detect cycle triggered by HPD polling.
2403          */
2404         intel_display_power_flush_work(dev_priv);
2405
2406         return status;
2407 }
2408
2409 static void
2410 intel_hdmi_force(struct drm_connector *connector)
2411 {
2412         struct drm_i915_private *i915 = to_i915(connector->dev);
2413
2414         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2415                     connector->base.id, connector->name);
2416
2417         intel_hdmi_unset_edid(connector);
2418
2419         if (connector->status != connector_status_connected)
2420                 return;
2421
2422         intel_hdmi_set_edid(connector);
2423 }
2424
2425 static int intel_hdmi_get_modes(struct drm_connector *connector)
2426 {
2427         struct edid *edid;
2428
2429         edid = to_intel_connector(connector)->detect_edid;
2430         if (edid == NULL)
2431                 return 0;
2432
2433         return intel_connector_update_modes(connector, edid);
2434 }
2435
2436 static struct i2c_adapter *
2437 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2438 {
2439         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2440         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2441
2442         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2443 }
2444
2445 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2446 {
2447         struct drm_i915_private *i915 = to_i915(connector->dev);
2448         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2449         struct kobject *i2c_kobj = &adapter->dev.kobj;
2450         struct kobject *connector_kobj = &connector->kdev->kobj;
2451         int ret;
2452
2453         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2454         if (ret)
2455                 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2456 }
2457
2458 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2459 {
2460         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2461         struct kobject *i2c_kobj = &adapter->dev.kobj;
2462         struct kobject *connector_kobj = &connector->kdev->kobj;
2463
2464         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2465 }
2466
2467 static int
2468 intel_hdmi_connector_register(struct drm_connector *connector)
2469 {
2470         int ret;
2471
2472         ret = intel_connector_register(connector);
2473         if (ret)
2474                 return ret;
2475
2476         intel_hdmi_create_i2c_symlink(connector);
2477
2478         return ret;
2479 }
2480
2481 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2482 {
2483         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2484
2485         cec_notifier_conn_unregister(n);
2486
2487         intel_hdmi_remove_i2c_symlink(connector);
2488         intel_connector_unregister(connector);
2489 }
2490
2491 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2492         .detect = intel_hdmi_detect,
2493         .force = intel_hdmi_force,
2494         .fill_modes = drm_helper_probe_single_connector_modes,
2495         .atomic_get_property = intel_digital_connector_atomic_get_property,
2496         .atomic_set_property = intel_digital_connector_atomic_set_property,
2497         .late_register = intel_hdmi_connector_register,
2498         .early_unregister = intel_hdmi_connector_unregister,
2499         .destroy = intel_connector_destroy,
2500         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2501         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2502 };
2503
2504 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2505         .get_modes = intel_hdmi_get_modes,
2506         .mode_valid = intel_hdmi_mode_valid,
2507         .atomic_check = intel_digital_connector_atomic_check,
2508 };
2509
2510 static void
2511 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2512 {
2513         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2514
2515         intel_attach_force_audio_property(connector);
2516         intel_attach_broadcast_rgb_property(connector);
2517         intel_attach_aspect_ratio_property(connector);
2518
2519         intel_attach_hdmi_colorspace_property(connector);
2520         drm_connector_attach_content_type_property(connector);
2521
2522         if (DISPLAY_VER(dev_priv) >= 10)
2523                 drm_connector_attach_hdr_output_metadata_property(connector);
2524
2525         if (!HAS_GMCH(dev_priv))
2526                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2527 }
2528
2529 /*
2530  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2531  * @encoder: intel_encoder
2532  * @connector: drm_connector
2533  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2534  *  or reset the high tmds clock ratio for scrambling
2535  * @scrambling: bool to Indicate if the function needs to set or reset
2536  *  sink scrambling
2537  *
2538  * This function handles scrambling on HDMI 2.0 capable sinks.
2539  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2540  * it enables scrambling. This should be called before enabling the HDMI
2541  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2542  * detect a scrambled clock within 100 ms.
2543  *
2544  * Returns:
2545  * True on success, false on failure.
2546  */
2547 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2548                                        struct drm_connector *connector,
2549                                        bool high_tmds_clock_ratio,
2550                                        bool scrambling)
2551 {
2552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2553         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2554         struct drm_scrambling *sink_scrambling =
2555                 &connector->display_info.hdmi.scdc.scrambling;
2556         struct i2c_adapter *adapter =
2557                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2558
2559         if (!sink_scrambling->supported)
2560                 return true;
2561
2562         drm_dbg_kms(&dev_priv->drm,
2563                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2564                     connector->base.id, connector->name,
2565                     yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2566
2567         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2568         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2569                                                   high_tmds_clock_ratio) &&
2570                 drm_scdc_set_scrambling(adapter, scrambling);
2571 }
2572
2573 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2574 {
2575         u8 ddc_pin;
2576
2577         switch (port) {
2578         case PORT_B:
2579                 ddc_pin = GMBUS_PIN_DPB;
2580                 break;
2581         case PORT_C:
2582                 ddc_pin = GMBUS_PIN_DPC;
2583                 break;
2584         case PORT_D:
2585                 ddc_pin = GMBUS_PIN_DPD_CHV;
2586                 break;
2587         default:
2588                 MISSING_CASE(port);
2589                 ddc_pin = GMBUS_PIN_DPB;
2590                 break;
2591         }
2592         return ddc_pin;
2593 }
2594
2595 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2596 {
2597         u8 ddc_pin;
2598
2599         switch (port) {
2600         case PORT_B:
2601                 ddc_pin = GMBUS_PIN_1_BXT;
2602                 break;
2603         case PORT_C:
2604                 ddc_pin = GMBUS_PIN_2_BXT;
2605                 break;
2606         default:
2607                 MISSING_CASE(port);
2608                 ddc_pin = GMBUS_PIN_1_BXT;
2609                 break;
2610         }
2611         return ddc_pin;
2612 }
2613
2614 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2615                               enum port port)
2616 {
2617         u8 ddc_pin;
2618
2619         switch (port) {
2620         case PORT_B:
2621                 ddc_pin = GMBUS_PIN_1_BXT;
2622                 break;
2623         case PORT_C:
2624                 ddc_pin = GMBUS_PIN_2_BXT;
2625                 break;
2626         case PORT_D:
2627                 ddc_pin = GMBUS_PIN_4_CNP;
2628                 break;
2629         case PORT_F:
2630                 ddc_pin = GMBUS_PIN_3_BXT;
2631                 break;
2632         default:
2633                 MISSING_CASE(port);
2634                 ddc_pin = GMBUS_PIN_1_BXT;
2635                 break;
2636         }
2637         return ddc_pin;
2638 }
2639
2640 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2641 {
2642         enum phy phy = intel_port_to_phy(dev_priv, port);
2643
2644         if (intel_phy_is_combo(dev_priv, phy))
2645                 return GMBUS_PIN_1_BXT + port;
2646         else if (intel_phy_is_tc(dev_priv, phy))
2647                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2648
2649         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2650         return GMBUS_PIN_2_BXT;
2651 }
2652
2653 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2654 {
2655         enum phy phy = intel_port_to_phy(dev_priv, port);
2656         u8 ddc_pin;
2657
2658         switch (phy) {
2659         case PHY_A:
2660                 ddc_pin = GMBUS_PIN_1_BXT;
2661                 break;
2662         case PHY_B:
2663                 ddc_pin = GMBUS_PIN_2_BXT;
2664                 break;
2665         case PHY_C:
2666                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2667                 break;
2668         default:
2669                 MISSING_CASE(phy);
2670                 ddc_pin = GMBUS_PIN_1_BXT;
2671                 break;
2672         }
2673         return ddc_pin;
2674 }
2675
2676 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2677 {
2678         enum phy phy = intel_port_to_phy(dev_priv, port);
2679
2680         WARN_ON(port == PORT_C);
2681
2682         /*
2683          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2684          * final two outputs use type-c pins, even though they're actually
2685          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2686          * all outputs.
2687          */
2688         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2689                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2690
2691         return GMBUS_PIN_1_BXT + phy;
2692 }
2693
2694 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2695 {
2696         enum phy phy = intel_port_to_phy(i915, port);
2697
2698         drm_WARN_ON(&i915->drm, port == PORT_A);
2699
2700         /*
2701          * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2702          * final two outputs use type-c pins, even though they're actually
2703          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2704          * all outputs.
2705          */
2706         if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2707                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2708
2709         return GMBUS_PIN_1_BXT + phy;
2710 }
2711
2712 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2713 {
2714         return intel_port_to_phy(dev_priv, port) + 1;
2715 }
2716
2717 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2718 {
2719         enum phy phy = intel_port_to_phy(dev_priv, port);
2720
2721         WARN_ON(port == PORT_B || port == PORT_C);
2722
2723         /*
2724          * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2725          * except first combo output.
2726          */
2727         if (phy == PHY_A)
2728                 return GMBUS_PIN_1_BXT;
2729
2730         return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2731 }
2732
2733 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2734                               enum port port)
2735 {
2736         u8 ddc_pin;
2737
2738         switch (port) {
2739         case PORT_B:
2740                 ddc_pin = GMBUS_PIN_DPB;
2741                 break;
2742         case PORT_C:
2743                 ddc_pin = GMBUS_PIN_DPC;
2744                 break;
2745         case PORT_D:
2746                 ddc_pin = GMBUS_PIN_DPD;
2747                 break;
2748         default:
2749                 MISSING_CASE(port);
2750                 ddc_pin = GMBUS_PIN_DPB;
2751                 break;
2752         }
2753         return ddc_pin;
2754 }
2755
2756 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2757 {
2758         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2759         enum port port = encoder->port;
2760         u8 ddc_pin;
2761
2762         ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2763         if (ddc_pin) {
2764                 drm_dbg_kms(&dev_priv->drm,
2765                             "Using DDC pin 0x%x for port %c (VBT)\n",
2766                             ddc_pin, port_name(port));
2767                 return ddc_pin;
2768         }
2769
2770         if (IS_ALDERLAKE_S(dev_priv))
2771                 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2772         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2773                 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2774         else if (IS_ROCKETLAKE(dev_priv))
2775                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2776         else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2777                 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2778         else if (HAS_PCH_MCC(dev_priv))
2779                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2780         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2781                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2782         else if (HAS_PCH_CNP(dev_priv))
2783                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2784         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2785                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2786         else if (IS_CHERRYVIEW(dev_priv))
2787                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2788         else
2789                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2790
2791         drm_dbg_kms(&dev_priv->drm,
2792                     "Using DDC pin 0x%x for port %c (platform default)\n",
2793                     ddc_pin, port_name(port));
2794
2795         return ddc_pin;
2796 }
2797
2798 void intel_infoframe_init(struct intel_digital_port *dig_port)
2799 {
2800         struct drm_i915_private *dev_priv =
2801                 to_i915(dig_port->base.base.dev);
2802
2803         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2804                 dig_port->write_infoframe = vlv_write_infoframe;
2805                 dig_port->read_infoframe = vlv_read_infoframe;
2806                 dig_port->set_infoframes = vlv_set_infoframes;
2807                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2808         } else if (IS_G4X(dev_priv)) {
2809                 dig_port->write_infoframe = g4x_write_infoframe;
2810                 dig_port->read_infoframe = g4x_read_infoframe;
2811                 dig_port->set_infoframes = g4x_set_infoframes;
2812                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2813         } else if (HAS_DDI(dev_priv)) {
2814                 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2815                         dig_port->write_infoframe = lspcon_write_infoframe;
2816                         dig_port->read_infoframe = lspcon_read_infoframe;
2817                         dig_port->set_infoframes = lspcon_set_infoframes;
2818                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2819                 } else {
2820                         dig_port->write_infoframe = hsw_write_infoframe;
2821                         dig_port->read_infoframe = hsw_read_infoframe;
2822                         dig_port->set_infoframes = hsw_set_infoframes;
2823                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
2824                 }
2825         } else if (HAS_PCH_IBX(dev_priv)) {
2826                 dig_port->write_infoframe = ibx_write_infoframe;
2827                 dig_port->read_infoframe = ibx_read_infoframe;
2828                 dig_port->set_infoframes = ibx_set_infoframes;
2829                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2830         } else {
2831                 dig_port->write_infoframe = cpt_write_infoframe;
2832                 dig_port->read_infoframe = cpt_read_infoframe;
2833                 dig_port->set_infoframes = cpt_set_infoframes;
2834                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2835         }
2836 }
2837
2838 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2839                                struct intel_connector *intel_connector)
2840 {
2841         struct drm_connector *connector = &intel_connector->base;
2842         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2843         struct intel_encoder *intel_encoder = &dig_port->base;
2844         struct drm_device *dev = intel_encoder->base.dev;
2845         struct drm_i915_private *dev_priv = to_i915(dev);
2846         struct i2c_adapter *ddc;
2847         enum port port = intel_encoder->port;
2848         struct cec_connector_info conn_info;
2849
2850         drm_dbg_kms(&dev_priv->drm,
2851                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
2852                     intel_encoder->base.base.id, intel_encoder->base.name);
2853
2854         if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2855                 return;
2856
2857         if (drm_WARN(dev, dig_port->max_lanes < 4,
2858                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2859                      dig_port->max_lanes, intel_encoder->base.base.id,
2860                      intel_encoder->base.name))
2861                 return;
2862
2863         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2864         ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2865
2866         drm_connector_init_with_ddc(dev, connector,
2867                                     &intel_hdmi_connector_funcs,
2868                                     DRM_MODE_CONNECTOR_HDMIA,
2869                                     ddc);
2870         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2871
2872         connector->interlace_allowed = 1;
2873         connector->doublescan_allowed = 0;
2874         connector->stereo_allowed = 1;
2875
2876         if (DISPLAY_VER(dev_priv) >= 10)
2877                 connector->ycbcr_420_allowed = true;
2878
2879         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2880
2881         if (HAS_DDI(dev_priv))
2882                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2883         else
2884                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2885
2886         intel_hdmi_add_properties(intel_hdmi, connector);
2887
2888         intel_connector_attach_encoder(intel_connector, intel_encoder);
2889         intel_hdmi->attached_connector = intel_connector;
2890
2891         if (is_hdcp_supported(dev_priv, port)) {
2892                 int ret = intel_hdcp_init(intel_connector, dig_port,
2893                                           &intel_hdmi_hdcp_shim);
2894                 if (ret)
2895                         drm_dbg_kms(&dev_priv->drm,
2896                                     "HDCP init failed, skipping.\n");
2897         }
2898
2899         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2900          * 0xd.  Failure to do so will result in spurious interrupts being
2901          * generated on the port when a cable is not attached.
2902          */
2903         if (IS_G45(dev_priv)) {
2904                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2905                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2906                                (temp & ~0xf) | 0xd);
2907         }
2908
2909         cec_fill_conn_info_from_drm(&conn_info, connector);
2910
2911         intel_hdmi->cec_notifier =
2912                 cec_notifier_conn_register(dev->dev, port_identifier(port),
2913                                            &conn_info);
2914         if (!intel_hdmi->cec_notifier)
2915                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2916 }
2917
2918 /*
2919  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2920  * @vactive: Vactive of a display mode
2921  *
2922  * @return: appropriate dsc slice height for a given mode.
2923  */
2924 int intel_hdmi_dsc_get_slice_height(int vactive)
2925 {
2926         int slice_height;
2927
2928         /*
2929          * Slice Height determination : HDMI2.1 Section 7.7.5.2
2930          * Select smallest slice height >=96, that results in a valid PPS and
2931          * requires minimum padding lines required for final slice.
2932          *
2933          * Assumption : Vactive is even.
2934          */
2935         for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2936                 if (vactive % slice_height == 0)
2937                         return slice_height;
2938
2939         return 0;
2940 }
2941
2942 /*
2943  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2944  * and dsc decoder capabilities
2945  *
2946  * @crtc_state: intel crtc_state
2947  * @src_max_slices: maximum slices supported by the DSC encoder
2948  * @src_max_slice_width: maximum slice width supported by DSC encoder
2949  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2950  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2951  *
2952  * @return: num of dsc slices that can be supported by the dsc encoder
2953  * and decoder.
2954  */
2955 int
2956 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2957                               int src_max_slices, int src_max_slice_width,
2958                               int hdmi_max_slices, int hdmi_throughput)
2959 {
2960 /* Pixel rates in KPixels/sec */
2961 #define HDMI_DSC_PEAK_PIXEL_RATE                2720000
2962 /*
2963  * Rates at which the source and sink are required to process pixels in each
2964  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2965  */
2966 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0           340000
2967 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1           400000
2968
2969 /* Spec limits the slice width to 2720 pixels */
2970 #define MAX_HDMI_SLICE_WIDTH                    2720
2971         int kslice_adjust;
2972         int adjusted_clk_khz;
2973         int min_slices;
2974         int target_slices;
2975         int max_throughput; /* max clock freq. in khz per slice */
2976         int max_slice_width;
2977         int slice_width;
2978         int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2979
2980         if (!hdmi_throughput)
2981                 return 0;
2982
2983         /*
2984          * Slice Width determination : HDMI2.1 Section 7.7.5.1
2985          * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2986          * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2987          * dividing adjusted clock value by 10.
2988          */
2989         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2990             crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2991                 kslice_adjust = 10;
2992         else
2993                 kslice_adjust = 5;
2994
2995         /*
2996          * As per spec, the rate at which the source and the sink process
2997          * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2998          * This depends upon the pixel clock rate and output formats
2999          * (kslice adjust).
3000          * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3001          * at max 340MHz, otherwise they can be processed at max 400MHz.
3002          */
3003
3004         adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3005
3006         if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3007                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3008         else
3009                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3010
3011         /*
3012          * Taking into account the sink's capability for maximum
3013          * clock per slice (in MHz) as read from HF-VSDB.
3014          */
3015         max_throughput = min(max_throughput, hdmi_throughput * 1000);
3016
3017         min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3018         max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3019
3020         /*
3021          * Keep on increasing the num of slices/line, starting from min_slices
3022          * per line till we get such a number, for which the slice_width is
3023          * just less than max_slice_width. The slices/line selected should be
3024          * less than or equal to the max horizontal slices that the combination
3025          * of PCON encoder and HDMI decoder can support.
3026          */
3027         slice_width = max_slice_width;
3028
3029         do {
3030                 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3031                         target_slices = 1;
3032                 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3033                         target_slices = 2;
3034                 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3035                         target_slices = 4;
3036                 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3037                         target_slices = 8;
3038                 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3039                         target_slices = 12;
3040                 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3041                         target_slices = 16;
3042                 else
3043                         return 0;
3044
3045                 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3046                 if (slice_width >= max_slice_width)
3047                         min_slices = target_slices + 1;
3048         } while (slice_width >= max_slice_width);
3049
3050         return target_slices;
3051 }
3052
3053 /*
3054  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3055  * source and sink capabilities.
3056  *
3057  * @src_fraction_bpp: fractional bpp supported by the source
3058  * @slice_width: dsc slice width supported by the source and sink
3059  * @num_slices: num of slices supported by the source and sink
3060  * @output_format: video output format
3061  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3062  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3063  *
3064  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3065  */
3066 int
3067 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3068                        int output_format, bool hdmi_all_bpp,
3069                        int hdmi_max_chunk_bytes)
3070 {
3071         int max_dsc_bpp, min_dsc_bpp;
3072         int target_bytes;
3073         bool bpp_found = false;
3074         int bpp_decrement_x16;
3075         int bpp_target;
3076         int bpp_target_x16;
3077
3078         /*
3079          * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3080          * Start with the max bpp and keep on decrementing with
3081          * fractional bpp, if supported by PCON DSC encoder
3082          *
3083          * for each bpp we check if no of bytes can be supported by HDMI sink
3084          */
3085
3086         /* Assuming: bpc as 8*/
3087         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3088                 min_dsc_bpp = 6;
3089                 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3090         } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3091                    output_format == INTEL_OUTPUT_FORMAT_RGB) {
3092                 min_dsc_bpp = 8;
3093                 max_dsc_bpp = 3 * 8; /* 3*bpc */
3094         } else {
3095                 /* Assuming 4:2:2 encoding */
3096                 min_dsc_bpp = 7;
3097                 max_dsc_bpp = 2 * 8; /* 2*bpc */
3098         }
3099
3100         /*
3101          * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3102          * Section 7.7.34 : Source shall not enable compressed Video
3103          * Transport with bpp_target settings above 12 bpp unless
3104          * DSC_all_bpp is set to 1.
3105          */
3106         if (!hdmi_all_bpp)
3107                 max_dsc_bpp = min(max_dsc_bpp, 12);
3108
3109         /*
3110          * The Sink has a limit of compressed data in bytes for a scanline,
3111          * as described in max_chunk_bytes field in HFVSDB block of edid.
3112          * The no. of bytes depend on the target bits per pixel that the
3113          * source configures. So we start with the max_bpp and calculate
3114          * the target_chunk_bytes. We keep on decrementing the target_bpp,
3115          * till we get the target_chunk_bytes just less than what the sink's
3116          * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3117          *
3118          * The decrement is according to the fractional support from PCON DSC
3119          * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3120          *
3121          * bpp_target_x16 = bpp_target * 16
3122          * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3123          * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3124          */
3125
3126         bpp_target = max_dsc_bpp;
3127
3128         /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3129         if (!src_fractional_bpp)
3130                 src_fractional_bpp = 1;
3131         bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3132         bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3133
3134         while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3135                 int bpp;
3136
3137                 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3138                 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3139                 if (target_bytes <= hdmi_max_chunk_bytes) {
3140                         bpp_found = true;
3141                         break;
3142                 }
3143                 bpp_target_x16 -= bpp_decrement_x16;
3144         }
3145         if (bpp_found)
3146                 return bpp_target_x16;
3147
3148         return 0;
3149 }